4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/qemu-print.h"
32 #include "exec/semihost.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
39 #include "trace-tcg.h"
40 #include "translate-a64.h"
41 #include "qemu/atomic128.h"
43 static TCGv_i64 cpu_X
[32];
44 static TCGv_i64 cpu_pc
;
46 /* Load/store exclusive handling */
47 static TCGv_i64 cpu_exclusive_high
;
49 static const char *regnames
[] = {
50 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
51 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
52 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
53 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
57 A64_SHIFT_TYPE_LSL
= 0,
58 A64_SHIFT_TYPE_LSR
= 1,
59 A64_SHIFT_TYPE_ASR
= 2,
60 A64_SHIFT_TYPE_ROR
= 3
63 /* Table based decoder typedefs - used when the relevant bits for decode
64 * are too awkwardly scattered across the instruction (eg SIMD).
66 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
68 typedef struct AArch64DecodeTable
{
71 AArch64DecodeFn
*disas_fn
;
74 /* Function prototype for gen_ functions for calling Neon helpers */
75 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
76 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
78 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
80 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
81 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
82 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
83 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
84 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
85 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
86 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
87 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
88 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
89 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
91 /* initialize TCG globals. */
92 void a64_translate_init(void)
96 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
97 offsetof(CPUARMState
, pc
),
99 for (i
= 0; i
< 32; i
++) {
100 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, xregs
[i
]),
105 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
106 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
109 static inline int get_a64_user_mem_index(DisasContext
*s
)
111 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
112 * if EL1, access as if EL0; otherwise access at current EL
116 switch (s
->mmu_idx
) {
117 case ARMMMUIdx_S12NSE1
:
118 useridx
= ARMMMUIdx_S12NSE0
;
120 case ARMMMUIdx_S1SE1
:
121 useridx
= ARMMMUIdx_S1SE0
;
124 g_assert_not_reached();
126 useridx
= s
->mmu_idx
;
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 qemu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 qemu_fprintf(f
, " FPU disabled\n");
200 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 qemu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 qemu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 qemu_fprintf(f
, " [%x]=", j
);
266 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
339 * Return a "clean" address for ADDR according to TBID.
340 * This is always a fresh temporary, as we need to be able to
341 * increment this independently of a dirty write-back address.
343 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
345 TCGv_i64 clean
= new_tmp_a64(s
);
346 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
350 typedef struct DisasCompare64
{
355 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
359 arm_test_cc(&c32
, cc
);
361 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
362 * properly. The NE/EQ comparisons are also fine with this choice. */
363 c64
->cond
= c32
.cond
;
364 c64
->value
= tcg_temp_new_i64();
365 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
370 static void a64_free_cc(DisasCompare64
*c64
)
372 tcg_temp_free_i64(c64
->value
);
375 static void gen_exception_internal(int excp
)
377 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
379 assert(excp_is_internal(excp
));
380 gen_helper_exception_internal(cpu_env
, tcg_excp
);
381 tcg_temp_free_i32(tcg_excp
);
384 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
386 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
387 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
388 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
390 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
392 tcg_temp_free_i32(tcg_el
);
393 tcg_temp_free_i32(tcg_syn
);
394 tcg_temp_free_i32(tcg_excp
);
397 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
399 gen_a64_set_pc_im(s
->pc
- offset
);
400 gen_exception_internal(excp
);
401 s
->base
.is_jmp
= DISAS_NORETURN
;
404 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
405 uint32_t syndrome
, uint32_t target_el
)
407 gen_a64_set_pc_im(s
->pc
- offset
);
408 gen_exception(excp
, syndrome
, target_el
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
417 gen_a64_set_pc_im(s
->pc
- offset
);
418 tcg_syn
= tcg_const_i32(syndrome
);
419 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
420 tcg_temp_free_i32(tcg_syn
);
421 s
->base
.is_jmp
= DISAS_NORETURN
;
424 static void gen_step_complete_exception(DisasContext
*s
)
426 /* We just completed step of an insn. Move from Active-not-pending
427 * to Active-pending, and then also take the swstep exception.
428 * This corresponds to making the (IMPDEF) choice to prioritize
429 * swstep exceptions over asynchronous exceptions taken to an exception
430 * level where debug is disabled. This choice has the advantage that
431 * we do not need to maintain internal state corresponding to the
432 * ISV/EX syndrome bits between completion of the step and generation
433 * of the exception, and our syndrome information is always correct.
436 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
437 default_exception_el(s
));
438 s
->base
.is_jmp
= DISAS_NORETURN
;
441 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
443 /* No direct tb linking with singlestep (either QEMU's or the ARM
444 * debug architecture kind) or deterministic io
446 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
447 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
451 #ifndef CONFIG_USER_ONLY
452 /* Only link tbs from inside the same guest page */
453 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
461 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
463 TranslationBlock
*tb
;
466 if (use_goto_tb(s
, n
, dest
)) {
468 gen_a64_set_pc_im(dest
);
469 tcg_gen_exit_tb(tb
, n
);
470 s
->base
.is_jmp
= DISAS_NORETURN
;
472 gen_a64_set_pc_im(dest
);
474 gen_step_complete_exception(s
);
475 } else if (s
->base
.singlestep_enabled
) {
476 gen_exception_internal(EXCP_DEBUG
);
478 tcg_gen_lookup_and_goto_ptr();
479 s
->base
.is_jmp
= DISAS_NORETURN
;
484 void unallocated_encoding(DisasContext
*s
)
486 /* Unallocated and reserved encodings are uncategorized */
487 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
488 default_exception_el(s
));
491 static void init_tmp_a64_array(DisasContext
*s
)
493 #ifdef CONFIG_DEBUG_TCG
494 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
496 s
->tmp_a64_count
= 0;
499 static void free_tmp_a64(DisasContext
*s
)
502 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
503 tcg_temp_free_i64(s
->tmp_a64
[i
]);
505 init_tmp_a64_array(s
);
508 TCGv_i64
new_tmp_a64(DisasContext
*s
)
510 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
511 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
514 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
516 TCGv_i64 t
= new_tmp_a64(s
);
517 tcg_gen_movi_i64(t
, 0);
522 * Register access functions
524 * These functions are used for directly accessing a register in where
525 * changes to the final register value are likely to be made. If you
526 * need to use a register for temporary calculation (e.g. index type
527 * operations) use the read_* form.
529 * B1.2.1 Register mappings
531 * In instruction register encoding 31 can refer to ZR (zero register) or
532 * the SP (stack pointer) depending on context. In QEMU's case we map SP
533 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
534 * This is the point of the _sp forms.
536 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
539 return new_tmp_a64_zero(s
);
545 /* register access for when 31 == SP */
546 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
551 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
552 * representing the register contents. This TCGv is an auto-freed
553 * temporary so it need not be explicitly freed, and may be modified.
555 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
557 TCGv_i64 v
= new_tmp_a64(s
);
560 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
562 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
565 tcg_gen_movi_i64(v
, 0);
570 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
572 TCGv_i64 v
= new_tmp_a64(s
);
574 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
576 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
581 /* Return the offset into CPUARMState of a slice (from
582 * the least significant end) of FP register Qn (ie
584 * (Note that this is not the same mapping as for A32; see cpu.h)
586 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
588 return vec_reg_offset(s
, regno
, 0, size
);
591 /* Offset of the high half of the 128 bit vector Qn */
592 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
594 return vec_reg_offset(s
, regno
, 1, MO_64
);
597 /* Convenience accessors for reading and writing single and double
598 * FP registers. Writing clears the upper parts of the associated
599 * 128 bit vector register, as required by the architecture.
600 * Note that unlike the GP register accessors, the values returned
601 * by the read functions must be manually freed.
603 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
605 TCGv_i64 v
= tcg_temp_new_i64();
607 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
611 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
619 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
621 TCGv_i32 v
= tcg_temp_new_i32();
623 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
627 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
628 * If SVE is not enabled, then there are only 128 bits in the vector.
630 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
632 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
633 unsigned vsz
= vec_full_reg_size(s
);
636 TCGv_i64 tcg_zero
= tcg_const_i64(0);
637 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
638 tcg_temp_free_i64(tcg_zero
);
641 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
645 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
647 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
649 tcg_gen_st_i64(v
, cpu_env
, ofs
);
650 clear_vec_high(s
, false, reg
);
653 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
655 TCGv_i64 tmp
= tcg_temp_new_i64();
657 tcg_gen_extu_i32_i64(tmp
, v
);
658 write_fp_dreg(s
, reg
, tmp
);
659 tcg_temp_free_i64(tmp
);
662 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
664 TCGv_ptr statusptr
= tcg_temp_new_ptr();
667 /* In A64 all instructions (both FP and Neon) use the FPCR; there
668 * is no equivalent of the A32 Neon "standard FPSCR value".
669 * However half-precision operations operate under a different
670 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
673 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
675 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
677 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
681 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
682 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
683 GVecGen2Fn
*gvec_fn
, int vece
)
685 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
686 is_q
? 16 : 8, vec_full_reg_size(s
));
689 /* Expand a 2-operand + immediate AdvSIMD vector operation using
690 * an expander function.
692 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
693 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
700 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
701 GVecGen3Fn
*gvec_fn
, int vece
)
703 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
704 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
707 /* Expand a 2-operand + immediate AdvSIMD vector operation using
710 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
711 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
713 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
714 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
717 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
718 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
719 int rn
, int rm
, const GVecGen3
*gvec_op
)
721 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
722 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
723 vec_full_reg_size(s
), gvec_op
);
726 /* Expand a 3-operand operation using an out-of-line helper. */
727 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
728 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
730 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
731 vec_full_reg_offset(s
, rn
),
732 vec_full_reg_offset(s
, rm
),
733 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
736 /* Expand a 3-operand + env pointer operation using
737 * an out-of-line helper.
739 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
740 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
742 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
743 vec_full_reg_offset(s
, rn
),
744 vec_full_reg_offset(s
, rm
), cpu_env
,
745 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
748 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
749 * an out-of-line helper.
751 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
752 int rm
, bool is_fp16
, int data
,
753 gen_helper_gvec_3_ptr
*fn
)
755 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
756 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
757 vec_full_reg_offset(s
, rn
),
758 vec_full_reg_offset(s
, rm
), fpst
,
759 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
760 tcg_temp_free_ptr(fpst
);
763 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
764 * than the 32 bit equivalent.
766 static inline void gen_set_NZ64(TCGv_i64 result
)
768 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
769 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
772 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
773 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
776 gen_set_NZ64(result
);
778 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
779 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
781 tcg_gen_movi_i32(cpu_CF
, 0);
782 tcg_gen_movi_i32(cpu_VF
, 0);
785 /* dest = T0 + T1; compute C, N, V and Z flags */
786 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
789 TCGv_i64 result
, flag
, tmp
;
790 result
= tcg_temp_new_i64();
791 flag
= tcg_temp_new_i64();
792 tmp
= tcg_temp_new_i64();
794 tcg_gen_movi_i64(tmp
, 0);
795 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
797 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
799 gen_set_NZ64(result
);
801 tcg_gen_xor_i64(flag
, result
, t0
);
802 tcg_gen_xor_i64(tmp
, t0
, t1
);
803 tcg_gen_andc_i64(flag
, flag
, tmp
);
804 tcg_temp_free_i64(tmp
);
805 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
807 tcg_gen_mov_i64(dest
, result
);
808 tcg_temp_free_i64(result
);
809 tcg_temp_free_i64(flag
);
811 /* 32 bit arithmetic */
812 TCGv_i32 t0_32
= tcg_temp_new_i32();
813 TCGv_i32 t1_32
= tcg_temp_new_i32();
814 TCGv_i32 tmp
= tcg_temp_new_i32();
816 tcg_gen_movi_i32(tmp
, 0);
817 tcg_gen_extrl_i64_i32(t0_32
, t0
);
818 tcg_gen_extrl_i64_i32(t1_32
, t1
);
819 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
820 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
821 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
822 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
823 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
824 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
826 tcg_temp_free_i32(tmp
);
827 tcg_temp_free_i32(t0_32
);
828 tcg_temp_free_i32(t1_32
);
832 /* dest = T0 - T1; compute C, N, V and Z flags */
833 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
836 /* 64 bit arithmetic */
837 TCGv_i64 result
, flag
, tmp
;
839 result
= tcg_temp_new_i64();
840 flag
= tcg_temp_new_i64();
841 tcg_gen_sub_i64(result
, t0
, t1
);
843 gen_set_NZ64(result
);
845 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
846 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
848 tcg_gen_xor_i64(flag
, result
, t0
);
849 tmp
= tcg_temp_new_i64();
850 tcg_gen_xor_i64(tmp
, t0
, t1
);
851 tcg_gen_and_i64(flag
, flag
, tmp
);
852 tcg_temp_free_i64(tmp
);
853 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
854 tcg_gen_mov_i64(dest
, result
);
855 tcg_temp_free_i64(flag
);
856 tcg_temp_free_i64(result
);
858 /* 32 bit arithmetic */
859 TCGv_i32 t0_32
= tcg_temp_new_i32();
860 TCGv_i32 t1_32
= tcg_temp_new_i32();
863 tcg_gen_extrl_i64_i32(t0_32
, t0
);
864 tcg_gen_extrl_i64_i32(t1_32
, t1
);
865 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
866 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
867 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
868 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
869 tmp
= tcg_temp_new_i32();
870 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
871 tcg_temp_free_i32(t0_32
);
872 tcg_temp_free_i32(t1_32
);
873 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
874 tcg_temp_free_i32(tmp
);
875 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
879 /* dest = T0 + T1 + CF; do not compute flags. */
880 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
882 TCGv_i64 flag
= tcg_temp_new_i64();
883 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
884 tcg_gen_add_i64(dest
, t0
, t1
);
885 tcg_gen_add_i64(dest
, dest
, flag
);
886 tcg_temp_free_i64(flag
);
889 tcg_gen_ext32u_i64(dest
, dest
);
893 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
894 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
897 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
898 result
= tcg_temp_new_i64();
899 cf_64
= tcg_temp_new_i64();
900 vf_64
= tcg_temp_new_i64();
901 tmp
= tcg_const_i64(0);
903 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
904 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
905 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
906 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
907 gen_set_NZ64(result
);
909 tcg_gen_xor_i64(vf_64
, result
, t0
);
910 tcg_gen_xor_i64(tmp
, t0
, t1
);
911 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
912 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
914 tcg_gen_mov_i64(dest
, result
);
916 tcg_temp_free_i64(tmp
);
917 tcg_temp_free_i64(vf_64
);
918 tcg_temp_free_i64(cf_64
);
919 tcg_temp_free_i64(result
);
921 TCGv_i32 t0_32
, t1_32
, tmp
;
922 t0_32
= tcg_temp_new_i32();
923 t1_32
= tcg_temp_new_i32();
924 tmp
= tcg_const_i32(0);
926 tcg_gen_extrl_i64_i32(t0_32
, t0
);
927 tcg_gen_extrl_i64_i32(t1_32
, t1
);
928 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
929 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
931 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
932 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
933 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
934 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
935 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
937 tcg_temp_free_i32(tmp
);
938 tcg_temp_free_i32(t1_32
);
939 tcg_temp_free_i32(t0_32
);
944 * Load/Store generators
948 * Store from GPR register to memory.
950 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
951 TCGv_i64 tcg_addr
, int size
, int memidx
,
953 unsigned int iss_srt
,
954 bool iss_sf
, bool iss_ar
)
957 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
962 syn
= syn_data_abort_with_iss(0,
968 0, 0, 0, 0, 0, false);
969 disas_set_insn_syndrome(s
, syn
);
973 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
974 TCGv_i64 tcg_addr
, int size
,
976 unsigned int iss_srt
,
977 bool iss_sf
, bool iss_ar
)
979 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
980 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
984 * Load from memory to GPR register
986 static void do_gpr_ld_memidx(DisasContext
*s
,
987 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
988 int size
, bool is_signed
,
989 bool extend
, int memidx
,
990 bool iss_valid
, unsigned int iss_srt
,
991 bool iss_sf
, bool iss_ar
)
993 TCGMemOp memop
= s
->be_data
+ size
;
1001 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1003 if (extend
&& is_signed
) {
1005 tcg_gen_ext32u_i64(dest
, dest
);
1011 syn
= syn_data_abort_with_iss(0,
1017 0, 0, 0, 0, 0, false);
1018 disas_set_insn_syndrome(s
, syn
);
1022 static void do_gpr_ld(DisasContext
*s
,
1023 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1024 int size
, bool is_signed
, bool extend
,
1025 bool iss_valid
, unsigned int iss_srt
,
1026 bool iss_sf
, bool iss_ar
)
1028 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1030 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1034 * Store from FP register to memory
1036 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1038 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1039 TCGv_i64 tmp
= tcg_temp_new_i64();
1040 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1042 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1045 bool be
= s
->be_data
== MO_BE
;
1046 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1048 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1049 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1051 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1052 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1054 tcg_temp_free_i64(tcg_hiaddr
);
1057 tcg_temp_free_i64(tmp
);
1061 * Load from memory to FP register
1063 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1065 /* This always zero-extends and writes to a full 128 bit wide vector */
1066 TCGv_i64 tmplo
= tcg_temp_new_i64();
1070 TCGMemOp memop
= s
->be_data
+ size
;
1071 tmphi
= tcg_const_i64(0);
1072 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1074 bool be
= s
->be_data
== MO_BE
;
1075 TCGv_i64 tcg_hiaddr
;
1077 tmphi
= tcg_temp_new_i64();
1078 tcg_hiaddr
= tcg_temp_new_i64();
1080 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1081 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1083 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1085 tcg_temp_free_i64(tcg_hiaddr
);
1088 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1089 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1091 tcg_temp_free_i64(tmplo
);
1092 tcg_temp_free_i64(tmphi
);
1094 clear_vec_high(s
, true, destidx
);
1098 * Vector load/store helpers.
1100 * The principal difference between this and a FP load is that we don't
1101 * zero extend as we are filling a partial chunk of the vector register.
1102 * These functions don't support 128 bit loads/stores, which would be
1103 * normal load/store operations.
1105 * The _i32 versions are useful when operating on 32 bit quantities
1106 * (eg for floating point single or using Neon helper functions).
1109 /* Get value of an element within a vector register */
1110 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1111 int element
, TCGMemOp memop
)
1113 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1116 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1119 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1122 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1125 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1128 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1131 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1135 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1138 g_assert_not_reached();
1142 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1143 int element
, TCGMemOp memop
)
1145 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1148 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1151 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1154 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1157 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1161 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1164 g_assert_not_reached();
1168 /* Set value of an element within a vector register */
1169 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1170 int element
, TCGMemOp memop
)
1172 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1175 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1178 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1181 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1184 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1187 g_assert_not_reached();
1191 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1192 int destidx
, int element
, TCGMemOp memop
)
1194 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1197 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1200 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1203 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1206 g_assert_not_reached();
1210 /* Store from vector register to memory */
1211 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1212 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1214 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1216 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1217 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1219 tcg_temp_free_i64(tcg_tmp
);
1222 /* Load from memory to vector register */
1223 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1224 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1226 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1228 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1229 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1231 tcg_temp_free_i64(tcg_tmp
);
1234 /* Check that FP/Neon access is enabled. If it is, return
1235 * true. If not, emit code to generate an appropriate exception,
1236 * and return false; the caller should not emit any code for
1237 * the instruction. Note that this check must happen after all
1238 * unallocated-encoding checks (otherwise the syndrome information
1239 * for the resulting exception will be incorrect).
1241 static inline bool fp_access_check(DisasContext
*s
)
1243 assert(!s
->fp_access_checked
);
1244 s
->fp_access_checked
= true;
1246 if (!s
->fp_excp_el
) {
1250 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1255 /* Check that SVE access is enabled. If it is, return true.
1256 * If not, emit code to generate an appropriate exception and return false.
1258 bool sve_access_check(DisasContext
*s
)
1260 if (s
->sve_excp_el
) {
1261 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1265 return fp_access_check(s
);
1269 * This utility function is for doing register extension with an
1270 * optional shift. You will likely want to pass a temporary for the
1271 * destination register. See DecodeRegExtend() in the ARM ARM.
1273 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1274 int option
, unsigned int shift
)
1276 int extsize
= extract32(option
, 0, 2);
1277 bool is_signed
= extract32(option
, 2, 1);
1282 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1285 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1288 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1291 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1297 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1300 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1303 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1306 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1312 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1316 static inline void gen_check_sp_alignment(DisasContext
*s
)
1318 /* The AArch64 architecture mandates that (if enabled via PSTATE
1319 * or SCTLR bits) there is a check that SP is 16-aligned on every
1320 * SP-relative load or store (with an exception generated if it is not).
1321 * In line with general QEMU practice regarding misaligned accesses,
1322 * we omit these checks for the sake of guest program performance.
1323 * This function is provided as a hook so we can more easily add these
1324 * checks in future (possibly as a "favour catching guest program bugs
1325 * over speed" user selectable option).
1330 * This provides a simple table based table lookup decoder. It is
1331 * intended to be used when the relevant bits for decode are too
1332 * awkwardly placed and switch/if based logic would be confusing and
1333 * deeply nested. Since it's a linear search through the table, tables
1334 * should be kept small.
1336 * It returns the first handler where insn & mask == pattern, or
1337 * NULL if there is no match.
1338 * The table is terminated by an empty mask (i.e. 0)
1340 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1343 const AArch64DecodeTable
*tptr
= table
;
1345 while (tptr
->mask
) {
1346 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1347 return tptr
->disas_fn
;
1355 * The instruction disassembly implemented here matches
1356 * the instruction encoding classifications in chapter C4
1357 * of the ARM Architecture Reference Manual (DDI0487B_a);
1358 * classification names and decode diagrams here should generally
1359 * match up with those in the manual.
1362 /* Unconditional branch (immediate)
1364 * +----+-----------+-------------------------------------+
1365 * | op | 0 0 1 0 1 | imm26 |
1366 * +----+-----------+-------------------------------------+
1368 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1370 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1372 if (insn
& (1U << 31)) {
1373 /* BL Branch with link */
1374 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1377 /* B Branch / BL Branch with link */
1379 gen_goto_tb(s
, 0, addr
);
1382 /* Compare and branch (immediate)
1383 * 31 30 25 24 23 5 4 0
1384 * +----+-------------+----+---------------------+--------+
1385 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1386 * +----+-------------+----+---------------------+--------+
1388 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1390 unsigned int sf
, op
, rt
;
1392 TCGLabel
*label_match
;
1395 sf
= extract32(insn
, 31, 1);
1396 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1397 rt
= extract32(insn
, 0, 5);
1398 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1400 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1401 label_match
= gen_new_label();
1404 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1405 tcg_cmp
, 0, label_match
);
1407 gen_goto_tb(s
, 0, s
->pc
);
1408 gen_set_label(label_match
);
1409 gen_goto_tb(s
, 1, addr
);
1412 /* Test and branch (immediate)
1413 * 31 30 25 24 23 19 18 5 4 0
1414 * +----+-------------+----+-------+-------------+------+
1415 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1416 * +----+-------------+----+-------+-------------+------+
1418 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1420 unsigned int bit_pos
, op
, rt
;
1422 TCGLabel
*label_match
;
1425 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1426 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1427 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1428 rt
= extract32(insn
, 0, 5);
1430 tcg_cmp
= tcg_temp_new_i64();
1431 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1432 label_match
= gen_new_label();
1435 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1436 tcg_cmp
, 0, label_match
);
1437 tcg_temp_free_i64(tcg_cmp
);
1438 gen_goto_tb(s
, 0, s
->pc
);
1439 gen_set_label(label_match
);
1440 gen_goto_tb(s
, 1, addr
);
1443 /* Conditional branch (immediate)
1444 * 31 25 24 23 5 4 3 0
1445 * +---------------+----+---------------------+----+------+
1446 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1447 * +---------------+----+---------------------+----+------+
1449 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1454 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1455 unallocated_encoding(s
);
1458 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1459 cond
= extract32(insn
, 0, 4);
1463 /* genuinely conditional branches */
1464 TCGLabel
*label_match
= gen_new_label();
1465 arm_gen_test_cc(cond
, label_match
);
1466 gen_goto_tb(s
, 0, s
->pc
);
1467 gen_set_label(label_match
);
1468 gen_goto_tb(s
, 1, addr
);
1470 /* 0xe and 0xf are both "always" conditions */
1471 gen_goto_tb(s
, 0, addr
);
1475 /* HINT instruction group, including various allocated HINTs */
1476 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1477 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1479 unsigned int selector
= crm
<< 3 | op2
;
1482 unallocated_encoding(s
);
1487 case 0b00000: /* NOP */
1489 case 0b00011: /* WFI */
1490 s
->base
.is_jmp
= DISAS_WFI
;
1492 case 0b00001: /* YIELD */
1493 /* When running in MTTCG we don't generate jumps to the yield and
1494 * WFE helpers as it won't affect the scheduling of other vCPUs.
1495 * If we wanted to more completely model WFE/SEV so we don't busy
1496 * spin unnecessarily we would need to do something more involved.
1498 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1499 s
->base
.is_jmp
= DISAS_YIELD
;
1502 case 0b00010: /* WFE */
1503 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1504 s
->base
.is_jmp
= DISAS_WFE
;
1507 case 0b00100: /* SEV */
1508 case 0b00101: /* SEVL */
1509 /* we treat all as NOP at least for now */
1511 case 0b00111: /* XPACLRI */
1512 if (s
->pauth_active
) {
1513 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1516 case 0b01000: /* PACIA1716 */
1517 if (s
->pauth_active
) {
1518 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1521 case 0b01010: /* PACIB1716 */
1522 if (s
->pauth_active
) {
1523 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1526 case 0b01100: /* AUTIA1716 */
1527 if (s
->pauth_active
) {
1528 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1531 case 0b01110: /* AUTIB1716 */
1532 if (s
->pauth_active
) {
1533 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1536 case 0b11000: /* PACIAZ */
1537 if (s
->pauth_active
) {
1538 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1539 new_tmp_a64_zero(s
));
1542 case 0b11001: /* PACIASP */
1543 if (s
->pauth_active
) {
1544 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1547 case 0b11010: /* PACIBZ */
1548 if (s
->pauth_active
) {
1549 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1550 new_tmp_a64_zero(s
));
1553 case 0b11011: /* PACIBSP */
1554 if (s
->pauth_active
) {
1555 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1558 case 0b11100: /* AUTIAZ */
1559 if (s
->pauth_active
) {
1560 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1561 new_tmp_a64_zero(s
));
1564 case 0b11101: /* AUTIASP */
1565 if (s
->pauth_active
) {
1566 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1569 case 0b11110: /* AUTIBZ */
1570 if (s
->pauth_active
) {
1571 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1572 new_tmp_a64_zero(s
));
1575 case 0b11111: /* AUTIBSP */
1576 if (s
->pauth_active
) {
1577 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1581 /* default specified as NOP equivalent */
1586 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1588 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1591 /* CLREX, DSB, DMB, ISB */
1592 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1593 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1598 unallocated_encoding(s
);
1609 case 1: /* MBReqTypes_Reads */
1610 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1612 case 2: /* MBReqTypes_Writes */
1613 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1615 default: /* MBReqTypes_All */
1616 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1622 /* We need to break the TB after this insn to execute
1623 * a self-modified code correctly and also to take
1624 * any pending interrupts immediately.
1627 gen_goto_tb(s
, 0, s
->pc
);
1631 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1632 goto do_unallocated
;
1635 * TODO: There is no speculation barrier opcode for TCG;
1636 * MB and end the TB instead.
1638 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1639 gen_goto_tb(s
, 0, s
->pc
);
1644 unallocated_encoding(s
);
1649 static void gen_xaflag(void)
1651 TCGv_i32 z
= tcg_temp_new_i32();
1653 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1662 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1663 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1666 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1667 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1669 /* (!C & Z) << 31 -> -(Z & ~C) */
1670 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1671 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1674 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1676 tcg_temp_free_i32(z
);
1679 static void gen_axflag(void)
1681 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1682 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1684 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1685 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1687 tcg_gen_movi_i32(cpu_NF
, 0);
1688 tcg_gen_movi_i32(cpu_VF
, 0);
1691 /* MSR (immediate) - move immediate to processor state field */
1692 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1693 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1696 int op
= op1
<< 3 | op2
;
1698 /* End the TB by default, chaining is ok. */
1699 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1702 case 0x00: /* CFINV */
1703 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1704 goto do_unallocated
;
1706 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1707 s
->base
.is_jmp
= DISAS_NEXT
;
1710 case 0x01: /* XAFlag */
1711 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1712 goto do_unallocated
;
1715 s
->base
.is_jmp
= DISAS_NEXT
;
1718 case 0x02: /* AXFlag */
1719 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1720 goto do_unallocated
;
1723 s
->base
.is_jmp
= DISAS_NEXT
;
1726 case 0x05: /* SPSel */
1727 if (s
->current_el
== 0) {
1728 goto do_unallocated
;
1730 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1731 gen_helper_msr_i_spsel(cpu_env
, t1
);
1732 tcg_temp_free_i32(t1
);
1735 case 0x1e: /* DAIFSet */
1736 t1
= tcg_const_i32(crm
);
1737 gen_helper_msr_i_daifset(cpu_env
, t1
);
1738 tcg_temp_free_i32(t1
);
1741 case 0x1f: /* DAIFClear */
1742 t1
= tcg_const_i32(crm
);
1743 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1744 tcg_temp_free_i32(t1
);
1745 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1746 s
->base
.is_jmp
= DISAS_UPDATE
;
1751 unallocated_encoding(s
);
1756 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1758 TCGv_i32 tmp
= tcg_temp_new_i32();
1759 TCGv_i32 nzcv
= tcg_temp_new_i32();
1761 /* build bit 31, N */
1762 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1763 /* build bit 30, Z */
1764 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1765 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1766 /* build bit 29, C */
1767 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1768 /* build bit 28, V */
1769 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1770 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1771 /* generate result */
1772 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1774 tcg_temp_free_i32(nzcv
);
1775 tcg_temp_free_i32(tmp
);
1778 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1780 TCGv_i32 nzcv
= tcg_temp_new_i32();
1782 /* take NZCV from R[t] */
1783 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1786 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1788 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1789 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1791 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1792 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1794 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1795 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1796 tcg_temp_free_i32(nzcv
);
1799 /* MRS - move from system register
1800 * MSR (register) - move to system register
1803 * These are all essentially the same insn in 'read' and 'write'
1804 * versions, with varying op0 fields.
1806 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1807 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1808 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1810 const ARMCPRegInfo
*ri
;
1813 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1814 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1815 crn
, crm
, op0
, op1
, op2
));
1818 /* Unknown register; this might be a guest error or a QEMU
1819 * unimplemented feature.
1821 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1822 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1823 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1824 unallocated_encoding(s
);
1828 /* Check access permissions */
1829 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1830 unallocated_encoding(s
);
1835 /* Emit code to perform further access permissions checks at
1836 * runtime; this may result in an exception.
1839 TCGv_i32 tcg_syn
, tcg_isread
;
1842 gen_a64_set_pc_im(s
->pc
- 4);
1843 tmpptr
= tcg_const_ptr(ri
);
1844 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1845 tcg_syn
= tcg_const_i32(syndrome
);
1846 tcg_isread
= tcg_const_i32(isread
);
1847 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1848 tcg_temp_free_ptr(tmpptr
);
1849 tcg_temp_free_i32(tcg_syn
);
1850 tcg_temp_free_i32(tcg_isread
);
1853 /* Handle special cases first */
1854 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1858 tcg_rt
= cpu_reg(s
, rt
);
1860 gen_get_nzcv(tcg_rt
);
1862 gen_set_nzcv(tcg_rt
);
1865 case ARM_CP_CURRENTEL
:
1866 /* Reads as current EL value from pstate, which is
1867 * guaranteed to be constant by the tb flags.
1869 tcg_rt
= cpu_reg(s
, rt
);
1870 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1873 /* Writes clear the aligned block of memory which rt points into. */
1874 tcg_rt
= cpu_reg(s
, rt
);
1875 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1880 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1882 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1886 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1890 tcg_rt
= cpu_reg(s
, rt
);
1893 if (ri
->type
& ARM_CP_CONST
) {
1894 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1895 } else if (ri
->readfn
) {
1897 tmpptr
= tcg_const_ptr(ri
);
1898 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1899 tcg_temp_free_ptr(tmpptr
);
1901 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1904 if (ri
->type
& ARM_CP_CONST
) {
1905 /* If not forbidden by access permissions, treat as WI */
1907 } else if (ri
->writefn
) {
1909 tmpptr
= tcg_const_ptr(ri
);
1910 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1911 tcg_temp_free_ptr(tmpptr
);
1913 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1917 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1918 /* I/O operations must end the TB here (whether read or write) */
1920 s
->base
.is_jmp
= DISAS_UPDATE
;
1921 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1922 /* We default to ending the TB on a coprocessor register write,
1923 * but allow this to be suppressed by the register definition
1924 * (usually only necessary to work around guest bugs).
1926 s
->base
.is_jmp
= DISAS_UPDATE
;
1931 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1932 * +---------------------+---+-----+-----+-------+-------+-----+------+
1933 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1934 * +---------------------+---+-----+-----+-------+-------+-----+------+
1936 static void disas_system(DisasContext
*s
, uint32_t insn
)
1938 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1939 l
= extract32(insn
, 21, 1);
1940 op0
= extract32(insn
, 19, 2);
1941 op1
= extract32(insn
, 16, 3);
1942 crn
= extract32(insn
, 12, 4);
1943 crm
= extract32(insn
, 8, 4);
1944 op2
= extract32(insn
, 5, 3);
1945 rt
= extract32(insn
, 0, 5);
1948 if (l
|| rt
!= 31) {
1949 unallocated_encoding(s
);
1953 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1954 handle_hint(s
, insn
, op1
, op2
, crm
);
1956 case 3: /* CLREX, DSB, DMB, ISB */
1957 handle_sync(s
, insn
, op1
, op2
, crm
);
1959 case 4: /* MSR (immediate) */
1960 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1963 unallocated_encoding(s
);
1968 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1971 /* Exception generation
1973 * 31 24 23 21 20 5 4 2 1 0
1974 * +-----------------+-----+------------------------+-----+----+
1975 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1976 * +-----------------------+------------------------+----------+
1978 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1980 int opc
= extract32(insn
, 21, 3);
1981 int op2_ll
= extract32(insn
, 0, 5);
1982 int imm16
= extract32(insn
, 5, 16);
1987 /* For SVC, HVC and SMC we advance the single-step state
1988 * machine before taking the exception. This is architecturally
1989 * mandated, to ensure that single-stepping a system call
1990 * instruction works properly.
1995 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1996 default_exception_el(s
));
1999 if (s
->current_el
== 0) {
2000 unallocated_encoding(s
);
2003 /* The pre HVC helper handles cases when HVC gets trapped
2004 * as an undefined insn by runtime configuration.
2006 gen_a64_set_pc_im(s
->pc
- 4);
2007 gen_helper_pre_hvc(cpu_env
);
2009 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
2012 if (s
->current_el
== 0) {
2013 unallocated_encoding(s
);
2016 gen_a64_set_pc_im(s
->pc
- 4);
2017 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2018 gen_helper_pre_smc(cpu_env
, tmp
);
2019 tcg_temp_free_i32(tmp
);
2021 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
2024 unallocated_encoding(s
);
2030 unallocated_encoding(s
);
2034 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
2038 unallocated_encoding(s
);
2041 /* HLT. This has two purposes.
2042 * Architecturally, it is an external halting debug instruction.
2043 * Since QEMU doesn't implement external debug, we treat this as
2044 * it is required for halting debug disabled: it will UNDEF.
2045 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2047 if (semihosting_enabled() && imm16
== 0xf000) {
2048 #ifndef CONFIG_USER_ONLY
2049 /* In system mode, don't allow userspace access to semihosting,
2050 * to provide some semblance of security (and for consistency
2051 * with our 32-bit semihosting).
2053 if (s
->current_el
== 0) {
2054 unsupported_encoding(s
, insn
);
2058 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
2060 unsupported_encoding(s
, insn
);
2064 if (op2_ll
< 1 || op2_ll
> 3) {
2065 unallocated_encoding(s
);
2068 /* DCPS1, DCPS2, DCPS3 */
2069 unsupported_encoding(s
, insn
);
2072 unallocated_encoding(s
);
2077 /* Unconditional branch (register)
2078 * 31 25 24 21 20 16 15 10 9 5 4 0
2079 * +---------------+-------+-------+-------+------+-------+
2080 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2081 * +---------------+-------+-------+-------+------+-------+
2083 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2085 unsigned int opc
, op2
, op3
, rn
, op4
;
2086 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2090 opc
= extract32(insn
, 21, 4);
2091 op2
= extract32(insn
, 16, 5);
2092 op3
= extract32(insn
, 10, 6);
2093 rn
= extract32(insn
, 5, 5);
2094 op4
= extract32(insn
, 0, 5);
2097 goto do_unallocated
;
2109 goto do_unallocated
;
2111 dst
= cpu_reg(s
, rn
);
2116 if (!dc_isar_feature(aa64_pauth
, s
)) {
2117 goto do_unallocated
;
2121 if (rn
!= 0x1f || op4
!= 0x1f) {
2122 goto do_unallocated
;
2125 modifier
= cpu_X
[31];
2127 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2129 goto do_unallocated
;
2131 modifier
= new_tmp_a64_zero(s
);
2133 if (s
->pauth_active
) {
2134 dst
= new_tmp_a64(s
);
2136 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2138 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2141 dst
= cpu_reg(s
, rn
);
2146 goto do_unallocated
;
2148 gen_a64_set_pc(s
, dst
);
2149 /* BLR also needs to load return address */
2151 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2157 if (!dc_isar_feature(aa64_pauth
, s
)) {
2158 goto do_unallocated
;
2160 if ((op3
& ~1) != 2) {
2161 goto do_unallocated
;
2163 btype_mod
= opc
& 1;
2164 if (s
->pauth_active
) {
2165 dst
= new_tmp_a64(s
);
2166 modifier
= cpu_reg_sp(s
, op4
);
2168 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2170 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2173 dst
= cpu_reg(s
, rn
);
2175 gen_a64_set_pc(s
, dst
);
2176 /* BLRAA also needs to load return address */
2178 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2183 if (s
->current_el
== 0) {
2184 goto do_unallocated
;
2189 goto do_unallocated
;
2191 dst
= tcg_temp_new_i64();
2192 tcg_gen_ld_i64(dst
, cpu_env
,
2193 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2196 case 2: /* ERETAA */
2197 case 3: /* ERETAB */
2198 if (!dc_isar_feature(aa64_pauth
, s
)) {
2199 goto do_unallocated
;
2201 if (rn
!= 0x1f || op4
!= 0x1f) {
2202 goto do_unallocated
;
2204 dst
= tcg_temp_new_i64();
2205 tcg_gen_ld_i64(dst
, cpu_env
,
2206 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2207 if (s
->pauth_active
) {
2208 modifier
= cpu_X
[31];
2210 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2212 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2218 goto do_unallocated
;
2220 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2224 gen_helper_exception_return(cpu_env
, dst
);
2225 tcg_temp_free_i64(dst
);
2226 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2229 /* Must exit loop to check un-masked IRQs */
2230 s
->base
.is_jmp
= DISAS_EXIT
;
2234 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2235 goto do_unallocated
;
2237 unsupported_encoding(s
, insn
);
2243 unallocated_encoding(s
);
2247 switch (btype_mod
) {
2249 if (dc_isar_feature(aa64_bti
, s
)) {
2250 /* BR to {x16,x17} or !guard -> 1, else 3. */
2251 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2256 if (dc_isar_feature(aa64_bti
, s
)) {
2257 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2262 default: /* RET or none of the above. */
2263 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2267 s
->base
.is_jmp
= DISAS_JUMP
;
2270 /* Branches, exception generating and system instructions */
2271 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2273 switch (extract32(insn
, 25, 7)) {
2274 case 0x0a: case 0x0b:
2275 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2276 disas_uncond_b_imm(s
, insn
);
2278 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2279 disas_comp_b_imm(s
, insn
);
2281 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2282 disas_test_b_imm(s
, insn
);
2284 case 0x2a: /* Conditional branch (immediate) */
2285 disas_cond_b_imm(s
, insn
);
2287 case 0x6a: /* Exception generation / System */
2288 if (insn
& (1 << 24)) {
2289 if (extract32(insn
, 22, 2) == 0) {
2290 disas_system(s
, insn
);
2292 unallocated_encoding(s
);
2298 case 0x6b: /* Unconditional branch (register) */
2299 disas_uncond_b_reg(s
, insn
);
2302 unallocated_encoding(s
);
2308 * Load/Store exclusive instructions are implemented by remembering
2309 * the value/address loaded, and seeing if these are the same
2310 * when the store is performed. This is not actually the architecturally
2311 * mandated semantics, but it works for typical guest code sequences
2312 * and avoids having to monitor regular stores.
2314 * The store exclusive uses the atomic cmpxchg primitives to avoid
2315 * races in multi-threaded linux-user and when MTTCG softmmu is
2318 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2319 TCGv_i64 addr
, int size
, bool is_pair
)
2321 int idx
= get_mem_index(s
);
2322 TCGMemOp memop
= s
->be_data
;
2324 g_assert(size
<= 3);
2326 g_assert(size
>= 2);
2328 /* The pair must be single-copy atomic for the doubleword. */
2329 memop
|= MO_64
| MO_ALIGN
;
2330 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2331 if (s
->be_data
== MO_LE
) {
2332 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2333 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2335 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2336 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2339 /* The pair must be single-copy atomic for *each* doubleword, not
2340 the entire quadword, however it must be quadword aligned. */
2342 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2343 memop
| MO_ALIGN_16
);
2345 TCGv_i64 addr2
= tcg_temp_new_i64();
2346 tcg_gen_addi_i64(addr2
, addr
, 8);
2347 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2348 tcg_temp_free_i64(addr2
);
2350 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2351 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2354 memop
|= size
| MO_ALIGN
;
2355 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2356 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2358 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2361 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2362 TCGv_i64 addr
, int size
, int is_pair
)
2364 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2365 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2368 * [addr + datasize] = {Rt2};
2374 * env->exclusive_addr = -1;
2376 TCGLabel
*fail_label
= gen_new_label();
2377 TCGLabel
*done_label
= gen_new_label();
2380 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2382 tmp
= tcg_temp_new_i64();
2385 if (s
->be_data
== MO_LE
) {
2386 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2388 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2390 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2391 cpu_exclusive_val
, tmp
,
2393 MO_64
| MO_ALIGN
| s
->be_data
);
2394 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2395 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2396 if (!HAVE_CMPXCHG128
) {
2397 gen_helper_exit_atomic(cpu_env
);
2398 s
->base
.is_jmp
= DISAS_NORETURN
;
2399 } else if (s
->be_data
== MO_LE
) {
2400 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2405 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2410 } else if (s
->be_data
== MO_LE
) {
2411 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2412 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2414 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2415 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2418 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2419 cpu_reg(s
, rt
), get_mem_index(s
),
2420 size
| MO_ALIGN
| s
->be_data
);
2421 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2423 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2424 tcg_temp_free_i64(tmp
);
2425 tcg_gen_br(done_label
);
2427 gen_set_label(fail_label
);
2428 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2429 gen_set_label(done_label
);
2430 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2433 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2436 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2437 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2438 int memidx
= get_mem_index(s
);
2439 TCGv_i64 clean_addr
;
2442 gen_check_sp_alignment(s
);
2444 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2445 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2446 size
| MO_ALIGN
| s
->be_data
);
2449 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2452 TCGv_i64 s1
= cpu_reg(s
, rs
);
2453 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2454 TCGv_i64 t1
= cpu_reg(s
, rt
);
2455 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2456 TCGv_i64 clean_addr
;
2457 int memidx
= get_mem_index(s
);
2460 gen_check_sp_alignment(s
);
2462 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2465 TCGv_i64 cmp
= tcg_temp_new_i64();
2466 TCGv_i64 val
= tcg_temp_new_i64();
2468 if (s
->be_data
== MO_LE
) {
2469 tcg_gen_concat32_i64(val
, t1
, t2
);
2470 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2472 tcg_gen_concat32_i64(val
, t2
, t1
);
2473 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2476 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2477 MO_64
| MO_ALIGN
| s
->be_data
);
2478 tcg_temp_free_i64(val
);
2480 if (s
->be_data
== MO_LE
) {
2481 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2483 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2485 tcg_temp_free_i64(cmp
);
2486 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2487 if (HAVE_CMPXCHG128
) {
2488 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2489 if (s
->be_data
== MO_LE
) {
2490 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2491 clean_addr
, t1
, t2
);
2493 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2494 clean_addr
, t1
, t2
);
2496 tcg_temp_free_i32(tcg_rs
);
2498 gen_helper_exit_atomic(cpu_env
);
2499 s
->base
.is_jmp
= DISAS_NORETURN
;
2502 TCGv_i64 d1
= tcg_temp_new_i64();
2503 TCGv_i64 d2
= tcg_temp_new_i64();
2504 TCGv_i64 a2
= tcg_temp_new_i64();
2505 TCGv_i64 c1
= tcg_temp_new_i64();
2506 TCGv_i64 c2
= tcg_temp_new_i64();
2507 TCGv_i64 zero
= tcg_const_i64(0);
2509 /* Load the two words, in memory order. */
2510 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2511 MO_64
| MO_ALIGN_16
| s
->be_data
);
2512 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2513 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2515 /* Compare the two words, also in memory order. */
2516 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2517 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2518 tcg_gen_and_i64(c2
, c2
, c1
);
2520 /* If compare equal, write back new data, else write back old data. */
2521 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2522 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2523 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2524 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2525 tcg_temp_free_i64(a2
);
2526 tcg_temp_free_i64(c1
);
2527 tcg_temp_free_i64(c2
);
2528 tcg_temp_free_i64(zero
);
2530 /* Write back the data from memory to Rs. */
2531 tcg_gen_mov_i64(s1
, d1
);
2532 tcg_gen_mov_i64(s2
, d2
);
2533 tcg_temp_free_i64(d1
);
2534 tcg_temp_free_i64(d2
);
2538 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2539 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2541 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2543 int opc0
= extract32(opc
, 0, 1);
2547 regsize
= opc0
? 32 : 64;
2549 regsize
= size
== 3 ? 64 : 32;
2551 return regsize
== 64;
2554 /* Load/store exclusive
2556 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2557 * +-----+-------------+----+---+----+------+----+-------+------+------+
2558 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2559 * +-----+-------------+----+---+----+------+----+-------+------+------+
2561 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2562 * L: 0 -> store, 1 -> load
2563 * o2: 0 -> exclusive, 1 -> not
2564 * o1: 0 -> single register, 1 -> register pair
2565 * o0: 1 -> load-acquire/store-release, 0 -> not
2567 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2569 int rt
= extract32(insn
, 0, 5);
2570 int rn
= extract32(insn
, 5, 5);
2571 int rt2
= extract32(insn
, 10, 5);
2572 int rs
= extract32(insn
, 16, 5);
2573 int is_lasr
= extract32(insn
, 15, 1);
2574 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2575 int size
= extract32(insn
, 30, 2);
2576 TCGv_i64 clean_addr
;
2578 switch (o2_L_o1_o0
) {
2579 case 0x0: /* STXR */
2580 case 0x1: /* STLXR */
2582 gen_check_sp_alignment(s
);
2585 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2587 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2588 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2591 case 0x4: /* LDXR */
2592 case 0x5: /* LDAXR */
2594 gen_check_sp_alignment(s
);
2596 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2598 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2600 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2604 case 0x8: /* STLLR */
2605 if (!dc_isar_feature(aa64_lor
, s
)) {
2608 /* StoreLORelease is the same as Store-Release for QEMU. */
2610 case 0x9: /* STLR */
2611 /* Generate ISS for non-exclusive accesses including LASR. */
2613 gen_check_sp_alignment(s
);
2615 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2616 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2617 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2618 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2621 case 0xc: /* LDLAR */
2622 if (!dc_isar_feature(aa64_lor
, s
)) {
2625 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2627 case 0xd: /* LDAR */
2628 /* Generate ISS for non-exclusive accesses including LASR. */
2630 gen_check_sp_alignment(s
);
2632 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2633 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2634 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2635 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2638 case 0x2: case 0x3: /* CASP / STXP */
2639 if (size
& 2) { /* STXP / STLXP */
2641 gen_check_sp_alignment(s
);
2644 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2646 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2647 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2651 && ((rt
| rs
) & 1) == 0
2652 && dc_isar_feature(aa64_atomics
, s
)) {
2654 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2659 case 0x6: case 0x7: /* CASPA / LDXP */
2660 if (size
& 2) { /* LDXP / LDAXP */
2662 gen_check_sp_alignment(s
);
2664 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2666 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2668 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2673 && ((rt
| rs
) & 1) == 0
2674 && dc_isar_feature(aa64_atomics
, s
)) {
2675 /* CASPA / CASPAL */
2676 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2682 case 0xb: /* CASL */
2683 case 0xe: /* CASA */
2684 case 0xf: /* CASAL */
2685 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2686 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2691 unallocated_encoding(s
);
2695 * Load register (literal)
2697 * 31 30 29 27 26 25 24 23 5 4 0
2698 * +-----+-------+---+-----+-------------------+-------+
2699 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2700 * +-----+-------+---+-----+-------------------+-------+
2702 * V: 1 -> vector (simd/fp)
2703 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2704 * 10-> 32 bit signed, 11 -> prefetch
2705 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2707 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2709 int rt
= extract32(insn
, 0, 5);
2710 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2711 bool is_vector
= extract32(insn
, 26, 1);
2712 int opc
= extract32(insn
, 30, 2);
2713 bool is_signed
= false;
2715 TCGv_i64 tcg_rt
, clean_addr
;
2719 unallocated_encoding(s
);
2723 if (!fp_access_check(s
)) {
2728 /* PRFM (literal) : prefetch */
2731 size
= 2 + extract32(opc
, 0, 1);
2732 is_signed
= extract32(opc
, 1, 1);
2735 tcg_rt
= cpu_reg(s
, rt
);
2737 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2739 do_fp_ld(s
, rt
, clean_addr
, size
);
2741 /* Only unsigned 32bit loads target 32bit registers. */
2742 bool iss_sf
= opc
!= 0;
2744 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2745 true, rt
, iss_sf
, false);
2747 tcg_temp_free_i64(clean_addr
);
2751 * LDNP (Load Pair - non-temporal hint)
2752 * LDP (Load Pair - non vector)
2753 * LDPSW (Load Pair Signed Word - non vector)
2754 * STNP (Store Pair - non-temporal hint)
2755 * STP (Store Pair - non vector)
2756 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2757 * LDP (Load Pair of SIMD&FP)
2758 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2759 * STP (Store Pair of SIMD&FP)
2761 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2762 * +-----+-------+---+---+-------+---+-----------------------------+
2763 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2764 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2766 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2768 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2769 * V: 0 -> GPR, 1 -> Vector
2770 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2771 * 10 -> signed offset, 11 -> pre-index
2772 * L: 0 -> Store 1 -> Load
2774 * Rt, Rt2 = GPR or SIMD registers to be stored
2775 * Rn = general purpose register containing address
2776 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2778 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2780 int rt
= extract32(insn
, 0, 5);
2781 int rn
= extract32(insn
, 5, 5);
2782 int rt2
= extract32(insn
, 10, 5);
2783 uint64_t offset
= sextract64(insn
, 15, 7);
2784 int index
= extract32(insn
, 23, 2);
2785 bool is_vector
= extract32(insn
, 26, 1);
2786 bool is_load
= extract32(insn
, 22, 1);
2787 int opc
= extract32(insn
, 30, 2);
2789 bool is_signed
= false;
2790 bool postindex
= false;
2793 TCGv_i64 clean_addr
, dirty_addr
;
2798 unallocated_encoding(s
);
2805 size
= 2 + extract32(opc
, 1, 1);
2806 is_signed
= extract32(opc
, 0, 1);
2807 if (!is_load
&& is_signed
) {
2808 unallocated_encoding(s
);
2814 case 1: /* post-index */
2819 /* signed offset with "non-temporal" hint. Since we don't emulate
2820 * caches we don't care about hints to the cache system about
2821 * data access patterns, and handle this identically to plain
2825 /* There is no non-temporal-hint version of LDPSW */
2826 unallocated_encoding(s
);
2831 case 2: /* signed offset, rn not updated */
2834 case 3: /* pre-index */
2840 if (is_vector
&& !fp_access_check(s
)) {
2847 gen_check_sp_alignment(s
);
2850 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2852 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2854 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2858 do_fp_ld(s
, rt
, clean_addr
, size
);
2860 do_fp_st(s
, rt
, clean_addr
, size
);
2862 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2864 do_fp_ld(s
, rt2
, clean_addr
, size
);
2866 do_fp_st(s
, rt2
, clean_addr
, size
);
2869 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2870 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2873 TCGv_i64 tmp
= tcg_temp_new_i64();
2875 /* Do not modify tcg_rt before recognizing any exception
2876 * from the second load.
2878 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2879 false, 0, false, false);
2880 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2881 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2882 false, 0, false, false);
2884 tcg_gen_mov_i64(tcg_rt
, tmp
);
2885 tcg_temp_free_i64(tmp
);
2887 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2888 false, 0, false, false);
2889 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2890 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2891 false, 0, false, false);
2897 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2899 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2904 * Load/store (immediate post-indexed)
2905 * Load/store (immediate pre-indexed)
2906 * Load/store (unscaled immediate)
2908 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2909 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2910 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2911 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2913 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2915 * V = 0 -> non-vector
2916 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2917 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2919 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2925 int rn
= extract32(insn
, 5, 5);
2926 int imm9
= sextract32(insn
, 12, 9);
2927 int idx
= extract32(insn
, 10, 2);
2928 bool is_signed
= false;
2929 bool is_store
= false;
2930 bool is_extended
= false;
2931 bool is_unpriv
= (idx
== 2);
2932 bool iss_valid
= !is_vector
;
2936 TCGv_i64 clean_addr
, dirty_addr
;
2939 size
|= (opc
& 2) << 1;
2940 if (size
> 4 || is_unpriv
) {
2941 unallocated_encoding(s
);
2944 is_store
= ((opc
& 1) == 0);
2945 if (!fp_access_check(s
)) {
2949 if (size
== 3 && opc
== 2) {
2950 /* PRFM - prefetch */
2952 unallocated_encoding(s
);
2957 if (opc
== 3 && size
> 1) {
2958 unallocated_encoding(s
);
2961 is_store
= (opc
== 0);
2962 is_signed
= extract32(opc
, 1, 1);
2963 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2981 g_assert_not_reached();
2985 gen_check_sp_alignment(s
);
2988 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2990 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2992 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2996 do_fp_st(s
, rt
, clean_addr
, size
);
2998 do_fp_ld(s
, rt
, clean_addr
, size
);
3001 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3002 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3003 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3006 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3007 iss_valid
, rt
, iss_sf
, false);
3009 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3010 is_signed
, is_extended
, memidx
,
3011 iss_valid
, rt
, iss_sf
, false);
3016 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3018 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3020 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3025 * Load/store (register offset)
3027 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3028 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3029 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3030 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3033 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3034 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3036 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3037 * opc<0>: 0 -> store, 1 -> load
3038 * V: 1 -> vector/simd
3039 * opt: extend encoding (see DecodeRegExtend)
3040 * S: if S=1 then scale (essentially index by sizeof(size))
3041 * Rt: register to transfer into/out of
3042 * Rn: address register or SP for base
3043 * Rm: offset register or ZR for offset
3045 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3051 int rn
= extract32(insn
, 5, 5);
3052 int shift
= extract32(insn
, 12, 1);
3053 int rm
= extract32(insn
, 16, 5);
3054 int opt
= extract32(insn
, 13, 3);
3055 bool is_signed
= false;
3056 bool is_store
= false;
3057 bool is_extended
= false;
3059 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3061 if (extract32(opt
, 1, 1) == 0) {
3062 unallocated_encoding(s
);
3067 size
|= (opc
& 2) << 1;
3069 unallocated_encoding(s
);
3072 is_store
= !extract32(opc
, 0, 1);
3073 if (!fp_access_check(s
)) {
3077 if (size
== 3 && opc
== 2) {
3078 /* PRFM - prefetch */
3081 if (opc
== 3 && size
> 1) {
3082 unallocated_encoding(s
);
3085 is_store
= (opc
== 0);
3086 is_signed
= extract32(opc
, 1, 1);
3087 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3091 gen_check_sp_alignment(s
);
3093 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3095 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3096 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3098 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3099 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3103 do_fp_st(s
, rt
, clean_addr
, size
);
3105 do_fp_ld(s
, rt
, clean_addr
, size
);
3108 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3109 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3111 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3112 true, rt
, iss_sf
, false);
3114 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3115 is_signed
, is_extended
,
3116 true, rt
, iss_sf
, false);
3122 * Load/store (unsigned immediate)
3124 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3125 * +----+-------+---+-----+-----+------------+-------+------+
3126 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3127 * +----+-------+---+-----+-----+------------+-------+------+
3130 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3131 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3133 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3134 * opc<0>: 0 -> store, 1 -> load
3135 * Rn: base address register (inc SP)
3136 * Rt: target register
3138 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3144 int rn
= extract32(insn
, 5, 5);
3145 unsigned int imm12
= extract32(insn
, 10, 12);
3146 unsigned int offset
;
3148 TCGv_i64 clean_addr
, dirty_addr
;
3151 bool is_signed
= false;
3152 bool is_extended
= false;
3155 size
|= (opc
& 2) << 1;
3157 unallocated_encoding(s
);
3160 is_store
= !extract32(opc
, 0, 1);
3161 if (!fp_access_check(s
)) {
3165 if (size
== 3 && opc
== 2) {
3166 /* PRFM - prefetch */
3169 if (opc
== 3 && size
> 1) {
3170 unallocated_encoding(s
);
3173 is_store
= (opc
== 0);
3174 is_signed
= extract32(opc
, 1, 1);
3175 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3179 gen_check_sp_alignment(s
);
3181 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3182 offset
= imm12
<< size
;
3183 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3184 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3188 do_fp_st(s
, rt
, clean_addr
, size
);
3190 do_fp_ld(s
, rt
, clean_addr
, size
);
3193 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3194 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3196 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3197 true, rt
, iss_sf
, false);
3199 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3200 true, rt
, iss_sf
, false);
3205 /* Atomic memory operations
3207 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3208 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3209 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3210 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3212 * Rt: the result register
3213 * Rn: base address or SP
3214 * Rs: the source register for the operation
3215 * V: vector flag (always 0 as of v8.3)
3219 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3220 int size
, int rt
, bool is_vector
)
3222 int rs
= extract32(insn
, 16, 5);
3223 int rn
= extract32(insn
, 5, 5);
3224 int o3_opc
= extract32(insn
, 12, 4);
3225 TCGv_i64 tcg_rs
, clean_addr
;
3226 AtomicThreeOpFn
*fn
;
3228 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3229 unallocated_encoding(s
);
3233 case 000: /* LDADD */
3234 fn
= tcg_gen_atomic_fetch_add_i64
;
3236 case 001: /* LDCLR */
3237 fn
= tcg_gen_atomic_fetch_and_i64
;
3239 case 002: /* LDEOR */
3240 fn
= tcg_gen_atomic_fetch_xor_i64
;
3242 case 003: /* LDSET */
3243 fn
= tcg_gen_atomic_fetch_or_i64
;
3245 case 004: /* LDSMAX */
3246 fn
= tcg_gen_atomic_fetch_smax_i64
;
3248 case 005: /* LDSMIN */
3249 fn
= tcg_gen_atomic_fetch_smin_i64
;
3251 case 006: /* LDUMAX */
3252 fn
= tcg_gen_atomic_fetch_umax_i64
;
3254 case 007: /* LDUMIN */
3255 fn
= tcg_gen_atomic_fetch_umin_i64
;
3258 fn
= tcg_gen_atomic_xchg_i64
;
3261 unallocated_encoding(s
);
3266 gen_check_sp_alignment(s
);
3268 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3269 tcg_rs
= read_cpu_reg(s
, rs
, true);
3271 if (o3_opc
== 1) { /* LDCLR */
3272 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3275 /* The tcg atomic primitives are all full barriers. Therefore we
3276 * can ignore the Acquire and Release bits of this instruction.
3278 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3279 s
->be_data
| size
| MO_ALIGN
);
3283 * PAC memory operations
3285 * 31 30 27 26 24 22 21 12 11 10 5 0
3286 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3287 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3288 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3290 * Rt: the result register
3291 * Rn: base address or SP
3292 * V: vector flag (always 0 as of v8.3)
3293 * M: clear for key DA, set for key DB
3294 * W: pre-indexing flag
3297 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3298 int size
, int rt
, bool is_vector
)
3300 int rn
= extract32(insn
, 5, 5);
3301 bool is_wback
= extract32(insn
, 11, 1);
3302 bool use_key_a
= !extract32(insn
, 23, 1);
3304 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3306 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3307 unallocated_encoding(s
);
3312 gen_check_sp_alignment(s
);
3314 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3316 if (s
->pauth_active
) {
3318 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3320 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3324 /* Form the 10-bit signed, scaled offset. */
3325 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3326 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3327 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3329 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3330 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3332 tcg_rt
= cpu_reg(s
, rt
);
3333 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3334 /* extend */ false, /* iss_valid */ !is_wback
,
3335 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3338 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3342 /* Load/store register (all forms) */
3343 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3345 int rt
= extract32(insn
, 0, 5);
3346 int opc
= extract32(insn
, 22, 2);
3347 bool is_vector
= extract32(insn
, 26, 1);
3348 int size
= extract32(insn
, 30, 2);
3350 switch (extract32(insn
, 24, 2)) {
3352 if (extract32(insn
, 21, 1) == 0) {
3353 /* Load/store register (unscaled immediate)
3354 * Load/store immediate pre/post-indexed
3355 * Load/store register unprivileged
3357 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3360 switch (extract32(insn
, 10, 2)) {
3362 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3365 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3368 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3373 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3376 unallocated_encoding(s
);
3379 /* AdvSIMD load/store multiple structures
3381 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3382 * +---+---+---------------+---+-------------+--------+------+------+------+
3383 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3384 * +---+---+---------------+---+-------------+--------+------+------+------+
3386 * AdvSIMD load/store multiple structures (post-indexed)
3388 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3389 * +---+---+---------------+---+---+---------+--------+------+------+------+
3390 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3391 * +---+---+---------------+---+---+---------+--------+------+------+------+
3393 * Rt: first (or only) SIMD&FP register to be transferred
3394 * Rn: base address or SP
3395 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3397 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3399 int rt
= extract32(insn
, 0, 5);
3400 int rn
= extract32(insn
, 5, 5);
3401 int rm
= extract32(insn
, 16, 5);
3402 int size
= extract32(insn
, 10, 2);
3403 int opcode
= extract32(insn
, 12, 4);
3404 bool is_store
= !extract32(insn
, 22, 1);
3405 bool is_postidx
= extract32(insn
, 23, 1);
3406 bool is_q
= extract32(insn
, 30, 1);
3407 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3408 TCGMemOp endian
= s
->be_data
;
3410 int ebytes
; /* bytes per element */
3411 int elements
; /* elements per vector */
3412 int rpt
; /* num iterations */
3413 int selem
; /* structure elements */
3416 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3417 unallocated_encoding(s
);
3421 if (!is_postidx
&& rm
!= 0) {
3422 unallocated_encoding(s
);
3426 /* From the shared decode logic */
3457 unallocated_encoding(s
);
3461 if (size
== 3 && !is_q
&& selem
!= 1) {
3463 unallocated_encoding(s
);
3467 if (!fp_access_check(s
)) {
3472 gen_check_sp_alignment(s
);
3475 /* For our purposes, bytes are always little-endian. */
3480 /* Consecutive little-endian elements from a single register
3481 * can be promoted to a larger little-endian operation.
3483 if (selem
== 1 && endian
== MO_LE
) {
3487 elements
= (is_q
? 16 : 8) / ebytes
;
3489 tcg_rn
= cpu_reg_sp(s
, rn
);
3490 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3491 tcg_ebytes
= tcg_const_i64(ebytes
);
3493 for (r
= 0; r
< rpt
; r
++) {
3495 for (e
= 0; e
< elements
; e
++) {
3497 for (xs
= 0; xs
< selem
; xs
++) {
3498 int tt
= (rt
+ r
+ xs
) % 32;
3500 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3502 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3504 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3508 tcg_temp_free_i64(tcg_ebytes
);
3511 /* For non-quad operations, setting a slice of the low
3512 * 64 bits of the register clears the high 64 bits (in
3513 * the ARM ARM pseudocode this is implicit in the fact
3514 * that 'rval' is a 64 bit wide variable).
3515 * For quad operations, we might still need to zero the
3518 for (r
= 0; r
< rpt
* selem
; r
++) {
3519 int tt
= (rt
+ r
) % 32;
3520 clear_vec_high(s
, is_q
, tt
);
3526 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3528 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3533 /* AdvSIMD load/store single structure
3535 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3536 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3537 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3538 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3540 * AdvSIMD load/store single structure (post-indexed)
3542 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3543 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3544 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3545 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3547 * Rt: first (or only) SIMD&FP register to be transferred
3548 * Rn: base address or SP
3549 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3550 * index = encoded in Q:S:size dependent on size
3552 * lane_size = encoded in R, opc
3553 * transfer width = encoded in opc, S, size
3555 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3557 int rt
= extract32(insn
, 0, 5);
3558 int rn
= extract32(insn
, 5, 5);
3559 int rm
= extract32(insn
, 16, 5);
3560 int size
= extract32(insn
, 10, 2);
3561 int S
= extract32(insn
, 12, 1);
3562 int opc
= extract32(insn
, 13, 3);
3563 int R
= extract32(insn
, 21, 1);
3564 int is_load
= extract32(insn
, 22, 1);
3565 int is_postidx
= extract32(insn
, 23, 1);
3566 int is_q
= extract32(insn
, 30, 1);
3568 int scale
= extract32(opc
, 1, 2);
3569 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3570 bool replicate
= false;
3571 int index
= is_q
<< 3 | S
<< 2 | size
;
3573 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3575 if (extract32(insn
, 31, 1)) {
3576 unallocated_encoding(s
);
3579 if (!is_postidx
&& rm
!= 0) {
3580 unallocated_encoding(s
);
3586 if (!is_load
|| S
) {
3587 unallocated_encoding(s
);
3596 if (extract32(size
, 0, 1)) {
3597 unallocated_encoding(s
);
3603 if (extract32(size
, 1, 1)) {
3604 unallocated_encoding(s
);
3607 if (!extract32(size
, 0, 1)) {
3611 unallocated_encoding(s
);
3619 g_assert_not_reached();
3622 if (!fp_access_check(s
)) {
3626 ebytes
= 1 << scale
;
3629 gen_check_sp_alignment(s
);
3632 tcg_rn
= cpu_reg_sp(s
, rn
);
3633 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3634 tcg_ebytes
= tcg_const_i64(ebytes
);
3636 for (xs
= 0; xs
< selem
; xs
++) {
3638 /* Load and replicate to all elements */
3639 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3641 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3642 get_mem_index(s
), s
->be_data
+ scale
);
3643 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3644 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3646 tcg_temp_free_i64(tcg_tmp
);
3648 /* Load/store one element per register */
3650 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3652 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3655 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3658 tcg_temp_free_i64(tcg_ebytes
);
3662 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3664 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3669 /* Loads and stores */
3670 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3672 switch (extract32(insn
, 24, 6)) {
3673 case 0x08: /* Load/store exclusive */
3674 disas_ldst_excl(s
, insn
);
3676 case 0x18: case 0x1c: /* Load register (literal) */
3677 disas_ld_lit(s
, insn
);
3679 case 0x28: case 0x29:
3680 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3681 disas_ldst_pair(s
, insn
);
3683 case 0x38: case 0x39:
3684 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3685 disas_ldst_reg(s
, insn
);
3687 case 0x0c: /* AdvSIMD load/store multiple structures */
3688 disas_ldst_multiple_struct(s
, insn
);
3690 case 0x0d: /* AdvSIMD load/store single structure */
3691 disas_ldst_single_struct(s
, insn
);
3694 unallocated_encoding(s
);
3699 /* PC-rel. addressing
3700 * 31 30 29 28 24 23 5 4 0
3701 * +----+-------+-----------+-------------------+------+
3702 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3703 * +----+-------+-----------+-------------------+------+
3705 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3707 unsigned int page
, rd
;
3711 page
= extract32(insn
, 31, 1);
3712 /* SignExtend(immhi:immlo) -> offset */
3713 offset
= sextract64(insn
, 5, 19);
3714 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3715 rd
= extract32(insn
, 0, 5);
3719 /* ADRP (page based) */
3724 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3728 * Add/subtract (immediate)
3730 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3731 * +--+--+--+-----------+-----+-------------+-----+-----+
3732 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3733 * +--+--+--+-----------+-----+-------------+-----+-----+
3735 * sf: 0 -> 32bit, 1 -> 64bit
3736 * op: 0 -> add , 1 -> sub
3738 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3740 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3742 int rd
= extract32(insn
, 0, 5);
3743 int rn
= extract32(insn
, 5, 5);
3744 uint64_t imm
= extract32(insn
, 10, 12);
3745 int shift
= extract32(insn
, 22, 2);
3746 bool setflags
= extract32(insn
, 29, 1);
3747 bool sub_op
= extract32(insn
, 30, 1);
3748 bool is_64bit
= extract32(insn
, 31, 1);
3750 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3751 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3752 TCGv_i64 tcg_result
;
3761 unallocated_encoding(s
);
3765 tcg_result
= tcg_temp_new_i64();
3768 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3770 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3773 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3775 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3777 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3779 tcg_temp_free_i64(tcg_imm
);
3783 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3785 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3788 tcg_temp_free_i64(tcg_result
);
3791 /* The input should be a value in the bottom e bits (with higher
3792 * bits zero); returns that value replicated into every element
3793 * of size e in a 64 bit integer.
3795 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3805 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3806 static inline uint64_t bitmask64(unsigned int length
)
3808 assert(length
> 0 && length
<= 64);
3809 return ~0ULL >> (64 - length
);
3812 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3813 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3814 * value (ie should cause a guest UNDEF exception), and true if they are
3815 * valid, in which case the decoded bit pattern is written to result.
3817 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3818 unsigned int imms
, unsigned int immr
)
3821 unsigned e
, levels
, s
, r
;
3824 assert(immn
< 2 && imms
< 64 && immr
< 64);
3826 /* The bit patterns we create here are 64 bit patterns which
3827 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3828 * 64 bits each. Each element contains the same value: a run
3829 * of between 1 and e-1 non-zero bits, rotated within the
3830 * element by between 0 and e-1 bits.
3832 * The element size and run length are encoded into immn (1 bit)
3833 * and imms (6 bits) as follows:
3834 * 64 bit elements: immn = 1, imms = <length of run - 1>
3835 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3836 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3837 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3838 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3839 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3840 * Notice that immn = 0, imms = 11111x is the only combination
3841 * not covered by one of the above options; this is reserved.
3842 * Further, <length of run - 1> all-ones is a reserved pattern.
3844 * In all cases the rotation is by immr % e (and immr is 6 bits).
3847 /* First determine the element size */
3848 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3850 /* This is the immn == 0, imms == 0x11111x case */
3860 /* <length of run - 1> mustn't be all-ones. */
3864 /* Create the value of one element: s+1 set bits rotated
3865 * by r within the element (which is e bits wide)...
3867 mask
= bitmask64(s
+ 1);
3869 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3870 mask
&= bitmask64(e
);
3872 /* ...then replicate the element over the whole 64 bit value */
3873 mask
= bitfield_replicate(mask
, e
);
3878 /* Logical (immediate)
3879 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3880 * +----+-----+-------------+---+------+------+------+------+
3881 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3882 * +----+-----+-------------+---+------+------+------+------+
3884 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3886 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3887 TCGv_i64 tcg_rd
, tcg_rn
;
3889 bool is_and
= false;
3891 sf
= extract32(insn
, 31, 1);
3892 opc
= extract32(insn
, 29, 2);
3893 is_n
= extract32(insn
, 22, 1);
3894 immr
= extract32(insn
, 16, 6);
3895 imms
= extract32(insn
, 10, 6);
3896 rn
= extract32(insn
, 5, 5);
3897 rd
= extract32(insn
, 0, 5);
3900 unallocated_encoding(s
);
3904 if (opc
== 0x3) { /* ANDS */
3905 tcg_rd
= cpu_reg(s
, rd
);
3907 tcg_rd
= cpu_reg_sp(s
, rd
);
3909 tcg_rn
= cpu_reg(s
, rn
);
3911 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3912 /* some immediate field values are reserved */
3913 unallocated_encoding(s
);
3918 wmask
&= 0xffffffff;
3922 case 0x3: /* ANDS */
3924 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3928 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3931 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3934 assert(FALSE
); /* must handle all above */
3938 if (!sf
&& !is_and
) {
3939 /* zero extend final result; we know we can skip this for AND
3940 * since the immediate had the high 32 bits clear.
3942 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3945 if (opc
== 3) { /* ANDS */
3946 gen_logic_CC(sf
, tcg_rd
);
3951 * Move wide (immediate)
3953 * 31 30 29 28 23 22 21 20 5 4 0
3954 * +--+-----+-------------+-----+----------------+------+
3955 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3956 * +--+-----+-------------+-----+----------------+------+
3958 * sf: 0 -> 32 bit, 1 -> 64 bit
3959 * opc: 00 -> N, 10 -> Z, 11 -> K
3960 * hw: shift/16 (0,16, and sf only 32, 48)
3962 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3964 int rd
= extract32(insn
, 0, 5);
3965 uint64_t imm
= extract32(insn
, 5, 16);
3966 int sf
= extract32(insn
, 31, 1);
3967 int opc
= extract32(insn
, 29, 2);
3968 int pos
= extract32(insn
, 21, 2) << 4;
3969 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3972 if (!sf
&& (pos
>= 32)) {
3973 unallocated_encoding(s
);
3987 tcg_gen_movi_i64(tcg_rd
, imm
);
3990 tcg_imm
= tcg_const_i64(imm
);
3991 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3992 tcg_temp_free_i64(tcg_imm
);
3994 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3998 unallocated_encoding(s
);
4004 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4005 * +----+-----+-------------+---+------+------+------+------+
4006 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4007 * +----+-----+-------------+---+------+------+------+------+
4009 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4011 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4012 TCGv_i64 tcg_rd
, tcg_tmp
;
4014 sf
= extract32(insn
, 31, 1);
4015 opc
= extract32(insn
, 29, 2);
4016 n
= extract32(insn
, 22, 1);
4017 ri
= extract32(insn
, 16, 6);
4018 si
= extract32(insn
, 10, 6);
4019 rn
= extract32(insn
, 5, 5);
4020 rd
= extract32(insn
, 0, 5);
4021 bitsize
= sf
? 64 : 32;
4023 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4024 unallocated_encoding(s
);
4028 tcg_rd
= cpu_reg(s
, rd
);
4030 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4031 to be smaller than bitsize, we'll never reference data outside the
4032 low 32-bits anyway. */
4033 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4035 /* Recognize simple(r) extractions. */
4037 /* Wd<s-r:0> = Wn<s:r> */
4038 len
= (si
- ri
) + 1;
4039 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4040 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4042 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4043 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4046 /* opc == 1, BXFIL fall through to deposit */
4047 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
4050 /* Handle the ri > si case with a deposit
4051 * Wd<32+s-r,32-r> = Wn<s:0>
4054 pos
= (bitsize
- ri
) & (bitsize
- 1);
4057 if (opc
== 0 && len
< ri
) {
4058 /* SBFM: sign extend the destination field from len to fill
4059 the balance of the word. Let the deposit below insert all
4060 of those sign bits. */
4061 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4065 if (opc
== 1) { /* BFM, BXFIL */
4066 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4068 /* SBFM or UBFM: We start with zero, and we haven't modified
4069 any bits outside bitsize, therefore the zero-extension
4070 below is unneeded. */
4071 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4076 if (!sf
) { /* zero extend final result */
4077 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4082 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4083 * +----+------+-------------+---+----+------+--------+------+------+
4084 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4085 * +----+------+-------------+---+----+------+--------+------+------+
4087 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4089 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4091 sf
= extract32(insn
, 31, 1);
4092 n
= extract32(insn
, 22, 1);
4093 rm
= extract32(insn
, 16, 5);
4094 imm
= extract32(insn
, 10, 6);
4095 rn
= extract32(insn
, 5, 5);
4096 rd
= extract32(insn
, 0, 5);
4097 op21
= extract32(insn
, 29, 2);
4098 op0
= extract32(insn
, 21, 1);
4099 bitsize
= sf
? 64 : 32;
4101 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4102 unallocated_encoding(s
);
4104 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4106 tcg_rd
= cpu_reg(s
, rd
);
4108 if (unlikely(imm
== 0)) {
4109 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4110 * so an extract from bit 0 is a special case.
4113 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4115 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4117 } else if (rm
== rn
) { /* ROR */
4118 tcg_rm
= cpu_reg(s
, rm
);
4120 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
4122 TCGv_i32 tmp
= tcg_temp_new_i32();
4123 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
4124 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
4125 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
4126 tcg_temp_free_i32(tmp
);
4129 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4130 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4131 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
4132 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
4133 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
4135 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4141 /* Data processing - immediate */
4142 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4144 switch (extract32(insn
, 23, 6)) {
4145 case 0x20: case 0x21: /* PC-rel. addressing */
4146 disas_pc_rel_adr(s
, insn
);
4148 case 0x22: case 0x23: /* Add/subtract (immediate) */
4149 disas_add_sub_imm(s
, insn
);
4151 case 0x24: /* Logical (immediate) */
4152 disas_logic_imm(s
, insn
);
4154 case 0x25: /* Move wide (immediate) */
4155 disas_movw_imm(s
, insn
);
4157 case 0x26: /* Bitfield */
4158 disas_bitfield(s
, insn
);
4160 case 0x27: /* Extract */
4161 disas_extract(s
, insn
);
4164 unallocated_encoding(s
);
4169 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4170 * Note that it is the caller's responsibility to ensure that the
4171 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4172 * mandated semantics for out of range shifts.
4174 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4175 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4177 switch (shift_type
) {
4178 case A64_SHIFT_TYPE_LSL
:
4179 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4181 case A64_SHIFT_TYPE_LSR
:
4182 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4184 case A64_SHIFT_TYPE_ASR
:
4186 tcg_gen_ext32s_i64(dst
, src
);
4188 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4190 case A64_SHIFT_TYPE_ROR
:
4192 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4195 t0
= tcg_temp_new_i32();
4196 t1
= tcg_temp_new_i32();
4197 tcg_gen_extrl_i64_i32(t0
, src
);
4198 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4199 tcg_gen_rotr_i32(t0
, t0
, t1
);
4200 tcg_gen_extu_i32_i64(dst
, t0
);
4201 tcg_temp_free_i32(t0
);
4202 tcg_temp_free_i32(t1
);
4206 assert(FALSE
); /* all shift types should be handled */
4210 if (!sf
) { /* zero extend final result */
4211 tcg_gen_ext32u_i64(dst
, dst
);
4215 /* Shift a TCGv src by immediate, put result in dst.
4216 * The shift amount must be in range (this should always be true as the
4217 * relevant instructions will UNDEF on bad shift immediates).
4219 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4220 enum a64_shift_type shift_type
, unsigned int shift_i
)
4222 assert(shift_i
< (sf
? 64 : 32));
4225 tcg_gen_mov_i64(dst
, src
);
4227 TCGv_i64 shift_const
;
4229 shift_const
= tcg_const_i64(shift_i
);
4230 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4231 tcg_temp_free_i64(shift_const
);
4235 /* Logical (shifted register)
4236 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4237 * +----+-----+-----------+-------+---+------+--------+------+------+
4238 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4239 * +----+-----+-----------+-------+---+------+--------+------+------+
4241 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4243 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4244 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4246 sf
= extract32(insn
, 31, 1);
4247 opc
= extract32(insn
, 29, 2);
4248 shift_type
= extract32(insn
, 22, 2);
4249 invert
= extract32(insn
, 21, 1);
4250 rm
= extract32(insn
, 16, 5);
4251 shift_amount
= extract32(insn
, 10, 6);
4252 rn
= extract32(insn
, 5, 5);
4253 rd
= extract32(insn
, 0, 5);
4255 if (!sf
&& (shift_amount
& (1 << 5))) {
4256 unallocated_encoding(s
);
4260 tcg_rd
= cpu_reg(s
, rd
);
4262 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4263 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4264 * register-register MOV and MVN, so it is worth special casing.
4266 tcg_rm
= cpu_reg(s
, rm
);
4268 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4270 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4274 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4276 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4282 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4285 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4288 tcg_rn
= cpu_reg(s
, rn
);
4290 switch (opc
| (invert
<< 2)) {
4293 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4296 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4299 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4303 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4306 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4309 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4317 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4321 gen_logic_CC(sf
, tcg_rd
);
4326 * Add/subtract (extended register)
4328 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4329 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4330 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4331 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4333 * sf: 0 -> 32bit, 1 -> 64bit
4334 * op: 0 -> add , 1 -> sub
4337 * option: extension type (see DecodeRegExtend)
4338 * imm3: optional shift to Rm
4340 * Rd = Rn + LSL(extend(Rm), amount)
4342 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4344 int rd
= extract32(insn
, 0, 5);
4345 int rn
= extract32(insn
, 5, 5);
4346 int imm3
= extract32(insn
, 10, 3);
4347 int option
= extract32(insn
, 13, 3);
4348 int rm
= extract32(insn
, 16, 5);
4349 int opt
= extract32(insn
, 22, 2);
4350 bool setflags
= extract32(insn
, 29, 1);
4351 bool sub_op
= extract32(insn
, 30, 1);
4352 bool sf
= extract32(insn
, 31, 1);
4354 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4356 TCGv_i64 tcg_result
;
4358 if (imm3
> 4 || opt
!= 0) {
4359 unallocated_encoding(s
);
4363 /* non-flag setting ops may use SP */
4365 tcg_rd
= cpu_reg_sp(s
, rd
);
4367 tcg_rd
= cpu_reg(s
, rd
);
4369 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4371 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4372 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4374 tcg_result
= tcg_temp_new_i64();
4378 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4380 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4384 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4386 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4391 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4393 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4396 tcg_temp_free_i64(tcg_result
);
4400 * Add/subtract (shifted register)
4402 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4403 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4404 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4405 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4407 * sf: 0 -> 32bit, 1 -> 64bit
4408 * op: 0 -> add , 1 -> sub
4410 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4411 * imm6: Shift amount to apply to Rm before the add/sub
4413 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4415 int rd
= extract32(insn
, 0, 5);
4416 int rn
= extract32(insn
, 5, 5);
4417 int imm6
= extract32(insn
, 10, 6);
4418 int rm
= extract32(insn
, 16, 5);
4419 int shift_type
= extract32(insn
, 22, 2);
4420 bool setflags
= extract32(insn
, 29, 1);
4421 bool sub_op
= extract32(insn
, 30, 1);
4422 bool sf
= extract32(insn
, 31, 1);
4424 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4425 TCGv_i64 tcg_rn
, tcg_rm
;
4426 TCGv_i64 tcg_result
;
4428 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4429 unallocated_encoding(s
);
4433 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4434 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4436 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4438 tcg_result
= tcg_temp_new_i64();
4442 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4444 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4448 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4450 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4455 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4457 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4460 tcg_temp_free_i64(tcg_result
);
4463 /* Data-processing (3 source)
4465 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4466 * +--+------+-----------+------+------+----+------+------+------+
4467 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4468 * +--+------+-----------+------+------+----+------+------+------+
4470 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4472 int rd
= extract32(insn
, 0, 5);
4473 int rn
= extract32(insn
, 5, 5);
4474 int ra
= extract32(insn
, 10, 5);
4475 int rm
= extract32(insn
, 16, 5);
4476 int op_id
= (extract32(insn
, 29, 3) << 4) |
4477 (extract32(insn
, 21, 3) << 1) |
4478 extract32(insn
, 15, 1);
4479 bool sf
= extract32(insn
, 31, 1);
4480 bool is_sub
= extract32(op_id
, 0, 1);
4481 bool is_high
= extract32(op_id
, 2, 1);
4482 bool is_signed
= false;
4487 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4489 case 0x42: /* SMADDL */
4490 case 0x43: /* SMSUBL */
4491 case 0x44: /* SMULH */
4494 case 0x0: /* MADD (32bit) */
4495 case 0x1: /* MSUB (32bit) */
4496 case 0x40: /* MADD (64bit) */
4497 case 0x41: /* MSUB (64bit) */
4498 case 0x4a: /* UMADDL */
4499 case 0x4b: /* UMSUBL */
4500 case 0x4c: /* UMULH */
4503 unallocated_encoding(s
);
4508 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4509 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4510 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4511 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4514 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4516 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4519 tcg_temp_free_i64(low_bits
);
4523 tcg_op1
= tcg_temp_new_i64();
4524 tcg_op2
= tcg_temp_new_i64();
4525 tcg_tmp
= tcg_temp_new_i64();
4528 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4529 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4532 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4533 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4535 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4536 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4540 if (ra
== 31 && !is_sub
) {
4541 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4542 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4544 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4546 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4548 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4553 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4556 tcg_temp_free_i64(tcg_op1
);
4557 tcg_temp_free_i64(tcg_op2
);
4558 tcg_temp_free_i64(tcg_tmp
);
4561 /* Add/subtract (with carry)
4562 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4563 * +--+--+--+------------------------+------+-------------+------+-----+
4564 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4565 * +--+--+--+------------------------+------+-------------+------+-----+
4568 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4570 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4571 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4573 sf
= extract32(insn
, 31, 1);
4574 op
= extract32(insn
, 30, 1);
4575 setflags
= extract32(insn
, 29, 1);
4576 rm
= extract32(insn
, 16, 5);
4577 rn
= extract32(insn
, 5, 5);
4578 rd
= extract32(insn
, 0, 5);
4580 tcg_rd
= cpu_reg(s
, rd
);
4581 tcg_rn
= cpu_reg(s
, rn
);
4584 tcg_y
= new_tmp_a64(s
);
4585 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4587 tcg_y
= cpu_reg(s
, rm
);
4591 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4593 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4598 * Rotate right into flags
4599 * 31 30 29 21 15 10 5 4 0
4600 * +--+--+--+-----------------+--------+-----------+------+--+------+
4601 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4602 * +--+--+--+-----------------+--------+-----------+------+--+------+
4604 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4606 int mask
= extract32(insn
, 0, 4);
4607 int o2
= extract32(insn
, 4, 1);
4608 int rn
= extract32(insn
, 5, 5);
4609 int imm6
= extract32(insn
, 15, 6);
4610 int sf_op_s
= extract32(insn
, 29, 3);
4614 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4615 unallocated_encoding(s
);
4619 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4620 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4622 nzcv
= tcg_temp_new_i32();
4623 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4625 if (mask
& 8) { /* N */
4626 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4628 if (mask
& 4) { /* Z */
4629 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4630 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4632 if (mask
& 2) { /* C */
4633 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4635 if (mask
& 1) { /* V */
4636 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4639 tcg_temp_free_i32(nzcv
);
4643 * Evaluate into flags
4644 * 31 30 29 21 15 14 10 5 4 0
4645 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4646 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4647 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4649 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4651 int o3_mask
= extract32(insn
, 0, 5);
4652 int rn
= extract32(insn
, 5, 5);
4653 int o2
= extract32(insn
, 15, 6);
4654 int sz
= extract32(insn
, 14, 1);
4655 int sf_op_s
= extract32(insn
, 29, 3);
4659 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4660 !dc_isar_feature(aa64_condm_4
, s
)) {
4661 unallocated_encoding(s
);
4664 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4666 tmp
= tcg_temp_new_i32();
4667 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4668 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4669 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4670 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4671 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4672 tcg_temp_free_i32(tmp
);
4675 /* Conditional compare (immediate / register)
4676 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4677 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4678 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4679 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4682 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4684 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4685 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4686 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4689 if (!extract32(insn
, 29, 1)) {
4690 unallocated_encoding(s
);
4693 if (insn
& (1 << 10 | 1 << 4)) {
4694 unallocated_encoding(s
);
4697 sf
= extract32(insn
, 31, 1);
4698 op
= extract32(insn
, 30, 1);
4699 is_imm
= extract32(insn
, 11, 1);
4700 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4701 cond
= extract32(insn
, 12, 4);
4702 rn
= extract32(insn
, 5, 5);
4703 nzcv
= extract32(insn
, 0, 4);
4705 /* Set T0 = !COND. */
4706 tcg_t0
= tcg_temp_new_i32();
4707 arm_test_cc(&c
, cond
);
4708 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4711 /* Load the arguments for the new comparison. */
4713 tcg_y
= new_tmp_a64(s
);
4714 tcg_gen_movi_i64(tcg_y
, y
);
4716 tcg_y
= cpu_reg(s
, y
);
4718 tcg_rn
= cpu_reg(s
, rn
);
4720 /* Set the flags for the new comparison. */
4721 tcg_tmp
= tcg_temp_new_i64();
4723 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4725 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4727 tcg_temp_free_i64(tcg_tmp
);
4729 /* If COND was false, force the flags to #nzcv. Compute two masks
4730 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4731 * For tcg hosts that support ANDC, we can make do with just T1.
4732 * In either case, allow the tcg optimizer to delete any unused mask.
4734 tcg_t1
= tcg_temp_new_i32();
4735 tcg_t2
= tcg_temp_new_i32();
4736 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4737 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4739 if (nzcv
& 8) { /* N */
4740 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4742 if (TCG_TARGET_HAS_andc_i32
) {
4743 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4745 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4748 if (nzcv
& 4) { /* Z */
4749 if (TCG_TARGET_HAS_andc_i32
) {
4750 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4752 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4755 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4757 if (nzcv
& 2) { /* C */
4758 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4760 if (TCG_TARGET_HAS_andc_i32
) {
4761 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4763 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4766 if (nzcv
& 1) { /* V */
4767 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4769 if (TCG_TARGET_HAS_andc_i32
) {
4770 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4772 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4775 tcg_temp_free_i32(tcg_t0
);
4776 tcg_temp_free_i32(tcg_t1
);
4777 tcg_temp_free_i32(tcg_t2
);
4780 /* Conditional select
4781 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4782 * +----+----+---+-----------------+------+------+-----+------+------+
4783 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4784 * +----+----+---+-----------------+------+------+-----+------+------+
4786 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4788 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4789 TCGv_i64 tcg_rd
, zero
;
4792 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4793 /* S == 1 or op2<1> == 1 */
4794 unallocated_encoding(s
);
4797 sf
= extract32(insn
, 31, 1);
4798 else_inv
= extract32(insn
, 30, 1);
4799 rm
= extract32(insn
, 16, 5);
4800 cond
= extract32(insn
, 12, 4);
4801 else_inc
= extract32(insn
, 10, 1);
4802 rn
= extract32(insn
, 5, 5);
4803 rd
= extract32(insn
, 0, 5);
4805 tcg_rd
= cpu_reg(s
, rd
);
4807 a64_test_cc(&c
, cond
);
4808 zero
= tcg_const_i64(0);
4810 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4812 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4814 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4817 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4818 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4819 if (else_inv
&& else_inc
) {
4820 tcg_gen_neg_i64(t_false
, t_false
);
4821 } else if (else_inv
) {
4822 tcg_gen_not_i64(t_false
, t_false
);
4823 } else if (else_inc
) {
4824 tcg_gen_addi_i64(t_false
, t_false
, 1);
4826 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4829 tcg_temp_free_i64(zero
);
4833 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4837 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4838 unsigned int rn
, unsigned int rd
)
4840 TCGv_i64 tcg_rd
, tcg_rn
;
4841 tcg_rd
= cpu_reg(s
, rd
);
4842 tcg_rn
= cpu_reg(s
, rn
);
4845 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4847 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4848 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4849 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4850 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4851 tcg_temp_free_i32(tcg_tmp32
);
4855 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4856 unsigned int rn
, unsigned int rd
)
4858 TCGv_i64 tcg_rd
, tcg_rn
;
4859 tcg_rd
= cpu_reg(s
, rd
);
4860 tcg_rn
= cpu_reg(s
, rn
);
4863 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4865 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4866 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4867 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4868 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4869 tcg_temp_free_i32(tcg_tmp32
);
4873 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4874 unsigned int rn
, unsigned int rd
)
4876 TCGv_i64 tcg_rd
, tcg_rn
;
4877 tcg_rd
= cpu_reg(s
, rd
);
4878 tcg_rn
= cpu_reg(s
, rn
);
4881 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4883 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4884 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4885 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4886 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4887 tcg_temp_free_i32(tcg_tmp32
);
4891 /* REV with sf==1, opcode==3 ("REV64") */
4892 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4893 unsigned int rn
, unsigned int rd
)
4896 unallocated_encoding(s
);
4899 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4902 /* REV with sf==0, opcode==2
4903 * REV32 (sf==1, opcode==2)
4905 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4906 unsigned int rn
, unsigned int rd
)
4908 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4911 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4912 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4914 /* bswap32_i64 requires zero high word */
4915 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4916 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4917 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4918 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4919 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4921 tcg_temp_free_i64(tcg_tmp
);
4923 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4924 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4928 /* REV16 (opcode==1) */
4929 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4930 unsigned int rn
, unsigned int rd
)
4932 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4933 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4934 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4935 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4937 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4938 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4939 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4940 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4941 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4943 tcg_temp_free_i64(mask
);
4944 tcg_temp_free_i64(tcg_tmp
);
4947 /* Data-processing (1 source)
4948 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4949 * +----+---+---+-----------------+---------+--------+------+------+
4950 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4951 * +----+---+---+-----------------+---------+--------+------+------+
4953 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4955 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4958 if (extract32(insn
, 29, 1)) {
4959 unallocated_encoding(s
);
4963 sf
= extract32(insn
, 31, 1);
4964 opcode
= extract32(insn
, 10, 6);
4965 opcode2
= extract32(insn
, 16, 5);
4966 rn
= extract32(insn
, 5, 5);
4967 rd
= extract32(insn
, 0, 5);
4969 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4971 switch (MAP(sf
, opcode2
, opcode
)) {
4972 case MAP(0, 0x00, 0x00): /* RBIT */
4973 case MAP(1, 0x00, 0x00):
4974 handle_rbit(s
, sf
, rn
, rd
);
4976 case MAP(0, 0x00, 0x01): /* REV16 */
4977 case MAP(1, 0x00, 0x01):
4978 handle_rev16(s
, sf
, rn
, rd
);
4980 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4981 case MAP(1, 0x00, 0x02):
4982 handle_rev32(s
, sf
, rn
, rd
);
4984 case MAP(1, 0x00, 0x03): /* REV64 */
4985 handle_rev64(s
, sf
, rn
, rd
);
4987 case MAP(0, 0x00, 0x04): /* CLZ */
4988 case MAP(1, 0x00, 0x04):
4989 handle_clz(s
, sf
, rn
, rd
);
4991 case MAP(0, 0x00, 0x05): /* CLS */
4992 case MAP(1, 0x00, 0x05):
4993 handle_cls(s
, sf
, rn
, rd
);
4995 case MAP(1, 0x01, 0x00): /* PACIA */
4996 if (s
->pauth_active
) {
4997 tcg_rd
= cpu_reg(s
, rd
);
4998 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4999 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5000 goto do_unallocated
;
5003 case MAP(1, 0x01, 0x01): /* PACIB */
5004 if (s
->pauth_active
) {
5005 tcg_rd
= cpu_reg(s
, rd
);
5006 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5007 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5008 goto do_unallocated
;
5011 case MAP(1, 0x01, 0x02): /* PACDA */
5012 if (s
->pauth_active
) {
5013 tcg_rd
= cpu_reg(s
, rd
);
5014 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5015 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5016 goto do_unallocated
;
5019 case MAP(1, 0x01, 0x03): /* PACDB */
5020 if (s
->pauth_active
) {
5021 tcg_rd
= cpu_reg(s
, rd
);
5022 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5023 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5024 goto do_unallocated
;
5027 case MAP(1, 0x01, 0x04): /* AUTIA */
5028 if (s
->pauth_active
) {
5029 tcg_rd
= cpu_reg(s
, rd
);
5030 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5031 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5032 goto do_unallocated
;
5035 case MAP(1, 0x01, 0x05): /* AUTIB */
5036 if (s
->pauth_active
) {
5037 tcg_rd
= cpu_reg(s
, rd
);
5038 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5039 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5040 goto do_unallocated
;
5043 case MAP(1, 0x01, 0x06): /* AUTDA */
5044 if (s
->pauth_active
) {
5045 tcg_rd
= cpu_reg(s
, rd
);
5046 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5047 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5048 goto do_unallocated
;
5051 case MAP(1, 0x01, 0x07): /* AUTDB */
5052 if (s
->pauth_active
) {
5053 tcg_rd
= cpu_reg(s
, rd
);
5054 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5055 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5056 goto do_unallocated
;
5059 case MAP(1, 0x01, 0x08): /* PACIZA */
5060 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5061 goto do_unallocated
;
5062 } else if (s
->pauth_active
) {
5063 tcg_rd
= cpu_reg(s
, rd
);
5064 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5067 case MAP(1, 0x01, 0x09): /* PACIZB */
5068 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5069 goto do_unallocated
;
5070 } else if (s
->pauth_active
) {
5071 tcg_rd
= cpu_reg(s
, rd
);
5072 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5075 case MAP(1, 0x01, 0x0a): /* PACDZA */
5076 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5077 goto do_unallocated
;
5078 } else if (s
->pauth_active
) {
5079 tcg_rd
= cpu_reg(s
, rd
);
5080 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5083 case MAP(1, 0x01, 0x0b): /* PACDZB */
5084 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5085 goto do_unallocated
;
5086 } else if (s
->pauth_active
) {
5087 tcg_rd
= cpu_reg(s
, rd
);
5088 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5091 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5092 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5093 goto do_unallocated
;
5094 } else if (s
->pauth_active
) {
5095 tcg_rd
= cpu_reg(s
, rd
);
5096 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5099 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5100 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5101 goto do_unallocated
;
5102 } else if (s
->pauth_active
) {
5103 tcg_rd
= cpu_reg(s
, rd
);
5104 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5107 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5108 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5109 goto do_unallocated
;
5110 } else if (s
->pauth_active
) {
5111 tcg_rd
= cpu_reg(s
, rd
);
5112 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5115 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5116 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5117 goto do_unallocated
;
5118 } else if (s
->pauth_active
) {
5119 tcg_rd
= cpu_reg(s
, rd
);
5120 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5123 case MAP(1, 0x01, 0x10): /* XPACI */
5124 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5125 goto do_unallocated
;
5126 } else if (s
->pauth_active
) {
5127 tcg_rd
= cpu_reg(s
, rd
);
5128 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5131 case MAP(1, 0x01, 0x11): /* XPACD */
5132 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5133 goto do_unallocated
;
5134 } else if (s
->pauth_active
) {
5135 tcg_rd
= cpu_reg(s
, rd
);
5136 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5141 unallocated_encoding(s
);
5148 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5149 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5151 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5152 tcg_rd
= cpu_reg(s
, rd
);
5154 if (!sf
&& is_signed
) {
5155 tcg_n
= new_tmp_a64(s
);
5156 tcg_m
= new_tmp_a64(s
);
5157 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5158 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5160 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5161 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5165 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5167 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5170 if (!sf
) { /* zero extend final result */
5171 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5175 /* LSLV, LSRV, ASRV, RORV */
5176 static void handle_shift_reg(DisasContext
*s
,
5177 enum a64_shift_type shift_type
, unsigned int sf
,
5178 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5180 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5181 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5182 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5184 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5185 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5186 tcg_temp_free_i64(tcg_shift
);
5189 /* CRC32[BHWX], CRC32C[BHWX] */
5190 static void handle_crc32(DisasContext
*s
,
5191 unsigned int sf
, unsigned int sz
, bool crc32c
,
5192 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5194 TCGv_i64 tcg_acc
, tcg_val
;
5197 if (!dc_isar_feature(aa64_crc32
, s
)
5198 || (sf
== 1 && sz
!= 3)
5199 || (sf
== 0 && sz
== 3)) {
5200 unallocated_encoding(s
);
5205 tcg_val
= cpu_reg(s
, rm
);
5219 g_assert_not_reached();
5221 tcg_val
= new_tmp_a64(s
);
5222 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5225 tcg_acc
= cpu_reg(s
, rn
);
5226 tcg_bytes
= tcg_const_i32(1 << sz
);
5229 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5231 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5234 tcg_temp_free_i32(tcg_bytes
);
5237 /* Data-processing (2 source)
5238 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5239 * +----+---+---+-----------------+------+--------+------+------+
5240 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5241 * +----+---+---+-----------------+------+--------+------+------+
5243 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5245 unsigned int sf
, rm
, opcode
, rn
, rd
;
5246 sf
= extract32(insn
, 31, 1);
5247 rm
= extract32(insn
, 16, 5);
5248 opcode
= extract32(insn
, 10, 6);
5249 rn
= extract32(insn
, 5, 5);
5250 rd
= extract32(insn
, 0, 5);
5252 if (extract32(insn
, 29, 1)) {
5253 unallocated_encoding(s
);
5259 handle_div(s
, false, sf
, rm
, rn
, rd
);
5262 handle_div(s
, true, sf
, rm
, rn
, rd
);
5265 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5268 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5271 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5274 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5276 case 12: /* PACGA */
5277 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5278 goto do_unallocated
;
5280 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5281 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5290 case 23: /* CRC32 */
5292 int sz
= extract32(opcode
, 0, 2);
5293 bool crc32c
= extract32(opcode
, 2, 1);
5294 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5299 unallocated_encoding(s
);
5305 * Data processing - register
5306 * 31 30 29 28 25 21 20 16 10 0
5307 * +--+---+--+---+-------+-----+-------+-------+---------+
5308 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5309 * +--+---+--+---+-------+-----+-------+-------+---------+
5311 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5313 int op0
= extract32(insn
, 30, 1);
5314 int op1
= extract32(insn
, 28, 1);
5315 int op2
= extract32(insn
, 21, 4);
5316 int op3
= extract32(insn
, 10, 6);
5321 /* Add/sub (extended register) */
5322 disas_add_sub_ext_reg(s
, insn
);
5324 /* Add/sub (shifted register) */
5325 disas_add_sub_reg(s
, insn
);
5328 /* Logical (shifted register) */
5329 disas_logic_reg(s
, insn
);
5337 case 0x00: /* Add/subtract (with carry) */
5338 disas_adc_sbc(s
, insn
);
5341 case 0x01: /* Rotate right into flags */
5343 disas_rotate_right_into_flags(s
, insn
);
5346 case 0x02: /* Evaluate into flags */
5350 disas_evaluate_into_flags(s
, insn
);
5354 goto do_unallocated
;
5358 case 0x2: /* Conditional compare */
5359 disas_cc(s
, insn
); /* both imm and reg forms */
5362 case 0x4: /* Conditional select */
5363 disas_cond_select(s
, insn
);
5366 case 0x6: /* Data-processing */
5367 if (op0
) { /* (1 source) */
5368 disas_data_proc_1src(s
, insn
);
5369 } else { /* (2 source) */
5370 disas_data_proc_2src(s
, insn
);
5373 case 0x8 ... 0xf: /* (3 source) */
5374 disas_data_proc_3src(s
, insn
);
5379 unallocated_encoding(s
);
5384 static void handle_fp_compare(DisasContext
*s
, int size
,
5385 unsigned int rn
, unsigned int rm
,
5386 bool cmp_with_zero
, bool signal_all_nans
)
5388 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5389 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5391 if (size
== MO_64
) {
5392 TCGv_i64 tcg_vn
, tcg_vm
;
5394 tcg_vn
= read_fp_dreg(s
, rn
);
5395 if (cmp_with_zero
) {
5396 tcg_vm
= tcg_const_i64(0);
5398 tcg_vm
= read_fp_dreg(s
, rm
);
5400 if (signal_all_nans
) {
5401 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5403 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5405 tcg_temp_free_i64(tcg_vn
);
5406 tcg_temp_free_i64(tcg_vm
);
5408 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5409 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5411 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5412 if (cmp_with_zero
) {
5413 tcg_gen_movi_i32(tcg_vm
, 0);
5415 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5420 if (signal_all_nans
) {
5421 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5423 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5427 if (signal_all_nans
) {
5428 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5430 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5434 g_assert_not_reached();
5437 tcg_temp_free_i32(tcg_vn
);
5438 tcg_temp_free_i32(tcg_vm
);
5441 tcg_temp_free_ptr(fpst
);
5443 gen_set_nzcv(tcg_flags
);
5445 tcg_temp_free_i64(tcg_flags
);
5448 /* Floating point compare
5449 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5450 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5451 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5452 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5454 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5456 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5459 mos
= extract32(insn
, 29, 3);
5460 type
= extract32(insn
, 22, 2);
5461 rm
= extract32(insn
, 16, 5);
5462 op
= extract32(insn
, 14, 2);
5463 rn
= extract32(insn
, 5, 5);
5464 opc
= extract32(insn
, 3, 2);
5465 op2r
= extract32(insn
, 0, 3);
5467 if (mos
|| op
|| op2r
) {
5468 unallocated_encoding(s
);
5481 if (dc_isar_feature(aa64_fp16
, s
)) {
5486 unallocated_encoding(s
);
5490 if (!fp_access_check(s
)) {
5494 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5497 /* Floating point conditional compare
5498 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5499 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5500 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5501 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5503 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5505 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5507 TCGLabel
*label_continue
= NULL
;
5510 mos
= extract32(insn
, 29, 3);
5511 type
= extract32(insn
, 22, 2);
5512 rm
= extract32(insn
, 16, 5);
5513 cond
= extract32(insn
, 12, 4);
5514 rn
= extract32(insn
, 5, 5);
5515 op
= extract32(insn
, 4, 1);
5516 nzcv
= extract32(insn
, 0, 4);
5519 unallocated_encoding(s
);
5532 if (dc_isar_feature(aa64_fp16
, s
)) {
5537 unallocated_encoding(s
);
5541 if (!fp_access_check(s
)) {
5545 if (cond
< 0x0e) { /* not always */
5546 TCGLabel
*label_match
= gen_new_label();
5547 label_continue
= gen_new_label();
5548 arm_gen_test_cc(cond
, label_match
);
5550 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5551 gen_set_nzcv(tcg_flags
);
5552 tcg_temp_free_i64(tcg_flags
);
5553 tcg_gen_br(label_continue
);
5554 gen_set_label(label_match
);
5557 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5560 gen_set_label(label_continue
);
5564 /* Floating point conditional select
5565 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5566 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5567 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5568 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5570 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5572 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5573 TCGv_i64 t_true
, t_false
, t_zero
;
5577 mos
= extract32(insn
, 29, 3);
5578 type
= extract32(insn
, 22, 2);
5579 rm
= extract32(insn
, 16, 5);
5580 cond
= extract32(insn
, 12, 4);
5581 rn
= extract32(insn
, 5, 5);
5582 rd
= extract32(insn
, 0, 5);
5585 unallocated_encoding(s
);
5598 if (dc_isar_feature(aa64_fp16
, s
)) {
5603 unallocated_encoding(s
);
5607 if (!fp_access_check(s
)) {
5611 /* Zero extend sreg & hreg inputs to 64 bits now. */
5612 t_true
= tcg_temp_new_i64();
5613 t_false
= tcg_temp_new_i64();
5614 read_vec_element(s
, t_true
, rn
, 0, sz
);
5615 read_vec_element(s
, t_false
, rm
, 0, sz
);
5617 a64_test_cc(&c
, cond
);
5618 t_zero
= tcg_const_i64(0);
5619 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5620 tcg_temp_free_i64(t_zero
);
5621 tcg_temp_free_i64(t_false
);
5624 /* Note that sregs & hregs write back zeros to the high bits,
5625 and we've already done the zero-extension. */
5626 write_fp_dreg(s
, rd
, t_true
);
5627 tcg_temp_free_i64(t_true
);
5630 /* Floating-point data-processing (1 source) - half precision */
5631 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5633 TCGv_ptr fpst
= NULL
;
5634 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5635 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5638 case 0x0: /* FMOV */
5639 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5641 case 0x1: /* FABS */
5642 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5644 case 0x2: /* FNEG */
5645 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5647 case 0x3: /* FSQRT */
5648 fpst
= get_fpstatus_ptr(true);
5649 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5651 case 0x8: /* FRINTN */
5652 case 0x9: /* FRINTP */
5653 case 0xa: /* FRINTM */
5654 case 0xb: /* FRINTZ */
5655 case 0xc: /* FRINTA */
5657 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5658 fpst
= get_fpstatus_ptr(true);
5660 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5661 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5663 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5664 tcg_temp_free_i32(tcg_rmode
);
5667 case 0xe: /* FRINTX */
5668 fpst
= get_fpstatus_ptr(true);
5669 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5671 case 0xf: /* FRINTI */
5672 fpst
= get_fpstatus_ptr(true);
5673 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5679 write_fp_sreg(s
, rd
, tcg_res
);
5682 tcg_temp_free_ptr(fpst
);
5684 tcg_temp_free_i32(tcg_op
);
5685 tcg_temp_free_i32(tcg_res
);
5688 /* Floating-point data-processing (1 source) - single precision */
5689 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5691 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5692 TCGv_i32 tcg_op
, tcg_res
;
5696 tcg_op
= read_fp_sreg(s
, rn
);
5697 tcg_res
= tcg_temp_new_i32();
5700 case 0x0: /* FMOV */
5701 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5703 case 0x1: /* FABS */
5704 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5706 case 0x2: /* FNEG */
5707 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5709 case 0x3: /* FSQRT */
5710 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5712 case 0x8: /* FRINTN */
5713 case 0x9: /* FRINTP */
5714 case 0xa: /* FRINTM */
5715 case 0xb: /* FRINTZ */
5716 case 0xc: /* FRINTA */
5717 rmode
= arm_rmode_to_sf(opcode
& 7);
5718 gen_fpst
= gen_helper_rints
;
5720 case 0xe: /* FRINTX */
5721 gen_fpst
= gen_helper_rints_exact
;
5723 case 0xf: /* FRINTI */
5724 gen_fpst
= gen_helper_rints
;
5726 case 0x10: /* FRINT32Z */
5727 rmode
= float_round_to_zero
;
5728 gen_fpst
= gen_helper_frint32_s
;
5730 case 0x11: /* FRINT32X */
5731 gen_fpst
= gen_helper_frint32_s
;
5733 case 0x12: /* FRINT64Z */
5734 rmode
= float_round_to_zero
;
5735 gen_fpst
= gen_helper_frint64_s
;
5737 case 0x13: /* FRINT64X */
5738 gen_fpst
= gen_helper_frint64_s
;
5741 g_assert_not_reached();
5744 fpst
= get_fpstatus_ptr(false);
5746 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5747 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5748 gen_fpst(tcg_res
, tcg_op
, fpst
);
5749 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5750 tcg_temp_free_i32(tcg_rmode
);
5752 gen_fpst(tcg_res
, tcg_op
, fpst
);
5754 tcg_temp_free_ptr(fpst
);
5757 write_fp_sreg(s
, rd
, tcg_res
);
5758 tcg_temp_free_i32(tcg_op
);
5759 tcg_temp_free_i32(tcg_res
);
5762 /* Floating-point data-processing (1 source) - double precision */
5763 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5765 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5766 TCGv_i64 tcg_op
, tcg_res
;
5771 case 0x0: /* FMOV */
5772 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5776 tcg_op
= read_fp_dreg(s
, rn
);
5777 tcg_res
= tcg_temp_new_i64();
5780 case 0x1: /* FABS */
5781 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5783 case 0x2: /* FNEG */
5784 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5786 case 0x3: /* FSQRT */
5787 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5789 case 0x8: /* FRINTN */
5790 case 0x9: /* FRINTP */
5791 case 0xa: /* FRINTM */
5792 case 0xb: /* FRINTZ */
5793 case 0xc: /* FRINTA */
5794 rmode
= arm_rmode_to_sf(opcode
& 7);
5795 gen_fpst
= gen_helper_rintd
;
5797 case 0xe: /* FRINTX */
5798 gen_fpst
= gen_helper_rintd_exact
;
5800 case 0xf: /* FRINTI */
5801 gen_fpst
= gen_helper_rintd
;
5803 case 0x10: /* FRINT32Z */
5804 rmode
= float_round_to_zero
;
5805 gen_fpst
= gen_helper_frint32_d
;
5807 case 0x11: /* FRINT32X */
5808 gen_fpst
= gen_helper_frint32_d
;
5810 case 0x12: /* FRINT64Z */
5811 rmode
= float_round_to_zero
;
5812 gen_fpst
= gen_helper_frint64_d
;
5814 case 0x13: /* FRINT64X */
5815 gen_fpst
= gen_helper_frint64_d
;
5818 g_assert_not_reached();
5821 fpst
= get_fpstatus_ptr(false);
5823 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5824 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5825 gen_fpst(tcg_res
, tcg_op
, fpst
);
5826 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5827 tcg_temp_free_i32(tcg_rmode
);
5829 gen_fpst(tcg_res
, tcg_op
, fpst
);
5831 tcg_temp_free_ptr(fpst
);
5834 write_fp_dreg(s
, rd
, tcg_res
);
5835 tcg_temp_free_i64(tcg_op
);
5836 tcg_temp_free_i64(tcg_res
);
5839 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5840 int rd
, int rn
, int dtype
, int ntype
)
5845 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5847 /* Single to double */
5848 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5849 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5850 write_fp_dreg(s
, rd
, tcg_rd
);
5851 tcg_temp_free_i64(tcg_rd
);
5853 /* Single to half */
5854 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5855 TCGv_i32 ahp
= get_ahp_flag();
5856 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5858 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5859 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5860 write_fp_sreg(s
, rd
, tcg_rd
);
5861 tcg_temp_free_i32(tcg_rd
);
5862 tcg_temp_free_i32(ahp
);
5863 tcg_temp_free_ptr(fpst
);
5865 tcg_temp_free_i32(tcg_rn
);
5870 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5871 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5873 /* Double to single */
5874 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5876 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5877 TCGv_i32 ahp
= get_ahp_flag();
5878 /* Double to half */
5879 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5880 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5881 tcg_temp_free_ptr(fpst
);
5882 tcg_temp_free_i32(ahp
);
5884 write_fp_sreg(s
, rd
, tcg_rd
);
5885 tcg_temp_free_i32(tcg_rd
);
5886 tcg_temp_free_i64(tcg_rn
);
5891 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5892 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5893 TCGv_i32 tcg_ahp
= get_ahp_flag();
5894 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5896 /* Half to single */
5897 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5898 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5899 write_fp_sreg(s
, rd
, tcg_rd
);
5900 tcg_temp_free_ptr(tcg_fpst
);
5901 tcg_temp_free_i32(tcg_ahp
);
5902 tcg_temp_free_i32(tcg_rd
);
5904 /* Half to double */
5905 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5906 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5907 write_fp_dreg(s
, rd
, tcg_rd
);
5908 tcg_temp_free_i64(tcg_rd
);
5910 tcg_temp_free_i32(tcg_rn
);
5918 /* Floating point data-processing (1 source)
5919 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5920 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5921 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5922 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5924 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5926 int mos
= extract32(insn
, 29, 3);
5927 int type
= extract32(insn
, 22, 2);
5928 int opcode
= extract32(insn
, 15, 6);
5929 int rn
= extract32(insn
, 5, 5);
5930 int rd
= extract32(insn
, 0, 5);
5933 unallocated_encoding(s
);
5938 case 0x4: case 0x5: case 0x7:
5940 /* FCVT between half, single and double precision */
5941 int dtype
= extract32(opcode
, 0, 2);
5942 if (type
== 2 || dtype
== type
) {
5943 unallocated_encoding(s
);
5946 if (!fp_access_check(s
)) {
5950 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5954 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5955 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5956 unallocated_encoding(s
);
5963 /* 32-to-32 and 64-to-64 ops */
5966 if (!fp_access_check(s
)) {
5969 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5972 if (!fp_access_check(s
)) {
5975 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5978 if (!dc_isar_feature(aa64_fp16
, s
)) {
5979 unallocated_encoding(s
);
5983 if (!fp_access_check(s
)) {
5986 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5989 unallocated_encoding(s
);
5994 unallocated_encoding(s
);
5999 /* Floating-point data-processing (2 source) - single precision */
6000 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6001 int rd
, int rn
, int rm
)
6008 tcg_res
= tcg_temp_new_i32();
6009 fpst
= get_fpstatus_ptr(false);
6010 tcg_op1
= read_fp_sreg(s
, rn
);
6011 tcg_op2
= read_fp_sreg(s
, rm
);
6014 case 0x0: /* FMUL */
6015 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6017 case 0x1: /* FDIV */
6018 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6020 case 0x2: /* FADD */
6021 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6023 case 0x3: /* FSUB */
6024 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6026 case 0x4: /* FMAX */
6027 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6029 case 0x5: /* FMIN */
6030 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6032 case 0x6: /* FMAXNM */
6033 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6035 case 0x7: /* FMINNM */
6036 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6038 case 0x8: /* FNMUL */
6039 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6040 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6044 write_fp_sreg(s
, rd
, tcg_res
);
6046 tcg_temp_free_ptr(fpst
);
6047 tcg_temp_free_i32(tcg_op1
);
6048 tcg_temp_free_i32(tcg_op2
);
6049 tcg_temp_free_i32(tcg_res
);
6052 /* Floating-point data-processing (2 source) - double precision */
6053 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6054 int rd
, int rn
, int rm
)
6061 tcg_res
= tcg_temp_new_i64();
6062 fpst
= get_fpstatus_ptr(false);
6063 tcg_op1
= read_fp_dreg(s
, rn
);
6064 tcg_op2
= read_fp_dreg(s
, rm
);
6067 case 0x0: /* FMUL */
6068 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6070 case 0x1: /* FDIV */
6071 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6073 case 0x2: /* FADD */
6074 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6076 case 0x3: /* FSUB */
6077 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6079 case 0x4: /* FMAX */
6080 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6082 case 0x5: /* FMIN */
6083 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6085 case 0x6: /* FMAXNM */
6086 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6088 case 0x7: /* FMINNM */
6089 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6091 case 0x8: /* FNMUL */
6092 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6093 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6097 write_fp_dreg(s
, rd
, tcg_res
);
6099 tcg_temp_free_ptr(fpst
);
6100 tcg_temp_free_i64(tcg_op1
);
6101 tcg_temp_free_i64(tcg_op2
);
6102 tcg_temp_free_i64(tcg_res
);
6105 /* Floating-point data-processing (2 source) - half precision */
6106 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6107 int rd
, int rn
, int rm
)
6114 tcg_res
= tcg_temp_new_i32();
6115 fpst
= get_fpstatus_ptr(true);
6116 tcg_op1
= read_fp_hreg(s
, rn
);
6117 tcg_op2
= read_fp_hreg(s
, rm
);
6120 case 0x0: /* FMUL */
6121 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6123 case 0x1: /* FDIV */
6124 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6126 case 0x2: /* FADD */
6127 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6129 case 0x3: /* FSUB */
6130 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6132 case 0x4: /* FMAX */
6133 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6135 case 0x5: /* FMIN */
6136 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6138 case 0x6: /* FMAXNM */
6139 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6141 case 0x7: /* FMINNM */
6142 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6144 case 0x8: /* FNMUL */
6145 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6146 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6149 g_assert_not_reached();
6152 write_fp_sreg(s
, rd
, tcg_res
);
6154 tcg_temp_free_ptr(fpst
);
6155 tcg_temp_free_i32(tcg_op1
);
6156 tcg_temp_free_i32(tcg_op2
);
6157 tcg_temp_free_i32(tcg_res
);
6160 /* Floating point data-processing (2 source)
6161 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6162 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6163 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6164 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6166 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6168 int mos
= extract32(insn
, 29, 3);
6169 int type
= extract32(insn
, 22, 2);
6170 int rd
= extract32(insn
, 0, 5);
6171 int rn
= extract32(insn
, 5, 5);
6172 int rm
= extract32(insn
, 16, 5);
6173 int opcode
= extract32(insn
, 12, 4);
6175 if (opcode
> 8 || mos
) {
6176 unallocated_encoding(s
);
6182 if (!fp_access_check(s
)) {
6185 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6188 if (!fp_access_check(s
)) {
6191 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6194 if (!dc_isar_feature(aa64_fp16
, s
)) {
6195 unallocated_encoding(s
);
6198 if (!fp_access_check(s
)) {
6201 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6204 unallocated_encoding(s
);
6208 /* Floating-point data-processing (3 source) - single precision */
6209 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6210 int rd
, int rn
, int rm
, int ra
)
6212 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6213 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6214 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6216 tcg_op1
= read_fp_sreg(s
, rn
);
6217 tcg_op2
= read_fp_sreg(s
, rm
);
6218 tcg_op3
= read_fp_sreg(s
, ra
);
6220 /* These are fused multiply-add, and must be done as one
6221 * floating point operation with no rounding between the
6222 * multiplication and addition steps.
6223 * NB that doing the negations here as separate steps is
6224 * correct : an input NaN should come out with its sign bit
6225 * flipped if it is a negated-input.
6228 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6232 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6235 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6237 write_fp_sreg(s
, rd
, tcg_res
);
6239 tcg_temp_free_ptr(fpst
);
6240 tcg_temp_free_i32(tcg_op1
);
6241 tcg_temp_free_i32(tcg_op2
);
6242 tcg_temp_free_i32(tcg_op3
);
6243 tcg_temp_free_i32(tcg_res
);
6246 /* Floating-point data-processing (3 source) - double precision */
6247 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6248 int rd
, int rn
, int rm
, int ra
)
6250 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6251 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6252 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6254 tcg_op1
= read_fp_dreg(s
, rn
);
6255 tcg_op2
= read_fp_dreg(s
, rm
);
6256 tcg_op3
= read_fp_dreg(s
, ra
);
6258 /* These are fused multiply-add, and must be done as one
6259 * floating point operation with no rounding between the
6260 * multiplication and addition steps.
6261 * NB that doing the negations here as separate steps is
6262 * correct : an input NaN should come out with its sign bit
6263 * flipped if it is a negated-input.
6266 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6270 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6273 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6275 write_fp_dreg(s
, rd
, tcg_res
);
6277 tcg_temp_free_ptr(fpst
);
6278 tcg_temp_free_i64(tcg_op1
);
6279 tcg_temp_free_i64(tcg_op2
);
6280 tcg_temp_free_i64(tcg_op3
);
6281 tcg_temp_free_i64(tcg_res
);
6284 /* Floating-point data-processing (3 source) - half precision */
6285 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6286 int rd
, int rn
, int rm
, int ra
)
6288 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6289 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6290 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6292 tcg_op1
= read_fp_hreg(s
, rn
);
6293 tcg_op2
= read_fp_hreg(s
, rm
);
6294 tcg_op3
= read_fp_hreg(s
, ra
);
6296 /* These are fused multiply-add, and must be done as one
6297 * floating point operation with no rounding between the
6298 * multiplication and addition steps.
6299 * NB that doing the negations here as separate steps is
6300 * correct : an input NaN should come out with its sign bit
6301 * flipped if it is a negated-input.
6304 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6308 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6311 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6313 write_fp_sreg(s
, rd
, tcg_res
);
6315 tcg_temp_free_ptr(fpst
);
6316 tcg_temp_free_i32(tcg_op1
);
6317 tcg_temp_free_i32(tcg_op2
);
6318 tcg_temp_free_i32(tcg_op3
);
6319 tcg_temp_free_i32(tcg_res
);
6322 /* Floating point data-processing (3 source)
6323 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6324 * +---+---+---+-----------+------+----+------+----+------+------+------+
6325 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6326 * +---+---+---+-----------+------+----+------+----+------+------+------+
6328 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6330 int mos
= extract32(insn
, 29, 3);
6331 int type
= extract32(insn
, 22, 2);
6332 int rd
= extract32(insn
, 0, 5);
6333 int rn
= extract32(insn
, 5, 5);
6334 int ra
= extract32(insn
, 10, 5);
6335 int rm
= extract32(insn
, 16, 5);
6336 bool o0
= extract32(insn
, 15, 1);
6337 bool o1
= extract32(insn
, 21, 1);
6340 unallocated_encoding(s
);
6346 if (!fp_access_check(s
)) {
6349 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6352 if (!fp_access_check(s
)) {
6355 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6358 if (!dc_isar_feature(aa64_fp16
, s
)) {
6359 unallocated_encoding(s
);
6362 if (!fp_access_check(s
)) {
6365 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6368 unallocated_encoding(s
);
6372 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6373 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6374 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6376 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6382 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6383 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6384 extract32(imm8
, 0, 6);
6388 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6389 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6390 (extract32(imm8
, 0, 6) << 3);
6394 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6395 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6396 (extract32(imm8
, 0, 6) << 6);
6399 g_assert_not_reached();
6404 /* Floating point immediate
6405 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6406 * +---+---+---+-----------+------+---+------------+-------+------+------+
6407 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6408 * +---+---+---+-----------+------+---+------------+-------+------+------+
6410 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6412 int rd
= extract32(insn
, 0, 5);
6413 int imm5
= extract32(insn
, 5, 5);
6414 int imm8
= extract32(insn
, 13, 8);
6415 int type
= extract32(insn
, 22, 2);
6416 int mos
= extract32(insn
, 29, 3);
6422 unallocated_encoding(s
);
6435 if (dc_isar_feature(aa64_fp16
, s
)) {
6440 unallocated_encoding(s
);
6444 if (!fp_access_check(s
)) {
6448 imm
= vfp_expand_imm(sz
, imm8
);
6450 tcg_res
= tcg_const_i64(imm
);
6451 write_fp_dreg(s
, rd
, tcg_res
);
6452 tcg_temp_free_i64(tcg_res
);
6455 /* Handle floating point <=> fixed point conversions. Note that we can
6456 * also deal with fp <=> integer conversions as a special case (scale == 64)
6457 * OPTME: consider handling that special case specially or at least skipping
6458 * the call to scalbn in the helpers for zero shifts.
6460 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6461 bool itof
, int rmode
, int scale
, int sf
, int type
)
6463 bool is_signed
= !(opcode
& 1);
6464 TCGv_ptr tcg_fpstatus
;
6465 TCGv_i32 tcg_shift
, tcg_single
;
6466 TCGv_i64 tcg_double
;
6468 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6470 tcg_shift
= tcg_const_i32(64 - scale
);
6473 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6475 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6478 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6480 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6483 tcg_int
= tcg_extend
;
6487 case 1: /* float64 */
6488 tcg_double
= tcg_temp_new_i64();
6490 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6491 tcg_shift
, tcg_fpstatus
);
6493 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6494 tcg_shift
, tcg_fpstatus
);
6496 write_fp_dreg(s
, rd
, tcg_double
);
6497 tcg_temp_free_i64(tcg_double
);
6500 case 0: /* float32 */
6501 tcg_single
= tcg_temp_new_i32();
6503 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6504 tcg_shift
, tcg_fpstatus
);
6506 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6507 tcg_shift
, tcg_fpstatus
);
6509 write_fp_sreg(s
, rd
, tcg_single
);
6510 tcg_temp_free_i32(tcg_single
);
6513 case 3: /* float16 */
6514 tcg_single
= tcg_temp_new_i32();
6516 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6517 tcg_shift
, tcg_fpstatus
);
6519 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6520 tcg_shift
, tcg_fpstatus
);
6522 write_fp_sreg(s
, rd
, tcg_single
);
6523 tcg_temp_free_i32(tcg_single
);
6527 g_assert_not_reached();
6530 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6533 if (extract32(opcode
, 2, 1)) {
6534 /* There are too many rounding modes to all fit into rmode,
6535 * so FCVTA[US] is a special case.
6537 rmode
= FPROUNDING_TIEAWAY
;
6540 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6542 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6545 case 1: /* float64 */
6546 tcg_double
= read_fp_dreg(s
, rn
);
6549 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6550 tcg_shift
, tcg_fpstatus
);
6552 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6553 tcg_shift
, tcg_fpstatus
);
6557 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6558 tcg_shift
, tcg_fpstatus
);
6560 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6561 tcg_shift
, tcg_fpstatus
);
6565 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6567 tcg_temp_free_i64(tcg_double
);
6570 case 0: /* float32 */
6571 tcg_single
= read_fp_sreg(s
, rn
);
6574 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6575 tcg_shift
, tcg_fpstatus
);
6577 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6578 tcg_shift
, tcg_fpstatus
);
6581 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6583 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6584 tcg_shift
, tcg_fpstatus
);
6586 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6587 tcg_shift
, tcg_fpstatus
);
6589 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6590 tcg_temp_free_i32(tcg_dest
);
6592 tcg_temp_free_i32(tcg_single
);
6595 case 3: /* float16 */
6596 tcg_single
= read_fp_sreg(s
, rn
);
6599 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6600 tcg_shift
, tcg_fpstatus
);
6602 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6603 tcg_shift
, tcg_fpstatus
);
6606 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6608 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6609 tcg_shift
, tcg_fpstatus
);
6611 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6612 tcg_shift
, tcg_fpstatus
);
6614 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6615 tcg_temp_free_i32(tcg_dest
);
6617 tcg_temp_free_i32(tcg_single
);
6621 g_assert_not_reached();
6624 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6625 tcg_temp_free_i32(tcg_rmode
);
6628 tcg_temp_free_ptr(tcg_fpstatus
);
6629 tcg_temp_free_i32(tcg_shift
);
6632 /* Floating point <-> fixed point conversions
6633 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6634 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6635 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6636 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6638 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6640 int rd
= extract32(insn
, 0, 5);
6641 int rn
= extract32(insn
, 5, 5);
6642 int scale
= extract32(insn
, 10, 6);
6643 int opcode
= extract32(insn
, 16, 3);
6644 int rmode
= extract32(insn
, 19, 2);
6645 int type
= extract32(insn
, 22, 2);
6646 bool sbit
= extract32(insn
, 29, 1);
6647 bool sf
= extract32(insn
, 31, 1);
6650 if (sbit
|| (!sf
&& scale
< 32)) {
6651 unallocated_encoding(s
);
6656 case 0: /* float32 */
6657 case 1: /* float64 */
6659 case 3: /* float16 */
6660 if (dc_isar_feature(aa64_fp16
, s
)) {
6665 unallocated_encoding(s
);
6669 switch ((rmode
<< 3) | opcode
) {
6670 case 0x2: /* SCVTF */
6671 case 0x3: /* UCVTF */
6674 case 0x18: /* FCVTZS */
6675 case 0x19: /* FCVTZU */
6679 unallocated_encoding(s
);
6683 if (!fp_access_check(s
)) {
6687 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6690 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6692 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6693 * without conversion.
6697 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6703 tmp
= tcg_temp_new_i64();
6704 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6705 write_fp_dreg(s
, rd
, tmp
);
6706 tcg_temp_free_i64(tmp
);
6710 write_fp_dreg(s
, rd
, tcg_rn
);
6713 /* 64 bit to top half. */
6714 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6715 clear_vec_high(s
, true, rd
);
6719 tmp
= tcg_temp_new_i64();
6720 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6721 write_fp_dreg(s
, rd
, tmp
);
6722 tcg_temp_free_i64(tmp
);
6725 g_assert_not_reached();
6728 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6733 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6737 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6740 /* 64 bits from top half */
6741 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6745 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6748 g_assert_not_reached();
6753 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6755 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6756 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6758 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6760 tcg_temp_free_ptr(fpstatus
);
6762 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6763 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6764 tcg_gen_movi_i32(cpu_CF
, 0);
6765 tcg_gen_movi_i32(cpu_NF
, 0);
6766 tcg_gen_movi_i32(cpu_VF
, 0);
6768 tcg_temp_free_i64(t
);
6771 /* Floating point <-> integer conversions
6772 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6773 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6774 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6775 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6777 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6779 int rd
= extract32(insn
, 0, 5);
6780 int rn
= extract32(insn
, 5, 5);
6781 int opcode
= extract32(insn
, 16, 3);
6782 int rmode
= extract32(insn
, 19, 2);
6783 int type
= extract32(insn
, 22, 2);
6784 bool sbit
= extract32(insn
, 29, 1);
6785 bool sf
= extract32(insn
, 31, 1);
6789 goto do_unallocated
;
6797 case 4: /* FCVTAS */
6798 case 5: /* FCVTAU */
6800 goto do_unallocated
;
6803 case 0: /* FCVT[NPMZ]S */
6804 case 1: /* FCVT[NPMZ]U */
6806 case 0: /* float32 */
6807 case 1: /* float64 */
6809 case 3: /* float16 */
6810 if (!dc_isar_feature(aa64_fp16
, s
)) {
6811 goto do_unallocated
;
6815 goto do_unallocated
;
6817 if (!fp_access_check(s
)) {
6820 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6824 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6825 case 0b01100110: /* FMOV half <-> 32-bit int */
6827 case 0b11100110: /* FMOV half <-> 64-bit int */
6829 if (!dc_isar_feature(aa64_fp16
, s
)) {
6830 goto do_unallocated
;
6833 case 0b00000110: /* FMOV 32-bit */
6835 case 0b10100110: /* FMOV 64-bit */
6837 case 0b11001110: /* FMOV top half of 128-bit */
6839 if (!fp_access_check(s
)) {
6843 handle_fmov(s
, rd
, rn
, type
, itof
);
6846 case 0b00111110: /* FJCVTZS */
6847 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6848 goto do_unallocated
;
6849 } else if (fp_access_check(s
)) {
6850 handle_fjcvtzs(s
, rd
, rn
);
6856 unallocated_encoding(s
);
6863 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6864 * 31 30 29 28 25 24 0
6865 * +---+---+---+---------+-----------------------------+
6866 * | | 0 | | 1 1 1 1 | |
6867 * +---+---+---+---------+-----------------------------+
6869 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6871 if (extract32(insn
, 24, 1)) {
6872 /* Floating point data-processing (3 source) */
6873 disas_fp_3src(s
, insn
);
6874 } else if (extract32(insn
, 21, 1) == 0) {
6875 /* Floating point to fixed point conversions */
6876 disas_fp_fixed_conv(s
, insn
);
6878 switch (extract32(insn
, 10, 2)) {
6880 /* Floating point conditional compare */
6881 disas_fp_ccomp(s
, insn
);
6884 /* Floating point data-processing (2 source) */
6885 disas_fp_2src(s
, insn
);
6888 /* Floating point conditional select */
6889 disas_fp_csel(s
, insn
);
6892 switch (ctz32(extract32(insn
, 12, 4))) {
6893 case 0: /* [15:12] == xxx1 */
6894 /* Floating point immediate */
6895 disas_fp_imm(s
, insn
);
6897 case 1: /* [15:12] == xx10 */
6898 /* Floating point compare */
6899 disas_fp_compare(s
, insn
);
6901 case 2: /* [15:12] == x100 */
6902 /* Floating point data-processing (1 source) */
6903 disas_fp_1src(s
, insn
);
6905 case 3: /* [15:12] == 1000 */
6906 unallocated_encoding(s
);
6908 default: /* [15:12] == 0000 */
6909 /* Floating point <-> integer conversions */
6910 disas_fp_int_conv(s
, insn
);
6918 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6921 /* Extract 64 bits from the middle of two concatenated 64 bit
6922 * vector register slices left:right. The extracted bits start
6923 * at 'pos' bits into the right (least significant) side.
6924 * We return the result in tcg_right, and guarantee not to
6927 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6928 assert(pos
> 0 && pos
< 64);
6930 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6931 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6932 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6934 tcg_temp_free_i64(tcg_tmp
);
6938 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6939 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6940 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6941 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6943 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6945 int is_q
= extract32(insn
, 30, 1);
6946 int op2
= extract32(insn
, 22, 2);
6947 int imm4
= extract32(insn
, 11, 4);
6948 int rm
= extract32(insn
, 16, 5);
6949 int rn
= extract32(insn
, 5, 5);
6950 int rd
= extract32(insn
, 0, 5);
6951 int pos
= imm4
<< 3;
6952 TCGv_i64 tcg_resl
, tcg_resh
;
6954 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6955 unallocated_encoding(s
);
6959 if (!fp_access_check(s
)) {
6963 tcg_resh
= tcg_temp_new_i64();
6964 tcg_resl
= tcg_temp_new_i64();
6966 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6967 * either extracting 128 bits from a 128:128 concatenation, or
6968 * extracting 64 bits from a 64:64 concatenation.
6971 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6973 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6974 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6976 tcg_gen_movi_i64(tcg_resh
, 0);
6983 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6984 EltPosns
*elt
= eltposns
;
6991 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6993 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6996 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6997 tcg_hh
= tcg_temp_new_i64();
6998 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6999 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7000 tcg_temp_free_i64(tcg_hh
);
7004 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7005 tcg_temp_free_i64(tcg_resl
);
7006 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7007 tcg_temp_free_i64(tcg_resh
);
7011 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7012 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7013 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7014 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7016 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7018 int op2
= extract32(insn
, 22, 2);
7019 int is_q
= extract32(insn
, 30, 1);
7020 int rm
= extract32(insn
, 16, 5);
7021 int rn
= extract32(insn
, 5, 5);
7022 int rd
= extract32(insn
, 0, 5);
7023 int is_tblx
= extract32(insn
, 12, 1);
7024 int len
= extract32(insn
, 13, 2);
7025 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7026 TCGv_i32 tcg_regno
, tcg_numregs
;
7029 unallocated_encoding(s
);
7033 if (!fp_access_check(s
)) {
7037 /* This does a table lookup: for every byte element in the input
7038 * we index into a table formed from up to four vector registers,
7039 * and then the output is the result of the lookups. Our helper
7040 * function does the lookup operation for a single 64 bit part of
7043 tcg_resl
= tcg_temp_new_i64();
7044 tcg_resh
= tcg_temp_new_i64();
7047 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7049 tcg_gen_movi_i64(tcg_resl
, 0);
7051 if (is_tblx
&& is_q
) {
7052 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7054 tcg_gen_movi_i64(tcg_resh
, 0);
7057 tcg_idx
= tcg_temp_new_i64();
7058 tcg_regno
= tcg_const_i32(rn
);
7059 tcg_numregs
= tcg_const_i32(len
+ 1);
7060 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7061 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7062 tcg_regno
, tcg_numregs
);
7064 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7065 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7066 tcg_regno
, tcg_numregs
);
7068 tcg_temp_free_i64(tcg_idx
);
7069 tcg_temp_free_i32(tcg_regno
);
7070 tcg_temp_free_i32(tcg_numregs
);
7072 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7073 tcg_temp_free_i64(tcg_resl
);
7074 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7075 tcg_temp_free_i64(tcg_resh
);
7079 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7080 * +---+---+-------------+------+---+------+---+------------------+------+
7081 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7082 * +---+---+-------------+------+---+------+---+------------------+------+
7084 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7086 int rd
= extract32(insn
, 0, 5);
7087 int rn
= extract32(insn
, 5, 5);
7088 int rm
= extract32(insn
, 16, 5);
7089 int size
= extract32(insn
, 22, 2);
7090 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7091 * bit 2 indicates 1 vs 2 variant of the insn.
7093 int opcode
= extract32(insn
, 12, 2);
7094 bool part
= extract32(insn
, 14, 1);
7095 bool is_q
= extract32(insn
, 30, 1);
7096 int esize
= 8 << size
;
7098 int datasize
= is_q
? 128 : 64;
7099 int elements
= datasize
/ esize
;
7100 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7102 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7103 unallocated_encoding(s
);
7107 if (!fp_access_check(s
)) {
7111 tcg_resl
= tcg_const_i64(0);
7112 tcg_resh
= tcg_const_i64(0);
7113 tcg_res
= tcg_temp_new_i64();
7115 for (i
= 0; i
< elements
; i
++) {
7117 case 1: /* UZP1/2 */
7119 int midpoint
= elements
/ 2;
7121 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7123 read_vec_element(s
, tcg_res
, rm
,
7124 2 * (i
- midpoint
) + part
, size
);
7128 case 2: /* TRN1/2 */
7130 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7132 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7135 case 3: /* ZIP1/2 */
7137 int base
= part
* elements
/ 2;
7139 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7141 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7146 g_assert_not_reached();
7151 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7152 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7154 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7155 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7159 tcg_temp_free_i64(tcg_res
);
7161 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7162 tcg_temp_free_i64(tcg_resl
);
7163 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7164 tcg_temp_free_i64(tcg_resh
);
7168 * do_reduction_op helper
7170 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7171 * important for correct NaN propagation that we do these
7172 * operations in exactly the order specified by the pseudocode.
7174 * This is a recursive function, TCG temps should be freed by the
7175 * calling function once it is done with the values.
7177 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7178 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7180 if (esize
== size
) {
7182 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7185 /* We should have one register left here */
7186 assert(ctpop8(vmap
) == 1);
7187 element
= ctz32(vmap
);
7188 assert(element
< 8);
7190 tcg_elem
= tcg_temp_new_i32();
7191 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7194 int bits
= size
/ 2;
7195 int shift
= ctpop8(vmap
) / 2;
7196 int vmap_lo
= (vmap
>> shift
) & vmap
;
7197 int vmap_hi
= (vmap
& ~vmap_lo
);
7198 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7200 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7201 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7202 tcg_res
= tcg_temp_new_i32();
7205 case 0x0c: /* fmaxnmv half-precision */
7206 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7208 case 0x0f: /* fmaxv half-precision */
7209 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7211 case 0x1c: /* fminnmv half-precision */
7212 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7214 case 0x1f: /* fminv half-precision */
7215 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7217 case 0x2c: /* fmaxnmv */
7218 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7220 case 0x2f: /* fmaxv */
7221 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7223 case 0x3c: /* fminnmv */
7224 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7226 case 0x3f: /* fminv */
7227 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7230 g_assert_not_reached();
7233 tcg_temp_free_i32(tcg_hi
);
7234 tcg_temp_free_i32(tcg_lo
);
7239 /* AdvSIMD across lanes
7240 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7241 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7242 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7243 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7245 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7247 int rd
= extract32(insn
, 0, 5);
7248 int rn
= extract32(insn
, 5, 5);
7249 int size
= extract32(insn
, 22, 2);
7250 int opcode
= extract32(insn
, 12, 5);
7251 bool is_q
= extract32(insn
, 30, 1);
7252 bool is_u
= extract32(insn
, 29, 1);
7254 bool is_min
= false;
7258 TCGv_i64 tcg_res
, tcg_elt
;
7261 case 0x1b: /* ADDV */
7263 unallocated_encoding(s
);
7267 case 0x3: /* SADDLV, UADDLV */
7268 case 0xa: /* SMAXV, UMAXV */
7269 case 0x1a: /* SMINV, UMINV */
7270 if (size
== 3 || (size
== 2 && !is_q
)) {
7271 unallocated_encoding(s
);
7275 case 0xc: /* FMAXNMV, FMINNMV */
7276 case 0xf: /* FMAXV, FMINV */
7277 /* Bit 1 of size field encodes min vs max and the actual size
7278 * depends on the encoding of the U bit. If not set (and FP16
7279 * enabled) then we do half-precision float instead of single
7282 is_min
= extract32(size
, 1, 1);
7284 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7286 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7287 unallocated_encoding(s
);
7294 unallocated_encoding(s
);
7298 if (!fp_access_check(s
)) {
7303 elements
= (is_q
? 128 : 64) / esize
;
7305 tcg_res
= tcg_temp_new_i64();
7306 tcg_elt
= tcg_temp_new_i64();
7308 /* These instructions operate across all lanes of a vector
7309 * to produce a single result. We can guarantee that a 64
7310 * bit intermediate is sufficient:
7311 * + for [US]ADDLV the maximum element size is 32 bits, and
7312 * the result type is 64 bits
7313 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7314 * same as the element size, which is 32 bits at most
7315 * For the integer operations we can choose to work at 64
7316 * or 32 bits and truncate at the end; for simplicity
7317 * we use 64 bits always. The floating point
7318 * ops do require 32 bit intermediates, though.
7321 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7323 for (i
= 1; i
< elements
; i
++) {
7324 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7327 case 0x03: /* SADDLV / UADDLV */
7328 case 0x1b: /* ADDV */
7329 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7331 case 0x0a: /* SMAXV / UMAXV */
7333 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7335 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7338 case 0x1a: /* SMINV / UMINV */
7340 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7342 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7346 g_assert_not_reached();
7351 /* Floating point vector reduction ops which work across 32
7352 * bit (single) or 16 bit (half-precision) intermediates.
7353 * Note that correct NaN propagation requires that we do these
7354 * operations in exactly the order specified by the pseudocode.
7356 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7357 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7358 int vmap
= (1 << elements
) - 1;
7359 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7360 (is_q
? 128 : 64), vmap
, fpst
);
7361 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7362 tcg_temp_free_i32(tcg_res32
);
7363 tcg_temp_free_ptr(fpst
);
7366 tcg_temp_free_i64(tcg_elt
);
7368 /* Now truncate the result to the width required for the final output */
7369 if (opcode
== 0x03) {
7370 /* SADDLV, UADDLV: result is 2*esize */
7376 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7379 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7382 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7387 g_assert_not_reached();
7390 write_fp_dreg(s
, rd
, tcg_res
);
7391 tcg_temp_free_i64(tcg_res
);
7394 /* DUP (Element, Vector)
7396 * 31 30 29 21 20 16 15 10 9 5 4 0
7397 * +---+---+-------------------+--------+-------------+------+------+
7398 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7399 * +---+---+-------------------+--------+-------------+------+------+
7401 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7403 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7406 int size
= ctz32(imm5
);
7407 int index
= imm5
>> (size
+ 1);
7409 if (size
> 3 || (size
== 3 && !is_q
)) {
7410 unallocated_encoding(s
);
7414 if (!fp_access_check(s
)) {
7418 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7419 vec_reg_offset(s
, rn
, index
, size
),
7420 is_q
? 16 : 8, vec_full_reg_size(s
));
7423 /* DUP (element, scalar)
7424 * 31 21 20 16 15 10 9 5 4 0
7425 * +-----------------------+--------+-------------+------+------+
7426 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7427 * +-----------------------+--------+-------------+------+------+
7429 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7432 int size
= ctz32(imm5
);
7437 unallocated_encoding(s
);
7441 if (!fp_access_check(s
)) {
7445 index
= imm5
>> (size
+ 1);
7447 /* This instruction just extracts the specified element and
7448 * zero-extends it into the bottom of the destination register.
7450 tmp
= tcg_temp_new_i64();
7451 read_vec_element(s
, tmp
, rn
, index
, size
);
7452 write_fp_dreg(s
, rd
, tmp
);
7453 tcg_temp_free_i64(tmp
);
7458 * 31 30 29 21 20 16 15 10 9 5 4 0
7459 * +---+---+-------------------+--------+-------------+------+------+
7460 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7461 * +---+---+-------------------+--------+-------------+------+------+
7463 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7465 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7468 int size
= ctz32(imm5
);
7469 uint32_t dofs
, oprsz
, maxsz
;
7471 if (size
> 3 || ((size
== 3) && !is_q
)) {
7472 unallocated_encoding(s
);
7476 if (!fp_access_check(s
)) {
7480 dofs
= vec_full_reg_offset(s
, rd
);
7481 oprsz
= is_q
? 16 : 8;
7482 maxsz
= vec_full_reg_size(s
);
7484 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7489 * 31 21 20 16 15 14 11 10 9 5 4 0
7490 * +-----------------------+--------+------------+---+------+------+
7491 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7492 * +-----------------------+--------+------------+---+------+------+
7494 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7495 * index: encoded in imm5<4:size+1>
7497 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7500 int size
= ctz32(imm5
);
7501 int src_index
, dst_index
;
7505 unallocated_encoding(s
);
7509 if (!fp_access_check(s
)) {
7513 dst_index
= extract32(imm5
, 1+size
, 5);
7514 src_index
= extract32(imm4
, size
, 4);
7516 tmp
= tcg_temp_new_i64();
7518 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7519 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7521 tcg_temp_free_i64(tmp
);
7527 * 31 21 20 16 15 10 9 5 4 0
7528 * +-----------------------+--------+-------------+------+------+
7529 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7530 * +-----------------------+--------+-------------+------+------+
7532 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7533 * index: encoded in imm5<4:size+1>
7535 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7537 int size
= ctz32(imm5
);
7541 unallocated_encoding(s
);
7545 if (!fp_access_check(s
)) {
7549 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7550 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7557 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7558 * +---+---+-------------------+--------+-------------+------+------+
7559 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7560 * +---+---+-------------------+--------+-------------+------+------+
7562 * U: unsigned when set
7563 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7565 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7566 int rn
, int rd
, int imm5
)
7568 int size
= ctz32(imm5
);
7572 /* Check for UnallocatedEncodings */
7574 if (size
> 2 || (size
== 2 && !is_q
)) {
7575 unallocated_encoding(s
);
7580 || (size
< 3 && is_q
)
7581 || (size
== 3 && !is_q
)) {
7582 unallocated_encoding(s
);
7587 if (!fp_access_check(s
)) {
7591 element
= extract32(imm5
, 1+size
, 4);
7593 tcg_rd
= cpu_reg(s
, rd
);
7594 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7595 if (is_signed
&& !is_q
) {
7596 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7601 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7602 * +---+---+----+-----------------+------+---+------+---+------+------+
7603 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7604 * +---+---+----+-----------------+------+---+------+---+------+------+
7606 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7608 int rd
= extract32(insn
, 0, 5);
7609 int rn
= extract32(insn
, 5, 5);
7610 int imm4
= extract32(insn
, 11, 4);
7611 int op
= extract32(insn
, 29, 1);
7612 int is_q
= extract32(insn
, 30, 1);
7613 int imm5
= extract32(insn
, 16, 5);
7618 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7620 unallocated_encoding(s
);
7625 /* DUP (element - vector) */
7626 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7630 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7635 handle_simd_insg(s
, rd
, rn
, imm5
);
7637 unallocated_encoding(s
);
7642 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7643 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7646 unallocated_encoding(s
);
7652 /* AdvSIMD modified immediate
7653 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7654 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7655 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7656 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7658 * There are a number of operations that can be carried out here:
7659 * MOVI - move (shifted) imm into register
7660 * MVNI - move inverted (shifted) imm into register
7661 * ORR - bitwise OR of (shifted) imm with register
7662 * BIC - bitwise clear of (shifted) imm with register
7663 * With ARMv8.2 we also have:
7664 * FMOV half-precision
7666 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7668 int rd
= extract32(insn
, 0, 5);
7669 int cmode
= extract32(insn
, 12, 4);
7670 int cmode_3_1
= extract32(cmode
, 1, 3);
7671 int cmode_0
= extract32(cmode
, 0, 1);
7672 int o2
= extract32(insn
, 11, 1);
7673 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7674 bool is_neg
= extract32(insn
, 29, 1);
7675 bool is_q
= extract32(insn
, 30, 1);
7678 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7679 /* Check for FMOV (vector, immediate) - half-precision */
7680 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7681 unallocated_encoding(s
);
7686 if (!fp_access_check(s
)) {
7690 /* See AdvSIMDExpandImm() in ARM ARM */
7691 switch (cmode_3_1
) {
7692 case 0: /* Replicate(Zeros(24):imm8, 2) */
7693 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7694 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7695 case 3: /* Replicate(imm8:Zeros(24), 2) */
7697 int shift
= cmode_3_1
* 8;
7698 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7701 case 4: /* Replicate(Zeros(8):imm8, 4) */
7702 case 5: /* Replicate(imm8:Zeros(8), 4) */
7704 int shift
= (cmode_3_1
& 0x1) * 8;
7705 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7710 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7711 imm
= (abcdefgh
<< 16) | 0xffff;
7713 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7714 imm
= (abcdefgh
<< 8) | 0xff;
7716 imm
= bitfield_replicate(imm
, 32);
7719 if (!cmode_0
&& !is_neg
) {
7720 imm
= bitfield_replicate(abcdefgh
, 8);
7721 } else if (!cmode_0
&& is_neg
) {
7724 for (i
= 0; i
< 8; i
++) {
7725 if ((abcdefgh
) & (1 << i
)) {
7726 imm
|= 0xffULL
<< (i
* 8);
7729 } else if (cmode_0
) {
7731 imm
= (abcdefgh
& 0x3f) << 48;
7732 if (abcdefgh
& 0x80) {
7733 imm
|= 0x8000000000000000ULL
;
7735 if (abcdefgh
& 0x40) {
7736 imm
|= 0x3fc0000000000000ULL
;
7738 imm
|= 0x4000000000000000ULL
;
7742 /* FMOV (vector, immediate) - half-precision */
7743 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7744 /* now duplicate across the lanes */
7745 imm
= bitfield_replicate(imm
, 16);
7747 imm
= (abcdefgh
& 0x3f) << 19;
7748 if (abcdefgh
& 0x80) {
7751 if (abcdefgh
& 0x40) {
7762 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7763 g_assert_not_reached();
7766 if (cmode_3_1
!= 7 && is_neg
) {
7770 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7771 /* MOVI or MVNI, with MVNI negation handled above. */
7772 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7773 vec_full_reg_size(s
), imm
);
7775 /* ORR or BIC, with BIC negation to AND handled above. */
7777 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7779 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7784 /* AdvSIMD scalar copy
7785 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7786 * +-----+----+-----------------+------+---+------+---+------+------+
7787 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7788 * +-----+----+-----------------+------+---+------+---+------+------+
7790 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7792 int rd
= extract32(insn
, 0, 5);
7793 int rn
= extract32(insn
, 5, 5);
7794 int imm4
= extract32(insn
, 11, 4);
7795 int imm5
= extract32(insn
, 16, 5);
7796 int op
= extract32(insn
, 29, 1);
7798 if (op
!= 0 || imm4
!= 0) {
7799 unallocated_encoding(s
);
7803 /* DUP (element, scalar) */
7804 handle_simd_dupes(s
, rd
, rn
, imm5
);
7807 /* AdvSIMD scalar pairwise
7808 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7809 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7810 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7811 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7813 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7815 int u
= extract32(insn
, 29, 1);
7816 int size
= extract32(insn
, 22, 2);
7817 int opcode
= extract32(insn
, 12, 5);
7818 int rn
= extract32(insn
, 5, 5);
7819 int rd
= extract32(insn
, 0, 5);
7822 /* For some ops (the FP ones), size[1] is part of the encoding.
7823 * For ADDP strictly it is not but size[1] is always 1 for valid
7826 opcode
|= (extract32(size
, 1, 1) << 5);
7829 case 0x3b: /* ADDP */
7830 if (u
|| size
!= 3) {
7831 unallocated_encoding(s
);
7834 if (!fp_access_check(s
)) {
7840 case 0xc: /* FMAXNMP */
7841 case 0xd: /* FADDP */
7842 case 0xf: /* FMAXP */
7843 case 0x2c: /* FMINNMP */
7844 case 0x2f: /* FMINP */
7845 /* FP op, size[0] is 32 or 64 bit*/
7847 if (!dc_isar_feature(aa64_fp16
, s
)) {
7848 unallocated_encoding(s
);
7854 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7857 if (!fp_access_check(s
)) {
7861 fpst
= get_fpstatus_ptr(size
== MO_16
);
7864 unallocated_encoding(s
);
7868 if (size
== MO_64
) {
7869 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7870 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7871 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7873 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7874 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7877 case 0x3b: /* ADDP */
7878 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7880 case 0xc: /* FMAXNMP */
7881 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7883 case 0xd: /* FADDP */
7884 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7886 case 0xf: /* FMAXP */
7887 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7889 case 0x2c: /* FMINNMP */
7890 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7892 case 0x2f: /* FMINP */
7893 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7896 g_assert_not_reached();
7899 write_fp_dreg(s
, rd
, tcg_res
);
7901 tcg_temp_free_i64(tcg_op1
);
7902 tcg_temp_free_i64(tcg_op2
);
7903 tcg_temp_free_i64(tcg_res
);
7905 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7906 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7907 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7909 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7910 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7912 if (size
== MO_16
) {
7914 case 0xc: /* FMAXNMP */
7915 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7917 case 0xd: /* FADDP */
7918 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7920 case 0xf: /* FMAXP */
7921 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7923 case 0x2c: /* FMINNMP */
7924 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7926 case 0x2f: /* FMINP */
7927 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7930 g_assert_not_reached();
7934 case 0xc: /* FMAXNMP */
7935 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7937 case 0xd: /* FADDP */
7938 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7940 case 0xf: /* FMAXP */
7941 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7943 case 0x2c: /* FMINNMP */
7944 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7946 case 0x2f: /* FMINP */
7947 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7950 g_assert_not_reached();
7954 write_fp_sreg(s
, rd
, tcg_res
);
7956 tcg_temp_free_i32(tcg_op1
);
7957 tcg_temp_free_i32(tcg_op2
);
7958 tcg_temp_free_i32(tcg_res
);
7962 tcg_temp_free_ptr(fpst
);
7967 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7969 * This code is handles the common shifting code and is used by both
7970 * the vector and scalar code.
7972 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7973 TCGv_i64 tcg_rnd
, bool accumulate
,
7974 bool is_u
, int size
, int shift
)
7976 bool extended_result
= false;
7977 bool round
= tcg_rnd
!= NULL
;
7979 TCGv_i64 tcg_src_hi
;
7981 if (round
&& size
== 3) {
7982 extended_result
= true;
7983 ext_lshift
= 64 - shift
;
7984 tcg_src_hi
= tcg_temp_new_i64();
7985 } else if (shift
== 64) {
7986 if (!accumulate
&& is_u
) {
7987 /* result is zero */
7988 tcg_gen_movi_i64(tcg_res
, 0);
7993 /* Deal with the rounding step */
7995 if (extended_result
) {
7996 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7998 /* take care of sign extending tcg_res */
7999 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8000 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8001 tcg_src
, tcg_src_hi
,
8004 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8008 tcg_temp_free_i64(tcg_zero
);
8010 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8014 /* Now do the shift right */
8015 if (round
&& extended_result
) {
8016 /* extended case, >64 bit precision required */
8017 if (ext_lshift
== 0) {
8018 /* special case, only high bits matter */
8019 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8021 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8022 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8023 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8028 /* essentially shifting in 64 zeros */
8029 tcg_gen_movi_i64(tcg_src
, 0);
8031 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8035 /* effectively extending the sign-bit */
8036 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8038 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8044 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8046 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8049 if (extended_result
) {
8050 tcg_temp_free_i64(tcg_src_hi
);
8054 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8055 static void handle_scalar_simd_shri(DisasContext
*s
,
8056 bool is_u
, int immh
, int immb
,
8057 int opcode
, int rn
, int rd
)
8060 int immhb
= immh
<< 3 | immb
;
8061 int shift
= 2 * (8 << size
) - immhb
;
8062 bool accumulate
= false;
8064 bool insert
= false;
8069 if (!extract32(immh
, 3, 1)) {
8070 unallocated_encoding(s
);
8074 if (!fp_access_check(s
)) {
8079 case 0x02: /* SSRA / USRA (accumulate) */
8082 case 0x04: /* SRSHR / URSHR (rounding) */
8085 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8086 accumulate
= round
= true;
8088 case 0x08: /* SRI */
8094 uint64_t round_const
= 1ULL << (shift
- 1);
8095 tcg_round
= tcg_const_i64(round_const
);
8100 tcg_rn
= read_fp_dreg(s
, rn
);
8101 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8104 /* shift count same as element size is valid but does nothing;
8105 * special case to avoid potential shift by 64.
8107 int esize
= 8 << size
;
8108 if (shift
!= esize
) {
8109 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8110 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8113 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8114 accumulate
, is_u
, size
, shift
);
8117 write_fp_dreg(s
, rd
, tcg_rd
);
8119 tcg_temp_free_i64(tcg_rn
);
8120 tcg_temp_free_i64(tcg_rd
);
8122 tcg_temp_free_i64(tcg_round
);
8126 /* SHL/SLI - Scalar shift left */
8127 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8128 int immh
, int immb
, int opcode
,
8131 int size
= 32 - clz32(immh
) - 1;
8132 int immhb
= immh
<< 3 | immb
;
8133 int shift
= immhb
- (8 << size
);
8134 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8135 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8137 if (!extract32(immh
, 3, 1)) {
8138 unallocated_encoding(s
);
8142 if (!fp_access_check(s
)) {
8146 tcg_rn
= read_fp_dreg(s
, rn
);
8147 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8150 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8152 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8155 write_fp_dreg(s
, rd
, tcg_rd
);
8157 tcg_temp_free_i64(tcg_rn
);
8158 tcg_temp_free_i64(tcg_rd
);
8161 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8162 * (signed/unsigned) narrowing */
8163 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8164 bool is_u_shift
, bool is_u_narrow
,
8165 int immh
, int immb
, int opcode
,
8168 int immhb
= immh
<< 3 | immb
;
8169 int size
= 32 - clz32(immh
) - 1;
8170 int esize
= 8 << size
;
8171 int shift
= (2 * esize
) - immhb
;
8172 int elements
= is_scalar
? 1 : (64 / esize
);
8173 bool round
= extract32(opcode
, 0, 1);
8174 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8175 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8176 TCGv_i32 tcg_rd_narrowed
;
8179 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8180 { gen_helper_neon_narrow_sat_s8
,
8181 gen_helper_neon_unarrow_sat8
},
8182 { gen_helper_neon_narrow_sat_s16
,
8183 gen_helper_neon_unarrow_sat16
},
8184 { gen_helper_neon_narrow_sat_s32
,
8185 gen_helper_neon_unarrow_sat32
},
8188 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8189 gen_helper_neon_narrow_sat_u8
,
8190 gen_helper_neon_narrow_sat_u16
,
8191 gen_helper_neon_narrow_sat_u32
,
8194 NeonGenNarrowEnvFn
*narrowfn
;
8200 if (extract32(immh
, 3, 1)) {
8201 unallocated_encoding(s
);
8205 if (!fp_access_check(s
)) {
8210 narrowfn
= unsigned_narrow_fns
[size
];
8212 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8215 tcg_rn
= tcg_temp_new_i64();
8216 tcg_rd
= tcg_temp_new_i64();
8217 tcg_rd_narrowed
= tcg_temp_new_i32();
8218 tcg_final
= tcg_const_i64(0);
8221 uint64_t round_const
= 1ULL << (shift
- 1);
8222 tcg_round
= tcg_const_i64(round_const
);
8227 for (i
= 0; i
< elements
; i
++) {
8228 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8229 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8230 false, is_u_shift
, size
+1, shift
);
8231 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8232 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8233 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8237 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8239 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8243 tcg_temp_free_i64(tcg_round
);
8245 tcg_temp_free_i64(tcg_rn
);
8246 tcg_temp_free_i64(tcg_rd
);
8247 tcg_temp_free_i32(tcg_rd_narrowed
);
8248 tcg_temp_free_i64(tcg_final
);
8250 clear_vec_high(s
, is_q
, rd
);
8253 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8254 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8255 bool src_unsigned
, bool dst_unsigned
,
8256 int immh
, int immb
, int rn
, int rd
)
8258 int immhb
= immh
<< 3 | immb
;
8259 int size
= 32 - clz32(immh
) - 1;
8260 int shift
= immhb
- (8 << size
);
8264 assert(!(scalar
&& is_q
));
8267 if (!is_q
&& extract32(immh
, 3, 1)) {
8268 unallocated_encoding(s
);
8272 /* Since we use the variable-shift helpers we must
8273 * replicate the shift count into each element of
8274 * the tcg_shift value.
8278 shift
|= shift
<< 8;
8281 shift
|= shift
<< 16;
8287 g_assert_not_reached();
8291 if (!fp_access_check(s
)) {
8296 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8297 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8298 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8299 { NULL
, gen_helper_neon_qshl_u64
},
8301 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8302 int maxpass
= is_q
? 2 : 1;
8304 for (pass
= 0; pass
< maxpass
; pass
++) {
8305 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8307 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8308 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8309 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8311 tcg_temp_free_i64(tcg_op
);
8313 tcg_temp_free_i64(tcg_shift
);
8314 clear_vec_high(s
, is_q
, rd
);
8316 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8317 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8319 { gen_helper_neon_qshl_s8
,
8320 gen_helper_neon_qshl_s16
,
8321 gen_helper_neon_qshl_s32
},
8322 { gen_helper_neon_qshlu_s8
,
8323 gen_helper_neon_qshlu_s16
,
8324 gen_helper_neon_qshlu_s32
}
8326 { NULL
, NULL
, NULL
},
8327 { gen_helper_neon_qshl_u8
,
8328 gen_helper_neon_qshl_u16
,
8329 gen_helper_neon_qshl_u32
}
8332 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8333 TCGMemOp memop
= scalar
? size
: MO_32
;
8334 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8336 for (pass
= 0; pass
< maxpass
; pass
++) {
8337 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8339 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8340 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8344 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8347 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8352 g_assert_not_reached();
8354 write_fp_sreg(s
, rd
, tcg_op
);
8356 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8359 tcg_temp_free_i32(tcg_op
);
8361 tcg_temp_free_i32(tcg_shift
);
8364 clear_vec_high(s
, is_q
, rd
);
8369 /* Common vector code for handling integer to FP conversion */
8370 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8371 int elements
, int is_signed
,
8372 int fracbits
, int size
)
8374 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8375 TCGv_i32 tcg_shift
= NULL
;
8377 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8380 if (fracbits
|| size
== MO_64
) {
8381 tcg_shift
= tcg_const_i32(fracbits
);
8384 if (size
== MO_64
) {
8385 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8386 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8388 for (pass
= 0; pass
< elements
; pass
++) {
8389 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8392 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8393 tcg_shift
, tcg_fpst
);
8395 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8396 tcg_shift
, tcg_fpst
);
8398 if (elements
== 1) {
8399 write_fp_dreg(s
, rd
, tcg_double
);
8401 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8405 tcg_temp_free_i64(tcg_int64
);
8406 tcg_temp_free_i64(tcg_double
);
8409 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8410 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8412 for (pass
= 0; pass
< elements
; pass
++) {
8413 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8419 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8420 tcg_shift
, tcg_fpst
);
8422 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8423 tcg_shift
, tcg_fpst
);
8427 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8429 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8436 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8437 tcg_shift
, tcg_fpst
);
8439 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8440 tcg_shift
, tcg_fpst
);
8444 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8446 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8451 g_assert_not_reached();
8454 if (elements
== 1) {
8455 write_fp_sreg(s
, rd
, tcg_float
);
8457 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8461 tcg_temp_free_i32(tcg_int32
);
8462 tcg_temp_free_i32(tcg_float
);
8465 tcg_temp_free_ptr(tcg_fpst
);
8467 tcg_temp_free_i32(tcg_shift
);
8470 clear_vec_high(s
, elements
<< size
== 16, rd
);
8473 /* UCVTF/SCVTF - Integer to FP conversion */
8474 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8475 bool is_q
, bool is_u
,
8476 int immh
, int immb
, int opcode
,
8479 int size
, elements
, fracbits
;
8480 int immhb
= immh
<< 3 | immb
;
8484 if (!is_scalar
&& !is_q
) {
8485 unallocated_encoding(s
);
8488 } else if (immh
& 4) {
8490 } else if (immh
& 2) {
8492 if (!dc_isar_feature(aa64_fp16
, s
)) {
8493 unallocated_encoding(s
);
8497 /* immh == 0 would be a failure of the decode logic */
8498 g_assert(immh
== 1);
8499 unallocated_encoding(s
);
8506 elements
= (8 << is_q
) >> size
;
8508 fracbits
= (16 << size
) - immhb
;
8510 if (!fp_access_check(s
)) {
8514 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8517 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8518 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8519 bool is_q
, bool is_u
,
8520 int immh
, int immb
, int rn
, int rd
)
8522 int immhb
= immh
<< 3 | immb
;
8523 int pass
, size
, fracbits
;
8524 TCGv_ptr tcg_fpstatus
;
8525 TCGv_i32 tcg_rmode
, tcg_shift
;
8529 if (!is_scalar
&& !is_q
) {
8530 unallocated_encoding(s
);
8533 } else if (immh
& 0x4) {
8535 } else if (immh
& 0x2) {
8537 if (!dc_isar_feature(aa64_fp16
, s
)) {
8538 unallocated_encoding(s
);
8542 /* Should have split out AdvSIMD modified immediate earlier. */
8544 unallocated_encoding(s
);
8548 if (!fp_access_check(s
)) {
8552 assert(!(is_scalar
&& is_q
));
8554 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8555 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8556 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8557 fracbits
= (16 << size
) - immhb
;
8558 tcg_shift
= tcg_const_i32(fracbits
);
8560 if (size
== MO_64
) {
8561 int maxpass
= is_scalar
? 1 : 2;
8563 for (pass
= 0; pass
< maxpass
; pass
++) {
8564 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8566 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8568 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8570 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8572 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8573 tcg_temp_free_i64(tcg_op
);
8575 clear_vec_high(s
, is_q
, rd
);
8577 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8578 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8583 fn
= gen_helper_vfp_touhh
;
8585 fn
= gen_helper_vfp_toshh
;
8590 fn
= gen_helper_vfp_touls
;
8592 fn
= gen_helper_vfp_tosls
;
8596 g_assert_not_reached();
8599 for (pass
= 0; pass
< maxpass
; pass
++) {
8600 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8602 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8603 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8605 write_fp_sreg(s
, rd
, tcg_op
);
8607 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8609 tcg_temp_free_i32(tcg_op
);
8612 clear_vec_high(s
, is_q
, rd
);
8616 tcg_temp_free_ptr(tcg_fpstatus
);
8617 tcg_temp_free_i32(tcg_shift
);
8618 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8619 tcg_temp_free_i32(tcg_rmode
);
8622 /* AdvSIMD scalar shift by immediate
8623 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8624 * +-----+---+-------------+------+------+--------+---+------+------+
8625 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8626 * +-----+---+-------------+------+------+--------+---+------+------+
8628 * This is the scalar version so it works on a fixed sized registers
8630 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8632 int rd
= extract32(insn
, 0, 5);
8633 int rn
= extract32(insn
, 5, 5);
8634 int opcode
= extract32(insn
, 11, 5);
8635 int immb
= extract32(insn
, 16, 3);
8636 int immh
= extract32(insn
, 19, 4);
8637 bool is_u
= extract32(insn
, 29, 1);
8640 unallocated_encoding(s
);
8645 case 0x08: /* SRI */
8647 unallocated_encoding(s
);
8651 case 0x00: /* SSHR / USHR */
8652 case 0x02: /* SSRA / USRA */
8653 case 0x04: /* SRSHR / URSHR */
8654 case 0x06: /* SRSRA / URSRA */
8655 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8657 case 0x0a: /* SHL / SLI */
8658 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8660 case 0x1c: /* SCVTF, UCVTF */
8661 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8664 case 0x10: /* SQSHRUN, SQSHRUN2 */
8665 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8667 unallocated_encoding(s
);
8670 handle_vec_simd_sqshrn(s
, true, false, false, true,
8671 immh
, immb
, opcode
, rn
, rd
);
8673 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8674 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8675 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8676 immh
, immb
, opcode
, rn
, rd
);
8678 case 0xc: /* SQSHLU */
8680 unallocated_encoding(s
);
8683 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8685 case 0xe: /* SQSHL, UQSHL */
8686 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8688 case 0x1f: /* FCVTZS, FCVTZU */
8689 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8692 unallocated_encoding(s
);
8697 /* AdvSIMD scalar three different
8698 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8699 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8700 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8701 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8703 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8705 bool is_u
= extract32(insn
, 29, 1);
8706 int size
= extract32(insn
, 22, 2);
8707 int opcode
= extract32(insn
, 12, 4);
8708 int rm
= extract32(insn
, 16, 5);
8709 int rn
= extract32(insn
, 5, 5);
8710 int rd
= extract32(insn
, 0, 5);
8713 unallocated_encoding(s
);
8718 case 0x9: /* SQDMLAL, SQDMLAL2 */
8719 case 0xb: /* SQDMLSL, SQDMLSL2 */
8720 case 0xd: /* SQDMULL, SQDMULL2 */
8721 if (size
== 0 || size
== 3) {
8722 unallocated_encoding(s
);
8727 unallocated_encoding(s
);
8731 if (!fp_access_check(s
)) {
8736 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8737 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8738 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8740 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8741 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8743 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8744 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8747 case 0xd: /* SQDMULL, SQDMULL2 */
8749 case 0xb: /* SQDMLSL, SQDMLSL2 */
8750 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8752 case 0x9: /* SQDMLAL, SQDMLAL2 */
8753 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8754 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8758 g_assert_not_reached();
8761 write_fp_dreg(s
, rd
, tcg_res
);
8763 tcg_temp_free_i64(tcg_op1
);
8764 tcg_temp_free_i64(tcg_op2
);
8765 tcg_temp_free_i64(tcg_res
);
8767 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8768 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8769 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8771 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8772 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8775 case 0xd: /* SQDMULL, SQDMULL2 */
8777 case 0xb: /* SQDMLSL, SQDMLSL2 */
8778 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8780 case 0x9: /* SQDMLAL, SQDMLAL2 */
8782 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8783 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8784 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8786 tcg_temp_free_i64(tcg_op3
);
8790 g_assert_not_reached();
8793 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8794 write_fp_dreg(s
, rd
, tcg_res
);
8796 tcg_temp_free_i32(tcg_op1
);
8797 tcg_temp_free_i32(tcg_op2
);
8798 tcg_temp_free_i64(tcg_res
);
8802 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8803 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8805 /* Handle 64x64->64 opcodes which are shared between the scalar
8806 * and vector 3-same groups. We cover every opcode where size == 3
8807 * is valid in either the three-reg-same (integer, not pairwise)
8808 * or scalar-three-reg-same groups.
8813 case 0x1: /* SQADD */
8815 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8817 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8820 case 0x5: /* SQSUB */
8822 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8824 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8827 case 0x6: /* CMGT, CMHI */
8828 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8829 * We implement this using setcond (test) and then negating.
8831 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8833 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8834 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8836 case 0x7: /* CMGE, CMHS */
8837 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8839 case 0x11: /* CMTST, CMEQ */
8844 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8846 case 0x8: /* SSHL, USHL */
8848 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8850 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8853 case 0x9: /* SQSHL, UQSHL */
8855 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8857 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8860 case 0xa: /* SRSHL, URSHL */
8862 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8864 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8867 case 0xb: /* SQRSHL, UQRSHL */
8869 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8871 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8874 case 0x10: /* ADD, SUB */
8876 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8878 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8882 g_assert_not_reached();
8886 /* Handle the 3-same-operands float operations; shared by the scalar
8887 * and vector encodings. The caller must filter out any encodings
8888 * not allocated for the encoding it is dealing with.
8890 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8891 int fpopcode
, int rd
, int rn
, int rm
)
8894 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8896 for (pass
= 0; pass
< elements
; pass
++) {
8899 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8900 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8901 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8903 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8904 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8907 case 0x39: /* FMLS */
8908 /* As usual for ARM, separate negation for fused multiply-add */
8909 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8911 case 0x19: /* FMLA */
8912 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8913 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8916 case 0x18: /* FMAXNM */
8917 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8919 case 0x1a: /* FADD */
8920 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8922 case 0x1b: /* FMULX */
8923 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8925 case 0x1c: /* FCMEQ */
8926 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8928 case 0x1e: /* FMAX */
8929 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8931 case 0x1f: /* FRECPS */
8932 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8934 case 0x38: /* FMINNM */
8935 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8937 case 0x3a: /* FSUB */
8938 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8940 case 0x3e: /* FMIN */
8941 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8943 case 0x3f: /* FRSQRTS */
8944 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8946 case 0x5b: /* FMUL */
8947 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8949 case 0x5c: /* FCMGE */
8950 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8952 case 0x5d: /* FACGE */
8953 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8955 case 0x5f: /* FDIV */
8956 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8958 case 0x7a: /* FABD */
8959 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8960 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8962 case 0x7c: /* FCMGT */
8963 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8965 case 0x7d: /* FACGT */
8966 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8969 g_assert_not_reached();
8972 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8974 tcg_temp_free_i64(tcg_res
);
8975 tcg_temp_free_i64(tcg_op1
);
8976 tcg_temp_free_i64(tcg_op2
);
8979 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8980 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8981 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8983 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8984 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8987 case 0x39: /* FMLS */
8988 /* As usual for ARM, separate negation for fused multiply-add */
8989 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8991 case 0x19: /* FMLA */
8992 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8993 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8996 case 0x1a: /* FADD */
8997 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8999 case 0x1b: /* FMULX */
9000 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9002 case 0x1c: /* FCMEQ */
9003 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9005 case 0x1e: /* FMAX */
9006 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9008 case 0x1f: /* FRECPS */
9009 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9011 case 0x18: /* FMAXNM */
9012 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9014 case 0x38: /* FMINNM */
9015 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9017 case 0x3a: /* FSUB */
9018 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9020 case 0x3e: /* FMIN */
9021 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9023 case 0x3f: /* FRSQRTS */
9024 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9026 case 0x5b: /* FMUL */
9027 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9029 case 0x5c: /* FCMGE */
9030 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9032 case 0x5d: /* FACGE */
9033 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9035 case 0x5f: /* FDIV */
9036 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9038 case 0x7a: /* FABD */
9039 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9042 case 0x7c: /* FCMGT */
9043 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9045 case 0x7d: /* FACGT */
9046 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 g_assert_not_reached();
9052 if (elements
== 1) {
9053 /* scalar single so clear high part */
9054 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9056 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9057 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9058 tcg_temp_free_i64(tcg_tmp
);
9060 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9063 tcg_temp_free_i32(tcg_res
);
9064 tcg_temp_free_i32(tcg_op1
);
9065 tcg_temp_free_i32(tcg_op2
);
9069 tcg_temp_free_ptr(fpst
);
9071 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9074 /* AdvSIMD scalar three same
9075 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9076 * +-----+---+-----------+------+---+------+--------+---+------+------+
9077 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9078 * +-----+---+-----------+------+---+------+--------+---+------+------+
9080 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9082 int rd
= extract32(insn
, 0, 5);
9083 int rn
= extract32(insn
, 5, 5);
9084 int opcode
= extract32(insn
, 11, 5);
9085 int rm
= extract32(insn
, 16, 5);
9086 int size
= extract32(insn
, 22, 2);
9087 bool u
= extract32(insn
, 29, 1);
9090 if (opcode
>= 0x18) {
9091 /* Floating point: U, size[1] and opcode indicate operation */
9092 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9094 case 0x1b: /* FMULX */
9095 case 0x1f: /* FRECPS */
9096 case 0x3f: /* FRSQRTS */
9097 case 0x5d: /* FACGE */
9098 case 0x7d: /* FACGT */
9099 case 0x1c: /* FCMEQ */
9100 case 0x5c: /* FCMGE */
9101 case 0x7c: /* FCMGT */
9102 case 0x7a: /* FABD */
9105 unallocated_encoding(s
);
9109 if (!fp_access_check(s
)) {
9113 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9118 case 0x1: /* SQADD, UQADD */
9119 case 0x5: /* SQSUB, UQSUB */
9120 case 0x9: /* SQSHL, UQSHL */
9121 case 0xb: /* SQRSHL, UQRSHL */
9123 case 0x8: /* SSHL, USHL */
9124 case 0xa: /* SRSHL, URSHL */
9125 case 0x6: /* CMGT, CMHI */
9126 case 0x7: /* CMGE, CMHS */
9127 case 0x11: /* CMTST, CMEQ */
9128 case 0x10: /* ADD, SUB (vector) */
9130 unallocated_encoding(s
);
9134 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9135 if (size
!= 1 && size
!= 2) {
9136 unallocated_encoding(s
);
9141 unallocated_encoding(s
);
9145 if (!fp_access_check(s
)) {
9149 tcg_rd
= tcg_temp_new_i64();
9152 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9153 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9155 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9156 tcg_temp_free_i64(tcg_rn
);
9157 tcg_temp_free_i64(tcg_rm
);
9159 /* Do a single operation on the lowest element in the vector.
9160 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9161 * no side effects for all these operations.
9162 * OPTME: special-purpose helpers would avoid doing some
9163 * unnecessary work in the helper for the 8 and 16 bit cases.
9165 NeonGenTwoOpEnvFn
*genenvfn
;
9166 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9167 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9168 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9170 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9171 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9174 case 0x1: /* SQADD, UQADD */
9176 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9177 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9178 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9179 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9181 genenvfn
= fns
[size
][u
];
9184 case 0x5: /* SQSUB, UQSUB */
9186 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9187 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9188 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9189 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9191 genenvfn
= fns
[size
][u
];
9194 case 0x9: /* SQSHL, UQSHL */
9196 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9197 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9198 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9199 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9201 genenvfn
= fns
[size
][u
];
9204 case 0xb: /* SQRSHL, UQRSHL */
9206 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9207 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9208 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9209 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9211 genenvfn
= fns
[size
][u
];
9214 case 0x16: /* SQDMULH, SQRDMULH */
9216 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9217 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9218 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9220 assert(size
== 1 || size
== 2);
9221 genenvfn
= fns
[size
- 1][u
];
9225 g_assert_not_reached();
9228 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9229 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9230 tcg_temp_free_i32(tcg_rd32
);
9231 tcg_temp_free_i32(tcg_rn
);
9232 tcg_temp_free_i32(tcg_rm
);
9235 write_fp_dreg(s
, rd
, tcg_rd
);
9237 tcg_temp_free_i64(tcg_rd
);
9240 /* AdvSIMD scalar three same FP16
9241 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9242 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9243 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9244 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9245 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9246 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9248 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9251 int rd
= extract32(insn
, 0, 5);
9252 int rn
= extract32(insn
, 5, 5);
9253 int opcode
= extract32(insn
, 11, 3);
9254 int rm
= extract32(insn
, 16, 5);
9255 bool u
= extract32(insn
, 29, 1);
9256 bool a
= extract32(insn
, 23, 1);
9257 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9264 case 0x03: /* FMULX */
9265 case 0x04: /* FCMEQ (reg) */
9266 case 0x07: /* FRECPS */
9267 case 0x0f: /* FRSQRTS */
9268 case 0x14: /* FCMGE (reg) */
9269 case 0x15: /* FACGE */
9270 case 0x1a: /* FABD */
9271 case 0x1c: /* FCMGT (reg) */
9272 case 0x1d: /* FACGT */
9275 unallocated_encoding(s
);
9279 if (!dc_isar_feature(aa64_fp16
, s
)) {
9280 unallocated_encoding(s
);
9283 if (!fp_access_check(s
)) {
9287 fpst
= get_fpstatus_ptr(true);
9289 tcg_op1
= read_fp_hreg(s
, rn
);
9290 tcg_op2
= read_fp_hreg(s
, rm
);
9291 tcg_res
= tcg_temp_new_i32();
9294 case 0x03: /* FMULX */
9295 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9297 case 0x04: /* FCMEQ (reg) */
9298 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9300 case 0x07: /* FRECPS */
9301 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9303 case 0x0f: /* FRSQRTS */
9304 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9306 case 0x14: /* FCMGE (reg) */
9307 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9309 case 0x15: /* FACGE */
9310 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9312 case 0x1a: /* FABD */
9313 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9314 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9316 case 0x1c: /* FCMGT (reg) */
9317 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9319 case 0x1d: /* FACGT */
9320 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9323 g_assert_not_reached();
9326 write_fp_sreg(s
, rd
, tcg_res
);
9329 tcg_temp_free_i32(tcg_res
);
9330 tcg_temp_free_i32(tcg_op1
);
9331 tcg_temp_free_i32(tcg_op2
);
9332 tcg_temp_free_ptr(fpst
);
9335 /* AdvSIMD scalar three same extra
9336 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9337 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9338 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9339 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9341 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9344 int rd
= extract32(insn
, 0, 5);
9345 int rn
= extract32(insn
, 5, 5);
9346 int opcode
= extract32(insn
, 11, 4);
9347 int rm
= extract32(insn
, 16, 5);
9348 int size
= extract32(insn
, 22, 2);
9349 bool u
= extract32(insn
, 29, 1);
9350 TCGv_i32 ele1
, ele2
, ele3
;
9354 switch (u
* 16 + opcode
) {
9355 case 0x10: /* SQRDMLAH (vector) */
9356 case 0x11: /* SQRDMLSH (vector) */
9357 if (size
!= 1 && size
!= 2) {
9358 unallocated_encoding(s
);
9361 feature
= dc_isar_feature(aa64_rdm
, s
);
9364 unallocated_encoding(s
);
9368 unallocated_encoding(s
);
9371 if (!fp_access_check(s
)) {
9375 /* Do a single operation on the lowest element in the vector.
9376 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9377 * with no side effects for all these operations.
9378 * OPTME: special-purpose helpers would avoid doing some
9379 * unnecessary work in the helper for the 16 bit cases.
9381 ele1
= tcg_temp_new_i32();
9382 ele2
= tcg_temp_new_i32();
9383 ele3
= tcg_temp_new_i32();
9385 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9386 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9387 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9390 case 0x0: /* SQRDMLAH */
9392 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9394 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9397 case 0x1: /* SQRDMLSH */
9399 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9401 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9405 g_assert_not_reached();
9407 tcg_temp_free_i32(ele1
);
9408 tcg_temp_free_i32(ele2
);
9410 res
= tcg_temp_new_i64();
9411 tcg_gen_extu_i32_i64(res
, ele3
);
9412 tcg_temp_free_i32(ele3
);
9414 write_fp_dreg(s
, rd
, res
);
9415 tcg_temp_free_i64(res
);
9418 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9419 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9420 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9422 /* Handle 64->64 opcodes which are shared between the scalar and
9423 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9424 * is valid in either group and also the double-precision fp ops.
9425 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9431 case 0x4: /* CLS, CLZ */
9433 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9435 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9439 /* This opcode is shared with CNT and RBIT but we have earlier
9440 * enforced that size == 3 if and only if this is the NOT insn.
9442 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9444 case 0x7: /* SQABS, SQNEG */
9446 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9448 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9451 case 0xa: /* CMLT */
9452 /* 64 bit integer comparison against zero, result is
9453 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9458 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9459 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9461 case 0x8: /* CMGT, CMGE */
9462 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9464 case 0x9: /* CMEQ, CMLE */
9465 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9467 case 0xb: /* ABS, NEG */
9469 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9471 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9474 case 0x2f: /* FABS */
9475 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9477 case 0x6f: /* FNEG */
9478 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9480 case 0x7f: /* FSQRT */
9481 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9483 case 0x1a: /* FCVTNS */
9484 case 0x1b: /* FCVTMS */
9485 case 0x1c: /* FCVTAS */
9486 case 0x3a: /* FCVTPS */
9487 case 0x3b: /* FCVTZS */
9489 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9490 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9491 tcg_temp_free_i32(tcg_shift
);
9494 case 0x5a: /* FCVTNU */
9495 case 0x5b: /* FCVTMU */
9496 case 0x5c: /* FCVTAU */
9497 case 0x7a: /* FCVTPU */
9498 case 0x7b: /* FCVTZU */
9500 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9501 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9502 tcg_temp_free_i32(tcg_shift
);
9505 case 0x18: /* FRINTN */
9506 case 0x19: /* FRINTM */
9507 case 0x38: /* FRINTP */
9508 case 0x39: /* FRINTZ */
9509 case 0x58: /* FRINTA */
9510 case 0x79: /* FRINTI */
9511 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9513 case 0x59: /* FRINTX */
9514 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9516 case 0x1e: /* FRINT32Z */
9517 case 0x5e: /* FRINT32X */
9518 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9520 case 0x1f: /* FRINT64Z */
9521 case 0x5f: /* FRINT64X */
9522 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9525 g_assert_not_reached();
9529 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9530 bool is_scalar
, bool is_u
, bool is_q
,
9531 int size
, int rn
, int rd
)
9533 bool is_double
= (size
== MO_64
);
9536 if (!fp_access_check(s
)) {
9540 fpst
= get_fpstatus_ptr(size
== MO_16
);
9543 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9544 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9545 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9546 NeonGenTwoDoubleOPFn
*genfn
;
9551 case 0x2e: /* FCMLT (zero) */
9554 case 0x2c: /* FCMGT (zero) */
9555 genfn
= gen_helper_neon_cgt_f64
;
9557 case 0x2d: /* FCMEQ (zero) */
9558 genfn
= gen_helper_neon_ceq_f64
;
9560 case 0x6d: /* FCMLE (zero) */
9563 case 0x6c: /* FCMGE (zero) */
9564 genfn
= gen_helper_neon_cge_f64
;
9567 g_assert_not_reached();
9570 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9571 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9573 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9575 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9577 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9579 tcg_temp_free_i64(tcg_res
);
9580 tcg_temp_free_i64(tcg_zero
);
9581 tcg_temp_free_i64(tcg_op
);
9583 clear_vec_high(s
, !is_scalar
, rd
);
9585 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9586 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9587 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9588 NeonGenTwoSingleOPFn
*genfn
;
9590 int pass
, maxpasses
;
9592 if (size
== MO_16
) {
9594 case 0x2e: /* FCMLT (zero) */
9597 case 0x2c: /* FCMGT (zero) */
9598 genfn
= gen_helper_advsimd_cgt_f16
;
9600 case 0x2d: /* FCMEQ (zero) */
9601 genfn
= gen_helper_advsimd_ceq_f16
;
9603 case 0x6d: /* FCMLE (zero) */
9606 case 0x6c: /* FCMGE (zero) */
9607 genfn
= gen_helper_advsimd_cge_f16
;
9610 g_assert_not_reached();
9614 case 0x2e: /* FCMLT (zero) */
9617 case 0x2c: /* FCMGT (zero) */
9618 genfn
= gen_helper_neon_cgt_f32
;
9620 case 0x2d: /* FCMEQ (zero) */
9621 genfn
= gen_helper_neon_ceq_f32
;
9623 case 0x6d: /* FCMLE (zero) */
9626 case 0x6c: /* FCMGE (zero) */
9627 genfn
= gen_helper_neon_cge_f32
;
9630 g_assert_not_reached();
9637 int vector_size
= 8 << is_q
;
9638 maxpasses
= vector_size
>> size
;
9641 for (pass
= 0; pass
< maxpasses
; pass
++) {
9642 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9644 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9646 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9649 write_fp_sreg(s
, rd
, tcg_res
);
9651 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9654 tcg_temp_free_i32(tcg_res
);
9655 tcg_temp_free_i32(tcg_zero
);
9656 tcg_temp_free_i32(tcg_op
);
9658 clear_vec_high(s
, is_q
, rd
);
9662 tcg_temp_free_ptr(fpst
);
9665 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9666 bool is_scalar
, bool is_u
, bool is_q
,
9667 int size
, int rn
, int rd
)
9669 bool is_double
= (size
== 3);
9670 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9673 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9674 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9677 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9678 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9680 case 0x3d: /* FRECPE */
9681 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9683 case 0x3f: /* FRECPX */
9684 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9686 case 0x7d: /* FRSQRTE */
9687 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9690 g_assert_not_reached();
9692 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9694 tcg_temp_free_i64(tcg_res
);
9695 tcg_temp_free_i64(tcg_op
);
9696 clear_vec_high(s
, !is_scalar
, rd
);
9698 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9699 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9700 int pass
, maxpasses
;
9705 maxpasses
= is_q
? 4 : 2;
9708 for (pass
= 0; pass
< maxpasses
; pass
++) {
9709 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9712 case 0x3c: /* URECPE */
9713 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9715 case 0x3d: /* FRECPE */
9716 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9718 case 0x3f: /* FRECPX */
9719 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9721 case 0x7d: /* FRSQRTE */
9722 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9725 g_assert_not_reached();
9729 write_fp_sreg(s
, rd
, tcg_res
);
9731 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9734 tcg_temp_free_i32(tcg_res
);
9735 tcg_temp_free_i32(tcg_op
);
9737 clear_vec_high(s
, is_q
, rd
);
9740 tcg_temp_free_ptr(fpst
);
9743 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9744 int opcode
, bool u
, bool is_q
,
9745 int size
, int rn
, int rd
)
9747 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9748 * in the source becomes a size element in the destination).
9751 TCGv_i32 tcg_res
[2];
9752 int destelt
= is_q
? 2 : 0;
9753 int passes
= scalar
? 1 : 2;
9756 tcg_res
[1] = tcg_const_i32(0);
9759 for (pass
= 0; pass
< passes
; pass
++) {
9760 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9761 NeonGenNarrowFn
*genfn
= NULL
;
9762 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9765 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9767 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9769 tcg_res
[pass
] = tcg_temp_new_i32();
9772 case 0x12: /* XTN, SQXTUN */
9774 static NeonGenNarrowFn
* const xtnfns
[3] = {
9775 gen_helper_neon_narrow_u8
,
9776 gen_helper_neon_narrow_u16
,
9777 tcg_gen_extrl_i64_i32
,
9779 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9780 gen_helper_neon_unarrow_sat8
,
9781 gen_helper_neon_unarrow_sat16
,
9782 gen_helper_neon_unarrow_sat32
,
9785 genenvfn
= sqxtunfns
[size
];
9787 genfn
= xtnfns
[size
];
9791 case 0x14: /* SQXTN, UQXTN */
9793 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9794 { gen_helper_neon_narrow_sat_s8
,
9795 gen_helper_neon_narrow_sat_u8
},
9796 { gen_helper_neon_narrow_sat_s16
,
9797 gen_helper_neon_narrow_sat_u16
},
9798 { gen_helper_neon_narrow_sat_s32
,
9799 gen_helper_neon_narrow_sat_u32
},
9801 genenvfn
= fns
[size
][u
];
9804 case 0x16: /* FCVTN, FCVTN2 */
9805 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9807 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9809 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9810 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9811 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9812 TCGv_i32 ahp
= get_ahp_flag();
9814 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9815 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9816 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9817 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9818 tcg_temp_free_i32(tcg_lo
);
9819 tcg_temp_free_i32(tcg_hi
);
9820 tcg_temp_free_ptr(fpst
);
9821 tcg_temp_free_i32(ahp
);
9824 case 0x56: /* FCVTXN, FCVTXN2 */
9825 /* 64 bit to 32 bit float conversion
9826 * with von Neumann rounding (round to odd)
9829 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9832 g_assert_not_reached();
9836 genfn(tcg_res
[pass
], tcg_op
);
9837 } else if (genenvfn
) {
9838 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9841 tcg_temp_free_i64(tcg_op
);
9844 for (pass
= 0; pass
< 2; pass
++) {
9845 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9846 tcg_temp_free_i32(tcg_res
[pass
]);
9848 clear_vec_high(s
, is_q
, rd
);
9851 /* Remaining saturating accumulating ops */
9852 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9853 bool is_q
, int size
, int rn
, int rd
)
9855 bool is_double
= (size
== 3);
9858 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9859 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9862 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9863 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9864 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9866 if (is_u
) { /* USQADD */
9867 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9868 } else { /* SUQADD */
9869 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9871 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9873 tcg_temp_free_i64(tcg_rd
);
9874 tcg_temp_free_i64(tcg_rn
);
9875 clear_vec_high(s
, !is_scalar
, rd
);
9877 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9878 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9879 int pass
, maxpasses
;
9884 maxpasses
= is_q
? 4 : 2;
9887 for (pass
= 0; pass
< maxpasses
; pass
++) {
9889 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9890 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9892 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9893 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9896 if (is_u
) { /* USQADD */
9899 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9902 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9905 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9908 g_assert_not_reached();
9910 } else { /* SUQADD */
9913 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9916 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9919 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9922 g_assert_not_reached();
9927 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9928 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9929 tcg_temp_free_i64(tcg_zero
);
9931 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9933 tcg_temp_free_i32(tcg_rd
);
9934 tcg_temp_free_i32(tcg_rn
);
9935 clear_vec_high(s
, is_q
, rd
);
9939 /* AdvSIMD scalar two reg misc
9940 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9941 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9942 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9943 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9945 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9947 int rd
= extract32(insn
, 0, 5);
9948 int rn
= extract32(insn
, 5, 5);
9949 int opcode
= extract32(insn
, 12, 5);
9950 int size
= extract32(insn
, 22, 2);
9951 bool u
= extract32(insn
, 29, 1);
9952 bool is_fcvt
= false;
9955 TCGv_ptr tcg_fpstatus
;
9958 case 0x3: /* USQADD / SUQADD*/
9959 if (!fp_access_check(s
)) {
9962 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9964 case 0x7: /* SQABS / SQNEG */
9966 case 0xa: /* CMLT */
9968 unallocated_encoding(s
);
9972 case 0x8: /* CMGT, CMGE */
9973 case 0x9: /* CMEQ, CMLE */
9974 case 0xb: /* ABS, NEG */
9976 unallocated_encoding(s
);
9980 case 0x12: /* SQXTUN */
9982 unallocated_encoding(s
);
9986 case 0x14: /* SQXTN, UQXTN */
9988 unallocated_encoding(s
);
9991 if (!fp_access_check(s
)) {
9994 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9999 /* Floating point: U, size[1] and opcode indicate operation;
10000 * size[0] indicates single or double precision.
10002 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10003 size
= extract32(size
, 0, 1) ? 3 : 2;
10005 case 0x2c: /* FCMGT (zero) */
10006 case 0x2d: /* FCMEQ (zero) */
10007 case 0x2e: /* FCMLT (zero) */
10008 case 0x6c: /* FCMGE (zero) */
10009 case 0x6d: /* FCMLE (zero) */
10010 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10012 case 0x1d: /* SCVTF */
10013 case 0x5d: /* UCVTF */
10015 bool is_signed
= (opcode
== 0x1d);
10016 if (!fp_access_check(s
)) {
10019 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10022 case 0x3d: /* FRECPE */
10023 case 0x3f: /* FRECPX */
10024 case 0x7d: /* FRSQRTE */
10025 if (!fp_access_check(s
)) {
10028 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10030 case 0x1a: /* FCVTNS */
10031 case 0x1b: /* FCVTMS */
10032 case 0x3a: /* FCVTPS */
10033 case 0x3b: /* FCVTZS */
10034 case 0x5a: /* FCVTNU */
10035 case 0x5b: /* FCVTMU */
10036 case 0x7a: /* FCVTPU */
10037 case 0x7b: /* FCVTZU */
10039 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10041 case 0x1c: /* FCVTAS */
10042 case 0x5c: /* FCVTAU */
10043 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10045 rmode
= FPROUNDING_TIEAWAY
;
10047 case 0x56: /* FCVTXN, FCVTXN2 */
10049 unallocated_encoding(s
);
10052 if (!fp_access_check(s
)) {
10055 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10058 unallocated_encoding(s
);
10063 unallocated_encoding(s
);
10067 if (!fp_access_check(s
)) {
10072 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10073 tcg_fpstatus
= get_fpstatus_ptr(false);
10074 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10077 tcg_fpstatus
= NULL
;
10081 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10082 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10084 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10085 write_fp_dreg(s
, rd
, tcg_rd
);
10086 tcg_temp_free_i64(tcg_rd
);
10087 tcg_temp_free_i64(tcg_rn
);
10089 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10090 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10092 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10095 case 0x7: /* SQABS, SQNEG */
10097 NeonGenOneOpEnvFn
*genfn
;
10098 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10099 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10100 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10101 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10103 genfn
= fns
[size
][u
];
10104 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10107 case 0x1a: /* FCVTNS */
10108 case 0x1b: /* FCVTMS */
10109 case 0x1c: /* FCVTAS */
10110 case 0x3a: /* FCVTPS */
10111 case 0x3b: /* FCVTZS */
10113 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10114 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10115 tcg_temp_free_i32(tcg_shift
);
10118 case 0x5a: /* FCVTNU */
10119 case 0x5b: /* FCVTMU */
10120 case 0x5c: /* FCVTAU */
10121 case 0x7a: /* FCVTPU */
10122 case 0x7b: /* FCVTZU */
10124 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10125 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10126 tcg_temp_free_i32(tcg_shift
);
10130 g_assert_not_reached();
10133 write_fp_sreg(s
, rd
, tcg_rd
);
10134 tcg_temp_free_i32(tcg_rd
);
10135 tcg_temp_free_i32(tcg_rn
);
10139 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10140 tcg_temp_free_i32(tcg_rmode
);
10141 tcg_temp_free_ptr(tcg_fpstatus
);
10145 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10146 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10147 int immh
, int immb
, int opcode
, int rn
, int rd
)
10149 int size
= 32 - clz32(immh
) - 1;
10150 int immhb
= immh
<< 3 | immb
;
10151 int shift
= 2 * (8 << size
) - immhb
;
10152 bool accumulate
= false;
10153 int dsize
= is_q
? 128 : 64;
10154 int esize
= 8 << size
;
10155 int elements
= dsize
/esize
;
10156 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10157 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10158 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10159 TCGv_i64 tcg_round
;
10160 uint64_t round_const
;
10163 if (extract32(immh
, 3, 1) && !is_q
) {
10164 unallocated_encoding(s
);
10167 tcg_debug_assert(size
<= 3);
10169 if (!fp_access_check(s
)) {
10174 case 0x02: /* SSRA / USRA (accumulate) */
10176 /* Shift count same as element size produces zero to add. */
10177 if (shift
== 8 << size
) {
10180 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10182 /* Shift count same as element size produces all sign to add. */
10183 if (shift
== 8 << size
) {
10186 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10189 case 0x08: /* SRI */
10190 /* Shift count same as element size is valid but does nothing. */
10191 if (shift
== 8 << size
) {
10194 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10197 case 0x00: /* SSHR / USHR */
10199 if (shift
== 8 << size
) {
10200 /* Shift count the same size as element size produces zero. */
10201 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10202 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10204 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10207 /* Shift count the same size as element size produces all sign. */
10208 if (shift
== 8 << size
) {
10211 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10215 case 0x04: /* SRSHR / URSHR (rounding) */
10217 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10221 g_assert_not_reached();
10224 round_const
= 1ULL << (shift
- 1);
10225 tcg_round
= tcg_const_i64(round_const
);
10227 for (i
= 0; i
< elements
; i
++) {
10228 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10230 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10233 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10234 accumulate
, is_u
, size
, shift
);
10236 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10238 tcg_temp_free_i64(tcg_round
);
10241 clear_vec_high(s
, is_q
, rd
);
10244 /* SHL/SLI - Vector shift left */
10245 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10246 int immh
, int immb
, int opcode
, int rn
, int rd
)
10248 int size
= 32 - clz32(immh
) - 1;
10249 int immhb
= immh
<< 3 | immb
;
10250 int shift
= immhb
- (8 << size
);
10252 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10253 assert(size
>= 0 && size
<= 3);
10255 if (extract32(immh
, 3, 1) && !is_q
) {
10256 unallocated_encoding(s
);
10260 if (!fp_access_check(s
)) {
10265 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10267 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10271 /* USHLL/SHLL - Vector shift left with widening */
10272 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10273 int immh
, int immb
, int opcode
, int rn
, int rd
)
10275 int size
= 32 - clz32(immh
) - 1;
10276 int immhb
= immh
<< 3 | immb
;
10277 int shift
= immhb
- (8 << size
);
10279 int esize
= 8 << size
;
10280 int elements
= dsize
/esize
;
10281 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10282 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10286 unallocated_encoding(s
);
10290 if (!fp_access_check(s
)) {
10294 /* For the LL variants the store is larger than the load,
10295 * so if rd == rn we would overwrite parts of our input.
10296 * So load everything right now and use shifts in the main loop.
10298 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10300 for (i
= 0; i
< elements
; i
++) {
10301 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10302 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10303 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10304 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10308 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10309 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10310 int immh
, int immb
, int opcode
, int rn
, int rd
)
10312 int immhb
= immh
<< 3 | immb
;
10313 int size
= 32 - clz32(immh
) - 1;
10315 int esize
= 8 << size
;
10316 int elements
= dsize
/esize
;
10317 int shift
= (2 * esize
) - immhb
;
10318 bool round
= extract32(opcode
, 0, 1);
10319 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10320 TCGv_i64 tcg_round
;
10323 if (extract32(immh
, 3, 1)) {
10324 unallocated_encoding(s
);
10328 if (!fp_access_check(s
)) {
10332 tcg_rn
= tcg_temp_new_i64();
10333 tcg_rd
= tcg_temp_new_i64();
10334 tcg_final
= tcg_temp_new_i64();
10335 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10338 uint64_t round_const
= 1ULL << (shift
- 1);
10339 tcg_round
= tcg_const_i64(round_const
);
10344 for (i
= 0; i
< elements
; i
++) {
10345 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10346 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10347 false, true, size
+1, shift
);
10349 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10353 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10355 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10358 tcg_temp_free_i64(tcg_round
);
10360 tcg_temp_free_i64(tcg_rn
);
10361 tcg_temp_free_i64(tcg_rd
);
10362 tcg_temp_free_i64(tcg_final
);
10364 clear_vec_high(s
, is_q
, rd
);
10368 /* AdvSIMD shift by immediate
10369 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10370 * +---+---+---+-------------+------+------+--------+---+------+------+
10371 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10372 * +---+---+---+-------------+------+------+--------+---+------+------+
10374 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10376 int rd
= extract32(insn
, 0, 5);
10377 int rn
= extract32(insn
, 5, 5);
10378 int opcode
= extract32(insn
, 11, 5);
10379 int immb
= extract32(insn
, 16, 3);
10380 int immh
= extract32(insn
, 19, 4);
10381 bool is_u
= extract32(insn
, 29, 1);
10382 bool is_q
= extract32(insn
, 30, 1);
10385 case 0x08: /* SRI */
10387 unallocated_encoding(s
);
10391 case 0x00: /* SSHR / USHR */
10392 case 0x02: /* SSRA / USRA (accumulate) */
10393 case 0x04: /* SRSHR / URSHR (rounding) */
10394 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10395 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10397 case 0x0a: /* SHL / SLI */
10398 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10400 case 0x10: /* SHRN */
10401 case 0x11: /* RSHRN / SQRSHRUN */
10403 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10406 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10409 case 0x12: /* SQSHRN / UQSHRN */
10410 case 0x13: /* SQRSHRN / UQRSHRN */
10411 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10414 case 0x14: /* SSHLL / USHLL */
10415 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10417 case 0x1c: /* SCVTF / UCVTF */
10418 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10421 case 0xc: /* SQSHLU */
10423 unallocated_encoding(s
);
10426 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10428 case 0xe: /* SQSHL, UQSHL */
10429 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10431 case 0x1f: /* FCVTZS/ FCVTZU */
10432 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10435 unallocated_encoding(s
);
10440 /* Generate code to do a "long" addition or subtraction, ie one done in
10441 * TCGv_i64 on vector lanes twice the width specified by size.
10443 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10444 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10446 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10447 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10448 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10449 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10451 NeonGenTwo64OpFn
*genfn
;
10454 genfn
= fns
[size
][is_sub
];
10455 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10458 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10459 int opcode
, int rd
, int rn
, int rm
)
10461 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10462 TCGv_i64 tcg_res
[2];
10465 tcg_res
[0] = tcg_temp_new_i64();
10466 tcg_res
[1] = tcg_temp_new_i64();
10468 /* Does this op do an adding accumulate, a subtracting accumulate,
10469 * or no accumulate at all?
10487 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10488 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10491 /* size == 2 means two 32x32->64 operations; this is worth special
10492 * casing because we can generally handle it inline.
10495 for (pass
= 0; pass
< 2; pass
++) {
10496 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10497 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10498 TCGv_i64 tcg_passres
;
10499 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10501 int elt
= pass
+ is_q
* 2;
10503 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10504 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10507 tcg_passres
= tcg_res
[pass
];
10509 tcg_passres
= tcg_temp_new_i64();
10513 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10514 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10516 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10517 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10519 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10520 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10522 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10523 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10525 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10526 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10527 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10529 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10530 tcg_temp_free_i64(tcg_tmp1
);
10531 tcg_temp_free_i64(tcg_tmp2
);
10534 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10535 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10536 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10537 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10539 case 9: /* SQDMLAL, SQDMLAL2 */
10540 case 11: /* SQDMLSL, SQDMLSL2 */
10541 case 13: /* SQDMULL, SQDMULL2 */
10542 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10543 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10544 tcg_passres
, tcg_passres
);
10547 g_assert_not_reached();
10550 if (opcode
== 9 || opcode
== 11) {
10551 /* saturating accumulate ops */
10553 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10555 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10556 tcg_res
[pass
], tcg_passres
);
10557 } else if (accop
> 0) {
10558 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10559 } else if (accop
< 0) {
10560 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10564 tcg_temp_free_i64(tcg_passres
);
10567 tcg_temp_free_i64(tcg_op1
);
10568 tcg_temp_free_i64(tcg_op2
);
10571 /* size 0 or 1, generally helper functions */
10572 for (pass
= 0; pass
< 2; pass
++) {
10573 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10574 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10575 TCGv_i64 tcg_passres
;
10576 int elt
= pass
+ is_q
* 2;
10578 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10579 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10582 tcg_passres
= tcg_res
[pass
];
10584 tcg_passres
= tcg_temp_new_i64();
10588 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10589 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10591 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10592 static NeonGenWidenFn
* const widenfns
[2][2] = {
10593 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10594 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10596 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10598 widenfn(tcg_op2_64
, tcg_op2
);
10599 widenfn(tcg_passres
, tcg_op1
);
10600 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10601 tcg_passres
, tcg_op2_64
);
10602 tcg_temp_free_i64(tcg_op2_64
);
10605 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10606 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10609 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10611 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10615 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10617 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10621 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10622 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10623 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10626 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10628 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10632 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10634 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10638 case 9: /* SQDMLAL, SQDMLAL2 */
10639 case 11: /* SQDMLSL, SQDMLSL2 */
10640 case 13: /* SQDMULL, SQDMULL2 */
10642 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10643 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10644 tcg_passres
, tcg_passres
);
10646 case 14: /* PMULL */
10648 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10651 g_assert_not_reached();
10653 tcg_temp_free_i32(tcg_op1
);
10654 tcg_temp_free_i32(tcg_op2
);
10657 if (opcode
== 9 || opcode
== 11) {
10658 /* saturating accumulate ops */
10660 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10662 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10666 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10667 tcg_res
[pass
], tcg_passres
);
10669 tcg_temp_free_i64(tcg_passres
);
10674 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10675 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10676 tcg_temp_free_i64(tcg_res
[0]);
10677 tcg_temp_free_i64(tcg_res
[1]);
10680 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10681 int opcode
, int rd
, int rn
, int rm
)
10683 TCGv_i64 tcg_res
[2];
10684 int part
= is_q
? 2 : 0;
10687 for (pass
= 0; pass
< 2; pass
++) {
10688 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10689 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10690 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10691 static NeonGenWidenFn
* const widenfns
[3][2] = {
10692 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10693 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10694 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10696 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10698 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10699 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10700 widenfn(tcg_op2_wide
, tcg_op2
);
10701 tcg_temp_free_i32(tcg_op2
);
10702 tcg_res
[pass
] = tcg_temp_new_i64();
10703 gen_neon_addl(size
, (opcode
== 3),
10704 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10705 tcg_temp_free_i64(tcg_op1
);
10706 tcg_temp_free_i64(tcg_op2_wide
);
10709 for (pass
= 0; pass
< 2; pass
++) {
10710 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10711 tcg_temp_free_i64(tcg_res
[pass
]);
10715 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10717 tcg_gen_addi_i64(in
, in
, 1U << 31);
10718 tcg_gen_extrh_i64_i32(res
, in
);
10721 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10722 int opcode
, int rd
, int rn
, int rm
)
10724 TCGv_i32 tcg_res
[2];
10725 int part
= is_q
? 2 : 0;
10728 for (pass
= 0; pass
< 2; pass
++) {
10729 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10730 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10731 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10732 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10733 { gen_helper_neon_narrow_high_u8
,
10734 gen_helper_neon_narrow_round_high_u8
},
10735 { gen_helper_neon_narrow_high_u16
,
10736 gen_helper_neon_narrow_round_high_u16
},
10737 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10739 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10741 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10742 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10744 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10746 tcg_temp_free_i64(tcg_op1
);
10747 tcg_temp_free_i64(tcg_op2
);
10749 tcg_res
[pass
] = tcg_temp_new_i32();
10750 gennarrow(tcg_res
[pass
], tcg_wideres
);
10751 tcg_temp_free_i64(tcg_wideres
);
10754 for (pass
= 0; pass
< 2; pass
++) {
10755 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10756 tcg_temp_free_i32(tcg_res
[pass
]);
10758 clear_vec_high(s
, is_q
, rd
);
10761 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10763 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10764 * is the only three-reg-diff instruction which produces a
10765 * 128-bit wide result from a single operation. However since
10766 * it's possible to calculate the two halves more or less
10767 * separately we just use two helper calls.
10769 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10770 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10771 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10773 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10774 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10775 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10776 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10777 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10778 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10780 tcg_temp_free_i64(tcg_op1
);
10781 tcg_temp_free_i64(tcg_op2
);
10782 tcg_temp_free_i64(tcg_res
);
10785 /* AdvSIMD three different
10786 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10787 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10788 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10789 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10791 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10793 /* Instructions in this group fall into three basic classes
10794 * (in each case with the operation working on each element in
10795 * the input vectors):
10796 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10798 * (2) wide 64 x 128 -> 128
10799 * (3) narrowing 128 x 128 -> 64
10800 * Here we do initial decode, catch unallocated cases and
10801 * dispatch to separate functions for each class.
10803 int is_q
= extract32(insn
, 30, 1);
10804 int is_u
= extract32(insn
, 29, 1);
10805 int size
= extract32(insn
, 22, 2);
10806 int opcode
= extract32(insn
, 12, 4);
10807 int rm
= extract32(insn
, 16, 5);
10808 int rn
= extract32(insn
, 5, 5);
10809 int rd
= extract32(insn
, 0, 5);
10812 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10813 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10814 /* 64 x 128 -> 128 */
10816 unallocated_encoding(s
);
10819 if (!fp_access_check(s
)) {
10822 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10824 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10825 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10826 /* 128 x 128 -> 64 */
10828 unallocated_encoding(s
);
10831 if (!fp_access_check(s
)) {
10834 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10836 case 14: /* PMULL, PMULL2 */
10837 if (is_u
|| size
== 1 || size
== 2) {
10838 unallocated_encoding(s
);
10842 if (!dc_isar_feature(aa64_pmull
, s
)) {
10843 unallocated_encoding(s
);
10846 if (!fp_access_check(s
)) {
10849 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10853 case 9: /* SQDMLAL, SQDMLAL2 */
10854 case 11: /* SQDMLSL, SQDMLSL2 */
10855 case 13: /* SQDMULL, SQDMULL2 */
10856 if (is_u
|| size
== 0) {
10857 unallocated_encoding(s
);
10861 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10862 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10863 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10864 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10865 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10866 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10867 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10868 /* 64 x 64 -> 128 */
10870 unallocated_encoding(s
);
10874 if (!fp_access_check(s
)) {
10878 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10881 /* opcode 15 not allocated */
10882 unallocated_encoding(s
);
10887 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10888 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10890 int rd
= extract32(insn
, 0, 5);
10891 int rn
= extract32(insn
, 5, 5);
10892 int rm
= extract32(insn
, 16, 5);
10893 int size
= extract32(insn
, 22, 2);
10894 bool is_u
= extract32(insn
, 29, 1);
10895 bool is_q
= extract32(insn
, 30, 1);
10897 if (!fp_access_check(s
)) {
10901 switch (size
+ 4 * is_u
) {
10903 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10906 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10909 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10912 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10915 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10918 case 5: /* BSL bitwise select */
10919 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10921 case 6: /* BIT, bitwise insert if true */
10922 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10924 case 7: /* BIF, bitwise insert if false */
10925 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10929 g_assert_not_reached();
10933 /* Pairwise op subgroup of C3.6.16.
10935 * This is called directly or via the handle_3same_float for float pairwise
10936 * operations where the opcode and size are calculated differently.
10938 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10939 int size
, int rn
, int rm
, int rd
)
10944 /* Floating point operations need fpst */
10945 if (opcode
>= 0x58) {
10946 fpst
= get_fpstatus_ptr(false);
10951 if (!fp_access_check(s
)) {
10955 /* These operations work on the concatenated rm:rn, with each pair of
10956 * adjacent elements being operated on to produce an element in the result.
10959 TCGv_i64 tcg_res
[2];
10961 for (pass
= 0; pass
< 2; pass
++) {
10962 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10963 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10964 int passreg
= (pass
== 0) ? rn
: rm
;
10966 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10967 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10968 tcg_res
[pass
] = tcg_temp_new_i64();
10971 case 0x17: /* ADDP */
10972 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10974 case 0x58: /* FMAXNMP */
10975 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10977 case 0x5a: /* FADDP */
10978 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10980 case 0x5e: /* FMAXP */
10981 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10983 case 0x78: /* FMINNMP */
10984 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10986 case 0x7e: /* FMINP */
10987 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10990 g_assert_not_reached();
10993 tcg_temp_free_i64(tcg_op1
);
10994 tcg_temp_free_i64(tcg_op2
);
10997 for (pass
= 0; pass
< 2; pass
++) {
10998 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10999 tcg_temp_free_i64(tcg_res
[pass
]);
11002 int maxpass
= is_q
? 4 : 2;
11003 TCGv_i32 tcg_res
[4];
11005 for (pass
= 0; pass
< maxpass
; pass
++) {
11006 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11007 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11008 NeonGenTwoOpFn
*genfn
= NULL
;
11009 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11010 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11012 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11013 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11014 tcg_res
[pass
] = tcg_temp_new_i32();
11017 case 0x17: /* ADDP */
11019 static NeonGenTwoOpFn
* const fns
[3] = {
11020 gen_helper_neon_padd_u8
,
11021 gen_helper_neon_padd_u16
,
11027 case 0x14: /* SMAXP, UMAXP */
11029 static NeonGenTwoOpFn
* const fns
[3][2] = {
11030 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11031 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11032 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11034 genfn
= fns
[size
][u
];
11037 case 0x15: /* SMINP, UMINP */
11039 static NeonGenTwoOpFn
* const fns
[3][2] = {
11040 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11041 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11042 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11044 genfn
= fns
[size
][u
];
11047 /* The FP operations are all on single floats (32 bit) */
11048 case 0x58: /* FMAXNMP */
11049 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11051 case 0x5a: /* FADDP */
11052 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11054 case 0x5e: /* FMAXP */
11055 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11057 case 0x78: /* FMINNMP */
11058 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11060 case 0x7e: /* FMINP */
11061 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11064 g_assert_not_reached();
11067 /* FP ops called directly, otherwise call now */
11069 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11072 tcg_temp_free_i32(tcg_op1
);
11073 tcg_temp_free_i32(tcg_op2
);
11076 for (pass
= 0; pass
< maxpass
; pass
++) {
11077 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11078 tcg_temp_free_i32(tcg_res
[pass
]);
11080 clear_vec_high(s
, is_q
, rd
);
11084 tcg_temp_free_ptr(fpst
);
11088 /* Floating point op subgroup of C3.6.16. */
11089 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11091 /* For floating point ops, the U, size[1] and opcode bits
11092 * together indicate the operation. size[0] indicates single
11095 int fpopcode
= extract32(insn
, 11, 5)
11096 | (extract32(insn
, 23, 1) << 5)
11097 | (extract32(insn
, 29, 1) << 6);
11098 int is_q
= extract32(insn
, 30, 1);
11099 int size
= extract32(insn
, 22, 1);
11100 int rm
= extract32(insn
, 16, 5);
11101 int rn
= extract32(insn
, 5, 5);
11102 int rd
= extract32(insn
, 0, 5);
11104 int datasize
= is_q
? 128 : 64;
11105 int esize
= 32 << size
;
11106 int elements
= datasize
/ esize
;
11108 if (size
== 1 && !is_q
) {
11109 unallocated_encoding(s
);
11113 switch (fpopcode
) {
11114 case 0x58: /* FMAXNMP */
11115 case 0x5a: /* FADDP */
11116 case 0x5e: /* FMAXP */
11117 case 0x78: /* FMINNMP */
11118 case 0x7e: /* FMINP */
11119 if (size
&& !is_q
) {
11120 unallocated_encoding(s
);
11123 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11126 case 0x1b: /* FMULX */
11127 case 0x1f: /* FRECPS */
11128 case 0x3f: /* FRSQRTS */
11129 case 0x5d: /* FACGE */
11130 case 0x7d: /* FACGT */
11131 case 0x19: /* FMLA */
11132 case 0x39: /* FMLS */
11133 case 0x18: /* FMAXNM */
11134 case 0x1a: /* FADD */
11135 case 0x1c: /* FCMEQ */
11136 case 0x1e: /* FMAX */
11137 case 0x38: /* FMINNM */
11138 case 0x3a: /* FSUB */
11139 case 0x3e: /* FMIN */
11140 case 0x5b: /* FMUL */
11141 case 0x5c: /* FCMGE */
11142 case 0x5f: /* FDIV */
11143 case 0x7a: /* FABD */
11144 case 0x7c: /* FCMGT */
11145 if (!fp_access_check(s
)) {
11148 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11151 case 0x1d: /* FMLAL */
11152 case 0x3d: /* FMLSL */
11153 case 0x59: /* FMLAL2 */
11154 case 0x79: /* FMLSL2 */
11155 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11156 unallocated_encoding(s
);
11159 if (fp_access_check(s
)) {
11160 int is_s
= extract32(insn
, 23, 1);
11161 int is_2
= extract32(insn
, 29, 1);
11162 int data
= (is_2
<< 1) | is_s
;
11163 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11164 vec_full_reg_offset(s
, rn
),
11165 vec_full_reg_offset(s
, rm
), cpu_env
,
11166 is_q
? 16 : 8, vec_full_reg_size(s
),
11167 data
, gen_helper_gvec_fmlal_a64
);
11172 unallocated_encoding(s
);
11177 /* Integer op subgroup of C3.6.16. */
11178 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11180 int is_q
= extract32(insn
, 30, 1);
11181 int u
= extract32(insn
, 29, 1);
11182 int size
= extract32(insn
, 22, 2);
11183 int opcode
= extract32(insn
, 11, 5);
11184 int rm
= extract32(insn
, 16, 5);
11185 int rn
= extract32(insn
, 5, 5);
11186 int rd
= extract32(insn
, 0, 5);
11191 case 0x13: /* MUL, PMUL */
11192 if (u
&& size
!= 0) {
11193 unallocated_encoding(s
);
11197 case 0x0: /* SHADD, UHADD */
11198 case 0x2: /* SRHADD, URHADD */
11199 case 0x4: /* SHSUB, UHSUB */
11200 case 0xc: /* SMAX, UMAX */
11201 case 0xd: /* SMIN, UMIN */
11202 case 0xe: /* SABD, UABD */
11203 case 0xf: /* SABA, UABA */
11204 case 0x12: /* MLA, MLS */
11206 unallocated_encoding(s
);
11210 case 0x16: /* SQDMULH, SQRDMULH */
11211 if (size
== 0 || size
== 3) {
11212 unallocated_encoding(s
);
11217 if (size
== 3 && !is_q
) {
11218 unallocated_encoding(s
);
11224 if (!fp_access_check(s
)) {
11229 case 0x01: /* SQADD, UQADD */
11230 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11231 offsetof(CPUARMState
, vfp
.qc
),
11232 vec_full_reg_offset(s
, rn
),
11233 vec_full_reg_offset(s
, rm
),
11234 is_q
? 16 : 8, vec_full_reg_size(s
),
11235 (u
? uqadd_op
: sqadd_op
) + size
);
11237 case 0x05: /* SQSUB, UQSUB */
11238 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11239 offsetof(CPUARMState
, vfp
.qc
),
11240 vec_full_reg_offset(s
, rn
),
11241 vec_full_reg_offset(s
, rm
),
11242 is_q
? 16 : 8, vec_full_reg_size(s
),
11243 (u
? uqsub_op
: sqsub_op
) + size
);
11245 case 0x0c: /* SMAX, UMAX */
11247 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11249 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11252 case 0x0d: /* SMIN, UMIN */
11254 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11256 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11259 case 0x10: /* ADD, SUB */
11261 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11263 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11266 case 0x13: /* MUL, PMUL */
11267 if (!u
) { /* MUL */
11268 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11272 case 0x12: /* MLA, MLS */
11274 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11276 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11280 if (!u
) { /* CMTST */
11281 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11285 cond
= TCG_COND_EQ
;
11287 case 0x06: /* CMGT, CMHI */
11288 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11290 case 0x07: /* CMGE, CMHS */
11291 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11293 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11294 vec_full_reg_offset(s
, rn
),
11295 vec_full_reg_offset(s
, rm
),
11296 is_q
? 16 : 8, vec_full_reg_size(s
));
11302 for (pass
= 0; pass
< 2; pass
++) {
11303 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11304 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11305 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11307 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11308 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11310 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11312 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11314 tcg_temp_free_i64(tcg_res
);
11315 tcg_temp_free_i64(tcg_op1
);
11316 tcg_temp_free_i64(tcg_op2
);
11319 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11320 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11321 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11322 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11323 NeonGenTwoOpFn
*genfn
= NULL
;
11324 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11326 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11327 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11330 case 0x0: /* SHADD, UHADD */
11332 static NeonGenTwoOpFn
* const fns
[3][2] = {
11333 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11334 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11335 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11337 genfn
= fns
[size
][u
];
11340 case 0x2: /* SRHADD, URHADD */
11342 static NeonGenTwoOpFn
* const fns
[3][2] = {
11343 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11344 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11345 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11347 genfn
= fns
[size
][u
];
11350 case 0x4: /* SHSUB, UHSUB */
11352 static NeonGenTwoOpFn
* const fns
[3][2] = {
11353 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11354 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11355 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11357 genfn
= fns
[size
][u
];
11360 case 0x8: /* SSHL, USHL */
11362 static NeonGenTwoOpFn
* const fns
[3][2] = {
11363 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11364 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11365 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11367 genfn
= fns
[size
][u
];
11370 case 0x9: /* SQSHL, UQSHL */
11372 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11373 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11374 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11375 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11377 genenvfn
= fns
[size
][u
];
11380 case 0xa: /* SRSHL, URSHL */
11382 static NeonGenTwoOpFn
* const fns
[3][2] = {
11383 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11384 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11385 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11387 genfn
= fns
[size
][u
];
11390 case 0xb: /* SQRSHL, UQRSHL */
11392 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11393 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11394 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11395 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11397 genenvfn
= fns
[size
][u
];
11400 case 0xe: /* SABD, UABD */
11401 case 0xf: /* SABA, UABA */
11403 static NeonGenTwoOpFn
* const fns
[3][2] = {
11404 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11405 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11406 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11408 genfn
= fns
[size
][u
];
11411 case 0x13: /* MUL, PMUL */
11412 assert(u
); /* PMUL */
11414 genfn
= gen_helper_neon_mul_p8
;
11416 case 0x16: /* SQDMULH, SQRDMULH */
11418 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11419 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11420 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11422 assert(size
== 1 || size
== 2);
11423 genenvfn
= fns
[size
- 1][u
];
11427 g_assert_not_reached();
11431 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11433 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11436 if (opcode
== 0xf) {
11437 /* SABA, UABA: accumulating ops */
11438 static NeonGenTwoOpFn
* const fns
[3] = {
11439 gen_helper_neon_add_u8
,
11440 gen_helper_neon_add_u16
,
11444 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11445 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11448 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11450 tcg_temp_free_i32(tcg_res
);
11451 tcg_temp_free_i32(tcg_op1
);
11452 tcg_temp_free_i32(tcg_op2
);
11455 clear_vec_high(s
, is_q
, rd
);
11458 /* AdvSIMD three same
11459 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11460 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11461 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11462 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11464 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11466 int opcode
= extract32(insn
, 11, 5);
11469 case 0x3: /* logic ops */
11470 disas_simd_3same_logic(s
, insn
);
11472 case 0x17: /* ADDP */
11473 case 0x14: /* SMAXP, UMAXP */
11474 case 0x15: /* SMINP, UMINP */
11476 /* Pairwise operations */
11477 int is_q
= extract32(insn
, 30, 1);
11478 int u
= extract32(insn
, 29, 1);
11479 int size
= extract32(insn
, 22, 2);
11480 int rm
= extract32(insn
, 16, 5);
11481 int rn
= extract32(insn
, 5, 5);
11482 int rd
= extract32(insn
, 0, 5);
11483 if (opcode
== 0x17) {
11484 if (u
|| (size
== 3 && !is_q
)) {
11485 unallocated_encoding(s
);
11490 unallocated_encoding(s
);
11494 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11497 case 0x18 ... 0x31:
11498 /* floating point ops, sz[1] and U are part of opcode */
11499 disas_simd_3same_float(s
, insn
);
11502 disas_simd_3same_int(s
, insn
);
11508 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11510 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11511 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11512 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11513 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11515 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11516 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11519 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11521 int opcode
, fpopcode
;
11522 int is_q
, u
, a
, rm
, rn
, rd
;
11523 int datasize
, elements
;
11526 bool pairwise
= false;
11528 if (!dc_isar_feature(aa64_fp16
, s
)) {
11529 unallocated_encoding(s
);
11533 if (!fp_access_check(s
)) {
11537 /* For these floating point ops, the U, a and opcode bits
11538 * together indicate the operation.
11540 opcode
= extract32(insn
, 11, 3);
11541 u
= extract32(insn
, 29, 1);
11542 a
= extract32(insn
, 23, 1);
11543 is_q
= extract32(insn
, 30, 1);
11544 rm
= extract32(insn
, 16, 5);
11545 rn
= extract32(insn
, 5, 5);
11546 rd
= extract32(insn
, 0, 5);
11548 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11549 datasize
= is_q
? 128 : 64;
11550 elements
= datasize
/ 16;
11552 switch (fpopcode
) {
11553 case 0x10: /* FMAXNMP */
11554 case 0x12: /* FADDP */
11555 case 0x16: /* FMAXP */
11556 case 0x18: /* FMINNMP */
11557 case 0x1e: /* FMINP */
11562 fpst
= get_fpstatus_ptr(true);
11565 int maxpass
= is_q
? 8 : 4;
11566 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11567 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11568 TCGv_i32 tcg_res
[8];
11570 for (pass
= 0; pass
< maxpass
; pass
++) {
11571 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11572 int passelt
= (pass
<< 1) & (maxpass
- 1);
11574 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11575 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11576 tcg_res
[pass
] = tcg_temp_new_i32();
11578 switch (fpopcode
) {
11579 case 0x10: /* FMAXNMP */
11580 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11583 case 0x12: /* FADDP */
11584 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11586 case 0x16: /* FMAXP */
11587 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11589 case 0x18: /* FMINNMP */
11590 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11593 case 0x1e: /* FMINP */
11594 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11597 g_assert_not_reached();
11601 for (pass
= 0; pass
< maxpass
; pass
++) {
11602 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11603 tcg_temp_free_i32(tcg_res
[pass
]);
11606 tcg_temp_free_i32(tcg_op1
);
11607 tcg_temp_free_i32(tcg_op2
);
11610 for (pass
= 0; pass
< elements
; pass
++) {
11611 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11612 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11613 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11615 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11616 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11618 switch (fpopcode
) {
11619 case 0x0: /* FMAXNM */
11620 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11622 case 0x1: /* FMLA */
11623 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11624 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11627 case 0x2: /* FADD */
11628 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11630 case 0x3: /* FMULX */
11631 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11633 case 0x4: /* FCMEQ */
11634 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11636 case 0x6: /* FMAX */
11637 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11639 case 0x7: /* FRECPS */
11640 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11642 case 0x8: /* FMINNM */
11643 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11645 case 0x9: /* FMLS */
11646 /* As usual for ARM, separate negation for fused multiply-add */
11647 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11648 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11649 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11652 case 0xa: /* FSUB */
11653 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11655 case 0xe: /* FMIN */
11656 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11658 case 0xf: /* FRSQRTS */
11659 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11661 case 0x13: /* FMUL */
11662 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11664 case 0x14: /* FCMGE */
11665 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11667 case 0x15: /* FACGE */
11668 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11670 case 0x17: /* FDIV */
11671 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11673 case 0x1a: /* FABD */
11674 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11675 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11677 case 0x1c: /* FCMGT */
11678 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11680 case 0x1d: /* FACGT */
11681 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11684 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11685 __func__
, insn
, fpopcode
, s
->pc
);
11686 g_assert_not_reached();
11689 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11690 tcg_temp_free_i32(tcg_res
);
11691 tcg_temp_free_i32(tcg_op1
);
11692 tcg_temp_free_i32(tcg_op2
);
11696 tcg_temp_free_ptr(fpst
);
11698 clear_vec_high(s
, is_q
, rd
);
11701 /* AdvSIMD three same extra
11702 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11703 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11704 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11705 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11707 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11709 int rd
= extract32(insn
, 0, 5);
11710 int rn
= extract32(insn
, 5, 5);
11711 int opcode
= extract32(insn
, 11, 4);
11712 int rm
= extract32(insn
, 16, 5);
11713 int size
= extract32(insn
, 22, 2);
11714 bool u
= extract32(insn
, 29, 1);
11715 bool is_q
= extract32(insn
, 30, 1);
11719 switch (u
* 16 + opcode
) {
11720 case 0x10: /* SQRDMLAH (vector) */
11721 case 0x11: /* SQRDMLSH (vector) */
11722 if (size
!= 1 && size
!= 2) {
11723 unallocated_encoding(s
);
11726 feature
= dc_isar_feature(aa64_rdm
, s
);
11728 case 0x02: /* SDOT (vector) */
11729 case 0x12: /* UDOT (vector) */
11730 if (size
!= MO_32
) {
11731 unallocated_encoding(s
);
11734 feature
= dc_isar_feature(aa64_dp
, s
);
11736 case 0x18: /* FCMLA, #0 */
11737 case 0x19: /* FCMLA, #90 */
11738 case 0x1a: /* FCMLA, #180 */
11739 case 0x1b: /* FCMLA, #270 */
11740 case 0x1c: /* FCADD, #90 */
11741 case 0x1e: /* FCADD, #270 */
11743 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11744 || (size
== 3 && !is_q
)) {
11745 unallocated_encoding(s
);
11748 feature
= dc_isar_feature(aa64_fcma
, s
);
11751 unallocated_encoding(s
);
11755 unallocated_encoding(s
);
11758 if (!fp_access_check(s
)) {
11763 case 0x0: /* SQRDMLAH (vector) */
11766 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11769 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11772 g_assert_not_reached();
11776 case 0x1: /* SQRDMLSH (vector) */
11779 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11782 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11785 g_assert_not_reached();
11789 case 0x2: /* SDOT / UDOT */
11790 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11791 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11794 case 0x8: /* FCMLA, #0 */
11795 case 0x9: /* FCMLA, #90 */
11796 case 0xa: /* FCMLA, #180 */
11797 case 0xb: /* FCMLA, #270 */
11798 rot
= extract32(opcode
, 0, 2);
11801 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11802 gen_helper_gvec_fcmlah
);
11805 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11806 gen_helper_gvec_fcmlas
);
11809 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11810 gen_helper_gvec_fcmlad
);
11813 g_assert_not_reached();
11817 case 0xc: /* FCADD, #90 */
11818 case 0xe: /* FCADD, #270 */
11819 rot
= extract32(opcode
, 1, 1);
11822 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11823 gen_helper_gvec_fcaddh
);
11826 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11827 gen_helper_gvec_fcadds
);
11830 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11831 gen_helper_gvec_fcaddd
);
11834 g_assert_not_reached();
11839 g_assert_not_reached();
11843 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11844 int size
, int rn
, int rd
)
11846 /* Handle 2-reg-misc ops which are widening (so each size element
11847 * in the source becomes a 2*size element in the destination.
11848 * The only instruction like this is FCVTL.
11853 /* 32 -> 64 bit fp conversion */
11854 TCGv_i64 tcg_res
[2];
11855 int srcelt
= is_q
? 2 : 0;
11857 for (pass
= 0; pass
< 2; pass
++) {
11858 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11859 tcg_res
[pass
] = tcg_temp_new_i64();
11861 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11862 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11863 tcg_temp_free_i32(tcg_op
);
11865 for (pass
= 0; pass
< 2; pass
++) {
11866 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11867 tcg_temp_free_i64(tcg_res
[pass
]);
11870 /* 16 -> 32 bit fp conversion */
11871 int srcelt
= is_q
? 4 : 0;
11872 TCGv_i32 tcg_res
[4];
11873 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11874 TCGv_i32 ahp
= get_ahp_flag();
11876 for (pass
= 0; pass
< 4; pass
++) {
11877 tcg_res
[pass
] = tcg_temp_new_i32();
11879 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11880 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11883 for (pass
= 0; pass
< 4; pass
++) {
11884 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11885 tcg_temp_free_i32(tcg_res
[pass
]);
11888 tcg_temp_free_ptr(fpst
);
11889 tcg_temp_free_i32(ahp
);
11893 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11894 bool is_q
, int size
, int rn
, int rd
)
11896 int op
= (opcode
<< 1) | u
;
11897 int opsz
= op
+ size
;
11898 int grp_size
= 3 - opsz
;
11899 int dsize
= is_q
? 128 : 64;
11903 unallocated_encoding(s
);
11907 if (!fp_access_check(s
)) {
11912 /* Special case bytes, use bswap op on each group of elements */
11913 int groups
= dsize
/ (8 << grp_size
);
11915 for (i
= 0; i
< groups
; i
++) {
11916 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11918 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11919 switch (grp_size
) {
11921 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11924 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11927 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11930 g_assert_not_reached();
11932 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11933 tcg_temp_free_i64(tcg_tmp
);
11935 clear_vec_high(s
, is_q
, rd
);
11937 int revmask
= (1 << grp_size
) - 1;
11938 int esize
= 8 << size
;
11939 int elements
= dsize
/ esize
;
11940 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11941 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11942 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11944 for (i
= 0; i
< elements
; i
++) {
11945 int e_rev
= (i
& 0xf) ^ revmask
;
11946 int off
= e_rev
* esize
;
11947 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11949 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11950 tcg_rn
, off
- 64, esize
);
11952 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11955 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11956 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11958 tcg_temp_free_i64(tcg_rd_hi
);
11959 tcg_temp_free_i64(tcg_rd
);
11960 tcg_temp_free_i64(tcg_rn
);
11964 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11965 bool is_q
, int size
, int rn
, int rd
)
11967 /* Implement the pairwise operations from 2-misc:
11968 * SADDLP, UADDLP, SADALP, UADALP.
11969 * These all add pairs of elements in the input to produce a
11970 * double-width result element in the output (possibly accumulating).
11972 bool accum
= (opcode
== 0x6);
11973 int maxpass
= is_q
? 2 : 1;
11975 TCGv_i64 tcg_res
[2];
11978 /* 32 + 32 -> 64 op */
11979 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11981 for (pass
= 0; pass
< maxpass
; pass
++) {
11982 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11983 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11985 tcg_res
[pass
] = tcg_temp_new_i64();
11987 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11988 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11989 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11991 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11992 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11995 tcg_temp_free_i64(tcg_op1
);
11996 tcg_temp_free_i64(tcg_op2
);
11999 for (pass
= 0; pass
< maxpass
; pass
++) {
12000 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12001 NeonGenOneOpFn
*genfn
;
12002 static NeonGenOneOpFn
* const fns
[2][2] = {
12003 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12004 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12007 genfn
= fns
[size
][u
];
12009 tcg_res
[pass
] = tcg_temp_new_i64();
12011 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12012 genfn(tcg_res
[pass
], tcg_op
);
12015 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12017 gen_helper_neon_addl_u16(tcg_res
[pass
],
12018 tcg_res
[pass
], tcg_op
);
12020 gen_helper_neon_addl_u32(tcg_res
[pass
],
12021 tcg_res
[pass
], tcg_op
);
12024 tcg_temp_free_i64(tcg_op
);
12028 tcg_res
[1] = tcg_const_i64(0);
12030 for (pass
= 0; pass
< 2; pass
++) {
12031 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12032 tcg_temp_free_i64(tcg_res
[pass
]);
12036 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12038 /* Implement SHLL and SHLL2 */
12040 int part
= is_q
? 2 : 0;
12041 TCGv_i64 tcg_res
[2];
12043 for (pass
= 0; pass
< 2; pass
++) {
12044 static NeonGenWidenFn
* const widenfns
[3] = {
12045 gen_helper_neon_widen_u8
,
12046 gen_helper_neon_widen_u16
,
12047 tcg_gen_extu_i32_i64
,
12049 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12050 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12052 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12053 tcg_res
[pass
] = tcg_temp_new_i64();
12054 widenfn(tcg_res
[pass
], tcg_op
);
12055 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12057 tcg_temp_free_i32(tcg_op
);
12060 for (pass
= 0; pass
< 2; pass
++) {
12061 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12062 tcg_temp_free_i64(tcg_res
[pass
]);
12066 /* AdvSIMD two reg misc
12067 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12068 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12069 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12070 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12072 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12074 int size
= extract32(insn
, 22, 2);
12075 int opcode
= extract32(insn
, 12, 5);
12076 bool u
= extract32(insn
, 29, 1);
12077 bool is_q
= extract32(insn
, 30, 1);
12078 int rn
= extract32(insn
, 5, 5);
12079 int rd
= extract32(insn
, 0, 5);
12080 bool need_fpstatus
= false;
12081 bool need_rmode
= false;
12083 TCGv_i32 tcg_rmode
;
12084 TCGv_ptr tcg_fpstatus
;
12087 case 0x0: /* REV64, REV32 */
12088 case 0x1: /* REV16 */
12089 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12091 case 0x5: /* CNT, NOT, RBIT */
12092 if (u
&& size
== 0) {
12095 } else if (u
&& size
== 1) {
12098 } else if (!u
&& size
== 0) {
12102 unallocated_encoding(s
);
12104 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12105 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12107 unallocated_encoding(s
);
12110 if (!fp_access_check(s
)) {
12114 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12116 case 0x4: /* CLS, CLZ */
12118 unallocated_encoding(s
);
12122 case 0x2: /* SADDLP, UADDLP */
12123 case 0x6: /* SADALP, UADALP */
12125 unallocated_encoding(s
);
12128 if (!fp_access_check(s
)) {
12131 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12133 case 0x13: /* SHLL, SHLL2 */
12134 if (u
== 0 || size
== 3) {
12135 unallocated_encoding(s
);
12138 if (!fp_access_check(s
)) {
12141 handle_shll(s
, is_q
, size
, rn
, rd
);
12143 case 0xa: /* CMLT */
12145 unallocated_encoding(s
);
12149 case 0x8: /* CMGT, CMGE */
12150 case 0x9: /* CMEQ, CMLE */
12151 case 0xb: /* ABS, NEG */
12152 if (size
== 3 && !is_q
) {
12153 unallocated_encoding(s
);
12157 case 0x3: /* SUQADD, USQADD */
12158 if (size
== 3 && !is_q
) {
12159 unallocated_encoding(s
);
12162 if (!fp_access_check(s
)) {
12165 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12167 case 0x7: /* SQABS, SQNEG */
12168 if (size
== 3 && !is_q
) {
12169 unallocated_encoding(s
);
12174 case 0x16 ... 0x1f:
12176 /* Floating point: U, size[1] and opcode indicate operation;
12177 * size[0] indicates single or double precision.
12179 int is_double
= extract32(size
, 0, 1);
12180 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12181 size
= is_double
? 3 : 2;
12183 case 0x2f: /* FABS */
12184 case 0x6f: /* FNEG */
12185 if (size
== 3 && !is_q
) {
12186 unallocated_encoding(s
);
12190 case 0x1d: /* SCVTF */
12191 case 0x5d: /* UCVTF */
12193 bool is_signed
= (opcode
== 0x1d) ? true : false;
12194 int elements
= is_double
? 2 : is_q
? 4 : 2;
12195 if (is_double
&& !is_q
) {
12196 unallocated_encoding(s
);
12199 if (!fp_access_check(s
)) {
12202 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12205 case 0x2c: /* FCMGT (zero) */
12206 case 0x2d: /* FCMEQ (zero) */
12207 case 0x2e: /* FCMLT (zero) */
12208 case 0x6c: /* FCMGE (zero) */
12209 case 0x6d: /* FCMLE (zero) */
12210 if (size
== 3 && !is_q
) {
12211 unallocated_encoding(s
);
12214 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12216 case 0x7f: /* FSQRT */
12217 if (size
== 3 && !is_q
) {
12218 unallocated_encoding(s
);
12222 case 0x1a: /* FCVTNS */
12223 case 0x1b: /* FCVTMS */
12224 case 0x3a: /* FCVTPS */
12225 case 0x3b: /* FCVTZS */
12226 case 0x5a: /* FCVTNU */
12227 case 0x5b: /* FCVTMU */
12228 case 0x7a: /* FCVTPU */
12229 case 0x7b: /* FCVTZU */
12230 need_fpstatus
= true;
12232 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12233 if (size
== 3 && !is_q
) {
12234 unallocated_encoding(s
);
12238 case 0x5c: /* FCVTAU */
12239 case 0x1c: /* FCVTAS */
12240 need_fpstatus
= true;
12242 rmode
= FPROUNDING_TIEAWAY
;
12243 if (size
== 3 && !is_q
) {
12244 unallocated_encoding(s
);
12248 case 0x3c: /* URECPE */
12250 unallocated_encoding(s
);
12254 case 0x3d: /* FRECPE */
12255 case 0x7d: /* FRSQRTE */
12256 if (size
== 3 && !is_q
) {
12257 unallocated_encoding(s
);
12260 if (!fp_access_check(s
)) {
12263 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12265 case 0x56: /* FCVTXN, FCVTXN2 */
12267 unallocated_encoding(s
);
12271 case 0x16: /* FCVTN, FCVTN2 */
12272 /* handle_2misc_narrow does a 2*size -> size operation, but these
12273 * instructions encode the source size rather than dest size.
12275 if (!fp_access_check(s
)) {
12278 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12280 case 0x17: /* FCVTL, FCVTL2 */
12281 if (!fp_access_check(s
)) {
12284 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12286 case 0x18: /* FRINTN */
12287 case 0x19: /* FRINTM */
12288 case 0x38: /* FRINTP */
12289 case 0x39: /* FRINTZ */
12291 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12293 case 0x59: /* FRINTX */
12294 case 0x79: /* FRINTI */
12295 need_fpstatus
= true;
12296 if (size
== 3 && !is_q
) {
12297 unallocated_encoding(s
);
12301 case 0x58: /* FRINTA */
12303 rmode
= FPROUNDING_TIEAWAY
;
12304 need_fpstatus
= true;
12305 if (size
== 3 && !is_q
) {
12306 unallocated_encoding(s
);
12310 case 0x7c: /* URSQRTE */
12312 unallocated_encoding(s
);
12315 need_fpstatus
= true;
12317 case 0x1e: /* FRINT32Z */
12318 case 0x1f: /* FRINT64Z */
12320 rmode
= FPROUNDING_ZERO
;
12322 case 0x5e: /* FRINT32X */
12323 case 0x5f: /* FRINT64X */
12324 need_fpstatus
= true;
12325 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12326 unallocated_encoding(s
);
12331 unallocated_encoding(s
);
12337 unallocated_encoding(s
);
12341 if (!fp_access_check(s
)) {
12345 if (need_fpstatus
|| need_rmode
) {
12346 tcg_fpstatus
= get_fpstatus_ptr(false);
12348 tcg_fpstatus
= NULL
;
12351 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12352 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12359 if (u
&& size
== 0) { /* NOT */
12360 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12365 if (u
) { /* ABS, NEG */
12366 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12368 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12374 /* All 64-bit element operations can be shared with scalar 2misc */
12377 /* Coverity claims (size == 3 && !is_q) has been eliminated
12378 * from all paths leading to here.
12380 tcg_debug_assert(is_q
);
12381 for (pass
= 0; pass
< 2; pass
++) {
12382 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12383 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12385 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12387 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12388 tcg_rmode
, tcg_fpstatus
);
12390 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12392 tcg_temp_free_i64(tcg_res
);
12393 tcg_temp_free_i64(tcg_op
);
12398 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12399 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12400 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12403 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12406 /* Special cases for 32 bit elements */
12408 case 0xa: /* CMLT */
12409 /* 32 bit integer comparison against zero, result is
12410 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12413 cond
= TCG_COND_LT
;
12415 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12416 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12418 case 0x8: /* CMGT, CMGE */
12419 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12421 case 0x9: /* CMEQ, CMLE */
12422 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12424 case 0x4: /* CLS */
12426 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12428 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12431 case 0x7: /* SQABS, SQNEG */
12433 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12435 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12438 case 0x2f: /* FABS */
12439 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12441 case 0x6f: /* FNEG */
12442 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12444 case 0x7f: /* FSQRT */
12445 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12447 case 0x1a: /* FCVTNS */
12448 case 0x1b: /* FCVTMS */
12449 case 0x1c: /* FCVTAS */
12450 case 0x3a: /* FCVTPS */
12451 case 0x3b: /* FCVTZS */
12453 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12454 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12455 tcg_shift
, tcg_fpstatus
);
12456 tcg_temp_free_i32(tcg_shift
);
12459 case 0x5a: /* FCVTNU */
12460 case 0x5b: /* FCVTMU */
12461 case 0x5c: /* FCVTAU */
12462 case 0x7a: /* FCVTPU */
12463 case 0x7b: /* FCVTZU */
12465 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12466 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12467 tcg_shift
, tcg_fpstatus
);
12468 tcg_temp_free_i32(tcg_shift
);
12471 case 0x18: /* FRINTN */
12472 case 0x19: /* FRINTM */
12473 case 0x38: /* FRINTP */
12474 case 0x39: /* FRINTZ */
12475 case 0x58: /* FRINTA */
12476 case 0x79: /* FRINTI */
12477 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12479 case 0x59: /* FRINTX */
12480 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12482 case 0x7c: /* URSQRTE */
12483 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12485 case 0x1e: /* FRINT32Z */
12486 case 0x5e: /* FRINT32X */
12487 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12489 case 0x1f: /* FRINT64Z */
12490 case 0x5f: /* FRINT64X */
12491 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12494 g_assert_not_reached();
12497 /* Use helpers for 8 and 16 bit elements */
12499 case 0x5: /* CNT, RBIT */
12500 /* For these two insns size is part of the opcode specifier
12501 * (handled earlier); they always operate on byte elements.
12504 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12506 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12509 case 0x7: /* SQABS, SQNEG */
12511 NeonGenOneOpEnvFn
*genfn
;
12512 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12513 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12514 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12516 genfn
= fns
[size
][u
];
12517 genfn(tcg_res
, cpu_env
, tcg_op
);
12520 case 0x8: /* CMGT, CMGE */
12521 case 0x9: /* CMEQ, CMLE */
12522 case 0xa: /* CMLT */
12524 static NeonGenTwoOpFn
* const fns
[3][2] = {
12525 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12526 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12527 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12529 NeonGenTwoOpFn
*genfn
;
12532 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12534 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12535 comp
= (opcode
- 0x8) * 2 + u
;
12536 /* ...but LE, LT are implemented as reverse GE, GT */
12537 reverse
= (comp
> 2);
12541 genfn
= fns
[comp
][size
];
12543 genfn(tcg_res
, tcg_zero
, tcg_op
);
12545 genfn(tcg_res
, tcg_op
, tcg_zero
);
12547 tcg_temp_free_i32(tcg_zero
);
12550 case 0x4: /* CLS, CLZ */
12553 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12555 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12559 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12561 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12566 g_assert_not_reached();
12570 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12572 tcg_temp_free_i32(tcg_res
);
12573 tcg_temp_free_i32(tcg_op
);
12576 clear_vec_high(s
, is_q
, rd
);
12579 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12580 tcg_temp_free_i32(tcg_rmode
);
12582 if (need_fpstatus
) {
12583 tcg_temp_free_ptr(tcg_fpstatus
);
12587 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12589 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12590 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12591 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12592 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12593 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12594 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12596 * This actually covers two groups where scalar access is governed by
12597 * bit 28. A bunch of the instructions (float to integral) only exist
12598 * in the vector form and are un-allocated for the scalar decode. Also
12599 * in the scalar decode Q is always 1.
12601 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12603 int fpop
, opcode
, a
, u
;
12607 bool only_in_vector
= false;
12610 TCGv_i32 tcg_rmode
= NULL
;
12611 TCGv_ptr tcg_fpstatus
= NULL
;
12612 bool need_rmode
= false;
12613 bool need_fpst
= true;
12616 if (!dc_isar_feature(aa64_fp16
, s
)) {
12617 unallocated_encoding(s
);
12621 rd
= extract32(insn
, 0, 5);
12622 rn
= extract32(insn
, 5, 5);
12624 a
= extract32(insn
, 23, 1);
12625 u
= extract32(insn
, 29, 1);
12626 is_scalar
= extract32(insn
, 28, 1);
12627 is_q
= extract32(insn
, 30, 1);
12629 opcode
= extract32(insn
, 12, 5);
12630 fpop
= deposit32(opcode
, 5, 1, a
);
12631 fpop
= deposit32(fpop
, 6, 1, u
);
12633 rd
= extract32(insn
, 0, 5);
12634 rn
= extract32(insn
, 5, 5);
12637 case 0x1d: /* SCVTF */
12638 case 0x5d: /* UCVTF */
12645 elements
= (is_q
? 8 : 4);
12648 if (!fp_access_check(s
)) {
12651 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12655 case 0x2c: /* FCMGT (zero) */
12656 case 0x2d: /* FCMEQ (zero) */
12657 case 0x2e: /* FCMLT (zero) */
12658 case 0x6c: /* FCMGE (zero) */
12659 case 0x6d: /* FCMLE (zero) */
12660 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12662 case 0x3d: /* FRECPE */
12663 case 0x3f: /* FRECPX */
12665 case 0x18: /* FRINTN */
12667 only_in_vector
= true;
12668 rmode
= FPROUNDING_TIEEVEN
;
12670 case 0x19: /* FRINTM */
12672 only_in_vector
= true;
12673 rmode
= FPROUNDING_NEGINF
;
12675 case 0x38: /* FRINTP */
12677 only_in_vector
= true;
12678 rmode
= FPROUNDING_POSINF
;
12680 case 0x39: /* FRINTZ */
12682 only_in_vector
= true;
12683 rmode
= FPROUNDING_ZERO
;
12685 case 0x58: /* FRINTA */
12687 only_in_vector
= true;
12688 rmode
= FPROUNDING_TIEAWAY
;
12690 case 0x59: /* FRINTX */
12691 case 0x79: /* FRINTI */
12692 only_in_vector
= true;
12693 /* current rounding mode */
12695 case 0x1a: /* FCVTNS */
12697 rmode
= FPROUNDING_TIEEVEN
;
12699 case 0x1b: /* FCVTMS */
12701 rmode
= FPROUNDING_NEGINF
;
12703 case 0x1c: /* FCVTAS */
12705 rmode
= FPROUNDING_TIEAWAY
;
12707 case 0x3a: /* FCVTPS */
12709 rmode
= FPROUNDING_POSINF
;
12711 case 0x3b: /* FCVTZS */
12713 rmode
= FPROUNDING_ZERO
;
12715 case 0x5a: /* FCVTNU */
12717 rmode
= FPROUNDING_TIEEVEN
;
12719 case 0x5b: /* FCVTMU */
12721 rmode
= FPROUNDING_NEGINF
;
12723 case 0x5c: /* FCVTAU */
12725 rmode
= FPROUNDING_TIEAWAY
;
12727 case 0x7a: /* FCVTPU */
12729 rmode
= FPROUNDING_POSINF
;
12731 case 0x7b: /* FCVTZU */
12733 rmode
= FPROUNDING_ZERO
;
12735 case 0x2f: /* FABS */
12736 case 0x6f: /* FNEG */
12739 case 0x7d: /* FRSQRTE */
12740 case 0x7f: /* FSQRT (vector) */
12743 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12744 g_assert_not_reached();
12748 /* Check additional constraints for the scalar encoding */
12751 unallocated_encoding(s
);
12754 /* FRINTxx is only in the vector form */
12755 if (only_in_vector
) {
12756 unallocated_encoding(s
);
12761 if (!fp_access_check(s
)) {
12765 if (need_rmode
|| need_fpst
) {
12766 tcg_fpstatus
= get_fpstatus_ptr(true);
12770 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12771 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12775 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12776 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12779 case 0x1a: /* FCVTNS */
12780 case 0x1b: /* FCVTMS */
12781 case 0x1c: /* FCVTAS */
12782 case 0x3a: /* FCVTPS */
12783 case 0x3b: /* FCVTZS */
12784 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12786 case 0x3d: /* FRECPE */
12787 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12789 case 0x3f: /* FRECPX */
12790 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12792 case 0x5a: /* FCVTNU */
12793 case 0x5b: /* FCVTMU */
12794 case 0x5c: /* FCVTAU */
12795 case 0x7a: /* FCVTPU */
12796 case 0x7b: /* FCVTZU */
12797 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12799 case 0x6f: /* FNEG */
12800 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12802 case 0x7d: /* FRSQRTE */
12803 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12806 g_assert_not_reached();
12809 /* limit any sign extension going on */
12810 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12811 write_fp_sreg(s
, rd
, tcg_res
);
12813 tcg_temp_free_i32(tcg_res
);
12814 tcg_temp_free_i32(tcg_op
);
12816 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12817 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12818 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12820 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12823 case 0x1a: /* FCVTNS */
12824 case 0x1b: /* FCVTMS */
12825 case 0x1c: /* FCVTAS */
12826 case 0x3a: /* FCVTPS */
12827 case 0x3b: /* FCVTZS */
12828 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12830 case 0x3d: /* FRECPE */
12831 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12833 case 0x5a: /* FCVTNU */
12834 case 0x5b: /* FCVTMU */
12835 case 0x5c: /* FCVTAU */
12836 case 0x7a: /* FCVTPU */
12837 case 0x7b: /* FCVTZU */
12838 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12840 case 0x18: /* FRINTN */
12841 case 0x19: /* FRINTM */
12842 case 0x38: /* FRINTP */
12843 case 0x39: /* FRINTZ */
12844 case 0x58: /* FRINTA */
12845 case 0x79: /* FRINTI */
12846 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12848 case 0x59: /* FRINTX */
12849 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12851 case 0x2f: /* FABS */
12852 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12854 case 0x6f: /* FNEG */
12855 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12857 case 0x7d: /* FRSQRTE */
12858 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12860 case 0x7f: /* FSQRT */
12861 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12864 g_assert_not_reached();
12867 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12869 tcg_temp_free_i32(tcg_res
);
12870 tcg_temp_free_i32(tcg_op
);
12873 clear_vec_high(s
, is_q
, rd
);
12877 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12878 tcg_temp_free_i32(tcg_rmode
);
12881 if (tcg_fpstatus
) {
12882 tcg_temp_free_ptr(tcg_fpstatus
);
12886 /* AdvSIMD scalar x indexed element
12887 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12888 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12889 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12890 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12891 * AdvSIMD vector x indexed element
12892 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12893 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12894 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12895 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12897 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12899 /* This encoding has two kinds of instruction:
12900 * normal, where we perform elt x idxelt => elt for each
12901 * element in the vector
12902 * long, where we perform elt x idxelt and generate a result of
12903 * double the width of the input element
12904 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12906 bool is_scalar
= extract32(insn
, 28, 1);
12907 bool is_q
= extract32(insn
, 30, 1);
12908 bool u
= extract32(insn
, 29, 1);
12909 int size
= extract32(insn
, 22, 2);
12910 int l
= extract32(insn
, 21, 1);
12911 int m
= extract32(insn
, 20, 1);
12912 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12913 int rm
= extract32(insn
, 16, 4);
12914 int opcode
= extract32(insn
, 12, 4);
12915 int h
= extract32(insn
, 11, 1);
12916 int rn
= extract32(insn
, 5, 5);
12917 int rd
= extract32(insn
, 0, 5);
12918 bool is_long
= false;
12920 bool is_fp16
= false;
12924 switch (16 * u
+ opcode
) {
12925 case 0x08: /* MUL */
12926 case 0x10: /* MLA */
12927 case 0x14: /* MLS */
12929 unallocated_encoding(s
);
12933 case 0x02: /* SMLAL, SMLAL2 */
12934 case 0x12: /* UMLAL, UMLAL2 */
12935 case 0x06: /* SMLSL, SMLSL2 */
12936 case 0x16: /* UMLSL, UMLSL2 */
12937 case 0x0a: /* SMULL, SMULL2 */
12938 case 0x1a: /* UMULL, UMULL2 */
12940 unallocated_encoding(s
);
12945 case 0x03: /* SQDMLAL, SQDMLAL2 */
12946 case 0x07: /* SQDMLSL, SQDMLSL2 */
12947 case 0x0b: /* SQDMULL, SQDMULL2 */
12950 case 0x0c: /* SQDMULH */
12951 case 0x0d: /* SQRDMULH */
12953 case 0x01: /* FMLA */
12954 case 0x05: /* FMLS */
12955 case 0x09: /* FMUL */
12956 case 0x19: /* FMULX */
12959 case 0x1d: /* SQRDMLAH */
12960 case 0x1f: /* SQRDMLSH */
12961 if (!dc_isar_feature(aa64_rdm
, s
)) {
12962 unallocated_encoding(s
);
12966 case 0x0e: /* SDOT */
12967 case 0x1e: /* UDOT */
12968 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12969 unallocated_encoding(s
);
12973 case 0x11: /* FCMLA #0 */
12974 case 0x13: /* FCMLA #90 */
12975 case 0x15: /* FCMLA #180 */
12976 case 0x17: /* FCMLA #270 */
12977 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12978 unallocated_encoding(s
);
12983 case 0x00: /* FMLAL */
12984 case 0x04: /* FMLSL */
12985 case 0x18: /* FMLAL2 */
12986 case 0x1c: /* FMLSL2 */
12987 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12988 unallocated_encoding(s
);
12992 /* is_fp, but we pass cpu_env not fp_status. */
12995 unallocated_encoding(s
);
13000 case 1: /* normal fp */
13001 /* convert insn encoded size to TCGMemOp size */
13003 case 0: /* half-precision */
13007 case MO_32
: /* single precision */
13008 case MO_64
: /* double precision */
13011 unallocated_encoding(s
);
13016 case 2: /* complex fp */
13017 /* Each indexable element is a complex pair. */
13022 unallocated_encoding(s
);
13030 unallocated_encoding(s
);
13035 default: /* integer */
13039 unallocated_encoding(s
);
13044 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13045 unallocated_encoding(s
);
13049 /* Given TCGMemOp size, adjust register and indexing. */
13052 index
= h
<< 2 | l
<< 1 | m
;
13055 index
= h
<< 1 | l
;
13060 unallocated_encoding(s
);
13067 g_assert_not_reached();
13070 if (!fp_access_check(s
)) {
13075 fpst
= get_fpstatus_ptr(is_fp16
);
13080 switch (16 * u
+ opcode
) {
13081 case 0x0e: /* SDOT */
13082 case 0x1e: /* UDOT */
13083 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13084 u
? gen_helper_gvec_udot_idx_b
13085 : gen_helper_gvec_sdot_idx_b
);
13087 case 0x11: /* FCMLA #0 */
13088 case 0x13: /* FCMLA #90 */
13089 case 0x15: /* FCMLA #180 */
13090 case 0x17: /* FCMLA #270 */
13092 int rot
= extract32(insn
, 13, 2);
13093 int data
= (index
<< 2) | rot
;
13094 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13095 vec_full_reg_offset(s
, rn
),
13096 vec_full_reg_offset(s
, rm
), fpst
,
13097 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13099 ? gen_helper_gvec_fcmlas_idx
13100 : gen_helper_gvec_fcmlah_idx
);
13101 tcg_temp_free_ptr(fpst
);
13105 case 0x00: /* FMLAL */
13106 case 0x04: /* FMLSL */
13107 case 0x18: /* FMLAL2 */
13108 case 0x1c: /* FMLSL2 */
13110 int is_s
= extract32(opcode
, 2, 1);
13112 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13113 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13114 vec_full_reg_offset(s
, rn
),
13115 vec_full_reg_offset(s
, rm
), cpu_env
,
13116 is_q
? 16 : 8, vec_full_reg_size(s
),
13117 data
, gen_helper_gvec_fmlal_idx_a64
);
13123 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13126 assert(is_fp
&& is_q
&& !is_long
);
13128 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13130 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13131 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13132 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13134 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13136 switch (16 * u
+ opcode
) {
13137 case 0x05: /* FMLS */
13138 /* As usual for ARM, separate negation for fused multiply-add */
13139 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13141 case 0x01: /* FMLA */
13142 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13143 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13145 case 0x09: /* FMUL */
13146 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13148 case 0x19: /* FMULX */
13149 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13152 g_assert_not_reached();
13155 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13156 tcg_temp_free_i64(tcg_op
);
13157 tcg_temp_free_i64(tcg_res
);
13160 tcg_temp_free_i64(tcg_idx
);
13161 clear_vec_high(s
, !is_scalar
, rd
);
13162 } else if (!is_long
) {
13163 /* 32 bit floating point, or 16 or 32 bit integer.
13164 * For the 16 bit scalar case we use the usual Neon helpers and
13165 * rely on the fact that 0 op 0 == 0 with no side effects.
13167 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13168 int pass
, maxpasses
;
13173 maxpasses
= is_q
? 4 : 2;
13176 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13178 if (size
== 1 && !is_scalar
) {
13179 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13180 * the index into both halves of the 32 bit tcg_idx and then use
13181 * the usual Neon helpers.
13183 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13186 for (pass
= 0; pass
< maxpasses
; pass
++) {
13187 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13188 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13190 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13192 switch (16 * u
+ opcode
) {
13193 case 0x08: /* MUL */
13194 case 0x10: /* MLA */
13195 case 0x14: /* MLS */
13197 static NeonGenTwoOpFn
* const fns
[2][2] = {
13198 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13199 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13201 NeonGenTwoOpFn
*genfn
;
13202 bool is_sub
= opcode
== 0x4;
13205 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13207 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13209 if (opcode
== 0x8) {
13212 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13213 genfn
= fns
[size
- 1][is_sub
];
13214 genfn(tcg_res
, tcg_op
, tcg_res
);
13217 case 0x05: /* FMLS */
13218 case 0x01: /* FMLA */
13219 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13220 is_scalar
? size
: MO_32
);
13223 if (opcode
== 0x5) {
13224 /* As usual for ARM, separate negation for fused
13226 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13229 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13232 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13237 if (opcode
== 0x5) {
13238 /* As usual for ARM, separate negation for
13239 * fused multiply-add */
13240 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13242 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13246 g_assert_not_reached();
13249 case 0x09: /* FMUL */
13253 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13256 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13261 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13264 g_assert_not_reached();
13267 case 0x19: /* FMULX */
13271 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13274 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13279 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13282 g_assert_not_reached();
13285 case 0x0c: /* SQDMULH */
13287 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13290 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13294 case 0x0d: /* SQRDMULH */
13296 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13299 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13303 case 0x1d: /* SQRDMLAH */
13304 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13305 is_scalar
? size
: MO_32
);
13307 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13308 tcg_op
, tcg_idx
, tcg_res
);
13310 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13311 tcg_op
, tcg_idx
, tcg_res
);
13314 case 0x1f: /* SQRDMLSH */
13315 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13316 is_scalar
? size
: MO_32
);
13318 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13319 tcg_op
, tcg_idx
, tcg_res
);
13321 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13322 tcg_op
, tcg_idx
, tcg_res
);
13326 g_assert_not_reached();
13330 write_fp_sreg(s
, rd
, tcg_res
);
13332 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13335 tcg_temp_free_i32(tcg_op
);
13336 tcg_temp_free_i32(tcg_res
);
13339 tcg_temp_free_i32(tcg_idx
);
13340 clear_vec_high(s
, is_q
, rd
);
13342 /* long ops: 16x16->32 or 32x32->64 */
13343 TCGv_i64 tcg_res
[2];
13345 bool satop
= extract32(opcode
, 0, 1);
13346 TCGMemOp memop
= MO_32
;
13353 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13355 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13357 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13358 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13359 TCGv_i64 tcg_passres
;
13365 passelt
= pass
+ (is_q
* 2);
13368 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13370 tcg_res
[pass
] = tcg_temp_new_i64();
13372 if (opcode
== 0xa || opcode
== 0xb) {
13373 /* Non-accumulating ops */
13374 tcg_passres
= tcg_res
[pass
];
13376 tcg_passres
= tcg_temp_new_i64();
13379 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13380 tcg_temp_free_i64(tcg_op
);
13383 /* saturating, doubling */
13384 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13385 tcg_passres
, tcg_passres
);
13388 if (opcode
== 0xa || opcode
== 0xb) {
13392 /* Accumulating op: handle accumulate step */
13393 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13396 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13397 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13399 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13400 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13402 case 0x7: /* SQDMLSL, SQDMLSL2 */
13403 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13405 case 0x3: /* SQDMLAL, SQDMLAL2 */
13406 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13411 g_assert_not_reached();
13413 tcg_temp_free_i64(tcg_passres
);
13415 tcg_temp_free_i64(tcg_idx
);
13417 clear_vec_high(s
, !is_scalar
, rd
);
13419 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13422 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13425 /* The simplest way to handle the 16x16 indexed ops is to
13426 * duplicate the index into both halves of the 32 bit tcg_idx
13427 * and then use the usual Neon helpers.
13429 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13432 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13433 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13434 TCGv_i64 tcg_passres
;
13437 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13439 read_vec_element_i32(s
, tcg_op
, rn
,
13440 pass
+ (is_q
* 2), MO_32
);
13443 tcg_res
[pass
] = tcg_temp_new_i64();
13445 if (opcode
== 0xa || opcode
== 0xb) {
13446 /* Non-accumulating ops */
13447 tcg_passres
= tcg_res
[pass
];
13449 tcg_passres
= tcg_temp_new_i64();
13452 if (memop
& MO_SIGN
) {
13453 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13455 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13458 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13459 tcg_passres
, tcg_passres
);
13461 tcg_temp_free_i32(tcg_op
);
13463 if (opcode
== 0xa || opcode
== 0xb) {
13467 /* Accumulating op: handle accumulate step */
13468 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13471 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13472 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13475 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13476 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13479 case 0x7: /* SQDMLSL, SQDMLSL2 */
13480 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13482 case 0x3: /* SQDMLAL, SQDMLAL2 */
13483 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13488 g_assert_not_reached();
13490 tcg_temp_free_i64(tcg_passres
);
13492 tcg_temp_free_i32(tcg_idx
);
13495 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13500 tcg_res
[1] = tcg_const_i64(0);
13503 for (pass
= 0; pass
< 2; pass
++) {
13504 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13505 tcg_temp_free_i64(tcg_res
[pass
]);
13510 tcg_temp_free_ptr(fpst
);
13515 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13516 * +-----------------+------+-----------+--------+-----+------+------+
13517 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13518 * +-----------------+------+-----------+--------+-----+------+------+
13520 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13522 int size
= extract32(insn
, 22, 2);
13523 int opcode
= extract32(insn
, 12, 5);
13524 int rn
= extract32(insn
, 5, 5);
13525 int rd
= extract32(insn
, 0, 5);
13527 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13528 TCGv_i32 tcg_decrypt
;
13529 CryptoThreeOpIntFn
*genfn
;
13531 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13532 unallocated_encoding(s
);
13537 case 0x4: /* AESE */
13539 genfn
= gen_helper_crypto_aese
;
13541 case 0x6: /* AESMC */
13543 genfn
= gen_helper_crypto_aesmc
;
13545 case 0x5: /* AESD */
13547 genfn
= gen_helper_crypto_aese
;
13549 case 0x7: /* AESIMC */
13551 genfn
= gen_helper_crypto_aesmc
;
13554 unallocated_encoding(s
);
13558 if (!fp_access_check(s
)) {
13562 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13563 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13564 tcg_decrypt
= tcg_const_i32(decrypt
);
13566 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13568 tcg_temp_free_ptr(tcg_rd_ptr
);
13569 tcg_temp_free_ptr(tcg_rn_ptr
);
13570 tcg_temp_free_i32(tcg_decrypt
);
13573 /* Crypto three-reg SHA
13574 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13575 * +-----------------+------+---+------+---+--------+-----+------+------+
13576 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13577 * +-----------------+------+---+------+---+--------+-----+------+------+
13579 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13581 int size
= extract32(insn
, 22, 2);
13582 int opcode
= extract32(insn
, 12, 3);
13583 int rm
= extract32(insn
, 16, 5);
13584 int rn
= extract32(insn
, 5, 5);
13585 int rd
= extract32(insn
, 0, 5);
13586 CryptoThreeOpFn
*genfn
;
13587 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13591 unallocated_encoding(s
);
13596 case 0: /* SHA1C */
13597 case 1: /* SHA1P */
13598 case 2: /* SHA1M */
13599 case 3: /* SHA1SU0 */
13601 feature
= dc_isar_feature(aa64_sha1
, s
);
13603 case 4: /* SHA256H */
13604 genfn
= gen_helper_crypto_sha256h
;
13605 feature
= dc_isar_feature(aa64_sha256
, s
);
13607 case 5: /* SHA256H2 */
13608 genfn
= gen_helper_crypto_sha256h2
;
13609 feature
= dc_isar_feature(aa64_sha256
, s
);
13611 case 6: /* SHA256SU1 */
13612 genfn
= gen_helper_crypto_sha256su1
;
13613 feature
= dc_isar_feature(aa64_sha256
, s
);
13616 unallocated_encoding(s
);
13621 unallocated_encoding(s
);
13625 if (!fp_access_check(s
)) {
13629 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13630 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13631 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13634 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13636 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13638 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13639 tcg_rm_ptr
, tcg_opcode
);
13640 tcg_temp_free_i32(tcg_opcode
);
13643 tcg_temp_free_ptr(tcg_rd_ptr
);
13644 tcg_temp_free_ptr(tcg_rn_ptr
);
13645 tcg_temp_free_ptr(tcg_rm_ptr
);
13648 /* Crypto two-reg SHA
13649 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13650 * +-----------------+------+-----------+--------+-----+------+------+
13651 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13652 * +-----------------+------+-----------+--------+-----+------+------+
13654 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13656 int size
= extract32(insn
, 22, 2);
13657 int opcode
= extract32(insn
, 12, 5);
13658 int rn
= extract32(insn
, 5, 5);
13659 int rd
= extract32(insn
, 0, 5);
13660 CryptoTwoOpFn
*genfn
;
13662 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13665 unallocated_encoding(s
);
13670 case 0: /* SHA1H */
13671 feature
= dc_isar_feature(aa64_sha1
, s
);
13672 genfn
= gen_helper_crypto_sha1h
;
13674 case 1: /* SHA1SU1 */
13675 feature
= dc_isar_feature(aa64_sha1
, s
);
13676 genfn
= gen_helper_crypto_sha1su1
;
13678 case 2: /* SHA256SU0 */
13679 feature
= dc_isar_feature(aa64_sha256
, s
);
13680 genfn
= gen_helper_crypto_sha256su0
;
13683 unallocated_encoding(s
);
13688 unallocated_encoding(s
);
13692 if (!fp_access_check(s
)) {
13696 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13697 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13699 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13701 tcg_temp_free_ptr(tcg_rd_ptr
);
13702 tcg_temp_free_ptr(tcg_rn_ptr
);
13705 /* Crypto three-reg SHA512
13706 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13707 * +-----------------------+------+---+---+-----+--------+------+------+
13708 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13709 * +-----------------------+------+---+---+-----+--------+------+------+
13711 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13713 int opcode
= extract32(insn
, 10, 2);
13714 int o
= extract32(insn
, 14, 1);
13715 int rm
= extract32(insn
, 16, 5);
13716 int rn
= extract32(insn
, 5, 5);
13717 int rd
= extract32(insn
, 0, 5);
13719 CryptoThreeOpFn
*genfn
;
13723 case 0: /* SHA512H */
13724 feature
= dc_isar_feature(aa64_sha512
, s
);
13725 genfn
= gen_helper_crypto_sha512h
;
13727 case 1: /* SHA512H2 */
13728 feature
= dc_isar_feature(aa64_sha512
, s
);
13729 genfn
= gen_helper_crypto_sha512h2
;
13731 case 2: /* SHA512SU1 */
13732 feature
= dc_isar_feature(aa64_sha512
, s
);
13733 genfn
= gen_helper_crypto_sha512su1
;
13736 feature
= dc_isar_feature(aa64_sha3
, s
);
13742 case 0: /* SM3PARTW1 */
13743 feature
= dc_isar_feature(aa64_sm3
, s
);
13744 genfn
= gen_helper_crypto_sm3partw1
;
13746 case 1: /* SM3PARTW2 */
13747 feature
= dc_isar_feature(aa64_sm3
, s
);
13748 genfn
= gen_helper_crypto_sm3partw2
;
13750 case 2: /* SM4EKEY */
13751 feature
= dc_isar_feature(aa64_sm4
, s
);
13752 genfn
= gen_helper_crypto_sm4ekey
;
13755 unallocated_encoding(s
);
13761 unallocated_encoding(s
);
13765 if (!fp_access_check(s
)) {
13770 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13772 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13773 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13774 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13776 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13778 tcg_temp_free_ptr(tcg_rd_ptr
);
13779 tcg_temp_free_ptr(tcg_rn_ptr
);
13780 tcg_temp_free_ptr(tcg_rm_ptr
);
13782 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13785 tcg_op1
= tcg_temp_new_i64();
13786 tcg_op2
= tcg_temp_new_i64();
13787 tcg_res
[0] = tcg_temp_new_i64();
13788 tcg_res
[1] = tcg_temp_new_i64();
13790 for (pass
= 0; pass
< 2; pass
++) {
13791 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13792 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13794 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13795 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13797 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13798 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13800 tcg_temp_free_i64(tcg_op1
);
13801 tcg_temp_free_i64(tcg_op2
);
13802 tcg_temp_free_i64(tcg_res
[0]);
13803 tcg_temp_free_i64(tcg_res
[1]);
13807 /* Crypto two-reg SHA512
13808 * 31 12 11 10 9 5 4 0
13809 * +-----------------------------------------+--------+------+------+
13810 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13811 * +-----------------------------------------+--------+------+------+
13813 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13815 int opcode
= extract32(insn
, 10, 2);
13816 int rn
= extract32(insn
, 5, 5);
13817 int rd
= extract32(insn
, 0, 5);
13818 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13820 CryptoTwoOpFn
*genfn
;
13823 case 0: /* SHA512SU0 */
13824 feature
= dc_isar_feature(aa64_sha512
, s
);
13825 genfn
= gen_helper_crypto_sha512su0
;
13828 feature
= dc_isar_feature(aa64_sm4
, s
);
13829 genfn
= gen_helper_crypto_sm4e
;
13832 unallocated_encoding(s
);
13837 unallocated_encoding(s
);
13841 if (!fp_access_check(s
)) {
13845 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13846 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13848 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13850 tcg_temp_free_ptr(tcg_rd_ptr
);
13851 tcg_temp_free_ptr(tcg_rn_ptr
);
13854 /* Crypto four-register
13855 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13856 * +-------------------+-----+------+---+------+------+------+
13857 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13858 * +-------------------+-----+------+---+------+------+------+
13860 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13862 int op0
= extract32(insn
, 21, 2);
13863 int rm
= extract32(insn
, 16, 5);
13864 int ra
= extract32(insn
, 10, 5);
13865 int rn
= extract32(insn
, 5, 5);
13866 int rd
= extract32(insn
, 0, 5);
13872 feature
= dc_isar_feature(aa64_sha3
, s
);
13874 case 2: /* SM3SS1 */
13875 feature
= dc_isar_feature(aa64_sm3
, s
);
13878 unallocated_encoding(s
);
13883 unallocated_encoding(s
);
13887 if (!fp_access_check(s
)) {
13892 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13895 tcg_op1
= tcg_temp_new_i64();
13896 tcg_op2
= tcg_temp_new_i64();
13897 tcg_op3
= tcg_temp_new_i64();
13898 tcg_res
[0] = tcg_temp_new_i64();
13899 tcg_res
[1] = tcg_temp_new_i64();
13901 for (pass
= 0; pass
< 2; pass
++) {
13902 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13903 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13904 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13908 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13911 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13913 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13915 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13916 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13918 tcg_temp_free_i64(tcg_op1
);
13919 tcg_temp_free_i64(tcg_op2
);
13920 tcg_temp_free_i64(tcg_op3
);
13921 tcg_temp_free_i64(tcg_res
[0]);
13922 tcg_temp_free_i64(tcg_res
[1]);
13924 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13926 tcg_op1
= tcg_temp_new_i32();
13927 tcg_op2
= tcg_temp_new_i32();
13928 tcg_op3
= tcg_temp_new_i32();
13929 tcg_res
= tcg_temp_new_i32();
13930 tcg_zero
= tcg_const_i32(0);
13932 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13933 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13934 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13936 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13937 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13938 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13939 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13941 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13942 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13943 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13944 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13946 tcg_temp_free_i32(tcg_op1
);
13947 tcg_temp_free_i32(tcg_op2
);
13948 tcg_temp_free_i32(tcg_op3
);
13949 tcg_temp_free_i32(tcg_res
);
13950 tcg_temp_free_i32(tcg_zero
);
13955 * 31 21 20 16 15 10 9 5 4 0
13956 * +-----------------------+------+--------+------+------+
13957 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13958 * +-----------------------+------+--------+------+------+
13960 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13962 int rm
= extract32(insn
, 16, 5);
13963 int imm6
= extract32(insn
, 10, 6);
13964 int rn
= extract32(insn
, 5, 5);
13965 int rd
= extract32(insn
, 0, 5);
13966 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13969 if (!dc_isar_feature(aa64_sha3
, s
)) {
13970 unallocated_encoding(s
);
13974 if (!fp_access_check(s
)) {
13978 tcg_op1
= tcg_temp_new_i64();
13979 tcg_op2
= tcg_temp_new_i64();
13980 tcg_res
[0] = tcg_temp_new_i64();
13981 tcg_res
[1] = tcg_temp_new_i64();
13983 for (pass
= 0; pass
< 2; pass
++) {
13984 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13985 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13987 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13988 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13990 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13991 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13993 tcg_temp_free_i64(tcg_op1
);
13994 tcg_temp_free_i64(tcg_op2
);
13995 tcg_temp_free_i64(tcg_res
[0]);
13996 tcg_temp_free_i64(tcg_res
[1]);
13999 /* Crypto three-reg imm2
14000 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14001 * +-----------------------+------+-----+------+--------+------+------+
14002 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14003 * +-----------------------+------+-----+------+--------+------+------+
14005 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14007 int opcode
= extract32(insn
, 10, 2);
14008 int imm2
= extract32(insn
, 12, 2);
14009 int rm
= extract32(insn
, 16, 5);
14010 int rn
= extract32(insn
, 5, 5);
14011 int rd
= extract32(insn
, 0, 5);
14012 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
14013 TCGv_i32 tcg_imm2
, tcg_opcode
;
14015 if (!dc_isar_feature(aa64_sm3
, s
)) {
14016 unallocated_encoding(s
);
14020 if (!fp_access_check(s
)) {
14024 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
14025 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
14026 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
14027 tcg_imm2
= tcg_const_i32(imm2
);
14028 tcg_opcode
= tcg_const_i32(opcode
);
14030 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
14033 tcg_temp_free_ptr(tcg_rd_ptr
);
14034 tcg_temp_free_ptr(tcg_rn_ptr
);
14035 tcg_temp_free_ptr(tcg_rm_ptr
);
14036 tcg_temp_free_i32(tcg_imm2
);
14037 tcg_temp_free_i32(tcg_opcode
);
14040 /* C3.6 Data processing - SIMD, inc Crypto
14042 * As the decode gets a little complex we are using a table based
14043 * approach for this part of the decode.
14045 static const AArch64DecodeTable data_proc_simd
[] = {
14046 /* pattern , mask , fn */
14047 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14048 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14049 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14050 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14051 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14052 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14053 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14054 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14055 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14056 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14057 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14058 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14059 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14060 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14061 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14062 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14063 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14064 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14065 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14066 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14067 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14068 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14069 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14070 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14071 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14072 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14073 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14074 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14075 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14076 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14077 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14078 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14079 { 0x00000000, 0x00000000, NULL
}
14082 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14084 /* Note that this is called with all non-FP cases from
14085 * table C3-6 so it must UNDEF for entries not specifically
14086 * allocated to instructions in that table.
14088 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14092 unallocated_encoding(s
);
14096 /* C3.6 Data processing - SIMD and floating point */
14097 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14099 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14100 disas_data_proc_fp(s
, insn
);
14102 /* SIMD, including crypto */
14103 disas_data_proc_simd(s
, insn
);
14109 * @env: The cpu environment
14110 * @s: The DisasContext
14112 * Return true if the page is guarded.
14114 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14116 #ifdef CONFIG_USER_ONLY
14117 return false; /* FIXME */
14119 uint64_t addr
= s
->base
.pc_first
;
14120 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14121 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14122 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14125 * We test this immediately after reading an insn, which means
14126 * that any normal page must be in the TLB. The only exception
14127 * would be for executing from flash or device memory, which
14128 * does not retain the TLB entry.
14130 * FIXME: Assume false for those, for now. We could use
14131 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14132 * table entry even for that case.
14134 return (tlb_hit(entry
->addr_code
, addr
) &&
14135 env
->iotlb
[mmu_idx
][index
].attrs
.target_tlb_bit0
);
14140 * btype_destination_ok:
14141 * @insn: The instruction at the branch destination
14142 * @bt: SCTLR_ELx.BT
14143 * @btype: PSTATE.BTYPE, and is non-zero
14145 * On a guarded page, there are a limited number of insns
14146 * that may be present at the branch target:
14147 * - branch target identifiers,
14148 * - paciasp, pacibsp,
14151 * Anything else causes a Branch Target Exception.
14153 * Return true if the branch is compatible, false to raise BTITRAP.
14155 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14157 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14159 switch (extract32(insn
, 5, 7)) {
14160 case 0b011001: /* PACIASP */
14161 case 0b011011: /* PACIBSP */
14163 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14164 * with btype == 3. Otherwise all btype are ok.
14166 return !bt
|| btype
!= 3;
14167 case 0b100000: /* BTI */
14168 /* Not compatible with any btype. */
14170 case 0b100010: /* BTI c */
14171 /* Not compatible with btype == 3 */
14173 case 0b100100: /* BTI j */
14174 /* Not compatible with btype == 2 */
14176 case 0b100110: /* BTI jc */
14177 /* Compatible with any btype. */
14181 switch (insn
& 0xffe0001fu
) {
14182 case 0xd4200000u
: /* BRK */
14183 case 0xd4400000u
: /* HLT */
14184 /* Give priority to the breakpoint exception. */
14191 /* C3.1 A64 instruction index by encoding */
14192 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14196 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
14200 s
->fp_access_checked
= false;
14202 if (dc_isar_feature(aa64_bti
, s
)) {
14203 if (s
->base
.num_insns
== 1) {
14205 * At the first insn of the TB, compute s->guarded_page.
14206 * We delayed computing this until successfully reading
14207 * the first insn of the TB, above. This (mostly) ensures
14208 * that the softmmu tlb entry has been populated, and the
14209 * page table GP bit is available.
14211 * Note that we need to compute this even if btype == 0,
14212 * because this value is used for BR instructions later
14213 * where ENV is not available.
14215 s
->guarded_page
= is_guarded_page(env
, s
);
14217 /* First insn can have btype set to non-zero. */
14218 tcg_debug_assert(s
->btype
>= 0);
14221 * Note that the Branch Target Exception has fairly high
14222 * priority -- below debugging exceptions but above most
14223 * everything else. This allows us to handle this now
14224 * instead of waiting until the insn is otherwise decoded.
14228 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14229 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
14230 default_exception_el(s
));
14234 /* Not the first insn: btype must be 0. */
14235 tcg_debug_assert(s
->btype
== 0);
14239 switch (extract32(insn
, 25, 4)) {
14240 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14241 unallocated_encoding(s
);
14244 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14245 unallocated_encoding(s
);
14248 case 0x8: case 0x9: /* Data processing - immediate */
14249 disas_data_proc_imm(s
, insn
);
14251 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14252 disas_b_exc_sys(s
, insn
);
14257 case 0xe: /* Loads and stores */
14258 disas_ldst(s
, insn
);
14261 case 0xd: /* Data processing - register */
14262 disas_data_proc_reg(s
, insn
);
14265 case 0xf: /* Data processing - SIMD and floating point */
14266 disas_data_proc_simd_fp(s
, insn
);
14269 assert(FALSE
); /* all 15 cases should be handled above */
14273 /* if we allocated any temporaries, free them here */
14277 * After execution of most insns, btype is reset to 0.
14278 * Note that we set btype == -1 when the insn sets btype.
14280 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14285 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14288 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14289 CPUARMState
*env
= cpu
->env_ptr
;
14290 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
14291 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14292 int bound
, core_mmu_idx
;
14294 dc
->isar
= &arm_cpu
->isar
;
14295 dc
->pc
= dc
->base
.pc_first
;
14299 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14300 * there is no secure EL1, so we route exceptions to EL3.
14302 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14303 !arm_el_is_aa64(env
, 3);
14306 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14307 dc
->condexec_mask
= 0;
14308 dc
->condexec_cond
= 0;
14309 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14310 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14311 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14312 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14313 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14314 #if !defined(CONFIG_USER_ONLY)
14315 dc
->user
= (dc
->current_el
== 0);
14317 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14318 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14319 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14320 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14321 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14322 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14324 dc
->vec_stride
= 0;
14325 dc
->cp_regs
= arm_cpu
->cp_regs
;
14326 dc
->features
= env
->features
;
14328 /* Single step state. The code-generation logic here is:
14330 * generate code with no special handling for single-stepping (except
14331 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14332 * this happens anyway because those changes are all system register or
14334 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14335 * emit code for one insn
14336 * emit code to clear PSTATE.SS
14337 * emit code to generate software step exception for completed step
14338 * end TB (as usual for having generated an exception)
14339 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14340 * emit code to generate a software step exception
14343 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14344 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14345 dc
->is_ldex
= false;
14346 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14348 /* Bound the number of insns to execute to those left on the page. */
14349 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14351 /* If architectural single step active, limit to 1. */
14352 if (dc
->ss_active
) {
14355 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14357 init_tmp_a64_array(dc
);
14360 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14364 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14366 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14368 tcg_gen_insn_start(dc
->pc
, 0, 0);
14369 dc
->insn_start
= tcg_last_op();
14372 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14373 const CPUBreakpoint
*bp
)
14375 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14377 if (bp
->flags
& BP_CPU
) {
14378 gen_a64_set_pc_im(dc
->pc
);
14379 gen_helper_check_breakpoints(cpu_env
);
14380 /* End the TB early; it likely won't be executed */
14381 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14383 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14384 /* The address covered by the breakpoint must be
14385 included in [tb->pc, tb->pc + tb->size) in order
14386 to for it to be properly cleared -- thus we
14387 increment the PC here so that the logic setting
14388 tb->size below does the right thing. */
14390 dc
->base
.is_jmp
= DISAS_NORETURN
;
14396 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14398 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14399 CPUARMState
*env
= cpu
->env_ptr
;
14401 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14402 /* Singlestep state is Active-pending.
14403 * If we're in this state at the start of a TB then either
14404 * a) we just took an exception to an EL which is being debugged
14405 * and this is the first insn in the exception handler
14406 * b) debug exceptions were masked and we just unmasked them
14407 * without changing EL (eg by clearing PSTATE.D)
14408 * In either case we're going to take a swstep exception in the
14409 * "did not step an insn" case, and so the syndrome ISV and EX
14410 * bits should be zero.
14412 assert(dc
->base
.num_insns
== 1);
14413 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14414 default_exception_el(dc
));
14415 dc
->base
.is_jmp
= DISAS_NORETURN
;
14417 disas_a64_insn(env
, dc
);
14420 dc
->base
.pc_next
= dc
->pc
;
14421 translator_loop_temp_check(&dc
->base
);
14424 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14426 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14428 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14429 /* Note that this means single stepping WFI doesn't halt the CPU.
14430 * For conditional branch insns this is harmless unreachable code as
14431 * gen_goto_tb() has already handled emitting the debug exception
14432 * (and thus a tb-jump is not possible when singlestepping).
14434 switch (dc
->base
.is_jmp
) {
14436 gen_a64_set_pc_im(dc
->pc
);
14440 if (dc
->base
.singlestep_enabled
) {
14441 gen_exception_internal(EXCP_DEBUG
);
14443 gen_step_complete_exception(dc
);
14446 case DISAS_NORETURN
:
14450 switch (dc
->base
.is_jmp
) {
14452 case DISAS_TOO_MANY
:
14453 gen_goto_tb(dc
, 1, dc
->pc
);
14457 gen_a64_set_pc_im(dc
->pc
);
14460 tcg_gen_exit_tb(NULL
, 0);
14463 tcg_gen_lookup_and_goto_ptr();
14465 case DISAS_NORETURN
:
14469 gen_a64_set_pc_im(dc
->pc
);
14470 gen_helper_wfe(cpu_env
);
14473 gen_a64_set_pc_im(dc
->pc
);
14474 gen_helper_yield(cpu_env
);
14478 /* This is a special case because we don't want to just halt the CPU
14479 * if trying to debug across a WFI.
14481 TCGv_i32 tmp
= tcg_const_i32(4);
14483 gen_a64_set_pc_im(dc
->pc
);
14484 gen_helper_wfi(cpu_env
, tmp
);
14485 tcg_temp_free_i32(tmp
);
14486 /* The helper doesn't necessarily throw an exception, but we
14487 * must go back to the main loop to check for interrupts anyway.
14489 tcg_gen_exit_tb(NULL
, 0);
14495 /* Functions above can change dc->pc, so re-align db->pc_next */
14496 dc
->base
.pc_next
= dc
->pc
;
14499 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14502 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14504 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14505 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14508 const TranslatorOps aarch64_translator_ops
= {
14509 .init_disas_context
= aarch64_tr_init_disas_context
,
14510 .tb_start
= aarch64_tr_tb_start
,
14511 .insn_start
= aarch64_tr_insn_start
,
14512 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14513 .translate_insn
= aarch64_tr_translate_insn
,
14514 .tb_stop
= aarch64_tr_tb_stop
,
14515 .disas_log
= aarch64_tr_disas_log
,