2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_cpu_core.h"
16 #include "hw/ppc/spapr_xive.h"
17 #include "hw/ppc/xics.h"
18 #include "hw/ppc/xics_spapr.h"
19 #include "cpu-models.h"
20 #include "sysemu/kvm.h"
24 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
26 spapr
->irq_map_nr
= nr_msis
;
27 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
30 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
36 * The 'align_mask' parameter of bitmap_find_next_zero_area()
37 * should be one less than a power of 2; 0 means no
38 * alignment. Adapt the 'align' value of the former allocator
39 * to fit the requirements of bitmap_find_next_zero_area()
43 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
45 if (irq
== spapr
->irq_map_nr
) {
46 error_setg(errp
, "can't find a free %d-IRQ block", num
);
50 bitmap_set(spapr
->irq_map
, irq
, num
);
52 return irq
+ SPAPR_IRQ_MSI
;
55 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
57 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
60 void spapr_irq_msi_reset(SpaprMachineState
*spapr
)
62 bitmap_clear(spapr
->irq_map
, 0, spapr
->irq_map_nr
);
65 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
66 SpaprIrq
*irq
, Error
**errp
)
68 MachineState
*machine
= MACHINE(spapr
);
69 Error
*local_err
= NULL
;
71 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
72 irq
->init_kvm(spapr
, &local_err
);
73 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
74 error_prepend(&local_err
,
75 "kernel_irqchip requested but unavailable: ");
76 error_propagate(errp
, local_err
);
85 * We failed to initialize the KVM device, fallback to
88 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
89 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
90 warn_report_err(local_err
);
98 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, int nr_irqs
,
102 Error
*local_err
= NULL
;
104 obj
= object_new(TYPE_ICS_SIMPLE
);
105 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
106 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
108 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &error_fatal
);
109 object_property_set_bool(obj
, true, "realized", &local_err
);
111 error_propagate(errp
, local_err
);
115 spapr
->ics
= ICS_BASE(obj
);
117 xics_spapr_init(spapr
);
120 #define ICS_IRQ_FREE(ics, srcno) \
121 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
123 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
126 ICSState
*ics
= spapr
->ics
;
130 if (!ics_valid_irq(ics
, irq
)) {
131 error_setg(errp
, "IRQ %d is invalid", irq
);
135 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
136 error_setg(errp
, "IRQ %d is not free", irq
);
140 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
144 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
146 ICSState
*ics
= spapr
->ics
;
147 uint32_t srcno
= irq
- ics
->offset
;
150 if (ics_valid_irq(ics
, irq
)) {
151 trace_spapr_irq_free(0, irq
, num
);
152 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
153 if (ICS_IRQ_FREE(ics
, i
)) {
154 trace_spapr_irq_free_warn(0, i
);
156 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
161 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
163 ICSState
*ics
= spapr
->ics
;
164 uint32_t srcno
= irq
- ics
->offset
;
166 if (ics_valid_irq(ics
, irq
)) {
167 return spapr
->qirqs
[srcno
];
173 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
178 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
180 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
183 ics_pic_print_info(spapr
->ics
, mon
);
186 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
187 PowerPCCPU
*cpu
, Error
**errp
)
189 Error
*local_err
= NULL
;
191 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
193 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
196 error_propagate(errp
, local_err
);
200 spapr_cpu
->icp
= ICP(obj
);
203 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
205 if (!kvm_irqchip_in_kernel()) {
208 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
209 icp_resend(spapr_cpu_state(cpu
)->icp
);
215 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
217 SpaprMachineState
*spapr
= opaque
;
219 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
222 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
224 Error
*local_err
= NULL
;
226 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
228 error_propagate(errp
, local_err
);
233 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
235 return XICS_NODENAME
;
238 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
241 xics_kvm_connect(spapr
, errp
);
245 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
246 #define SPAPR_IRQ_XICS_NR_MSIS \
247 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
249 SpaprIrq spapr_irq_xics
= {
250 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
251 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
252 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
254 .init
= spapr_irq_init_xics
,
255 .claim
= spapr_irq_claim_xics
,
256 .free
= spapr_irq_free_xics
,
257 .qirq
= spapr_qirq_xics
,
258 .print_info
= spapr_irq_print_info_xics
,
259 .dt_populate
= spapr_dt_xics
,
260 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
261 .post_load
= spapr_irq_post_load_xics
,
262 .reset
= spapr_irq_reset_xics
,
263 .set_irq
= spapr_irq_set_irq_xics
,
264 .get_nodename
= spapr_irq_get_nodename_xics
,
265 .init_kvm
= spapr_irq_init_kvm_xics
,
271 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, int nr_irqs
,
274 uint32_t nr_servers
= spapr_max_server_number(spapr
);
278 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
279 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
281 * 8 XIVE END structures per CPU. One for each available priority
283 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
284 qdev_init_nofail(dev
);
286 spapr
->xive
= SPAPR_XIVE(dev
);
288 /* Enable the CPU IPIs */
289 for (i
= 0; i
< nr_servers
; ++i
) {
290 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
293 spapr_xive_hcall_init(spapr
);
296 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
299 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
300 error_setg(errp
, "IRQ %d is invalid", irq
);
306 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
310 for (i
= irq
; i
< irq
+ num
; ++i
) {
311 spapr_xive_irq_free(spapr
->xive
, i
);
315 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
317 SpaprXive
*xive
= spapr
->xive
;
319 if (irq
>= xive
->nr_irqs
) {
323 /* The sPAPR machine/device should have claimed the IRQ before */
324 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
326 return spapr
->qirqs
[irq
];
329 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
335 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
337 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
340 spapr_xive_pic_print_info(spapr
->xive
, mon
);
343 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
344 PowerPCCPU
*cpu
, Error
**errp
)
346 Error
*local_err
= NULL
;
348 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
350 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
352 error_propagate(errp
, local_err
);
356 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
359 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
360 * don't beneficiate from the reset of the XIVE IRQ backend
362 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
365 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
367 return spapr_xive_post_load(spapr
->xive
, version_id
);
370 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
373 Error
*local_err
= NULL
;
376 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
378 /* (TCG) Set the OS CAM line of the thread interrupt context. */
379 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
382 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
384 error_propagate(errp
, local_err
);
388 /* Activate the XIVE MMIOs */
389 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
392 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
394 SpaprMachineState
*spapr
= opaque
;
396 if (kvm_irqchip_in_kernel()) {
397 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
399 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
403 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
405 return spapr
->xive
->nodename
;
408 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
411 kvmppc_xive_connect(spapr
->xive
, errp
);
416 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
420 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
421 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
423 SpaprIrq spapr_irq_xive
= {
424 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
425 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
426 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
428 .init
= spapr_irq_init_xive
,
429 .claim
= spapr_irq_claim_xive
,
430 .free
= spapr_irq_free_xive
,
431 .qirq
= spapr_qirq_xive
,
432 .print_info
= spapr_irq_print_info_xive
,
433 .dt_populate
= spapr_dt_xive
,
434 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
435 .post_load
= spapr_irq_post_load_xive
,
436 .reset
= spapr_irq_reset_xive
,
437 .set_irq
= spapr_irq_set_irq_xive
,
438 .get_nodename
= spapr_irq_get_nodename_xive
,
439 .init_kvm
= spapr_irq_init_kvm_xive
,
443 * Dual XIVE and XICS IRQ backend.
445 * Both interrupt mode, XIVE and XICS, objects are created but the
446 * machine starts in legacy interrupt mode (XICS). It can be changed
447 * by the CAS negotiation process and, in that case, the new mode is
448 * activated after an extra machine reset.
452 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
455 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
457 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
458 &spapr_irq_xive
: &spapr_irq_xics
;
461 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, int nr_irqs
,
464 Error
*local_err
= NULL
;
466 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
468 error_propagate(errp
, local_err
);
472 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
474 error_propagate(errp
, local_err
);
479 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
482 Error
*local_err
= NULL
;
485 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
487 error_propagate(errp
, local_err
);
491 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
493 error_propagate(errp
, local_err
);
500 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
502 spapr_irq_xics
.free(spapr
, irq
, num
);
503 spapr_irq_xive
.free(spapr
, irq
, num
);
506 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
508 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
511 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
513 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
516 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
517 uint32_t nr_servers
, void *fdt
,
520 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
523 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
524 PowerPCCPU
*cpu
, Error
**errp
)
526 Error
*local_err
= NULL
;
528 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
530 error_propagate(errp
, local_err
);
534 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
537 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
540 * Force a reset of the XIVE backend after migration. The machine
541 * defaults to XICS at startup.
543 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
544 if (kvm_irqchip_in_kernel()) {
545 xics_kvm_disconnect(spapr
, &error_fatal
);
547 spapr_irq_xive
.reset(spapr
, &error_fatal
);
550 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
553 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
555 Error
*local_err
= NULL
;
558 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
561 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
563 /* Destroy all KVM devices */
564 if (kvm_irqchip_in_kernel()) {
565 xics_kvm_disconnect(spapr
, &local_err
);
567 error_propagate(errp
, local_err
);
568 error_prepend(errp
, "KVM XICS disconnect failed: ");
571 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
573 error_propagate(errp
, local_err
);
574 error_prepend(errp
, "KVM XIVE disconnect failed: ");
579 spapr_irq_current(spapr
)->reset(spapr
, errp
);
582 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
584 SpaprMachineState
*spapr
= opaque
;
586 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
589 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
591 return spapr_irq_current(spapr
)->get_nodename(spapr
);
595 * Define values in sync with the XIVE and XICS backend
597 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
598 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
600 SpaprIrq spapr_irq_dual
= {
601 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
602 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
603 .ov5
= SPAPR_OV5_XIVE_BOTH
,
605 .init
= spapr_irq_init_dual
,
606 .claim
= spapr_irq_claim_dual
,
607 .free
= spapr_irq_free_dual
,
608 .qirq
= spapr_qirq_dual
,
609 .print_info
= spapr_irq_print_info_dual
,
610 .dt_populate
= spapr_irq_dt_populate_dual
,
611 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
612 .post_load
= spapr_irq_post_load_dual
,
613 .reset
= spapr_irq_reset_dual
,
614 .set_irq
= spapr_irq_set_irq_dual
,
615 .get_nodename
= spapr_irq_get_nodename_dual
,
616 .init_kvm
= NULL
, /* should not be used */
620 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
622 MachineState
*machine
= MACHINE(spapr
);
625 * Sanity checks on non-P9 machines. On these, XIVE is not
626 * advertised, see spapr_dt_ov5_platform_support()
628 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
629 0, spapr
->max_compat_pvr
)) {
631 * If the 'dual' interrupt mode is selected, force XICS as CAS
632 * negotiation is useless.
634 if (spapr
->irq
== &spapr_irq_dual
) {
635 spapr
->irq
= &spapr_irq_xics
;
640 * Non-P9 machines using only XIVE is a bogus setup. We have two
641 * scenarios to take into account because of the compat mode:
643 * 1. POWER7/8 machines should fail to init later on when creating
644 * the XIVE interrupt presenters because a POWER9 exception
647 * 2. POWER9 machines using the POWER8 compat mode won't fail and
648 * will let the OS boot with a partial XIVE setup : DT
649 * properties but no hcalls.
651 * To cover both and not confuse the OS, add an early failure in
654 if (spapr
->irq
== &spapr_irq_xive
) {
655 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
661 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
662 * re-created. Detect that early to avoid QEMU to exit later when the
666 spapr
->irq
== &spapr_irq_dual
&&
667 machine_kernel_irqchip_required(machine
) &&
668 xics_kvm_has_broken_disconnect(spapr
)) {
669 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
675 * sPAPR IRQ frontend routines for devices
677 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
679 MachineState
*machine
= MACHINE(spapr
);
680 Error
*local_err
= NULL
;
682 if (machine_kernel_irqchip_split(machine
)) {
683 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
687 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
689 "kernel_irqchip requested but only available with KVM");
693 spapr_irq_check(spapr
, &local_err
);
695 error_propagate(errp
, local_err
);
699 /* Initialize the MSI IRQ allocator. */
700 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
701 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
704 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
706 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
707 spapr
->irq
->nr_irqs
);
710 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
712 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
715 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
717 spapr
->irq
->free(spapr
, irq
, num
);
720 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
722 return spapr
->irq
->qirq(spapr
, irq
);
725 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
727 return spapr
->irq
->post_load(spapr
, version_id
);
730 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
732 if (spapr
->irq
->reset
) {
733 spapr
->irq
->reset(spapr
, errp
);
737 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
739 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
742 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
744 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
745 fdt_strerror(offset
));
749 phandle
= fdt_get_phandle(fdt
, offset
);
751 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
759 * XICS legacy routines - to deprecate one day
762 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
766 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
767 if (num
> (ics
->nr_irqs
- first
)) {
770 for (i
= first
; i
< first
+ num
; ++i
) {
771 if (!ICS_IRQ_FREE(ics
, i
)) {
775 if (i
== (first
+ num
)) {
783 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
785 ICSState
*ics
= spapr
->ics
;
791 * MSIMesage::data is used for storing VIRQ so
792 * it has to be aligned to num to support multiple
793 * MSI vectors. MSI-X is not affected by this.
794 * The hint is used for the first IRQ, the rest should
795 * be allocated continuously.
798 assert((num
== 1) || (num
== 2) || (num
== 4) ||
799 (num
== 8) || (num
== 16) || (num
== 32));
800 first
= ics_find_free_block(ics
, num
, num
);
802 first
= ics_find_free_block(ics
, num
, 1);
806 error_setg(errp
, "can't find a free %d-IRQ block", num
);
810 return first
+ ics
->offset
;
813 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
815 SpaprIrq spapr_irq_xics_legacy
= {
816 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
817 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
818 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
820 .init
= spapr_irq_init_xics
,
821 .claim
= spapr_irq_claim_xics
,
822 .free
= spapr_irq_free_xics
,
823 .qirq
= spapr_qirq_xics
,
824 .print_info
= spapr_irq_print_info_xics
,
825 .dt_populate
= spapr_dt_xics
,
826 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
827 .post_load
= spapr_irq_post_load_xics
,
828 .reset
= spapr_irq_reset_xics
,
829 .set_irq
= spapr_irq_set_irq_xics
,
830 .get_nodename
= spapr_irq_get_nodename_xics
,
831 .init_kvm
= spapr_irq_init_kvm_xics
,