2 * i386 breakpoint helpers
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "helper-tcg.h"
27 #ifndef CONFIG_USER_ONLY
28 static inline bool hw_local_breakpoint_enabled(unsigned long dr7
, int index
)
30 return (dr7
>> (index
* 2)) & 1;
33 static inline bool hw_global_breakpoint_enabled(unsigned long dr7
, int index
)
35 return (dr7
>> (index
* 2)) & 2;
38 static inline bool hw_breakpoint_enabled(unsigned long dr7
, int index
)
40 return hw_global_breakpoint_enabled(dr7
, index
) ||
41 hw_local_breakpoint_enabled(dr7
, index
);
44 static inline int hw_breakpoint_type(unsigned long dr7
, int index
)
46 return (dr7
>> (DR7_TYPE_SHIFT
+ (index
* 4))) & 3;
49 static inline int hw_breakpoint_len(unsigned long dr7
, int index
)
51 int len
= ((dr7
>> (DR7_LEN_SHIFT
+ (index
* 4))) & 3);
52 return (len
== 2) ? 8 : len
+ 1;
55 static int hw_breakpoint_insert(CPUX86State
*env
, int index
)
57 CPUState
*cs
= env_cpu(env
);
58 target_ulong dr7
= env
->dr
[7];
59 target_ulong drN
= env
->dr
[index
];
62 switch (hw_breakpoint_type(dr7
, index
)) {
63 case DR7_TYPE_BP_INST
:
64 if (hw_breakpoint_enabled(dr7
, index
)) {
65 err
= cpu_breakpoint_insert(cs
, drN
, BP_CPU
,
66 &env
->cpu_breakpoint
[index
]);
71 /* Notice when we should enable calls to bpt_io. */
72 return hw_breakpoint_enabled(env
->dr
[7], index
)
75 case DR7_TYPE_DATA_WR
:
76 if (hw_breakpoint_enabled(dr7
, index
)) {
77 err
= cpu_watchpoint_insert(cs
, drN
,
78 hw_breakpoint_len(dr7
, index
),
79 BP_CPU
| BP_MEM_WRITE
,
80 &env
->cpu_watchpoint
[index
]);
84 case DR7_TYPE_DATA_RW
:
85 if (hw_breakpoint_enabled(dr7
, index
)) {
86 err
= cpu_watchpoint_insert(cs
, drN
,
87 hw_breakpoint_len(dr7
, index
),
88 BP_CPU
| BP_MEM_ACCESS
,
89 &env
->cpu_watchpoint
[index
]);
94 env
->cpu_breakpoint
[index
] = NULL
;
99 static void hw_breakpoint_remove(CPUX86State
*env
, int index
)
101 CPUState
*cs
= env_cpu(env
);
103 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
104 case DR7_TYPE_BP_INST
:
105 if (env
->cpu_breakpoint
[index
]) {
106 cpu_breakpoint_remove_by_ref(cs
, env
->cpu_breakpoint
[index
]);
107 env
->cpu_breakpoint
[index
] = NULL
;
111 case DR7_TYPE_DATA_WR
:
112 case DR7_TYPE_DATA_RW
:
113 if (env
->cpu_breakpoint
[index
]) {
114 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[index
]);
115 env
->cpu_breakpoint
[index
] = NULL
;
120 /* HF_IOBPT_MASK cleared elsewhere. */
125 void cpu_x86_update_dr7(CPUX86State
*env
, uint32_t new_dr7
)
127 target_ulong old_dr7
= env
->dr
[7];
131 new_dr7
|= DR7_FIXED_1
;
133 /* If nothing is changing except the global/local enable bits,
134 then we can make the change more efficient. */
135 if (((old_dr7
^ new_dr7
) & ~0xff) == 0) {
136 /* Fold the global and local enable bits together into the
137 global fields, then xor to show which registers have
138 changed collective enable state. */
139 int mod
= ((old_dr7
| old_dr7
* 2) ^ (new_dr7
| new_dr7
* 2)) & 0xff;
141 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
142 if ((mod
& (2 << i
* 2)) && !hw_breakpoint_enabled(new_dr7
, i
)) {
143 hw_breakpoint_remove(env
, i
);
146 env
->dr
[7] = new_dr7
;
147 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
148 if (mod
& (2 << i
* 2) && hw_breakpoint_enabled(new_dr7
, i
)) {
149 iobpt
|= hw_breakpoint_insert(env
, i
);
150 } else if (hw_breakpoint_type(new_dr7
, i
) == DR7_TYPE_IO_RW
151 && hw_breakpoint_enabled(new_dr7
, i
)) {
152 iobpt
|= HF_IOBPT_MASK
;
156 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
157 hw_breakpoint_remove(env
, i
);
159 env
->dr
[7] = new_dr7
;
160 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
161 iobpt
|= hw_breakpoint_insert(env
, i
);
165 env
->hflags
= (env
->hflags
& ~HF_IOBPT_MASK
) | iobpt
;
168 static bool check_hw_breakpoints(CPUX86State
*env
, bool force_dr6_update
)
172 bool hit_enabled
= false;
174 dr6
= env
->dr
[6] & ~0xf;
175 for (reg
= 0; reg
< DR7_MAX_BP
; reg
++) {
176 bool bp_match
= false;
177 bool wp_match
= false;
179 switch (hw_breakpoint_type(env
->dr
[7], reg
)) {
180 case DR7_TYPE_BP_INST
:
181 if (env
->dr
[reg
] == env
->eip
) {
185 case DR7_TYPE_DATA_WR
:
186 case DR7_TYPE_DATA_RW
:
187 if (env
->cpu_watchpoint
[reg
] &&
188 env
->cpu_watchpoint
[reg
]->flags
& BP_WATCHPOINT_HIT
) {
195 if (bp_match
|| wp_match
) {
197 if (hw_breakpoint_enabled(env
->dr
[7], reg
)) {
203 if (hit_enabled
|| force_dr6_update
) {
210 void breakpoint_handler(CPUState
*cs
)
212 X86CPU
*cpu
= X86_CPU(cs
);
213 CPUX86State
*env
= &cpu
->env
;
216 if (cs
->watchpoint_hit
) {
217 if (cs
->watchpoint_hit
->flags
& BP_CPU
) {
218 cs
->watchpoint_hit
= NULL
;
219 if (check_hw_breakpoints(env
, false)) {
220 raise_exception(env
, EXCP01_DB
);
222 cpu_loop_exit_noexc(cs
);
226 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
227 if (bp
->pc
== env
->eip
) {
228 if (bp
->flags
& BP_CPU
) {
229 check_hw_breakpoints(env
, true);
230 raise_exception(env
, EXCP01_DB
);
239 void helper_single_step(CPUX86State
*env
)
241 #ifndef CONFIG_USER_ONLY
242 check_hw_breakpoints(env
, true);
243 env
->dr
[6] |= DR6_BS
;
245 raise_exception(env
, EXCP01_DB
);
248 void helper_rechecking_single_step(CPUX86State
*env
)
250 if ((env
->eflags
& TF_MASK
) != 0) {
251 helper_single_step(env
);
255 void helper_set_dr(CPUX86State
*env
, int reg
, target_ulong t0
)
257 #ifndef CONFIG_USER_ONLY
259 case 0: case 1: case 2: case 3:
260 if (hw_breakpoint_enabled(env
->dr
[7], reg
)
261 && hw_breakpoint_type(env
->dr
[7], reg
) != DR7_TYPE_IO_RW
) {
262 hw_breakpoint_remove(env
, reg
);
264 hw_breakpoint_insert(env
, reg
);
270 if (env
->cr
[4] & CR4_DE_MASK
) {
275 env
->dr
[6] = t0
| DR6_FIXED_1
;
278 if (env
->cr
[4] & CR4_DE_MASK
) {
283 cpu_x86_update_dr7(env
, t0
);
286 raise_exception_err_ra(env
, EXCP06_ILLOP
, 0, GETPC());
290 target_ulong
helper_get_dr(CPUX86State
*env
, int reg
)
293 case 0: case 1: case 2: case 3: case 6: case 7:
296 if (env
->cr
[4] & CR4_DE_MASK
) {
302 if (env
->cr
[4] & CR4_DE_MASK
) {
308 raise_exception_err_ra(env
, EXCP06_ILLOP
, 0, GETPC());
311 /* Check if Port I/O is trapped by a breakpoint. */
312 void helper_bpt_io(CPUX86State
*env
, uint32_t port
,
313 uint32_t size
, target_ulong next_eip
)
315 #ifndef CONFIG_USER_ONLY
316 target_ulong dr7
= env
->dr
[7];
319 for (i
= 0; i
< DR7_MAX_BP
; ++i
) {
320 if (hw_breakpoint_type(dr7
, i
) == DR7_TYPE_IO_RW
321 && hw_breakpoint_enabled(dr7
, i
)) {
322 int bpt_len
= hw_breakpoint_len(dr7
, i
);
323 if (port
+ size
- 1 >= env
->dr
[i
]
324 && port
<= env
->dr
[i
] + bpt_len
- 1) {
331 env
->dr
[6] = (env
->dr
[6] & ~0xf) | hit
;
333 raise_exception(env
, EXCP01_DB
);