hw/scsi/vmw_pvscsi.c

   1 /*
   2  * QEMU VMWARE PVSCSI paravirtual SCSI bus
   3  *
   4  * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
   5  *
   6  * Developed by Daynix Computing LTD (http://www.daynix.com)
   7  *
   8  * Based on implementation by Paolo Bonzini
   9  * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
  10  *
  11  * Authors:
  12  * Paolo Bonzini <pbonzini@redhat.com>
  13  * Dmitry Fleytman <dmitry@daynix.com>
  14  * Yan Vugenfirer <yan@daynix.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.
  17  * See the COPYING file in the top-level directory.
  18  *
  19  * NOTE about MSI-X:
  20  * MSI-X support has been removed for the moment because it leads Windows OS
  21  * to crash on startup. The crash happens because Windows driver requires
  22  * MSI-X shared memory to be part of the same BAR used for rings state
  23  * registers, etc. This is not supported by QEMU infrastructure so separate
  24  * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu/main-loop.h"
  31 #include "qemu/module.h"
  32 #include "hw/scsi/scsi.h"
  33 #include "migration/vmstate.h"
  34 #include "scsi/constants.h"
  35 #include "hw/pci/msi.h"
  36 #include "hw/qdev-properties.h"
  37 #include "vmw_pvscsi.h"
  38 #include "trace.h"
  39 #include "qom/object.h"
  40
  41
  42 #define PVSCSI_USE_64BIT         (true)
  43 #define PVSCSI_PER_VECTOR_MASK   (false)
  44
  45 #define PVSCSI_MAX_DEVS                   (64)
  46 #define PVSCSI_MSIX_NUM_VECTORS           (1)
  47
  48 #define PVSCSI_MAX_SG_ELEM                2048
  49
  50 #define PVSCSI_MAX_CMD_DATA_WORDS \
  51     (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
  52
  53 #define RS_GET_FIELD(m, field) \
  54     (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  55                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
  56 #define RS_SET_FIELD(m, field, val) \
  57     (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  58                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
  59
  60 struct PVSCSIClass {
  61     PCIDeviceClass parent_class;
  62     DeviceRealize parent_dc_realize;
  63 };
  64
  65 #define TYPE_PVSCSI "pvscsi"
  66 OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
  67
  68
  69 /* Compatibility flags for migration */
  70 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
  71 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
  72     (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
  73 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
  74 #define PVSCSI_COMPAT_DISABLE_PCIE \
  75     (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
  76
  77 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
  78     ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
  79 #define PVSCSI_MSI_OFFSET(s) \
  80     (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
  81 #define PVSCSI_EXP_EP_OFFSET (0x40)
  82
  83 typedef struct PVSCSIRingInfo {
  84     uint64_t            rs_pa;
  85     uint32_t            txr_len_mask;
  86     uint32_t            rxr_len_mask;
  87     uint32_t            msg_len_mask;
  88     uint64_t            req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  89     uint64_t            cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  90     uint64_t            msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
  91     uint64_t            consumed_ptr;
  92     uint64_t            filled_cmp_ptr;
  93     uint64_t            filled_msg_ptr;
  94 } PVSCSIRingInfo;
  95
  96 typedef struct PVSCSISGState {
  97     hwaddr elemAddr;
  98     hwaddr dataAddr;
  99     uint32_t resid;
 100 } PVSCSISGState;
 101
 102 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
 103
 104 struct PVSCSIState {
 105     PCIDevice parent_obj;
 106     MemoryRegion io_space;
 107     SCSIBus bus;
 108     QEMUBH *completion_worker;
 109     PVSCSIRequestList pending_queue;
 110     PVSCSIRequestList completion_queue;
 111
 112     uint64_t reg_interrupt_status;        /* Interrupt status register value */
 113     uint64_t reg_interrupt_enabled;       /* Interrupt mask register value   */
 114     uint64_t reg_command_status;          /* Command status register value   */
 115
 116     /* Command data adoption mechanism */
 117     uint64_t curr_cmd;                   /* Last command arrived             */
 118     uint32_t curr_cmd_data_cntr;         /* Amount of data for last command  */
 119
 120     /* Collector for current command data */
 121     uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
 122
 123     uint8_t rings_info_valid;            /* Whether data rings initialized   */
 124     uint8_t msg_ring_info_valid;         /* Whether message ring initialized */
 125     uint8_t use_msg;                     /* Whether to use message ring      */
 126
 127     uint8_t msi_used;                    /* For migration compatibility      */
 128     PVSCSIRingInfo rings;                /* Data transfer rings manager      */
 129     uint32_t resetting;                  /* Reset in progress                */
 130
 131     uint32_t compat_flags;
 132 };
 133
 134 typedef struct PVSCSIRequest {
 135     SCSIRequest *sreq;
 136     PVSCSIState *dev;
 137     uint8_t sense_key;
 138     uint8_t completed;
 139     int lun;
 140     QEMUSGList sgl;
 141     PVSCSISGState sg;
 142     struct PVSCSIRingReqDesc req;
 143     struct PVSCSIRingCmpDesc cmp;
 144     QTAILQ_ENTRY(PVSCSIRequest) next;
 145 } PVSCSIRequest;
 146
 147 /* Integer binary logarithm */
 148 static int
 149 pvscsi_log2(uint32_t input)
 150 {
 151     int log = 0;
 152     assert(input > 0);
 153     while (input >> ++log) {
 154     }
 155     return log;
 156 }
 157
 158 static void
 159 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
 160 {
 161     int i;
 162     uint32_t txr_len_log2, rxr_len_log2;
 163     uint32_t req_ring_size, cmp_ring_size;
 164     m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
 165
 166     req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 167     cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 168     txr_len_log2 = pvscsi_log2(req_ring_size - 1);
 169     rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
 170
 171     m->txr_len_mask = MASK(txr_len_log2);
 172     m->rxr_len_mask = MASK(rxr_len_log2);
 173
 174     m->consumed_ptr = 0;
 175     m->filled_cmp_ptr = 0;
 176
 177     for (i = 0; i < ri->reqRingNumPages; i++) {
 178         m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
 179     }
 180
 181     for (i = 0; i < ri->cmpRingNumPages; i++) {
 182         m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
 183     }
 184
 185     RS_SET_FIELD(m, reqProdIdx, 0);
 186     RS_SET_FIELD(m, reqConsIdx, 0);
 187     RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
 188
 189     RS_SET_FIELD(m, cmpProdIdx, 0);
 190     RS_SET_FIELD(m, cmpConsIdx, 0);
 191     RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
 192
 193     trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
 194
 195     /* Flush ring state page changes */
 196     smp_wmb();
 197 }
 198
 199 static int
 200 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
 201 {
 202     int i;
 203     uint32_t len_log2;
 204     uint32_t ring_size;
 205
 206     if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
 207         return -1;
 208     }
 209     ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 210     len_log2 = pvscsi_log2(ring_size - 1);
 211
 212     m->msg_len_mask = MASK(len_log2);
 213
 214     m->filled_msg_ptr = 0;
 215
 216     for (i = 0; i < ri->numPages; i++) {
 217         m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
 218     }
 219
 220     RS_SET_FIELD(m, msgProdIdx, 0);
 221     RS_SET_FIELD(m, msgConsIdx, 0);
 222     RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
 223
 224     trace_pvscsi_ring_init_msg(len_log2);
 225
 226     /* Flush ring state page changes */
 227     smp_wmb();
 228
 229     return 0;
 230 }
 231
 232 static void
 233 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
 234 {
 235     mgr->rs_pa = 0;
 236     mgr->txr_len_mask = 0;
 237     mgr->rxr_len_mask = 0;
 238     mgr->msg_len_mask = 0;
 239     mgr->consumed_ptr = 0;
 240     mgr->filled_cmp_ptr = 0;
 241     mgr->filled_msg_ptr = 0;
 242     memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
 243     memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
 244     memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
 245 }
 246
 247 static hwaddr
 248 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
 249 {
 250     uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
 251     uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING
 252                             * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 253
 254     if (ready_ptr != mgr->consumed_ptr
 255         && ready_ptr - mgr->consumed_ptr < ring_size) {
 256         uint32_t next_ready_ptr =
 257             mgr->consumed_ptr++ & mgr->txr_len_mask;
 258         uint32_t next_ready_page =
 259             next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 260         uint32_t inpage_idx =
 261             next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 262
 263         return mgr->req_ring_pages_pa[next_ready_page] +
 264                inpage_idx * sizeof(PVSCSIRingReqDesc);
 265     } else {
 266         return 0;
 267     }
 268 }
 269
 270 static void
 271 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
 272 {
 273     RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
 274 }
 275
 276 static hwaddr
 277 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
 278 {
 279     /*
 280      * According to Linux driver code it explicitly verifies that number
 281      * of requests being processed by device is less then the size of
 282      * completion queue, so device may omit completion queue overflow
 283      * conditions check. We assume that this is true for other (Windows)
 284      * drivers as well.
 285      */
 286
 287     uint32_t free_cmp_ptr =
 288         mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
 289     uint32_t free_cmp_page =
 290         free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 291     uint32_t inpage_idx =
 292         free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 293     return mgr->cmp_ring_pages_pa[free_cmp_page] +
 294            inpage_idx * sizeof(PVSCSIRingCmpDesc);
 295 }
 296
 297 static hwaddr
 298 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
 299 {
 300     uint32_t free_msg_ptr =
 301         mgr->filled_msg_ptr++ & mgr->msg_len_mask;
 302     uint32_t free_msg_page =
 303         free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 304     uint32_t inpage_idx =
 305         free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 306     return mgr->msg_ring_pages_pa[free_msg_page] +
 307            inpage_idx * sizeof(PVSCSIRingMsgDesc);
 308 }
 309
 310 static void
 311 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
 312 {
 313     /* Flush descriptor changes */
 314     smp_wmb();
 315
 316     trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
 317
 318     RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
 319 }
 320
 321 static bool
 322 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
 323 {
 324     uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
 325     uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
 326
 327     return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
 328 }
 329
 330 static void
 331 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
 332 {
 333     /* Flush descriptor changes */
 334     smp_wmb();
 335
 336     trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
 337
 338     RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
 339 }
 340
 341 static void
 342 pvscsi_reset_state(PVSCSIState *s)
 343 {
 344     s->curr_cmd = PVSCSI_CMD_FIRST;
 345     s->curr_cmd_data_cntr = 0;
 346     s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 347     s->reg_interrupt_status = 0;
 348     pvscsi_ring_cleanup(&s->rings);
 349     s->rings_info_valid = FALSE;
 350     s->msg_ring_info_valid = FALSE;
 351     QTAILQ_INIT(&s->pending_queue);
 352     QTAILQ_INIT(&s->completion_queue);
 353 }
 354
 355 static void
 356 pvscsi_update_irq_status(PVSCSIState *s)
 357 {
 358     PCIDevice *d = PCI_DEVICE(s);
 359     bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
 360
 361     trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
 362                                   s->reg_interrupt_status);
 363
 364     if (msi_enabled(d)) {
 365         if (should_raise) {
 366             trace_pvscsi_update_irq_msi();
 367             msi_notify(d, PVSCSI_VECTOR_COMPLETION);
 368         }
 369         return;
 370     }
 371
 372     pci_set_irq(d, !!should_raise);
 373 }
 374
 375 static void
 376 pvscsi_raise_completion_interrupt(PVSCSIState *s)
 377 {
 378     s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
 379
 380     /* Memory barrier to flush interrupt status register changes*/
 381     smp_wmb();
 382
 383     pvscsi_update_irq_status(s);
 384 }
 385
 386 static void
 387 pvscsi_raise_message_interrupt(PVSCSIState *s)
 388 {
 389     s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
 390
 391     /* Memory barrier to flush interrupt status register changes*/
 392     smp_wmb();
 393
 394     pvscsi_update_irq_status(s);
 395 }
 396
 397 static void
 398 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
 399 {
 400     hwaddr cmp_descr_pa;
 401
 402     cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
 403     trace_pvscsi_cmp_ring_put(cmp_descr_pa);
 404     cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc));
 405 }
 406
 407 static void
 408 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
 409 {
 410     hwaddr msg_descr_pa;
 411
 412     msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
 413     trace_pvscsi_msg_ring_put(msg_descr_pa);
 414     cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc));
 415 }
 416
 417 static void
 418 pvscsi_process_completion_queue(void *opaque)
 419 {
 420     PVSCSIState *s = opaque;
 421     PVSCSIRequest *pvscsi_req;
 422     bool has_completed = false;
 423
 424     while (!QTAILQ_EMPTY(&s->completion_queue)) {
 425         pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
 426         QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
 427         pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
 428         g_free(pvscsi_req);
 429         has_completed = true;
 430     }
 431
 432     if (has_completed) {
 433         pvscsi_ring_flush_cmp(&s->rings);
 434         pvscsi_raise_completion_interrupt(s);
 435     }
 436 }
 437
 438 static void
 439 pvscsi_reset_adapter(PVSCSIState *s)
 440 {
 441     s->resetting++;
 442     qbus_reset_all(BUS(&s->bus));
 443     s->resetting--;
 444     pvscsi_process_completion_queue(s);
 445     assert(QTAILQ_EMPTY(&s->pending_queue));
 446     pvscsi_reset_state(s);
 447 }
 448
 449 static void
 450 pvscsi_schedule_completion_processing(PVSCSIState *s)
 451 {
 452     /* Try putting more complete requests on the ring. */
 453     if (!QTAILQ_EMPTY(&s->completion_queue)) {
 454         qemu_bh_schedule(s->completion_worker);
 455     }
 456 }
 457
 458 static void
 459 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
 460 {
 461     assert(!r->completed);
 462
 463     trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
 464                                   r->sense_key);
 465     if (r->sreq != NULL) {
 466         scsi_req_unref(r->sreq);
 467         r->sreq = NULL;
 468     }
 469     r->completed = 1;
 470     QTAILQ_REMOVE(&s->pending_queue, r, next);
 471     QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
 472     pvscsi_schedule_completion_processing(s);
 473 }
 474
 475 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
 476 {
 477     PVSCSIRequest *req = r->hba_private;
 478
 479     trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
 480
 481     return &req->sgl;
 482 }
 483
 484 static void
 485 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
 486 {
 487     struct PVSCSISGElement elem;
 488
 489     cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem));
 490     if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
 491         /*
 492             * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
 493             * header file but its value is unknown. This flag requires
 494             * additional processing, so we put warning here to catch it
 495             * some day and make proper implementation
 496             */
 497         trace_pvscsi_get_next_sg_elem(elem.flags);
 498     }
 499
 500     sg->elemAddr += sizeof(elem);
 501     sg->dataAddr = elem.addr;
 502     sg->resid = elem.length;
 503 }
 504
 505 static void
 506 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
 507 {
 508     r->cmp.senseLen = MIN(r->req.senseLen, len);
 509     r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
 510     cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
 511 }
 512
 513 static void
 514 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
 515 {
 516     PVSCSIRequest *pvscsi_req = req->hba_private;
 517     PVSCSIState *s;
 518
 519     if (!pvscsi_req) {
 520         trace_pvscsi_command_complete_not_found(req->tag);
 521         return;
 522     }
 523     s = pvscsi_req->dev;
 524
 525     if (resid) {
 526         /* Short transfer.  */
 527         trace_pvscsi_command_complete_data_run();
 528         pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
 529     }
 530
 531     pvscsi_req->cmp.scsiStatus = status;
 532     if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
 533         uint8_t sense[SCSI_SENSE_BUF_SIZE];
 534         int sense_len =
 535             scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
 536
 537         trace_pvscsi_command_complete_sense_len(sense_len);
 538         pvscsi_write_sense(pvscsi_req, sense, sense_len);
 539     }
 540     qemu_sglist_destroy(&pvscsi_req->sgl);
 541     pvscsi_complete_request(s, pvscsi_req);
 542 }
 543
 544 static void
 545 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
 546 {
 547     if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
 548         PVSCSIMsgDescDevStatusChanged msg = {0};
 549
 550         msg.type = msg_type;
 551         msg.bus = dev->channel;
 552         msg.target = dev->id;
 553         msg.lun[1] = dev->lun;
 554
 555         pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
 556         pvscsi_ring_flush_msg(&s->rings);
 557         pvscsi_raise_message_interrupt(s);
 558     }
 559 }
 560
 561 static void
 562 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 563 {
 564     PVSCSIState *s = PVSCSI(hotplug_dev);
 565
 566     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
 567 }
 568
 569 static void
 570 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 571 {
 572     PVSCSIState *s = PVSCSI(hotplug_dev);
 573
 574     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
 575     qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
 576 }
 577
 578 static void
 579 pvscsi_request_cancelled(SCSIRequest *req)
 580 {
 581     PVSCSIRequest *pvscsi_req = req->hba_private;
 582     PVSCSIState *s = pvscsi_req->dev;
 583
 584     if (pvscsi_req->completed) {
 585         return;
 586     }
 587
 588    if (pvscsi_req->dev->resetting) {
 589        pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
 590     } else {
 591        pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 592     }
 593
 594     pvscsi_complete_request(s, pvscsi_req);
 595 }
 596
 597 static SCSIDevice*
 598 pvscsi_device_find(PVSCSIState *s, int channel, int target,
 599                    uint8_t *requested_lun, uint8_t *target_lun)
 600 {
 601     if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
 602         requested_lun[4] || requested_lun[5] || requested_lun[6] ||
 603         requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
 604         return NULL;
 605     } else {
 606         *target_lun = requested_lun[1];
 607         return scsi_device_find(&s->bus, channel, target, *target_lun);
 608     }
 609 }
 610
 611 static PVSCSIRequest *
 612 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
 613                                 struct PVSCSIRingReqDesc *descr)
 614 {
 615     PVSCSIRequest *pvscsi_req;
 616     uint8_t lun;
 617
 618     pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
 619     pvscsi_req->dev = s;
 620     pvscsi_req->req = *descr;
 621     pvscsi_req->cmp.context = pvscsi_req->req.context;
 622     QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
 623
 624     *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
 625     if (*d) {
 626         pvscsi_req->lun = lun;
 627     }
 628
 629     return pvscsi_req;
 630 }
 631
 632 static void
 633 pvscsi_convert_sglist(PVSCSIRequest *r)
 634 {
 635     uint32_t chunk_size, elmcnt = 0;
 636     uint64_t data_length = r->req.dataLen;
 637     PVSCSISGState sg = r->sg;
 638     while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
 639         while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
 640             pvscsi_get_next_sg_elem(&sg);
 641             trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
 642                                         r->sg.resid);
 643         }
 644         chunk_size = MIN(data_length, sg.resid);
 645         if (chunk_size) {
 646             qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
 647         }
 648
 649         sg.dataAddr += chunk_size;
 650         data_length -= chunk_size;
 651         sg.resid -= chunk_size;
 652     }
 653 }
 654
 655 static void
 656 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
 657 {
 658     PCIDevice *d = PCI_DEVICE(s);
 659
 660     pci_dma_sglist_init(&r->sgl, d, 1);
 661     if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 662         pvscsi_convert_sglist(r);
 663     } else {
 664         qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
 665     }
 666 }
 667
 668 static void
 669 pvscsi_process_request_descriptor(PVSCSIState *s,
 670                                   struct PVSCSIRingReqDesc *descr)
 671 {
 672     SCSIDevice *d;
 673     PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
 674     int64_t n;
 675
 676     trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
 677
 678     if (!d) {
 679         r->cmp.hostStatus = BTSTAT_SELTIMEO;
 680         trace_pvscsi_process_req_descr_unknown_device();
 681         pvscsi_complete_request(s, r);
 682         return;
 683     }
 684
 685     if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 686         r->sg.elemAddr = descr->dataAddr;
 687     }
 688
 689     r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
 690     if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
 691         (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
 692         r->cmp.hostStatus = BTSTAT_BADMSG;
 693         trace_pvscsi_process_req_descr_invalid_dir();
 694         scsi_req_cancel(r->sreq);
 695         return;
 696     }
 697     if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
 698         (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
 699         r->cmp.hostStatus = BTSTAT_BADMSG;
 700         trace_pvscsi_process_req_descr_invalid_dir();
 701         scsi_req_cancel(r->sreq);
 702         return;
 703     }
 704
 705     pvscsi_build_sglist(s, r);
 706     n = scsi_req_enqueue(r->sreq);
 707
 708     if (n) {
 709         scsi_req_continue(r->sreq);
 710     }
 711 }
 712
 713 static void
 714 pvscsi_process_io(PVSCSIState *s)
 715 {
 716     PVSCSIRingReqDesc descr;
 717     hwaddr next_descr_pa;
 718
 719     if (!s->rings_info_valid) {
 720         return;
 721     }
 722
 723     while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
 724
 725         /* Only read after production index verification */
 726         smp_rmb();
 727
 728         trace_pvscsi_process_io(next_descr_pa);
 729         cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
 730         pvscsi_process_request_descriptor(s, &descr);
 731     }
 732
 733     pvscsi_ring_flush_req(&s->rings);
 734 }
 735
 736 static void
 737 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
 738 {
 739     int i;
 740     trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
 741
 742     trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
 743     for (i = 0; i < rc->reqRingNumPages; i++) {
 744         trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
 745     }
 746
 747     trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
 748     for (i = 0; i < rc->cmpRingNumPages; i++) {
 749         trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
 750     }
 751 }
 752
 753 static uint64_t
 754 pvscsi_on_cmd_config(PVSCSIState *s)
 755 {
 756     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
 757     return PVSCSI_COMMAND_PROCESSING_FAILED;
 758 }
 759
 760 static uint64_t
 761 pvscsi_on_cmd_unplug(PVSCSIState *s)
 762 {
 763     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
 764     return PVSCSI_COMMAND_PROCESSING_FAILED;
 765 }
 766
 767 static uint64_t
 768 pvscsi_on_issue_scsi(PVSCSIState *s)
 769 {
 770     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
 771     return PVSCSI_COMMAND_PROCESSING_FAILED;
 772 }
 773
 774 static uint64_t
 775 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
 776 {
 777     PVSCSICmdDescSetupRings *rc =
 778         (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
 779
 780     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
 781
 782     if (!rc->reqRingNumPages
 783         || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
 784         || !rc->cmpRingNumPages
 785         || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
 786         return PVSCSI_COMMAND_PROCESSING_FAILED;
 787     }
 788
 789     pvscsi_dbg_dump_tx_rings_config(rc);
 790     pvscsi_ring_init_data(&s->rings, rc);
 791
 792     s->rings_info_valid = TRUE;
 793     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 794 }
 795
 796 static uint64_t
 797 pvscsi_on_cmd_abort(PVSCSIState *s)
 798 {
 799     PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
 800     PVSCSIRequest *r, *next;
 801
 802     trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
 803
 804     QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
 805         if (r->req.context == cmd->context) {
 806             break;
 807         }
 808     }
 809     if (r) {
 810         assert(!r->completed);
 811         r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 812         scsi_req_cancel(r->sreq);
 813     }
 814
 815     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 816 }
 817
 818 static uint64_t
 819 pvscsi_on_cmd_unknown(PVSCSIState *s)
 820 {
 821     trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
 822     return PVSCSI_COMMAND_PROCESSING_FAILED;
 823 }
 824
 825 static uint64_t
 826 pvscsi_on_cmd_reset_device(PVSCSIState *s)
 827 {
 828     uint8_t target_lun = 0;
 829     struct PVSCSICmdDescResetDevice *cmd =
 830         (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
 831     SCSIDevice *sdev;
 832
 833     sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
 834
 835     trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
 836
 837     if (sdev != NULL) {
 838         s->resetting++;
 839         device_legacy_reset(&sdev->qdev);
 840         s->resetting--;
 841         return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 842     }
 843
 844     return PVSCSI_COMMAND_PROCESSING_FAILED;
 845 }
 846
 847 static uint64_t
 848 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
 849 {
 850     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
 851
 852     s->resetting++;
 853     qbus_reset_all(BUS(&s->bus));
 854     s->resetting--;
 855     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 856 }
 857
 858 static uint64_t
 859 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
 860 {
 861     PVSCSICmdDescSetupMsgRing *rc =
 862         (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
 863
 864     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
 865
 866     if (!s->use_msg) {
 867         return PVSCSI_COMMAND_PROCESSING_FAILED;
 868     }
 869
 870     if (s->rings_info_valid) {
 871         if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
 872             return PVSCSI_COMMAND_PROCESSING_FAILED;
 873         }
 874         s->msg_ring_info_valid = TRUE;
 875     }
 876     return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
 877 }
 878
 879 static uint64_t
 880 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
 881 {
 882     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
 883
 884     pvscsi_reset_adapter(s);
 885     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 886 }
 887
 888 static const struct {
 889     int       data_size;
 890     uint64_t  (*handler_fn)(PVSCSIState *s);
 891 } pvscsi_commands[] = {
 892     [PVSCSI_CMD_FIRST] = {
 893         .data_size = 0,
 894         .handler_fn = pvscsi_on_cmd_unknown,
 895     },
 896
 897     /* Not implemented, data size defined based on what arrives on windows */
 898     [PVSCSI_CMD_CONFIG] = {
 899         .data_size = 6 * sizeof(uint32_t),
 900         .handler_fn = pvscsi_on_cmd_config,
 901     },
 902
 903     /* Command not implemented, data size is unknown */
 904     [PVSCSI_CMD_ISSUE_SCSI] = {
 905         .data_size = 0,
 906         .handler_fn = pvscsi_on_issue_scsi,
 907     },
 908
 909     /* Command not implemented, data size is unknown */
 910     [PVSCSI_CMD_DEVICE_UNPLUG] = {
 911         .data_size = 0,
 912         .handler_fn = pvscsi_on_cmd_unplug,
 913     },
 914
 915     [PVSCSI_CMD_SETUP_RINGS] = {
 916         .data_size = sizeof(PVSCSICmdDescSetupRings),
 917         .handler_fn = pvscsi_on_cmd_setup_rings,
 918     },
 919
 920     [PVSCSI_CMD_RESET_DEVICE] = {
 921         .data_size = sizeof(struct PVSCSICmdDescResetDevice),
 922         .handler_fn = pvscsi_on_cmd_reset_device,
 923     },
 924
 925     [PVSCSI_CMD_RESET_BUS] = {
 926         .data_size = 0,
 927         .handler_fn = pvscsi_on_cmd_reset_bus,
 928     },
 929
 930     [PVSCSI_CMD_SETUP_MSG_RING] = {
 931         .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
 932         .handler_fn = pvscsi_on_cmd_setup_msg_ring,
 933     },
 934
 935     [PVSCSI_CMD_ADAPTER_RESET] = {
 936         .data_size = 0,
 937         .handler_fn = pvscsi_on_cmd_adapter_reset,
 938     },
 939
 940     [PVSCSI_CMD_ABORT_CMD] = {
 941         .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
 942         .handler_fn = pvscsi_on_cmd_abort,
 943     },
 944 };
 945
 946 static void
 947 pvscsi_do_command_processing(PVSCSIState *s)
 948 {
 949     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 950
 951     assert(s->curr_cmd < PVSCSI_CMD_LAST);
 952     if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
 953         s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
 954         s->curr_cmd = PVSCSI_CMD_FIRST;
 955         s->curr_cmd_data_cntr   = 0;
 956     }
 957 }
 958
 959 static void
 960 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
 961 {
 962     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 963
 964     assert(bytes_arrived < sizeof(s->curr_cmd_data));
 965     s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
 966
 967     pvscsi_do_command_processing(s);
 968 }
 969
 970 static void
 971 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
 972 {
 973     if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
 974         s->curr_cmd = cmd_id;
 975     } else {
 976         s->curr_cmd = PVSCSI_CMD_FIRST;
 977         trace_pvscsi_on_cmd_unknown(cmd_id);
 978     }
 979
 980     s->curr_cmd_data_cntr = 0;
 981     s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
 982
 983     pvscsi_do_command_processing(s);
 984 }
 985
 986 static void
 987 pvscsi_io_write(void *opaque, hwaddr addr,
 988                 uint64_t val, unsigned size)
 989 {
 990     PVSCSIState *s = opaque;
 991
 992     switch (addr) {
 993     case PVSCSI_REG_OFFSET_COMMAND:
 994         pvscsi_on_command(s, val);
 995         break;
 996
 997     case PVSCSI_REG_OFFSET_COMMAND_DATA:
 998         pvscsi_on_command_data(s, (uint32_t) val);
 999         break;
1000
1001     case PVSCSI_REG_OFFSET_INTR_STATUS:
1002         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
1003         s->reg_interrupt_status &= ~val;
1004         pvscsi_update_irq_status(s);
1005         pvscsi_schedule_completion_processing(s);
1006         break;
1007
1008     case PVSCSI_REG_OFFSET_INTR_MASK:
1009         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1010         s->reg_interrupt_enabled = val;
1011         pvscsi_update_irq_status(s);
1012         break;
1013
1014     case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1015         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1016         pvscsi_process_io(s);
1017         break;
1018
1019     case PVSCSI_REG_OFFSET_KICK_RW_IO:
1020         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1021         pvscsi_process_io(s);
1022         break;
1023
1024     case PVSCSI_REG_OFFSET_DEBUG:
1025         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1026         break;
1027
1028     default:
1029         trace_pvscsi_io_write_unknown(addr, size, val);
1030         break;
1031     }
1032
1033 }
1034
1035 static uint64_t
1036 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1037 {
1038     PVSCSIState *s = opaque;
1039
1040     switch (addr) {
1041     case PVSCSI_REG_OFFSET_INTR_STATUS:
1042         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1043                              s->reg_interrupt_status);
1044         return s->reg_interrupt_status;
1045
1046     case PVSCSI_REG_OFFSET_INTR_MASK:
1047         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1048                              s->reg_interrupt_status);
1049         return s->reg_interrupt_enabled;
1050
1051     case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1052         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1053                              s->reg_interrupt_status);
1054         return s->reg_command_status;
1055
1056     default:
1057         trace_pvscsi_io_read_unknown(addr, size);
1058         return 0;
1059     }
1060 }
1061
1062
1063 static void
1064 pvscsi_init_msi(PVSCSIState *s)
1065 {
1066     int res;
1067     PCIDevice *d = PCI_DEVICE(s);
1068
1069     res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1070                    PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1071     if (res < 0) {
1072         trace_pvscsi_init_msi_fail(res);
1073         s->msi_used = false;
1074     } else {
1075         s->msi_used = true;
1076     }
1077 }
1078
1079 static void
1080 pvscsi_cleanup_msi(PVSCSIState *s)
1081 {
1082     PCIDevice *d = PCI_DEVICE(s);
1083
1084     msi_uninit(d);
1085 }
1086
1087 static const MemoryRegionOps pvscsi_ops = {
1088         .read = pvscsi_io_read,
1089         .write = pvscsi_io_write,
1090         .endianness = DEVICE_LITTLE_ENDIAN,
1091         .impl = {
1092                 .min_access_size = 4,
1093                 .max_access_size = 4,
1094         },
1095 };
1096
1097 static const struct SCSIBusInfo pvscsi_scsi_info = {
1098         .tcq = true,
1099         .max_target = PVSCSI_MAX_DEVS,
1100         .max_channel = 0,
1101         .max_lun = 0,
1102
1103         .get_sg_list = pvscsi_get_sg_list,
1104         .complete = pvscsi_command_complete,
1105         .cancel = pvscsi_request_cancelled,
1106 };
1107
1108 static void
1109 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
1110 {
1111     PVSCSIState *s = PVSCSI(pci_dev);
1112
1113     trace_pvscsi_state("init");
1114
1115     /* PCI subsystem ID, subsystem vendor ID, revision */
1116     if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1117         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1118     } else {
1119         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1120                      PCI_VENDOR_ID_VMWARE);
1121         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1122                      PCI_DEVICE_ID_VMWARE_PVSCSI);
1123         pci_config_set_revision(pci_dev->config, 0x2);
1124     }
1125
1126     /* PCI latency timer = 255 */
1127     pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1128
1129     /* Interrupt pin A */
1130     pci_config_set_interrupt_pin(pci_dev->config, 1);
1131
1132     memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1133                           "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1134     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1135
1136     pvscsi_init_msi(s);
1137
1138     if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) {
1139         pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1140     }
1141
1142     s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1143
1144     scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1145                  &pvscsi_scsi_info, NULL);
1146     /* override default SCSI bus hotplug-handler, with pvscsi's one */
1147     qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
1148     pvscsi_reset_state(s);
1149 }
1150
1151 static void
1152 pvscsi_uninit(PCIDevice *pci_dev)
1153 {
1154     PVSCSIState *s = PVSCSI(pci_dev);
1155
1156     trace_pvscsi_state("uninit");
1157     qemu_bh_delete(s->completion_worker);
1158
1159     pvscsi_cleanup_msi(s);
1160 }
1161
1162 static void
1163 pvscsi_reset(DeviceState *dev)
1164 {
1165     PCIDevice *d = PCI_DEVICE(dev);
1166     PVSCSIState *s = PVSCSI(d);
1167
1168     trace_pvscsi_state("reset");
1169     pvscsi_reset_adapter(s);
1170 }
1171
1172 static int
1173 pvscsi_pre_save(void *opaque)
1174 {
1175     PVSCSIState *s = (PVSCSIState *) opaque;
1176
1177     trace_pvscsi_state("presave");
1178
1179     assert(QTAILQ_EMPTY(&s->pending_queue));
1180     assert(QTAILQ_EMPTY(&s->completion_queue));
1181
1182     return 0;
1183 }
1184
1185 static int
1186 pvscsi_post_load(void *opaque, int version_id)
1187 {
1188     trace_pvscsi_state("postload");
1189     return 0;
1190 }
1191
1192 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1193 {
1194     PVSCSIState *s = PVSCSI(opaque);
1195
1196     return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1197 }
1198
1199 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1200 {
1201     return !pvscsi_vmstate_need_pcie_device(opaque);
1202 }
1203
1204 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1205     .name = "pvscsi/pcie",
1206     .needed = pvscsi_vmstate_need_pcie_device,
1207     .fields = (VMStateField[]) {
1208         VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
1209         VMSTATE_END_OF_LIST()
1210     }
1211 };
1212
1213 static const VMStateDescription vmstate_pvscsi = {
1214     .name = "pvscsi",
1215     .version_id = 0,
1216     .minimum_version_id = 0,
1217     .pre_save = pvscsi_pre_save,
1218     .post_load = pvscsi_post_load,
1219     .fields = (VMStateField[]) {
1220         VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1221                             pvscsi_vmstate_test_pci_device, 0,
1222                             vmstate_pci_device, PCIDevice),
1223         VMSTATE_UINT8(msi_used, PVSCSIState),
1224         VMSTATE_UINT32(resetting, PVSCSIState),
1225         VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1226         VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1227         VMSTATE_UINT64(reg_command_status, PVSCSIState),
1228         VMSTATE_UINT64(curr_cmd, PVSCSIState),
1229         VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1230         VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1231                              ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1232         VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1233         VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1234         VMSTATE_UINT8(use_msg, PVSCSIState),
1235
1236         VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1237         VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1238         VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1239         VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1240                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1241         VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1242                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1243         VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1244         VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1245
1246         VMSTATE_END_OF_LIST()
1247     },
1248     .subsections = (const VMStateDescription*[]) {
1249         &vmstate_pvscsi_pcie_device,
1250         NULL
1251     }
1252 };
1253
1254 static Property pvscsi_properties[] = {
1255     DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1256     DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1257                     PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1258     DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1259                     PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1260     DEFINE_PROP_END_OF_LIST(),
1261 };
1262
1263 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1264 {
1265     PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev);
1266     PCIDevice *pci_dev = PCI_DEVICE(qdev);
1267     PVSCSIState *s = PVSCSI(qdev);
1268
1269     if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1270         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1271     }
1272
1273     pvs_c->parent_dc_realize(qdev, errp);
1274 }
1275
1276 static void pvscsi_class_init(ObjectClass *klass, void *data)
1277 {
1278     DeviceClass *dc = DEVICE_CLASS(klass);
1279     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1280     PVSCSIClass *pvs_k = PVSCSI_CLASS(klass);
1281     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1282
1283     k->realize = pvscsi_realizefn;
1284     k->exit = pvscsi_uninit;
1285     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1286     k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1287     k->class_id = PCI_CLASS_STORAGE_SCSI;
1288     k->subsystem_id = 0x1000;
1289     device_class_set_parent_realize(dc, pvscsi_realize,
1290                                     &pvs_k->parent_dc_realize);
1291     dc->reset = pvscsi_reset;
1292     dc->vmsd = &vmstate_pvscsi;
1293     device_class_set_props(dc, pvscsi_properties);
1294     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1295     hc->unplug = pvscsi_hot_unplug;
1296     hc->plug = pvscsi_hotplug;
1297 }
1298
1299 static const TypeInfo pvscsi_info = {
1300     .name          = TYPE_PVSCSI,
1301     .parent        = TYPE_PCI_DEVICE,
1302     .class_size    = sizeof(PVSCSIClass),
1303     .instance_size = sizeof(PVSCSIState),
1304     .class_init    = pvscsi_class_init,
1305     .interfaces = (InterfaceInfo[]) {
1306         { TYPE_HOTPLUG_HANDLER },
1307         { INTERFACE_PCIE_DEVICE },
1308         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1309         { }
1310     }
1311 };
1312
1313 static void
1314 pvscsi_register_types(void)
1315 {
1316     type_register_static(&pvscsi_info);
1317 }
1318
1319 type_init(pvscsi_register_types);