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iotests: Test qemu-img convert -S 0 behavior
[qemu/ar7.git] / linux-user / main.c
blobb432bf2b1ed5e3dc1da787fb82903fa050ef1b56
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu/path.h"
26 #include "qemu/cutils.h"
27 #include "qemu/help_option.h"
28 #include "cpu.h"
29 #include "tcg.h"
30 #include "qemu/timer.h"
31 #include "qemu/envlist.h"
32 #include "elf.h"
33 #include "exec/log.h"
34
35 char *exec_path;
36
37 int singlestep;
38 static const char *filename;
39 static const char *argv0;
40 static int gdbstub_port;
41 static envlist_t *envlist;
42 static const char *cpu_model;
43 unsigned long mmap_min_addr;
44 unsigned long guest_base;
45 int have_guest_base;
46
47 #define EXCP_DUMP(env, fmt, ...) \
48 do { \
49 CPUState *cs = ENV_GET_CPU(env); \
50 fprintf(stderr, fmt , ## __VA_ARGS__); \
51 cpu_dump_state(cs, stderr, fprintf, 0); \
52 if (qemu_log_separate()) { \
53 qemu_log(fmt, ## __VA_ARGS__); \
54 log_cpu_state(cs, 0); \
55 } \
56 } while (0)
57
58 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
59 /*
60 * When running 32-on-64 we should make sure we can fit all of the possible
61 * guest address space into a contiguous chunk of virtual host memory.
62 *
63 * This way we will never overlap with our own libraries or binaries or stack
64 * or anything else that QEMU maps.
65 */
66 # ifdef TARGET_MIPS
67 /* MIPS only supports 31 bits of virtual address space for user space */
68 unsigned long reserved_va = 0x77000000;
69 # else
70 unsigned long reserved_va = 0xf7000000;
71 # endif
72 #else
73 unsigned long reserved_va;
74 #endif
75
76 static void usage(int exitcode);
77
78 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
79 const char *qemu_uname_release;
80
81 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
82 we allocate a bigger stack. Need a better solution, for example
83 by remapping the process stack directly at the right place */
84 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
85
86 void gemu_log(const char *fmt, ...)
87 {
88 va_list ap;
89
90 va_start(ap, fmt);
91 vfprintf(stderr, fmt, ap);
92 va_end(ap);
93 }
94
95 #if defined(TARGET_I386)
96 int cpu_get_pic_interrupt(CPUX86State *env)
97 {
98 return -1;
99 }
100 #endif
101
102 /***********************************************************/
103 /* Helper routines for implementing atomic operations. */
104
105 /* To implement exclusive operations we force all cpus to syncronise.
106 We don't require a full sync, only that no cpus are executing guest code.
107 The alternative is to map target atomic ops onto host equivalents,
108 which requires quite a lot of per host/target work. */
109 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
110 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
111 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
112 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
113 static int pending_cpus;
114
115 /* Make sure everything is in a consistent state for calling fork(). */
116 void fork_start(void)
117 {
118 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
119 pthread_mutex_lock(&exclusive_lock);
120 mmap_fork_start();
121 }
122
123 void fork_end(int child)
124 {
125 mmap_fork_end(child);
126 if (child) {
127 CPUState *cpu, *next_cpu;
128 /* Child processes created by fork() only have a single thread.
129 Discard information about the parent threads. */
130 CPU_FOREACH_SAFE(cpu, next_cpu) {
131 if (cpu != thread_cpu) {
132 QTAILQ_REMOVE(&cpus, thread_cpu, node);
133 }
134 }
135 pending_cpus = 0;
136 pthread_mutex_init(&exclusive_lock, NULL);
137 pthread_mutex_init(&cpu_list_mutex, NULL);
138 pthread_cond_init(&exclusive_cond, NULL);
139 pthread_cond_init(&exclusive_resume, NULL);
140 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
141 gdbserver_fork(thread_cpu);
142 } else {
143 pthread_mutex_unlock(&exclusive_lock);
144 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
145 }
146 }
147
148 /* Wait for pending exclusive operations to complete. The exclusive lock
149 must be held. */
150 static inline void exclusive_idle(void)
151 {
152 while (pending_cpus) {
153 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
154 }
155 }
156
157 /* Start an exclusive operation.
158 Must only be called from outside cpu_arm_exec. */
159 static inline void start_exclusive(void)
160 {
161 CPUState *other_cpu;
162
163 pthread_mutex_lock(&exclusive_lock);
164 exclusive_idle();
165
166 pending_cpus = 1;
167 /* Make all other cpus stop executing. */
168 CPU_FOREACH(other_cpu) {
169 if (other_cpu->running) {
170 pending_cpus++;
171 cpu_exit(other_cpu);
172 }
173 }
174 if (pending_cpus > 1) {
175 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
176 }
177 }
178
179 /* Finish an exclusive operation. */
180 static inline void __attribute__((unused)) end_exclusive(void)
181 {
182 pending_cpus = 0;
183 pthread_cond_broadcast(&exclusive_resume);
184 pthread_mutex_unlock(&exclusive_lock);
185 }
186
187 /* Wait for exclusive ops to finish, and begin cpu execution. */
188 static inline void cpu_exec_start(CPUState *cpu)
189 {
190 pthread_mutex_lock(&exclusive_lock);
191 exclusive_idle();
192 cpu->running = true;
193 pthread_mutex_unlock(&exclusive_lock);
194 }
195
196 /* Mark cpu as not executing, and release pending exclusive ops. */
197 static inline void cpu_exec_end(CPUState *cpu)
198 {
199 pthread_mutex_lock(&exclusive_lock);
200 cpu->running = false;
201 if (pending_cpus > 1) {
202 pending_cpus--;
203 if (pending_cpus == 1) {
204 pthread_cond_signal(&exclusive_cond);
205 }
206 }
207 exclusive_idle();
208 pthread_mutex_unlock(&exclusive_lock);
209 }
210
211 void cpu_list_lock(void)
212 {
213 pthread_mutex_lock(&cpu_list_mutex);
214 }
215
216 void cpu_list_unlock(void)
217 {
218 pthread_mutex_unlock(&cpu_list_mutex);
219 }
220
221
222 #ifdef TARGET_I386
223 /***********************************************************/
224 /* CPUX86 core interface */
225
226 uint64_t cpu_get_tsc(CPUX86State *env)
227 {
228 return cpu_get_host_ticks();
229 }
230
231 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
232 int flags)
233 {
234 unsigned int e1, e2;
235 uint32_t *p;
236 e1 = (addr << 16) | (limit & 0xffff);
237 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
238 e2 |= flags;
239 p = ptr;
240 p[0] = tswap32(e1);
241 p[1] = tswap32(e2);
242 }
243
244 static uint64_t *idt_table;
245 #ifdef TARGET_X86_64
246 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
247 uint64_t addr, unsigned int sel)
248 {
249 uint32_t *p, e1, e2;
250 e1 = (addr & 0xffff) | (sel << 16);
251 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
252 p = ptr;
253 p[0] = tswap32(e1);
254 p[1] = tswap32(e2);
255 p[2] = tswap32(addr >> 32);
256 p[3] = 0;
257 }
258 /* only dpl matters as we do only user space emulation */
259 static void set_idt(int n, unsigned int dpl)
260 {
261 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
262 }
263 #else
264 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
265 uint32_t addr, unsigned int sel)
266 {
267 uint32_t *p, e1, e2;
268 e1 = (addr & 0xffff) | (sel << 16);
269 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
270 p = ptr;
271 p[0] = tswap32(e1);
272 p[1] = tswap32(e2);
273 }
274
275 /* only dpl matters as we do only user space emulation */
276 static void set_idt(int n, unsigned int dpl)
277 {
278 set_gate(idt_table + n, 0, dpl, 0, 0);
279 }
280 #endif
281
282 void cpu_loop(CPUX86State *env)
283 {
284 CPUState *cs = CPU(x86_env_get_cpu(env));
285 int trapnr;
286 abi_ulong pc;
287 target_siginfo_t info;
288
289 for(;;) {
290 cpu_exec_start(cs);
291 trapnr = cpu_x86_exec(cs);
292 cpu_exec_end(cs);
293 switch(trapnr) {
294 case 0x80:
295 /* linux syscall from int $0x80 */
296 env->regs[R_EAX] = do_syscall(env,
297 env->regs[R_EAX],
298 env->regs[R_EBX],
299 env->regs[R_ECX],
300 env->regs[R_EDX],
301 env->regs[R_ESI],
302 env->regs[R_EDI],
303 env->regs[R_EBP],
304 0, 0);
305 break;
306 #ifndef TARGET_ABI32
307 case EXCP_SYSCALL:
308 /* linux syscall from syscall instruction */
309 env->regs[R_EAX] = do_syscall(env,
310 env->regs[R_EAX],
311 env->regs[R_EDI],
312 env->regs[R_ESI],
313 env->regs[R_EDX],
314 env->regs[10],
315 env->regs[8],
316 env->regs[9],
317 0, 0);
318 break;
319 #endif
320 case EXCP0B_NOSEG:
321 case EXCP0C_STACK:
322 info.si_signo = TARGET_SIGBUS;
323 info.si_errno = 0;
324 info.si_code = TARGET_SI_KERNEL;
325 info._sifields._sigfault._addr = 0;
326 queue_signal(env, info.si_signo, &info);
327 break;
328 case EXCP0D_GPF:
329 /* XXX: potential problem if ABI32 */
330 #ifndef TARGET_X86_64
331 if (env->eflags & VM_MASK) {
332 handle_vm86_fault(env);
333 } else
334 #endif
335 {
336 info.si_signo = TARGET_SIGSEGV;
337 info.si_errno = 0;
338 info.si_code = TARGET_SI_KERNEL;
339 info._sifields._sigfault._addr = 0;
340 queue_signal(env, info.si_signo, &info);
341 }
342 break;
343 case EXCP0E_PAGE:
344 info.si_signo = TARGET_SIGSEGV;
345 info.si_errno = 0;
346 if (!(env->error_code & 1))
347 info.si_code = TARGET_SEGV_MAPERR;
348 else
349 info.si_code = TARGET_SEGV_ACCERR;
350 info._sifields._sigfault._addr = env->cr[2];
351 queue_signal(env, info.si_signo, &info);
352 break;
353 case EXCP00_DIVZ:
354 #ifndef TARGET_X86_64
355 if (env->eflags & VM_MASK) {
356 handle_vm86_trap(env, trapnr);
357 } else
358 #endif
359 {
360 /* division by zero */
361 info.si_signo = TARGET_SIGFPE;
362 info.si_errno = 0;
363 info.si_code = TARGET_FPE_INTDIV;
364 info._sifields._sigfault._addr = env->eip;
365 queue_signal(env, info.si_signo, &info);
366 }
367 break;
368 case EXCP01_DB:
369 case EXCP03_INT3:
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_trap(env, trapnr);
373 } else
374 #endif
375 {
376 info.si_signo = TARGET_SIGTRAP;
377 info.si_errno = 0;
378 if (trapnr == EXCP01_DB) {
379 info.si_code = TARGET_TRAP_BRKPT;
380 info._sifields._sigfault._addr = env->eip;
381 } else {
382 info.si_code = TARGET_SI_KERNEL;
383 info._sifields._sigfault._addr = 0;
384 }
385 queue_signal(env, info.si_signo, &info);
386 }
387 break;
388 case EXCP04_INTO:
389 case EXCP05_BOUND:
390 #ifndef TARGET_X86_64
391 if (env->eflags & VM_MASK) {
392 handle_vm86_trap(env, trapnr);
393 } else
394 #endif
395 {
396 info.si_signo = TARGET_SIGSEGV;
397 info.si_errno = 0;
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 queue_signal(env, info.si_signo, &info);
401 }
402 break;
403 case EXCP06_ILLOP:
404 info.si_signo = TARGET_SIGILL;
405 info.si_errno = 0;
406 info.si_code = TARGET_ILL_ILLOPN;
407 info._sifields._sigfault._addr = env->eip;
408 queue_signal(env, info.si_signo, &info);
409 break;
410 case EXCP_INTERRUPT:
411 /* just indicate that signals should be handled asap */
412 break;
413 case EXCP_DEBUG:
414 {
415 int sig;
416
417 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
418 if (sig)
419 {
420 info.si_signo = sig;
421 info.si_errno = 0;
422 info.si_code = TARGET_TRAP_BRKPT;
423 queue_signal(env, info.si_signo, &info);
424 }
425 }
426 break;
427 default:
428 pc = env->segs[R_CS].base + env->eip;
429 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
430 (long)pc, trapnr);
431 abort();
432 }
433 process_pending_signals(env);
434 }
435 }
436 #endif
437
438 #ifdef TARGET_ARM
439
440 #define get_user_code_u32(x, gaddr, env) \
441 ({ abi_long __r = get_user_u32((x), (gaddr)); \
442 if (!__r && bswap_code(arm_sctlr_b(env))) { \
443 (x) = bswap32(x); \
444 } \
445 __r; \
446 })
447
448 #define get_user_code_u16(x, gaddr, env) \
449 ({ abi_long __r = get_user_u16((x), (gaddr)); \
450 if (!__r && bswap_code(arm_sctlr_b(env))) { \
451 (x) = bswap16(x); \
452 } \
453 __r; \
454 })
455
456 #define get_user_data_u32(x, gaddr, env) \
457 ({ abi_long __r = get_user_u32((x), (gaddr)); \
458 if (!__r && arm_cpu_bswap_data(env)) { \
459 (x) = bswap32(x); \
460 } \
461 __r; \
462 })
463
464 #define get_user_data_u16(x, gaddr, env) \
465 ({ abi_long __r = get_user_u16((x), (gaddr)); \
466 if (!__r && arm_cpu_bswap_data(env)) { \
467 (x) = bswap16(x); \
468 } \
469 __r; \
470 })
471
472 #define put_user_data_u32(x, gaddr, env) \
473 ({ typeof(x) __x = (x); \
474 if (arm_cpu_bswap_data(env)) { \
475 __x = bswap32(__x); \
476 } \
477 put_user_u32(__x, (gaddr)); \
478 })
479
480 #define put_user_data_u16(x, gaddr, env) \
481 ({ typeof(x) __x = (x); \
482 if (arm_cpu_bswap_data(env)) { \
483 __x = bswap16(__x); \
484 } \
485 put_user_u16(__x, (gaddr)); \
486 })
487
488 #ifdef TARGET_ABI32
489 /* Commpage handling -- there is no commpage for AArch64 */
490
491 /*
492 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
493 * Input:
494 * r0 = pointer to oldval
495 * r1 = pointer to newval
496 * r2 = pointer to target value
497 *
498 * Output:
499 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
500 * C set if *ptr was changed, clear if no exchange happened
501 *
502 * Note segv's in kernel helpers are a bit tricky, we can set the
503 * data address sensibly but the PC address is just the entry point.
504 */
505 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
506 {
507 uint64_t oldval, newval, val;
508 uint32_t addr, cpsr;
509 target_siginfo_t info;
510
511 /* Based on the 32 bit code in do_kernel_trap */
512
513 /* XXX: This only works between threads, not between processes.
514 It's probably possible to implement this with native host
515 operations. However things like ldrex/strex are much harder so
516 there's not much point trying. */
517 start_exclusive();
518 cpsr = cpsr_read(env);
519 addr = env->regs[2];
520
521 if (get_user_u64(oldval, env->regs[0])) {
522 env->exception.vaddress = env->regs[0];
523 goto segv;
524 };
525
526 if (get_user_u64(newval, env->regs[1])) {
527 env->exception.vaddress = env->regs[1];
528 goto segv;
529 };
530
531 if (get_user_u64(val, addr)) {
532 env->exception.vaddress = addr;
533 goto segv;
534 }
535
536 if (val == oldval) {
537 val = newval;
538
539 if (put_user_u64(val, addr)) {
540 env->exception.vaddress = addr;
541 goto segv;
542 };
543
544 env->regs[0] = 0;
545 cpsr |= CPSR_C;
546 } else {
547 env->regs[0] = -1;
548 cpsr &= ~CPSR_C;
549 }
550 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
551 end_exclusive();
552 return;
553
554 segv:
555 end_exclusive();
556 /* We get the PC of the entry address - which is as good as anything,
557 on a real kernel what you get depends on which mode it uses. */
558 info.si_signo = TARGET_SIGSEGV;
559 info.si_errno = 0;
560 /* XXX: check env->error_code */
561 info.si_code = TARGET_SEGV_MAPERR;
562 info._sifields._sigfault._addr = env->exception.vaddress;
563 queue_signal(env, info.si_signo, &info);
564 }
565
566 /* Handle a jump to the kernel code page. */
567 static int
568 do_kernel_trap(CPUARMState *env)
569 {
570 uint32_t addr;
571 uint32_t cpsr;
572 uint32_t val;
573
574 switch (env->regs[15]) {
575 case 0xffff0fa0: /* __kernel_memory_barrier */
576 /* ??? No-op. Will need to do better for SMP. */
577 break;
578 case 0xffff0fc0: /* __kernel_cmpxchg */
579 /* XXX: This only works between threads, not between processes.
580 It's probably possible to implement this with native host
581 operations. However things like ldrex/strex are much harder so
582 there's not much point trying. */
583 start_exclusive();
584 cpsr = cpsr_read(env);
585 addr = env->regs[2];
586 /* FIXME: This should SEGV if the access fails. */
587 if (get_user_u32(val, addr))
588 val = ~env->regs[0];
589 if (val == env->regs[0]) {
590 val = env->regs[1];
591 /* FIXME: Check for segfaults. */
592 put_user_u32(val, addr);
593 env->regs[0] = 0;
594 cpsr |= CPSR_C;
595 } else {
596 env->regs[0] = -1;
597 cpsr &= ~CPSR_C;
598 }
599 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
600 end_exclusive();
601 break;
602 case 0xffff0fe0: /* __kernel_get_tls */
603 env->regs[0] = cpu_get_tls(env);
604 break;
605 case 0xffff0f60: /* __kernel_cmpxchg64 */
606 arm_kernel_cmpxchg64_helper(env);
607 break;
608
609 default:
610 return 1;
611 }
612 /* Jump back to the caller. */
613 addr = env->regs[14];
614 if (addr & 1) {
615 env->thumb = 1;
616 addr &= ~1;
617 }
618 env->regs[15] = addr;
619
620 return 0;
621 }
622
623 /* Store exclusive handling for AArch32 */
624 static int do_strex(CPUARMState *env)
625 {
626 uint64_t val;
627 int size;
628 int rc = 1;
629 int segv = 0;
630 uint32_t addr;
631 start_exclusive();
632 if (env->exclusive_addr != env->exclusive_test) {
633 goto fail;
634 }
635 /* We know we're always AArch32 so the address is in uint32_t range
636 * unless it was the -1 exclusive-monitor-lost value (which won't
637 * match exclusive_test above).
638 */
639 assert(extract64(env->exclusive_addr, 32, 32) == 0);
640 addr = env->exclusive_addr;
641 size = env->exclusive_info & 0xf;
642 switch (size) {
643 case 0:
644 segv = get_user_u8(val, addr);
645 break;
646 case 1:
647 segv = get_user_data_u16(val, addr, env);
648 break;
649 case 2:
650 case 3:
651 segv = get_user_data_u32(val, addr, env);
652 break;
653 default:
654 abort();
655 }
656 if (segv) {
657 env->exception.vaddress = addr;
658 goto done;
659 }
660 if (size == 3) {
661 uint32_t valhi;
662 segv = get_user_data_u32(valhi, addr + 4, env);
663 if (segv) {
664 env->exception.vaddress = addr + 4;
665 goto done;
666 }
667 if (arm_cpu_bswap_data(env)) {
668 val = deposit64((uint64_t)valhi, 32, 32, val);
669 } else {
670 val = deposit64(val, 32, 32, valhi);
671 }
672 }
673 if (val != env->exclusive_val) {
674 goto fail;
675 }
676
677 val = env->regs[(env->exclusive_info >> 8) & 0xf];
678 switch (size) {
679 case 0:
680 segv = put_user_u8(val, addr);
681 break;
682 case 1:
683 segv = put_user_data_u16(val, addr, env);
684 break;
685 case 2:
686 case 3:
687 segv = put_user_data_u32(val, addr, env);
688 break;
689 }
690 if (segv) {
691 env->exception.vaddress = addr;
692 goto done;
693 }
694 if (size == 3) {
695 val = env->regs[(env->exclusive_info >> 12) & 0xf];
696 segv = put_user_data_u32(val, addr + 4, env);
697 if (segv) {
698 env->exception.vaddress = addr + 4;
699 goto done;
700 }
701 }
702 rc = 0;
703 fail:
704 env->regs[15] += 4;
705 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
706 done:
707 end_exclusive();
708 return segv;
709 }
710
711 void cpu_loop(CPUARMState *env)
712 {
713 CPUState *cs = CPU(arm_env_get_cpu(env));
714 int trapnr;
715 unsigned int n, insn;
716 target_siginfo_t info;
717 uint32_t addr;
718
719 for(;;) {
720 cpu_exec_start(cs);
721 trapnr = cpu_arm_exec(cs);
722 cpu_exec_end(cs);
723 switch(trapnr) {
724 case EXCP_UDEF:
725 {
726 TaskState *ts = cs->opaque;
727 uint32_t opcode;
728 int rc;
729
730 /* we handle the FPU emulation here, as Linux */
731 /* we get the opcode */
732 /* FIXME - what to do if get_user() fails? */
733 get_user_code_u32(opcode, env->regs[15], env);
734
735 rc = EmulateAll(opcode, &ts->fpa, env);
736 if (rc == 0) { /* illegal instruction */
737 info.si_signo = TARGET_SIGILL;
738 info.si_errno = 0;
739 info.si_code = TARGET_ILL_ILLOPN;
740 info._sifields._sigfault._addr = env->regs[15];
741 queue_signal(env, info.si_signo, &info);
742 } else if (rc < 0) { /* FP exception */
743 int arm_fpe=0;
744
745 /* translate softfloat flags to FPSR flags */
746 if (-rc & float_flag_invalid)
747 arm_fpe |= BIT_IOC;
748 if (-rc & float_flag_divbyzero)
749 arm_fpe |= BIT_DZC;
750 if (-rc & float_flag_overflow)
751 arm_fpe |= BIT_OFC;
752 if (-rc & float_flag_underflow)
753 arm_fpe |= BIT_UFC;
754 if (-rc & float_flag_inexact)
755 arm_fpe |= BIT_IXC;
756
757 FPSR fpsr = ts->fpa.fpsr;
758 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
759
760 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
761 info.si_signo = TARGET_SIGFPE;
762 info.si_errno = 0;
763
764 /* ordered by priority, least first */
765 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
766 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
767 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
768 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
769 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
770
771 info._sifields._sigfault._addr = env->regs[15];
772 queue_signal(env, info.si_signo, &info);
773 } else {
774 env->regs[15] += 4;
775 }
776
777 /* accumulate unenabled exceptions */
778 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
779 fpsr |= BIT_IXC;
780 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
781 fpsr |= BIT_UFC;
782 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
783 fpsr |= BIT_OFC;
784 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
785 fpsr |= BIT_DZC;
786 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
787 fpsr |= BIT_IOC;
788 ts->fpa.fpsr=fpsr;
789 } else { /* everything OK */
790 /* increment PC */
791 env->regs[15] += 4;
792 }
793 }
794 break;
795 case EXCP_SWI:
796 case EXCP_BKPT:
797 {
798 env->eabi = 1;
799 /* system call */
800 if (trapnr == EXCP_BKPT) {
801 if (env->thumb) {
802 /* FIXME - what to do if get_user() fails? */
803 get_user_code_u16(insn, env->regs[15], env);
804 n = insn & 0xff;
805 env->regs[15] += 2;
806 } else {
807 /* FIXME - what to do if get_user() fails? */
808 get_user_code_u32(insn, env->regs[15], env);
809 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
810 env->regs[15] += 4;
811 }
812 } else {
813 if (env->thumb) {
814 /* FIXME - what to do if get_user() fails? */
815 get_user_code_u16(insn, env->regs[15] - 2, env);
816 n = insn & 0xff;
817 } else {
818 /* FIXME - what to do if get_user() fails? */
819 get_user_code_u32(insn, env->regs[15] - 4, env);
820 n = insn & 0xffffff;
821 }
822 }
823
824 if (n == ARM_NR_cacheflush) {
825 /* nop */
826 } else if (n == ARM_NR_semihosting
827 || n == ARM_NR_thumb_semihosting) {
828 env->regs[0] = do_arm_semihosting (env);
829 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
830 /* linux syscall */
831 if (env->thumb || n == 0) {
832 n = env->regs[7];
833 } else {
834 n -= ARM_SYSCALL_BASE;
835 env->eabi = 0;
836 }
837 if ( n > ARM_NR_BASE) {
838 switch (n) {
839 case ARM_NR_cacheflush:
840 /* nop */
841 break;
842 case ARM_NR_set_tls:
843 cpu_set_tls(env, env->regs[0]);
844 env->regs[0] = 0;
845 break;
846 case ARM_NR_breakpoint:
847 env->regs[15] -= env->thumb ? 2 : 4;
848 goto excp_debug;
849 default:
850 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
851 n);
852 env->regs[0] = -TARGET_ENOSYS;
853 break;
854 }
855 } else {
856 env->regs[0] = do_syscall(env,
857 n,
858 env->regs[0],
859 env->regs[1],
860 env->regs[2],
861 env->regs[3],
862 env->regs[4],
863 env->regs[5],
864 0, 0);
865 }
866 } else {
867 goto error;
868 }
869 }
870 break;
871 case EXCP_INTERRUPT:
872 /* just indicate that signals should be handled asap */
873 break;
874 case EXCP_STREX:
875 if (!do_strex(env)) {
876 break;
877 }
878 /* fall through for segv */
879 case EXCP_PREFETCH_ABORT:
880 case EXCP_DATA_ABORT:
881 addr = env->exception.vaddress;
882 {
883 info.si_signo = TARGET_SIGSEGV;
884 info.si_errno = 0;
885 /* XXX: check env->error_code */
886 info.si_code = TARGET_SEGV_MAPERR;
887 info._sifields._sigfault._addr = addr;
888 queue_signal(env, info.si_signo, &info);
889 }
890 break;
891 case EXCP_DEBUG:
892 excp_debug:
893 {
894 int sig;
895
896 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
897 if (sig)
898 {
899 info.si_signo = sig;
900 info.si_errno = 0;
901 info.si_code = TARGET_TRAP_BRKPT;
902 queue_signal(env, info.si_signo, &info);
903 }
904 }
905 break;
906 case EXCP_KERNEL_TRAP:
907 if (do_kernel_trap(env))
908 goto error;
909 break;
910 default:
911 error:
912 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
913 abort();
914 }
915 process_pending_signals(env);
916 }
917 }
918
919 #else
920
921 /*
922 * Handle AArch64 store-release exclusive
923 *
924 * rs = gets the status result of store exclusive
925 * rt = is the register that is stored
926 * rt2 = is the second register store (in STP)
927 *
928 */
929 static int do_strex_a64(CPUARMState *env)
930 {
931 uint64_t val;
932 int size;
933 bool is_pair;
934 int rc = 1;
935 int segv = 0;
936 uint64_t addr;
937 int rs, rt, rt2;
938
939 start_exclusive();
940 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
941 size = extract32(env->exclusive_info, 0, 2);
942 is_pair = extract32(env->exclusive_info, 2, 1);
943 rs = extract32(env->exclusive_info, 4, 5);
944 rt = extract32(env->exclusive_info, 9, 5);
945 rt2 = extract32(env->exclusive_info, 14, 5);
946
947 addr = env->exclusive_addr;
948
949 if (addr != env->exclusive_test) {
950 goto finish;
951 }
952
953 switch (size) {
954 case 0:
955 segv = get_user_u8(val, addr);
956 break;
957 case 1:
958 segv = get_user_u16(val, addr);
959 break;
960 case 2:
961 segv = get_user_u32(val, addr);
962 break;
963 case 3:
964 segv = get_user_u64(val, addr);
965 break;
966 default:
967 abort();
968 }
969 if (segv) {
970 env->exception.vaddress = addr;
971 goto error;
972 }
973 if (val != env->exclusive_val) {
974 goto finish;
975 }
976 if (is_pair) {
977 if (size == 2) {
978 segv = get_user_u32(val, addr + 4);
979 } else {
980 segv = get_user_u64(val, addr + 8);
981 }
982 if (segv) {
983 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
984 goto error;
985 }
986 if (val != env->exclusive_high) {
987 goto finish;
988 }
989 }
990 /* handle the zero register */
991 val = rt == 31 ? 0 : env->xregs[rt];
992 switch (size) {
993 case 0:
994 segv = put_user_u8(val, addr);
995 break;
996 case 1:
997 segv = put_user_u16(val, addr);
998 break;
999 case 2:
1000 segv = put_user_u32(val, addr);
1001 break;
1002 case 3:
1003 segv = put_user_u64(val, addr);
1004 break;
1005 }
1006 if (segv) {
1007 goto error;
1008 }
1009 if (is_pair) {
1010 /* handle the zero register */
1011 val = rt2 == 31 ? 0 : env->xregs[rt2];
1012 if (size == 2) {
1013 segv = put_user_u32(val, addr + 4);
1014 } else {
1015 segv = put_user_u64(val, addr + 8);
1016 }
1017 if (segv) {
1018 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1019 goto error;
1020 }
1021 }
1022 rc = 0;
1023 finish:
1024 env->pc += 4;
1025 /* rs == 31 encodes a write to the ZR, thus throwing away
1026 * the status return. This is rather silly but valid.
1027 */
1028 if (rs < 31) {
1029 env->xregs[rs] = rc;
1030 }
1031 error:
1032 /* instruction faulted, PC does not advance */
1033 /* either way a strex releases any exclusive lock we have */
1034 env->exclusive_addr = -1;
1035 end_exclusive();
1036 return segv;
1037 }
1038
1039 /* AArch64 main loop */
1040 void cpu_loop(CPUARMState *env)
1041 {
1042 CPUState *cs = CPU(arm_env_get_cpu(env));
1043 int trapnr, sig;
1044 target_siginfo_t info;
1045
1046 for (;;) {
1047 cpu_exec_start(cs);
1048 trapnr = cpu_arm_exec(cs);
1049 cpu_exec_end(cs);
1050
1051 switch (trapnr) {
1052 case EXCP_SWI:
1053 env->xregs[0] = do_syscall(env,
1054 env->xregs[8],
1055 env->xregs[0],
1056 env->xregs[1],
1057 env->xregs[2],
1058 env->xregs[3],
1059 env->xregs[4],
1060 env->xregs[5],
1061 0, 0);
1062 break;
1063 case EXCP_INTERRUPT:
1064 /* just indicate that signals should be handled asap */
1065 break;
1066 case EXCP_UDEF:
1067 info.si_signo = TARGET_SIGILL;
1068 info.si_errno = 0;
1069 info.si_code = TARGET_ILL_ILLOPN;
1070 info._sifields._sigfault._addr = env->pc;
1071 queue_signal(env, info.si_signo, &info);
1072 break;
1073 case EXCP_STREX:
1074 if (!do_strex_a64(env)) {
1075 break;
1076 }
1077 /* fall through for segv */
1078 case EXCP_PREFETCH_ABORT:
1079 case EXCP_DATA_ABORT:
1080 info.si_signo = TARGET_SIGSEGV;
1081 info.si_errno = 0;
1082 /* XXX: check env->error_code */
1083 info.si_code = TARGET_SEGV_MAPERR;
1084 info._sifields._sigfault._addr = env->exception.vaddress;
1085 queue_signal(env, info.si_signo, &info);
1086 break;
1087 case EXCP_DEBUG:
1088 case EXCP_BKPT:
1089 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1090 if (sig) {
1091 info.si_signo = sig;
1092 info.si_errno = 0;
1093 info.si_code = TARGET_TRAP_BRKPT;
1094 queue_signal(env, info.si_signo, &info);
1095 }
1096 break;
1097 case EXCP_SEMIHOST:
1098 env->xregs[0] = do_arm_semihosting(env);
1099 break;
1100 default:
1101 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1102 abort();
1103 }
1104 process_pending_signals(env);
1105 /* Exception return on AArch64 always clears the exclusive monitor,
1106 * so any return to running guest code implies this.
1107 * A strex (successful or otherwise) also clears the monitor, so
1108 * we don't need to specialcase EXCP_STREX.
1109 */
1110 env->exclusive_addr = -1;
1111 }
1112 }
1113 #endif /* ndef TARGET_ABI32 */
1114
1115 #endif
1116
1117 #ifdef TARGET_UNICORE32
1118
1119 void cpu_loop(CPUUniCore32State *env)
1120 {
1121 CPUState *cs = CPU(uc32_env_get_cpu(env));
1122 int trapnr;
1123 unsigned int n, insn;
1124 target_siginfo_t info;
1125
1126 for (;;) {
1127 cpu_exec_start(cs);
1128 trapnr = uc32_cpu_exec(cs);
1129 cpu_exec_end(cs);
1130 switch (trapnr) {
1131 case UC32_EXCP_PRIV:
1132 {
1133 /* system call */
1134 get_user_u32(insn, env->regs[31] - 4);
1135 n = insn & 0xffffff;
1136
1137 if (n >= UC32_SYSCALL_BASE) {
1138 /* linux syscall */
1139 n -= UC32_SYSCALL_BASE;
1140 if (n == UC32_SYSCALL_NR_set_tls) {
1141 cpu_set_tls(env, env->regs[0]);
1142 env->regs[0] = 0;
1143 } else {
1144 env->regs[0] = do_syscall(env,
1145 n,
1146 env->regs[0],
1147 env->regs[1],
1148 env->regs[2],
1149 env->regs[3],
1150 env->regs[4],
1151 env->regs[5],
1152 0, 0);
1153 }
1154 } else {
1155 goto error;
1156 }
1157 }
1158 break;
1159 case UC32_EXCP_DTRAP:
1160 case UC32_EXCP_ITRAP:
1161 info.si_signo = TARGET_SIGSEGV;
1162 info.si_errno = 0;
1163 /* XXX: check env->error_code */
1164 info.si_code = TARGET_SEGV_MAPERR;
1165 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1166 queue_signal(env, info.si_signo, &info);
1167 break;
1168 case EXCP_INTERRUPT:
1169 /* just indicate that signals should be handled asap */
1170 break;
1171 case EXCP_DEBUG:
1172 {
1173 int sig;
1174
1175 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1176 if (sig) {
1177 info.si_signo = sig;
1178 info.si_errno = 0;
1179 info.si_code = TARGET_TRAP_BRKPT;
1180 queue_signal(env, info.si_signo, &info);
1181 }
1182 }
1183 break;
1184 default:
1185 goto error;
1186 }
1187 process_pending_signals(env);
1188 }
1189
1190 error:
1191 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1192 abort();
1193 }
1194 #endif
1195
1196 #ifdef TARGET_SPARC
1197 #define SPARC64_STACK_BIAS 2047
1198
1199 //#define DEBUG_WIN
1200
1201 /* WARNING: dealing with register windows _is_ complicated. More info
1202 can be found at http://www.sics.se/~psm/sparcstack.html */
1203 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1204 {
1205 index = (index + cwp * 16) % (16 * env->nwindows);
1206 /* wrap handling : if cwp is on the last window, then we use the
1207 registers 'after' the end */
1208 if (index < 8 && env->cwp == env->nwindows - 1)
1209 index += 16 * env->nwindows;
1210 return index;
1211 }
1212
1213 /* save the register window 'cwp1' */
1214 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1215 {
1216 unsigned int i;
1217 abi_ulong sp_ptr;
1218
1219 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1220 #ifdef TARGET_SPARC64
1221 if (sp_ptr & 3)
1222 sp_ptr += SPARC64_STACK_BIAS;
1223 #endif
1224 #if defined(DEBUG_WIN)
1225 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1226 sp_ptr, cwp1);
1227 #endif
1228 for(i = 0; i < 16; i++) {
1229 /* FIXME - what to do if put_user() fails? */
1230 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1231 sp_ptr += sizeof(abi_ulong);
1232 }
1233 }
1234
1235 static void save_window(CPUSPARCState *env)
1236 {
1237 #ifndef TARGET_SPARC64
1238 unsigned int new_wim;
1239 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1240 ((1LL << env->nwindows) - 1);
1241 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1242 env->wim = new_wim;
1243 #else
1244 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1245 env->cansave++;
1246 env->canrestore--;
1247 #endif
1248 }
1249
1250 static void restore_window(CPUSPARCState *env)
1251 {
1252 #ifndef TARGET_SPARC64
1253 unsigned int new_wim;
1254 #endif
1255 unsigned int i, cwp1;
1256 abi_ulong sp_ptr;
1257
1258 #ifndef TARGET_SPARC64
1259 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1260 ((1LL << env->nwindows) - 1);
1261 #endif
1262
1263 /* restore the invalid window */
1264 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1265 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1266 #ifdef TARGET_SPARC64
1267 if (sp_ptr & 3)
1268 sp_ptr += SPARC64_STACK_BIAS;
1269 #endif
1270 #if defined(DEBUG_WIN)
1271 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1272 sp_ptr, cwp1);
1273 #endif
1274 for(i = 0; i < 16; i++) {
1275 /* FIXME - what to do if get_user() fails? */
1276 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1277 sp_ptr += sizeof(abi_ulong);
1278 }
1279 #ifdef TARGET_SPARC64
1280 env->canrestore++;
1281 if (env->cleanwin < env->nwindows - 1)
1282 env->cleanwin++;
1283 env->cansave--;
1284 #else
1285 env->wim = new_wim;
1286 #endif
1287 }
1288
1289 static void flush_windows(CPUSPARCState *env)
1290 {
1291 int offset, cwp1;
1292
1293 offset = 1;
1294 for(;;) {
1295 /* if restore would invoke restore_window(), then we can stop */
1296 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1297 #ifndef TARGET_SPARC64
1298 if (env->wim & (1 << cwp1))
1299 break;
1300 #else
1301 if (env->canrestore == 0)
1302 break;
1303 env->cansave++;
1304 env->canrestore--;
1305 #endif
1306 save_window_offset(env, cwp1);
1307 offset++;
1308 }
1309 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1310 #ifndef TARGET_SPARC64
1311 /* set wim so that restore will reload the registers */
1312 env->wim = 1 << cwp1;
1313 #endif
1314 #if defined(DEBUG_WIN)
1315 printf("flush_windows: nb=%d\n", offset - 1);
1316 #endif
1317 }
1318
1319 void cpu_loop (CPUSPARCState *env)
1320 {
1321 CPUState *cs = CPU(sparc_env_get_cpu(env));
1322 int trapnr;
1323 abi_long ret;
1324 target_siginfo_t info;
1325
1326 while (1) {
1327 cpu_exec_start(cs);
1328 trapnr = cpu_sparc_exec(cs);
1329 cpu_exec_end(cs);
1330
1331 /* Compute PSR before exposing state. */
1332 if (env->cc_op != CC_OP_FLAGS) {
1333 cpu_get_psr(env);
1334 }
1335
1336 switch (trapnr) {
1337 #ifndef TARGET_SPARC64
1338 case 0x88:
1339 case 0x90:
1340 #else
1341 case 0x110:
1342 case 0x16d:
1343 #endif
1344 ret = do_syscall (env, env->gregs[1],
1345 env->regwptr[0], env->regwptr[1],
1346 env->regwptr[2], env->regwptr[3],
1347 env->regwptr[4], env->regwptr[5],
1348 0, 0);
1349 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1350 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1351 env->xcc |= PSR_CARRY;
1352 #else
1353 env->psr |= PSR_CARRY;
1354 #endif
1355 ret = -ret;
1356 } else {
1357 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1358 env->xcc &= ~PSR_CARRY;
1359 #else
1360 env->psr &= ~PSR_CARRY;
1361 #endif
1362 }
1363 env->regwptr[0] = ret;
1364 /* next instruction */
1365 env->pc = env->npc;
1366 env->npc = env->npc + 4;
1367 break;
1368 case 0x83: /* flush windows */
1369 #ifdef TARGET_ABI32
1370 case 0x103:
1371 #endif
1372 flush_windows(env);
1373 /* next instruction */
1374 env->pc = env->npc;
1375 env->npc = env->npc + 4;
1376 break;
1377 #ifndef TARGET_SPARC64
1378 case TT_WIN_OVF: /* window overflow */
1379 save_window(env);
1380 break;
1381 case TT_WIN_UNF: /* window underflow */
1382 restore_window(env);
1383 break;
1384 case TT_TFAULT:
1385 case TT_DFAULT:
1386 {
1387 info.si_signo = TARGET_SIGSEGV;
1388 info.si_errno = 0;
1389 /* XXX: check env->error_code */
1390 info.si_code = TARGET_SEGV_MAPERR;
1391 info._sifields._sigfault._addr = env->mmuregs[4];
1392 queue_signal(env, info.si_signo, &info);
1393 }
1394 break;
1395 #else
1396 case TT_SPILL: /* window overflow */
1397 save_window(env);
1398 break;
1399 case TT_FILL: /* window underflow */
1400 restore_window(env);
1401 break;
1402 case TT_TFAULT:
1403 case TT_DFAULT:
1404 {
1405 info.si_signo = TARGET_SIGSEGV;
1406 info.si_errno = 0;
1407 /* XXX: check env->error_code */
1408 info.si_code = TARGET_SEGV_MAPERR;
1409 if (trapnr == TT_DFAULT)
1410 info._sifields._sigfault._addr = env->dmmuregs[4];
1411 else
1412 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1413 queue_signal(env, info.si_signo, &info);
1414 }
1415 break;
1416 #ifndef TARGET_ABI32
1417 case 0x16e:
1418 flush_windows(env);
1419 sparc64_get_context(env);
1420 break;
1421 case 0x16f:
1422 flush_windows(env);
1423 sparc64_set_context(env);
1424 break;
1425 #endif
1426 #endif
1427 case EXCP_INTERRUPT:
1428 /* just indicate that signals should be handled asap */
1429 break;
1430 case TT_ILL_INSN:
1431 {
1432 info.si_signo = TARGET_SIGILL;
1433 info.si_errno = 0;
1434 info.si_code = TARGET_ILL_ILLOPC;
1435 info._sifields._sigfault._addr = env->pc;
1436 queue_signal(env, info.si_signo, &info);
1437 }
1438 break;
1439 case EXCP_DEBUG:
1440 {
1441 int sig;
1442
1443 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1444 if (sig)
1445 {
1446 info.si_signo = sig;
1447 info.si_errno = 0;
1448 info.si_code = TARGET_TRAP_BRKPT;
1449 queue_signal(env, info.si_signo, &info);
1450 }
1451 }
1452 break;
1453 default:
1454 printf ("Unhandled trap: 0x%x\n", trapnr);
1455 cpu_dump_state(cs, stderr, fprintf, 0);
1456 exit(EXIT_FAILURE);
1457 }
1458 process_pending_signals (env);
1459 }
1460 }
1461
1462 #endif
1463
1464 #ifdef TARGET_PPC
1465 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1466 {
1467 return cpu_get_host_ticks();
1468 }
1469
1470 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1471 {
1472 return cpu_ppc_get_tb(env);
1473 }
1474
1475 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1476 {
1477 return cpu_ppc_get_tb(env) >> 32;
1478 }
1479
1480 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1481 {
1482 return cpu_ppc_get_tb(env);
1483 }
1484
1485 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1486 {
1487 return cpu_ppc_get_tb(env) >> 32;
1488 }
1489
1490 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1491 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1492
1493 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1494 {
1495 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1496 }
1497
1498 /* XXX: to be fixed */
1499 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1500 {
1501 return -1;
1502 }
1503
1504 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1505 {
1506 return -1;
1507 }
1508
1509 static int do_store_exclusive(CPUPPCState *env)
1510 {
1511 target_ulong addr;
1512 target_ulong page_addr;
1513 target_ulong val, val2 __attribute__((unused)) = 0;
1514 int flags;
1515 int segv = 0;
1516
1517 addr = env->reserve_ea;
1518 page_addr = addr & TARGET_PAGE_MASK;
1519 start_exclusive();
1520 mmap_lock();
1521 flags = page_get_flags(page_addr);
1522 if ((flags & PAGE_READ) == 0) {
1523 segv = 1;
1524 } else {
1525 int reg = env->reserve_info & 0x1f;
1526 int size = env->reserve_info >> 5;
1527 int stored = 0;
1528
1529 if (addr == env->reserve_addr) {
1530 switch (size) {
1531 case 1: segv = get_user_u8(val, addr); break;
1532 case 2: segv = get_user_u16(val, addr); break;
1533 case 4: segv = get_user_u32(val, addr); break;
1534 #if defined(TARGET_PPC64)
1535 case 8: segv = get_user_u64(val, addr); break;
1536 case 16: {
1537 segv = get_user_u64(val, addr);
1538 if (!segv) {
1539 segv = get_user_u64(val2, addr + 8);
1540 }
1541 break;
1542 }
1543 #endif
1544 default: abort();
1545 }
1546 if (!segv && val == env->reserve_val) {
1547 val = env->gpr[reg];
1548 switch (size) {
1549 case 1: segv = put_user_u8(val, addr); break;
1550 case 2: segv = put_user_u16(val, addr); break;
1551 case 4: segv = put_user_u32(val, addr); break;
1552 #if defined(TARGET_PPC64)
1553 case 8: segv = put_user_u64(val, addr); break;
1554 case 16: {
1555 if (val2 == env->reserve_val2) {
1556 if (msr_le) {
1557 val2 = val;
1558 val = env->gpr[reg+1];
1559 } else {
1560 val2 = env->gpr[reg+1];
1561 }
1562 segv = put_user_u64(val, addr);
1563 if (!segv) {
1564 segv = put_user_u64(val2, addr + 8);
1565 }
1566 }
1567 break;
1568 }
1569 #endif
1570 default: abort();
1571 }
1572 if (!segv) {
1573 stored = 1;
1574 }
1575 }
1576 }
1577 env->crf[0] = (stored << 1) | xer_so;
1578 env->reserve_addr = (target_ulong)-1;
1579 }
1580 if (!segv) {
1581 env->nip += 4;
1582 }
1583 mmap_unlock();
1584 end_exclusive();
1585 return segv;
1586 }
1587
1588 void cpu_loop(CPUPPCState *env)
1589 {
1590 CPUState *cs = CPU(ppc_env_get_cpu(env));
1591 target_siginfo_t info;
1592 int trapnr;
1593 target_ulong ret;
1594
1595 for(;;) {
1596 cpu_exec_start(cs);
1597 trapnr = cpu_ppc_exec(cs);
1598 cpu_exec_end(cs);
1599 switch(trapnr) {
1600 case POWERPC_EXCP_NONE:
1601 /* Just go on */
1602 break;
1603 case POWERPC_EXCP_CRITICAL: /* Critical input */
1604 cpu_abort(cs, "Critical interrupt while in user mode. "
1605 "Aborting\n");
1606 break;
1607 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1608 cpu_abort(cs, "Machine check exception while in user mode. "
1609 "Aborting\n");
1610 break;
1611 case POWERPC_EXCP_DSI: /* Data storage exception */
1612 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1613 env->spr[SPR_DAR]);
1614 /* XXX: check this. Seems bugged */
1615 switch (env->error_code & 0xFF000000) {
1616 case 0x40000000:
1617 info.si_signo = TARGET_SIGSEGV;
1618 info.si_errno = 0;
1619 info.si_code = TARGET_SEGV_MAPERR;
1620 break;
1621 case 0x04000000:
1622 info.si_signo = TARGET_SIGILL;
1623 info.si_errno = 0;
1624 info.si_code = TARGET_ILL_ILLADR;
1625 break;
1626 case 0x08000000:
1627 info.si_signo = TARGET_SIGSEGV;
1628 info.si_errno = 0;
1629 info.si_code = TARGET_SEGV_ACCERR;
1630 break;
1631 default:
1632 /* Let's send a regular segfault... */
1633 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1634 env->error_code);
1635 info.si_signo = TARGET_SIGSEGV;
1636 info.si_errno = 0;
1637 info.si_code = TARGET_SEGV_MAPERR;
1638 break;
1639 }
1640 info._sifields._sigfault._addr = env->nip;
1641 queue_signal(env, info.si_signo, &info);
1642 break;
1643 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1644 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1645 "\n", env->spr[SPR_SRR0]);
1646 /* XXX: check this */
1647 switch (env->error_code & 0xFF000000) {
1648 case 0x40000000:
1649 info.si_signo = TARGET_SIGSEGV;
1650 info.si_errno = 0;
1651 info.si_code = TARGET_SEGV_MAPERR;
1652 break;
1653 case 0x10000000:
1654 case 0x08000000:
1655 info.si_signo = TARGET_SIGSEGV;
1656 info.si_errno = 0;
1657 info.si_code = TARGET_SEGV_ACCERR;
1658 break;
1659 default:
1660 /* Let's send a regular segfault... */
1661 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1662 env->error_code);
1663 info.si_signo = TARGET_SIGSEGV;
1664 info.si_errno = 0;
1665 info.si_code = TARGET_SEGV_MAPERR;
1666 break;
1667 }
1668 info._sifields._sigfault._addr = env->nip - 4;
1669 queue_signal(env, info.si_signo, &info);
1670 break;
1671 case POWERPC_EXCP_EXTERNAL: /* External input */
1672 cpu_abort(cs, "External interrupt while in user mode. "
1673 "Aborting\n");
1674 break;
1675 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1676 EXCP_DUMP(env, "Unaligned memory access\n");
1677 /* XXX: check this */
1678 info.si_signo = TARGET_SIGBUS;
1679 info.si_errno = 0;
1680 info.si_code = TARGET_BUS_ADRALN;
1681 info._sifields._sigfault._addr = env->nip;
1682 queue_signal(env, info.si_signo, &info);
1683 break;
1684 case POWERPC_EXCP_PROGRAM: /* Program exception */
1685 /* XXX: check this */
1686 switch (env->error_code & ~0xF) {
1687 case POWERPC_EXCP_FP:
1688 EXCP_DUMP(env, "Floating point program exception\n");
1689 info.si_signo = TARGET_SIGFPE;
1690 info.si_errno = 0;
1691 switch (env->error_code & 0xF) {
1692 case POWERPC_EXCP_FP_OX:
1693 info.si_code = TARGET_FPE_FLTOVF;
1694 break;
1695 case POWERPC_EXCP_FP_UX:
1696 info.si_code = TARGET_FPE_FLTUND;
1697 break;
1698 case POWERPC_EXCP_FP_ZX:
1699 case POWERPC_EXCP_FP_VXZDZ:
1700 info.si_code = TARGET_FPE_FLTDIV;
1701 break;
1702 case POWERPC_EXCP_FP_XX:
1703 info.si_code = TARGET_FPE_FLTRES;
1704 break;
1705 case POWERPC_EXCP_FP_VXSOFT:
1706 info.si_code = TARGET_FPE_FLTINV;
1707 break;
1708 case POWERPC_EXCP_FP_VXSNAN:
1709 case POWERPC_EXCP_FP_VXISI:
1710 case POWERPC_EXCP_FP_VXIDI:
1711 case POWERPC_EXCP_FP_VXIMZ:
1712 case POWERPC_EXCP_FP_VXVC:
1713 case POWERPC_EXCP_FP_VXSQRT:
1714 case POWERPC_EXCP_FP_VXCVI:
1715 info.si_code = TARGET_FPE_FLTSUB;
1716 break;
1717 default:
1718 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1719 env->error_code);
1720 break;
1721 }
1722 break;
1723 case POWERPC_EXCP_INVAL:
1724 EXCP_DUMP(env, "Invalid instruction\n");
1725 info.si_signo = TARGET_SIGILL;
1726 info.si_errno = 0;
1727 switch (env->error_code & 0xF) {
1728 case POWERPC_EXCP_INVAL_INVAL:
1729 info.si_code = TARGET_ILL_ILLOPC;
1730 break;
1731 case POWERPC_EXCP_INVAL_LSWX:
1732 info.si_code = TARGET_ILL_ILLOPN;
1733 break;
1734 case POWERPC_EXCP_INVAL_SPR:
1735 info.si_code = TARGET_ILL_PRVREG;
1736 break;
1737 case POWERPC_EXCP_INVAL_FP:
1738 info.si_code = TARGET_ILL_COPROC;
1739 break;
1740 default:
1741 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1742 env->error_code & 0xF);
1743 info.si_code = TARGET_ILL_ILLADR;
1744 break;
1745 }
1746 break;
1747 case POWERPC_EXCP_PRIV:
1748 EXCP_DUMP(env, "Privilege violation\n");
1749 info.si_signo = TARGET_SIGILL;
1750 info.si_errno = 0;
1751 switch (env->error_code & 0xF) {
1752 case POWERPC_EXCP_PRIV_OPC:
1753 info.si_code = TARGET_ILL_PRVOPC;
1754 break;
1755 case POWERPC_EXCP_PRIV_REG:
1756 info.si_code = TARGET_ILL_PRVREG;
1757 break;
1758 default:
1759 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1760 env->error_code & 0xF);
1761 info.si_code = TARGET_ILL_PRVOPC;
1762 break;
1763 }
1764 break;
1765 case POWERPC_EXCP_TRAP:
1766 cpu_abort(cs, "Tried to call a TRAP\n");
1767 break;
1768 default:
1769 /* Should not happen ! */
1770 cpu_abort(cs, "Unknown program exception (%02x)\n",
1771 env->error_code);
1772 break;
1773 }
1774 info._sifields._sigfault._addr = env->nip - 4;
1775 queue_signal(env, info.si_signo, &info);
1776 break;
1777 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1778 EXCP_DUMP(env, "No floating point allowed\n");
1779 info.si_signo = TARGET_SIGILL;
1780 info.si_errno = 0;
1781 info.si_code = TARGET_ILL_COPROC;
1782 info._sifields._sigfault._addr = env->nip - 4;
1783 queue_signal(env, info.si_signo, &info);
1784 break;
1785 case POWERPC_EXCP_SYSCALL: /* System call exception */
1786 cpu_abort(cs, "Syscall exception while in user mode. "
1787 "Aborting\n");
1788 break;
1789 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1790 EXCP_DUMP(env, "No APU instruction allowed\n");
1791 info.si_signo = TARGET_SIGILL;
1792 info.si_errno = 0;
1793 info.si_code = TARGET_ILL_COPROC;
1794 info._sifields._sigfault._addr = env->nip - 4;
1795 queue_signal(env, info.si_signo, &info);
1796 break;
1797 case POWERPC_EXCP_DECR: /* Decrementer exception */
1798 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1799 "Aborting\n");
1800 break;
1801 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1802 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1803 "Aborting\n");
1804 break;
1805 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1806 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1807 "Aborting\n");
1808 break;
1809 case POWERPC_EXCP_DTLB: /* Data TLB error */
1810 cpu_abort(cs, "Data TLB exception while in user mode. "
1811 "Aborting\n");
1812 break;
1813 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1814 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1815 "Aborting\n");
1816 break;
1817 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1818 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1819 info.si_signo = TARGET_SIGILL;
1820 info.si_errno = 0;
1821 info.si_code = TARGET_ILL_COPROC;
1822 info._sifields._sigfault._addr = env->nip - 4;
1823 queue_signal(env, info.si_signo, &info);
1824 break;
1825 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1826 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1827 break;
1828 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1829 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1830 break;
1831 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1832 cpu_abort(cs, "Performance monitor exception not handled\n");
1833 break;
1834 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1835 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1836 "Aborting\n");
1837 break;
1838 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1839 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1840 "Aborting\n");
1841 break;
1842 case POWERPC_EXCP_RESET: /* System reset exception */
1843 cpu_abort(cs, "Reset interrupt while in user mode. "
1844 "Aborting\n");
1845 break;
1846 case POWERPC_EXCP_DSEG: /* Data segment exception */
1847 cpu_abort(cs, "Data segment exception while in user mode. "
1848 "Aborting\n");
1849 break;
1850 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1851 cpu_abort(cs, "Instruction segment exception "
1852 "while in user mode. Aborting\n");
1853 break;
1854 /* PowerPC 64 with hypervisor mode support */
1855 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1856 cpu_abort(cs, "Hypervisor decrementer interrupt "
1857 "while in user mode. Aborting\n");
1858 break;
1859 case POWERPC_EXCP_TRACE: /* Trace exception */
1860 /* Nothing to do:
1861 * we use this exception to emulate step-by-step execution mode.
1862 */
1863 break;
1864 /* PowerPC 64 with hypervisor mode support */
1865 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1866 cpu_abort(cs, "Hypervisor data storage exception "
1867 "while in user mode. Aborting\n");
1868 break;
1869 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1870 cpu_abort(cs, "Hypervisor instruction storage exception "
1871 "while in user mode. Aborting\n");
1872 break;
1873 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1874 cpu_abort(cs, "Hypervisor data segment exception "
1875 "while in user mode. Aborting\n");
1876 break;
1877 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1878 cpu_abort(cs, "Hypervisor instruction segment exception "
1879 "while in user mode. Aborting\n");
1880 break;
1881 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1882 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1883 info.si_signo = TARGET_SIGILL;
1884 info.si_errno = 0;
1885 info.si_code = TARGET_ILL_COPROC;
1886 info._sifields._sigfault._addr = env->nip - 4;
1887 queue_signal(env, info.si_signo, &info);
1888 break;
1889 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1890 cpu_abort(cs, "Programmable interval timer interrupt "
1891 "while in user mode. Aborting\n");
1892 break;
1893 case POWERPC_EXCP_IO: /* IO error exception */
1894 cpu_abort(cs, "IO error exception while in user mode. "
1895 "Aborting\n");
1896 break;
1897 case POWERPC_EXCP_RUNM: /* Run mode exception */
1898 cpu_abort(cs, "Run mode exception while in user mode. "
1899 "Aborting\n");
1900 break;
1901 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1902 cpu_abort(cs, "Emulation trap exception not handled\n");
1903 break;
1904 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1905 cpu_abort(cs, "Instruction fetch TLB exception "
1906 "while in user-mode. Aborting");
1907 break;
1908 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1909 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1910 "Aborting");
1911 break;
1912 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1913 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1914 "Aborting");
1915 break;
1916 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1917 cpu_abort(cs, "Floating-point assist exception not handled\n");
1918 break;
1919 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1920 cpu_abort(cs, "Instruction address breakpoint exception "
1921 "not handled\n");
1922 break;
1923 case POWERPC_EXCP_SMI: /* System management interrupt */
1924 cpu_abort(cs, "System management interrupt while in user mode. "
1925 "Aborting\n");
1926 break;
1927 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1928 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1929 "Aborting\n");
1930 break;
1931 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1932 cpu_abort(cs, "Performance monitor exception not handled\n");
1933 break;
1934 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1935 cpu_abort(cs, "Vector assist exception not handled\n");
1936 break;
1937 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1938 cpu_abort(cs, "Soft patch exception not handled\n");
1939 break;
1940 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1941 cpu_abort(cs, "Maintenance exception while in user mode. "
1942 "Aborting\n");
1943 break;
1944 case POWERPC_EXCP_STOP: /* stop translation */
1945 /* We did invalidate the instruction cache. Go on */
1946 break;
1947 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1948 /* We just stopped because of a branch. Go on */
1949 break;
1950 case POWERPC_EXCP_SYSCALL_USER:
1951 /* system call in user-mode emulation */
1952 /* WARNING:
1953 * PPC ABI uses overflow flag in cr0 to signal an error
1954 * in syscalls.
1955 */
1956 env->crf[0] &= ~0x1;
1957 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1958 env->gpr[5], env->gpr[6], env->gpr[7],
1959 env->gpr[8], 0, 0);
1960 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1961 /* Returning from a successful sigreturn syscall.
1962 Avoid corrupting register state. */
1963 break;
1964 }
1965 if (ret > (target_ulong)(-515)) {
1966 env->crf[0] |= 0x1;
1967 ret = -ret;
1968 }
1969 env->gpr[3] = ret;
1970 break;
1971 case POWERPC_EXCP_STCX:
1972 if (do_store_exclusive(env)) {
1973 info.si_signo = TARGET_SIGSEGV;
1974 info.si_errno = 0;
1975 info.si_code = TARGET_SEGV_MAPERR;
1976 info._sifields._sigfault._addr = env->nip;
1977 queue_signal(env, info.si_signo, &info);
1978 }
1979 break;
1980 case EXCP_DEBUG:
1981 {
1982 int sig;
1983
1984 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1985 if (sig) {
1986 info.si_signo = sig;
1987 info.si_errno = 0;
1988 info.si_code = TARGET_TRAP_BRKPT;
1989 queue_signal(env, info.si_signo, &info);
1990 }
1991 }
1992 break;
1993 case EXCP_INTERRUPT:
1994 /* just indicate that signals should be handled asap */
1995 break;
1996 default:
1997 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
1998 break;
1999 }
2000 process_pending_signals(env);
2001 }
2002 }
2003 #endif
2004
2005 #ifdef TARGET_MIPS
2006
2007 # ifdef TARGET_ABI_MIPSO32
2008 # define MIPS_SYS(name, args) args,
2009 static const uint8_t mips_syscall_args[] = {
2010 MIPS_SYS(sys_syscall , 8) /* 4000 */
2011 MIPS_SYS(sys_exit , 1)
2012 MIPS_SYS(sys_fork , 0)
2013 MIPS_SYS(sys_read , 3)
2014 MIPS_SYS(sys_write , 3)
2015 MIPS_SYS(sys_open , 3) /* 4005 */
2016 MIPS_SYS(sys_close , 1)
2017 MIPS_SYS(sys_waitpid , 3)
2018 MIPS_SYS(sys_creat , 2)
2019 MIPS_SYS(sys_link , 2)
2020 MIPS_SYS(sys_unlink , 1) /* 4010 */
2021 MIPS_SYS(sys_execve , 0)
2022 MIPS_SYS(sys_chdir , 1)
2023 MIPS_SYS(sys_time , 1)
2024 MIPS_SYS(sys_mknod , 3)
2025 MIPS_SYS(sys_chmod , 2) /* 4015 */
2026 MIPS_SYS(sys_lchown , 3)
2027 MIPS_SYS(sys_ni_syscall , 0)
2028 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2029 MIPS_SYS(sys_lseek , 3)
2030 MIPS_SYS(sys_getpid , 0) /* 4020 */
2031 MIPS_SYS(sys_mount , 5)
2032 MIPS_SYS(sys_umount , 1)
2033 MIPS_SYS(sys_setuid , 1)
2034 MIPS_SYS(sys_getuid , 0)
2035 MIPS_SYS(sys_stime , 1) /* 4025 */
2036 MIPS_SYS(sys_ptrace , 4)
2037 MIPS_SYS(sys_alarm , 1)
2038 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2039 MIPS_SYS(sys_pause , 0)
2040 MIPS_SYS(sys_utime , 2) /* 4030 */
2041 MIPS_SYS(sys_ni_syscall , 0)
2042 MIPS_SYS(sys_ni_syscall , 0)
2043 MIPS_SYS(sys_access , 2)
2044 MIPS_SYS(sys_nice , 1)
2045 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2046 MIPS_SYS(sys_sync , 0)
2047 MIPS_SYS(sys_kill , 2)
2048 MIPS_SYS(sys_rename , 2)
2049 MIPS_SYS(sys_mkdir , 2)
2050 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2051 MIPS_SYS(sys_dup , 1)
2052 MIPS_SYS(sys_pipe , 0)
2053 MIPS_SYS(sys_times , 1)
2054 MIPS_SYS(sys_ni_syscall , 0)
2055 MIPS_SYS(sys_brk , 1) /* 4045 */
2056 MIPS_SYS(sys_setgid , 1)
2057 MIPS_SYS(sys_getgid , 0)
2058 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2059 MIPS_SYS(sys_geteuid , 0)
2060 MIPS_SYS(sys_getegid , 0) /* 4050 */
2061 MIPS_SYS(sys_acct , 0)
2062 MIPS_SYS(sys_umount2 , 2)
2063 MIPS_SYS(sys_ni_syscall , 0)
2064 MIPS_SYS(sys_ioctl , 3)
2065 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2066 MIPS_SYS(sys_ni_syscall , 2)
2067 MIPS_SYS(sys_setpgid , 2)
2068 MIPS_SYS(sys_ni_syscall , 0)
2069 MIPS_SYS(sys_olduname , 1)
2070 MIPS_SYS(sys_umask , 1) /* 4060 */
2071 MIPS_SYS(sys_chroot , 1)
2072 MIPS_SYS(sys_ustat , 2)
2073 MIPS_SYS(sys_dup2 , 2)
2074 MIPS_SYS(sys_getppid , 0)
2075 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2076 MIPS_SYS(sys_setsid , 0)
2077 MIPS_SYS(sys_sigaction , 3)
2078 MIPS_SYS(sys_sgetmask , 0)
2079 MIPS_SYS(sys_ssetmask , 1)
2080 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2081 MIPS_SYS(sys_setregid , 2)
2082 MIPS_SYS(sys_sigsuspend , 0)
2083 MIPS_SYS(sys_sigpending , 1)
2084 MIPS_SYS(sys_sethostname , 2)
2085 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2086 MIPS_SYS(sys_getrlimit , 2)
2087 MIPS_SYS(sys_getrusage , 2)
2088 MIPS_SYS(sys_gettimeofday, 2)
2089 MIPS_SYS(sys_settimeofday, 2)
2090 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2091 MIPS_SYS(sys_setgroups , 2)
2092 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2093 MIPS_SYS(sys_symlink , 2)
2094 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2095 MIPS_SYS(sys_readlink , 3) /* 4085 */
2096 MIPS_SYS(sys_uselib , 1)
2097 MIPS_SYS(sys_swapon , 2)
2098 MIPS_SYS(sys_reboot , 3)
2099 MIPS_SYS(old_readdir , 3)
2100 MIPS_SYS(old_mmap , 6) /* 4090 */
2101 MIPS_SYS(sys_munmap , 2)
2102 MIPS_SYS(sys_truncate , 2)
2103 MIPS_SYS(sys_ftruncate , 2)
2104 MIPS_SYS(sys_fchmod , 2)
2105 MIPS_SYS(sys_fchown , 3) /* 4095 */
2106 MIPS_SYS(sys_getpriority , 2)
2107 MIPS_SYS(sys_setpriority , 3)
2108 MIPS_SYS(sys_ni_syscall , 0)
2109 MIPS_SYS(sys_statfs , 2)
2110 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2111 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2112 MIPS_SYS(sys_socketcall , 2)
2113 MIPS_SYS(sys_syslog , 3)
2114 MIPS_SYS(sys_setitimer , 3)
2115 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2116 MIPS_SYS(sys_newstat , 2)
2117 MIPS_SYS(sys_newlstat , 2)
2118 MIPS_SYS(sys_newfstat , 2)
2119 MIPS_SYS(sys_uname , 1)
2120 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2121 MIPS_SYS(sys_vhangup , 0)
2122 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2123 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2124 MIPS_SYS(sys_wait4 , 4)
2125 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2126 MIPS_SYS(sys_sysinfo , 1)
2127 MIPS_SYS(sys_ipc , 6)
2128 MIPS_SYS(sys_fsync , 1)
2129 MIPS_SYS(sys_sigreturn , 0)
2130 MIPS_SYS(sys_clone , 6) /* 4120 */
2131 MIPS_SYS(sys_setdomainname, 2)
2132 MIPS_SYS(sys_newuname , 1)
2133 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2134 MIPS_SYS(sys_adjtimex , 1)
2135 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2136 MIPS_SYS(sys_sigprocmask , 3)
2137 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2138 MIPS_SYS(sys_init_module , 5)
2139 MIPS_SYS(sys_delete_module, 1)
2140 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2141 MIPS_SYS(sys_quotactl , 0)
2142 MIPS_SYS(sys_getpgid , 1)
2143 MIPS_SYS(sys_fchdir , 1)
2144 MIPS_SYS(sys_bdflush , 2)
2145 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2146 MIPS_SYS(sys_personality , 1)
2147 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2148 MIPS_SYS(sys_setfsuid , 1)
2149 MIPS_SYS(sys_setfsgid , 1)
2150 MIPS_SYS(sys_llseek , 5) /* 4140 */
2151 MIPS_SYS(sys_getdents , 3)
2152 MIPS_SYS(sys_select , 5)
2153 MIPS_SYS(sys_flock , 2)
2154 MIPS_SYS(sys_msync , 3)
2155 MIPS_SYS(sys_readv , 3) /* 4145 */
2156 MIPS_SYS(sys_writev , 3)
2157 MIPS_SYS(sys_cacheflush , 3)
2158 MIPS_SYS(sys_cachectl , 3)
2159 MIPS_SYS(sys_sysmips , 4)
2160 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2161 MIPS_SYS(sys_getsid , 1)
2162 MIPS_SYS(sys_fdatasync , 0)
2163 MIPS_SYS(sys_sysctl , 1)
2164 MIPS_SYS(sys_mlock , 2)
2165 MIPS_SYS(sys_munlock , 2) /* 4155 */
2166 MIPS_SYS(sys_mlockall , 1)
2167 MIPS_SYS(sys_munlockall , 0)
2168 MIPS_SYS(sys_sched_setparam, 2)
2169 MIPS_SYS(sys_sched_getparam, 2)
2170 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2171 MIPS_SYS(sys_sched_getscheduler, 1)
2172 MIPS_SYS(sys_sched_yield , 0)
2173 MIPS_SYS(sys_sched_get_priority_max, 1)
2174 MIPS_SYS(sys_sched_get_priority_min, 1)
2175 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2176 MIPS_SYS(sys_nanosleep, 2)
2177 MIPS_SYS(sys_mremap , 5)
2178 MIPS_SYS(sys_accept , 3)
2179 MIPS_SYS(sys_bind , 3)
2180 MIPS_SYS(sys_connect , 3) /* 4170 */
2181 MIPS_SYS(sys_getpeername , 3)
2182 MIPS_SYS(sys_getsockname , 3)
2183 MIPS_SYS(sys_getsockopt , 5)
2184 MIPS_SYS(sys_listen , 2)
2185 MIPS_SYS(sys_recv , 4) /* 4175 */
2186 MIPS_SYS(sys_recvfrom , 6)
2187 MIPS_SYS(sys_recvmsg , 3)
2188 MIPS_SYS(sys_send , 4)
2189 MIPS_SYS(sys_sendmsg , 3)
2190 MIPS_SYS(sys_sendto , 6) /* 4180 */
2191 MIPS_SYS(sys_setsockopt , 5)
2192 MIPS_SYS(sys_shutdown , 2)
2193 MIPS_SYS(sys_socket , 3)
2194 MIPS_SYS(sys_socketpair , 4)
2195 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2196 MIPS_SYS(sys_getresuid , 3)
2197 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2198 MIPS_SYS(sys_poll , 3)
2199 MIPS_SYS(sys_nfsservctl , 3)
2200 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2201 MIPS_SYS(sys_getresgid , 3)
2202 MIPS_SYS(sys_prctl , 5)
2203 MIPS_SYS(sys_rt_sigreturn, 0)
2204 MIPS_SYS(sys_rt_sigaction, 4)
2205 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2206 MIPS_SYS(sys_rt_sigpending, 2)
2207 MIPS_SYS(sys_rt_sigtimedwait, 4)
2208 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2209 MIPS_SYS(sys_rt_sigsuspend, 0)
2210 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2211 MIPS_SYS(sys_pwrite64 , 6)
2212 MIPS_SYS(sys_chown , 3)
2213 MIPS_SYS(sys_getcwd , 2)
2214 MIPS_SYS(sys_capget , 2)
2215 MIPS_SYS(sys_capset , 2) /* 4205 */
2216 MIPS_SYS(sys_sigaltstack , 2)
2217 MIPS_SYS(sys_sendfile , 4)
2218 MIPS_SYS(sys_ni_syscall , 0)
2219 MIPS_SYS(sys_ni_syscall , 0)
2220 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2221 MIPS_SYS(sys_truncate64 , 4)
2222 MIPS_SYS(sys_ftruncate64 , 4)
2223 MIPS_SYS(sys_stat64 , 2)
2224 MIPS_SYS(sys_lstat64 , 2)
2225 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2226 MIPS_SYS(sys_pivot_root , 2)
2227 MIPS_SYS(sys_mincore , 3)
2228 MIPS_SYS(sys_madvise , 3)
2229 MIPS_SYS(sys_getdents64 , 3)
2230 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2231 MIPS_SYS(sys_ni_syscall , 0)
2232 MIPS_SYS(sys_gettid , 0)
2233 MIPS_SYS(sys_readahead , 5)
2234 MIPS_SYS(sys_setxattr , 5)
2235 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2236 MIPS_SYS(sys_fsetxattr , 5)
2237 MIPS_SYS(sys_getxattr , 4)
2238 MIPS_SYS(sys_lgetxattr , 4)
2239 MIPS_SYS(sys_fgetxattr , 4)
2240 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2241 MIPS_SYS(sys_llistxattr , 3)
2242 MIPS_SYS(sys_flistxattr , 3)
2243 MIPS_SYS(sys_removexattr , 2)
2244 MIPS_SYS(sys_lremovexattr, 2)
2245 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2246 MIPS_SYS(sys_tkill , 2)
2247 MIPS_SYS(sys_sendfile64 , 5)
2248 MIPS_SYS(sys_futex , 6)
2249 MIPS_SYS(sys_sched_setaffinity, 3)
2250 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2251 MIPS_SYS(sys_io_setup , 2)
2252 MIPS_SYS(sys_io_destroy , 1)
2253 MIPS_SYS(sys_io_getevents, 5)
2254 MIPS_SYS(sys_io_submit , 3)
2255 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2256 MIPS_SYS(sys_exit_group , 1)
2257 MIPS_SYS(sys_lookup_dcookie, 3)
2258 MIPS_SYS(sys_epoll_create, 1)
2259 MIPS_SYS(sys_epoll_ctl , 4)
2260 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2261 MIPS_SYS(sys_remap_file_pages, 5)
2262 MIPS_SYS(sys_set_tid_address, 1)
2263 MIPS_SYS(sys_restart_syscall, 0)
2264 MIPS_SYS(sys_fadvise64_64, 7)
2265 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2266 MIPS_SYS(sys_fstatfs64 , 2)
2267 MIPS_SYS(sys_timer_create, 3)
2268 MIPS_SYS(sys_timer_settime, 4)
2269 MIPS_SYS(sys_timer_gettime, 2)
2270 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2271 MIPS_SYS(sys_timer_delete, 1)
2272 MIPS_SYS(sys_clock_settime, 2)
2273 MIPS_SYS(sys_clock_gettime, 2)
2274 MIPS_SYS(sys_clock_getres, 2)
2275 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2276 MIPS_SYS(sys_tgkill , 3)
2277 MIPS_SYS(sys_utimes , 2)
2278 MIPS_SYS(sys_mbind , 4)
2279 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2280 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2281 MIPS_SYS(sys_mq_open , 4)
2282 MIPS_SYS(sys_mq_unlink , 1)
2283 MIPS_SYS(sys_mq_timedsend, 5)
2284 MIPS_SYS(sys_mq_timedreceive, 5)
2285 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2286 MIPS_SYS(sys_mq_getsetattr, 3)
2287 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2288 MIPS_SYS(sys_waitid , 4)
2289 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2290 MIPS_SYS(sys_add_key , 5)
2291 MIPS_SYS(sys_request_key, 4)
2292 MIPS_SYS(sys_keyctl , 5)
2293 MIPS_SYS(sys_set_thread_area, 1)
2294 MIPS_SYS(sys_inotify_init, 0)
2295 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2296 MIPS_SYS(sys_inotify_rm_watch, 2)
2297 MIPS_SYS(sys_migrate_pages, 4)
2298 MIPS_SYS(sys_openat, 4)
2299 MIPS_SYS(sys_mkdirat, 3)
2300 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2301 MIPS_SYS(sys_fchownat, 5)
2302 MIPS_SYS(sys_futimesat, 3)
2303 MIPS_SYS(sys_fstatat64, 4)
2304 MIPS_SYS(sys_unlinkat, 3)
2305 MIPS_SYS(sys_renameat, 4) /* 4295 */
2306 MIPS_SYS(sys_linkat, 5)
2307 MIPS_SYS(sys_symlinkat, 3)
2308 MIPS_SYS(sys_readlinkat, 4)
2309 MIPS_SYS(sys_fchmodat, 3)
2310 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2311 MIPS_SYS(sys_pselect6, 6)
2312 MIPS_SYS(sys_ppoll, 5)
2313 MIPS_SYS(sys_unshare, 1)
2314 MIPS_SYS(sys_splice, 6)
2315 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2316 MIPS_SYS(sys_tee, 4)
2317 MIPS_SYS(sys_vmsplice, 4)
2318 MIPS_SYS(sys_move_pages, 6)
2319 MIPS_SYS(sys_set_robust_list, 2)
2320 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2321 MIPS_SYS(sys_kexec_load, 4)
2322 MIPS_SYS(sys_getcpu, 3)
2323 MIPS_SYS(sys_epoll_pwait, 6)
2324 MIPS_SYS(sys_ioprio_set, 3)
2325 MIPS_SYS(sys_ioprio_get, 2)
2326 MIPS_SYS(sys_utimensat, 4)
2327 MIPS_SYS(sys_signalfd, 3)
2328 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2329 MIPS_SYS(sys_eventfd, 1)
2330 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2331 MIPS_SYS(sys_timerfd_create, 2)
2332 MIPS_SYS(sys_timerfd_gettime, 2)
2333 MIPS_SYS(sys_timerfd_settime, 4)
2334 MIPS_SYS(sys_signalfd4, 4)
2335 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2336 MIPS_SYS(sys_epoll_create1, 1)
2337 MIPS_SYS(sys_dup3, 3)
2338 MIPS_SYS(sys_pipe2, 2)
2339 MIPS_SYS(sys_inotify_init1, 1)
2340 MIPS_SYS(sys_preadv, 6) /* 4330 */
2341 MIPS_SYS(sys_pwritev, 6)
2342 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2343 MIPS_SYS(sys_perf_event_open, 5)
2344 MIPS_SYS(sys_accept4, 4)
2345 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2346 MIPS_SYS(sys_fanotify_init, 2)
2347 MIPS_SYS(sys_fanotify_mark, 6)
2348 MIPS_SYS(sys_prlimit64, 4)
2349 MIPS_SYS(sys_name_to_handle_at, 5)
2350 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2351 MIPS_SYS(sys_clock_adjtime, 2)
2352 MIPS_SYS(sys_syncfs, 1)
2353 };
2354 # undef MIPS_SYS
2355 # endif /* O32 */
2356
2357 static int do_store_exclusive(CPUMIPSState *env)
2358 {
2359 target_ulong addr;
2360 target_ulong page_addr;
2361 target_ulong val;
2362 int flags;
2363 int segv = 0;
2364 int reg;
2365 int d;
2366
2367 addr = env->lladdr;
2368 page_addr = addr & TARGET_PAGE_MASK;
2369 start_exclusive();
2370 mmap_lock();
2371 flags = page_get_flags(page_addr);
2372 if ((flags & PAGE_READ) == 0) {
2373 segv = 1;
2374 } else {
2375 reg = env->llreg & 0x1f;
2376 d = (env->llreg & 0x20) != 0;
2377 if (d) {
2378 segv = get_user_s64(val, addr);
2379 } else {
2380 segv = get_user_s32(val, addr);
2381 }
2382 if (!segv) {
2383 if (val != env->llval) {
2384 env->active_tc.gpr[reg] = 0;
2385 } else {
2386 if (d) {
2387 segv = put_user_u64(env->llnewval, addr);
2388 } else {
2389 segv = put_user_u32(env->llnewval, addr);
2390 }
2391 if (!segv) {
2392 env->active_tc.gpr[reg] = 1;
2393 }
2394 }
2395 }
2396 }
2397 env->lladdr = -1;
2398 if (!segv) {
2399 env->active_tc.PC += 4;
2400 }
2401 mmap_unlock();
2402 end_exclusive();
2403 return segv;
2404 }
2405
2406 /* Break codes */
2407 enum {
2408 BRK_OVERFLOW = 6,
2409 BRK_DIVZERO = 7
2410 };
2411
2412 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2413 unsigned int code)
2414 {
2415 int ret = -1;
2416
2417 switch (code) {
2418 case BRK_OVERFLOW:
2419 case BRK_DIVZERO:
2420 info->si_signo = TARGET_SIGFPE;
2421 info->si_errno = 0;
2422 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2423 queue_signal(env, info->si_signo, &*info);
2424 ret = 0;
2425 break;
2426 default:
2427 info->si_signo = TARGET_SIGTRAP;
2428 info->si_errno = 0;
2429 queue_signal(env, info->si_signo, &*info);
2430 ret = 0;
2431 break;
2432 }
2433
2434 return ret;
2435 }
2436
2437 void cpu_loop(CPUMIPSState *env)
2438 {
2439 CPUState *cs = CPU(mips_env_get_cpu(env));
2440 target_siginfo_t info;
2441 int trapnr;
2442 abi_long ret;
2443 # ifdef TARGET_ABI_MIPSO32
2444 unsigned int syscall_num;
2445 # endif
2446
2447 for(;;) {
2448 cpu_exec_start(cs);
2449 trapnr = cpu_mips_exec(cs);
2450 cpu_exec_end(cs);
2451 switch(trapnr) {
2452 case EXCP_SYSCALL:
2453 env->active_tc.PC += 4;
2454 # ifdef TARGET_ABI_MIPSO32
2455 syscall_num = env->active_tc.gpr[2] - 4000;
2456 if (syscall_num >= sizeof(mips_syscall_args)) {
2457 ret = -TARGET_ENOSYS;
2458 } else {
2459 int nb_args;
2460 abi_ulong sp_reg;
2461 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2462
2463 nb_args = mips_syscall_args[syscall_num];
2464 sp_reg = env->active_tc.gpr[29];
2465 switch (nb_args) {
2466 /* these arguments are taken from the stack */
2467 case 8:
2468 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2469 goto done_syscall;
2470 }
2471 case 7:
2472 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2473 goto done_syscall;
2474 }
2475 case 6:
2476 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2477 goto done_syscall;
2478 }
2479 case 5:
2480 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2481 goto done_syscall;
2482 }
2483 default:
2484 break;
2485 }
2486 ret = do_syscall(env, env->active_tc.gpr[2],
2487 env->active_tc.gpr[4],
2488 env->active_tc.gpr[5],
2489 env->active_tc.gpr[6],
2490 env->active_tc.gpr[7],
2491 arg5, arg6, arg7, arg8);
2492 }
2493 done_syscall:
2494 # else
2495 ret = do_syscall(env, env->active_tc.gpr[2],
2496 env->active_tc.gpr[4], env->active_tc.gpr[5],
2497 env->active_tc.gpr[6], env->active_tc.gpr[7],
2498 env->active_tc.gpr[8], env->active_tc.gpr[9],
2499 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2500 # endif /* O32 */
2501 if (ret == -TARGET_QEMU_ESIGRETURN) {
2502 /* Returning from a successful sigreturn syscall.
2503 Avoid clobbering register state. */
2504 break;
2505 }
2506 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2507 env->active_tc.gpr[7] = 1; /* error flag */
2508 ret = -ret;
2509 } else {
2510 env->active_tc.gpr[7] = 0; /* error flag */
2511 }
2512 env->active_tc.gpr[2] = ret;
2513 break;
2514 case EXCP_TLBL:
2515 case EXCP_TLBS:
2516 case EXCP_AdEL:
2517 case EXCP_AdES:
2518 info.si_signo = TARGET_SIGSEGV;
2519 info.si_errno = 0;
2520 /* XXX: check env->error_code */
2521 info.si_code = TARGET_SEGV_MAPERR;
2522 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2523 queue_signal(env, info.si_signo, &info);
2524 break;
2525 case EXCP_CpU:
2526 case EXCP_RI:
2527 info.si_signo = TARGET_SIGILL;
2528 info.si_errno = 0;
2529 info.si_code = 0;
2530 queue_signal(env, info.si_signo, &info);
2531 break;
2532 case EXCP_INTERRUPT:
2533 /* just indicate that signals should be handled asap */
2534 break;
2535 case EXCP_DEBUG:
2536 {
2537 int sig;
2538
2539 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2540 if (sig)
2541 {
2542 info.si_signo = sig;
2543 info.si_errno = 0;
2544 info.si_code = TARGET_TRAP_BRKPT;
2545 queue_signal(env, info.si_signo, &info);
2546 }
2547 }
2548 break;
2549 case EXCP_SC:
2550 if (do_store_exclusive(env)) {
2551 info.si_signo = TARGET_SIGSEGV;
2552 info.si_errno = 0;
2553 info.si_code = TARGET_SEGV_MAPERR;
2554 info._sifields._sigfault._addr = env->active_tc.PC;
2555 queue_signal(env, info.si_signo, &info);
2556 }
2557 break;
2558 case EXCP_DSPDIS:
2559 info.si_signo = TARGET_SIGILL;
2560 info.si_errno = 0;
2561 info.si_code = TARGET_ILL_ILLOPC;
2562 queue_signal(env, info.si_signo, &info);
2563 break;
2564 /* The code below was inspired by the MIPS Linux kernel trap
2565 * handling code in arch/mips/kernel/traps.c.
2566 */
2567 case EXCP_BREAK:
2568 {
2569 abi_ulong trap_instr;
2570 unsigned int code;
2571
2572 if (env->hflags & MIPS_HFLAG_M16) {
2573 if (env->insn_flags & ASE_MICROMIPS) {
2574 /* microMIPS mode */
2575 ret = get_user_u16(trap_instr, env->active_tc.PC);
2576 if (ret != 0) {
2577 goto error;
2578 }
2579
2580 if ((trap_instr >> 10) == 0x11) {
2581 /* 16-bit instruction */
2582 code = trap_instr & 0xf;
2583 } else {
2584 /* 32-bit instruction */
2585 abi_ulong instr_lo;
2586
2587 ret = get_user_u16(instr_lo,
2588 env->active_tc.PC + 2);
2589 if (ret != 0) {
2590 goto error;
2591 }
2592 trap_instr = (trap_instr << 16) | instr_lo;
2593 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2594 /* Unfortunately, microMIPS also suffers from
2595 the old assembler bug... */
2596 if (code >= (1 << 10)) {
2597 code >>= 10;
2598 }
2599 }
2600 } else {
2601 /* MIPS16e mode */
2602 ret = get_user_u16(trap_instr, env->active_tc.PC);
2603 if (ret != 0) {
2604 goto error;
2605 }
2606 code = (trap_instr >> 6) & 0x3f;
2607 }
2608 } else {
2609 ret = get_user_u32(trap_instr, env->active_tc.PC);
2610 if (ret != 0) {
2611 goto error;
2612 }
2613
2614 /* As described in the original Linux kernel code, the
2615 * below checks on 'code' are to work around an old
2616 * assembly bug.
2617 */
2618 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2619 if (code >= (1 << 10)) {
2620 code >>= 10;
2621 }
2622 }
2623
2624 if (do_break(env, &info, code) != 0) {
2625 goto error;
2626 }
2627 }
2628 break;
2629 case EXCP_TRAP:
2630 {
2631 abi_ulong trap_instr;
2632 unsigned int code = 0;
2633
2634 if (env->hflags & MIPS_HFLAG_M16) {
2635 /* microMIPS mode */
2636 abi_ulong instr[2];
2637
2638 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2639 get_user_u16(instr[1], env->active_tc.PC + 2);
2640
2641 trap_instr = (instr[0] << 16) | instr[1];
2642 } else {
2643 ret = get_user_u32(trap_instr, env->active_tc.PC);
2644 }
2645
2646 if (ret != 0) {
2647 goto error;
2648 }
2649
2650 /* The immediate versions don't provide a code. */
2651 if (!(trap_instr & 0xFC000000)) {
2652 if (env->hflags & MIPS_HFLAG_M16) {
2653 /* microMIPS mode */
2654 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2655 } else {
2656 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2657 }
2658 }
2659
2660 if (do_break(env, &info, code) != 0) {
2661 goto error;
2662 }
2663 }
2664 break;
2665 default:
2666 error:
2667 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2668 abort();
2669 }
2670 process_pending_signals(env);
2671 }
2672 }
2673 #endif
2674
2675 #ifdef TARGET_OPENRISC
2676
2677 void cpu_loop(CPUOpenRISCState *env)
2678 {
2679 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2680 int trapnr, gdbsig;
2681
2682 for (;;) {
2683 cpu_exec_start(cs);
2684 trapnr = cpu_openrisc_exec(cs);
2685 cpu_exec_end(cs);
2686 gdbsig = 0;
2687
2688 switch (trapnr) {
2689 case EXCP_RESET:
2690 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2691 exit(EXIT_FAILURE);
2692 break;
2693 case EXCP_BUSERR:
2694 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2695 gdbsig = TARGET_SIGBUS;
2696 break;
2697 case EXCP_DPF:
2698 case EXCP_IPF:
2699 cpu_dump_state(cs, stderr, fprintf, 0);
2700 gdbsig = TARGET_SIGSEGV;
2701 break;
2702 case EXCP_TICK:
2703 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2704 break;
2705 case EXCP_ALIGN:
2706 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2707 gdbsig = TARGET_SIGBUS;
2708 break;
2709 case EXCP_ILLEGAL:
2710 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2711 gdbsig = TARGET_SIGILL;
2712 break;
2713 case EXCP_INT:
2714 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2715 break;
2716 case EXCP_DTLBMISS:
2717 case EXCP_ITLBMISS:
2718 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2719 break;
2720 case EXCP_RANGE:
2721 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2722 gdbsig = TARGET_SIGSEGV;
2723 break;
2724 case EXCP_SYSCALL:
2725 env->pc += 4; /* 0xc00; */
2726 env->gpr[11] = do_syscall(env,
2727 env->gpr[11], /* return value */
2728 env->gpr[3], /* r3 - r7 are params */
2729 env->gpr[4],
2730 env->gpr[5],
2731 env->gpr[6],
2732 env->gpr[7],
2733 env->gpr[8], 0, 0);
2734 break;
2735 case EXCP_FPE:
2736 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2737 break;
2738 case EXCP_TRAP:
2739 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2740 gdbsig = TARGET_SIGTRAP;
2741 break;
2742 case EXCP_NR:
2743 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2744 break;
2745 default:
2746 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2747 trapnr);
2748 gdbsig = TARGET_SIGILL;
2749 break;
2750 }
2751 if (gdbsig) {
2752 gdb_handlesig(cs, gdbsig);
2753 if (gdbsig != TARGET_SIGTRAP) {
2754 exit(EXIT_FAILURE);
2755 }
2756 }
2757
2758 process_pending_signals(env);
2759 }
2760 }
2761
2762 #endif /* TARGET_OPENRISC */
2763
2764 #ifdef TARGET_SH4
2765 void cpu_loop(CPUSH4State *env)
2766 {
2767 CPUState *cs = CPU(sh_env_get_cpu(env));
2768 int trapnr, ret;
2769 target_siginfo_t info;
2770
2771 while (1) {
2772 cpu_exec_start(cs);
2773 trapnr = cpu_sh4_exec(cs);
2774 cpu_exec_end(cs);
2775
2776 switch (trapnr) {
2777 case 0x160:
2778 env->pc += 2;
2779 ret = do_syscall(env,
2780 env->gregs[3],
2781 env->gregs[4],
2782 env->gregs[5],
2783 env->gregs[6],
2784 env->gregs[7],
2785 env->gregs[0],
2786 env->gregs[1],
2787 0, 0);
2788 env->gregs[0] = ret;
2789 break;
2790 case EXCP_INTERRUPT:
2791 /* just indicate that signals should be handled asap */
2792 break;
2793 case EXCP_DEBUG:
2794 {
2795 int sig;
2796
2797 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2798 if (sig)
2799 {
2800 info.si_signo = sig;
2801 info.si_errno = 0;
2802 info.si_code = TARGET_TRAP_BRKPT;
2803 queue_signal(env, info.si_signo, &info);
2804 }
2805 }
2806 break;
2807 case 0xa0:
2808 case 0xc0:
2809 info.si_signo = TARGET_SIGSEGV;
2810 info.si_errno = 0;
2811 info.si_code = TARGET_SEGV_MAPERR;
2812 info._sifields._sigfault._addr = env->tea;
2813 queue_signal(env, info.si_signo, &info);
2814 break;
2815
2816 default:
2817 printf ("Unhandled trap: 0x%x\n", trapnr);
2818 cpu_dump_state(cs, stderr, fprintf, 0);
2819 exit(EXIT_FAILURE);
2820 }
2821 process_pending_signals (env);
2822 }
2823 }
2824 #endif
2825
2826 #ifdef TARGET_CRIS
2827 void cpu_loop(CPUCRISState *env)
2828 {
2829 CPUState *cs = CPU(cris_env_get_cpu(env));
2830 int trapnr, ret;
2831 target_siginfo_t info;
2832
2833 while (1) {
2834 cpu_exec_start(cs);
2835 trapnr = cpu_cris_exec(cs);
2836 cpu_exec_end(cs);
2837 switch (trapnr) {
2838 case 0xaa:
2839 {
2840 info.si_signo = TARGET_SIGSEGV;
2841 info.si_errno = 0;
2842 /* XXX: check env->error_code */
2843 info.si_code = TARGET_SEGV_MAPERR;
2844 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2845 queue_signal(env, info.si_signo, &info);
2846 }
2847 break;
2848 case EXCP_INTERRUPT:
2849 /* just indicate that signals should be handled asap */
2850 break;
2851 case EXCP_BREAK:
2852 ret = do_syscall(env,
2853 env->regs[9],
2854 env->regs[10],
2855 env->regs[11],
2856 env->regs[12],
2857 env->regs[13],
2858 env->pregs[7],
2859 env->pregs[11],
2860 0, 0);
2861 env->regs[10] = ret;
2862 break;
2863 case EXCP_DEBUG:
2864 {
2865 int sig;
2866
2867 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2868 if (sig)
2869 {
2870 info.si_signo = sig;
2871 info.si_errno = 0;
2872 info.si_code = TARGET_TRAP_BRKPT;
2873 queue_signal(env, info.si_signo, &info);
2874 }
2875 }
2876 break;
2877 default:
2878 printf ("Unhandled trap: 0x%x\n", trapnr);
2879 cpu_dump_state(cs, stderr, fprintf, 0);
2880 exit(EXIT_FAILURE);
2881 }
2882 process_pending_signals (env);
2883 }
2884 }
2885 #endif
2886
2887 #ifdef TARGET_MICROBLAZE
2888 void cpu_loop(CPUMBState *env)
2889 {
2890 CPUState *cs = CPU(mb_env_get_cpu(env));
2891 int trapnr, ret;
2892 target_siginfo_t info;
2893
2894 while (1) {
2895 cpu_exec_start(cs);
2896 trapnr = cpu_mb_exec(cs);
2897 cpu_exec_end(cs);
2898 switch (trapnr) {
2899 case 0xaa:
2900 {
2901 info.si_signo = TARGET_SIGSEGV;
2902 info.si_errno = 0;
2903 /* XXX: check env->error_code */
2904 info.si_code = TARGET_SEGV_MAPERR;
2905 info._sifields._sigfault._addr = 0;
2906 queue_signal(env, info.si_signo, &info);
2907 }
2908 break;
2909 case EXCP_INTERRUPT:
2910 /* just indicate that signals should be handled asap */
2911 break;
2912 case EXCP_BREAK:
2913 /* Return address is 4 bytes after the call. */
2914 env->regs[14] += 4;
2915 env->sregs[SR_PC] = env->regs[14];
2916 ret = do_syscall(env,
2917 env->regs[12],
2918 env->regs[5],
2919 env->regs[6],
2920 env->regs[7],
2921 env->regs[8],
2922 env->regs[9],
2923 env->regs[10],
2924 0, 0);
2925 env->regs[3] = ret;
2926 break;
2927 case EXCP_HW_EXCP:
2928 env->regs[17] = env->sregs[SR_PC] + 4;
2929 if (env->iflags & D_FLAG) {
2930 env->sregs[SR_ESR] |= 1 << 12;
2931 env->sregs[SR_PC] -= 4;
2932 /* FIXME: if branch was immed, replay the imm as well. */
2933 }
2934
2935 env->iflags &= ~(IMM_FLAG | D_FLAG);
2936
2937 switch (env->sregs[SR_ESR] & 31) {
2938 case ESR_EC_DIVZERO:
2939 info.si_signo = TARGET_SIGFPE;
2940 info.si_errno = 0;
2941 info.si_code = TARGET_FPE_FLTDIV;
2942 info._sifields._sigfault._addr = 0;
2943 queue_signal(env, info.si_signo, &info);
2944 break;
2945 case ESR_EC_FPU:
2946 info.si_signo = TARGET_SIGFPE;
2947 info.si_errno = 0;
2948 if (env->sregs[SR_FSR] & FSR_IO) {
2949 info.si_code = TARGET_FPE_FLTINV;
2950 }
2951 if (env->sregs[SR_FSR] & FSR_DZ) {
2952 info.si_code = TARGET_FPE_FLTDIV;
2953 }
2954 info._sifields._sigfault._addr = 0;
2955 queue_signal(env, info.si_signo, &info);
2956 break;
2957 default:
2958 printf ("Unhandled hw-exception: 0x%x\n",
2959 env->sregs[SR_ESR] & ESR_EC_MASK);
2960 cpu_dump_state(cs, stderr, fprintf, 0);
2961 exit(EXIT_FAILURE);
2962 break;
2963 }
2964 break;
2965 case EXCP_DEBUG:
2966 {
2967 int sig;
2968
2969 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2970 if (sig)
2971 {
2972 info.si_signo = sig;
2973 info.si_errno = 0;
2974 info.si_code = TARGET_TRAP_BRKPT;
2975 queue_signal(env, info.si_signo, &info);
2976 }
2977 }
2978 break;
2979 default:
2980 printf ("Unhandled trap: 0x%x\n", trapnr);
2981 cpu_dump_state(cs, stderr, fprintf, 0);
2982 exit(EXIT_FAILURE);
2983 }
2984 process_pending_signals (env);
2985 }
2986 }
2987 #endif
2988
2989 #ifdef TARGET_M68K
2990
2991 void cpu_loop(CPUM68KState *env)
2992 {
2993 CPUState *cs = CPU(m68k_env_get_cpu(env));
2994 int trapnr;
2995 unsigned int n;
2996 target_siginfo_t info;
2997 TaskState *ts = cs->opaque;
2998
2999 for(;;) {
3000 cpu_exec_start(cs);
3001 trapnr = cpu_m68k_exec(cs);
3002 cpu_exec_end(cs);
3003 switch(trapnr) {
3004 case EXCP_ILLEGAL:
3005 {
3006 if (ts->sim_syscalls) {
3007 uint16_t nr;
3008 get_user_u16(nr, env->pc + 2);
3009 env->pc += 4;
3010 do_m68k_simcall(env, nr);
3011 } else {
3012 goto do_sigill;
3013 }
3014 }
3015 break;
3016 case EXCP_HALT_INSN:
3017 /* Semihosing syscall. */
3018 env->pc += 4;
3019 do_m68k_semihosting(env, env->dregs[0]);
3020 break;
3021 case EXCP_LINEA:
3022 case EXCP_LINEF:
3023 case EXCP_UNSUPPORTED:
3024 do_sigill:
3025 info.si_signo = TARGET_SIGILL;
3026 info.si_errno = 0;
3027 info.si_code = TARGET_ILL_ILLOPN;
3028 info._sifields._sigfault._addr = env->pc;
3029 queue_signal(env, info.si_signo, &info);
3030 break;
3031 case EXCP_TRAP0:
3032 {
3033 ts->sim_syscalls = 0;
3034 n = env->dregs[0];
3035 env->pc += 2;
3036 env->dregs[0] = do_syscall(env,
3037 n,
3038 env->dregs[1],
3039 env->dregs[2],
3040 env->dregs[3],
3041 env->dregs[4],
3042 env->dregs[5],
3043 env->aregs[0],
3044 0, 0);
3045 }
3046 break;
3047 case EXCP_INTERRUPT:
3048 /* just indicate that signals should be handled asap */
3049 break;
3050 case EXCP_ACCESS:
3051 {
3052 info.si_signo = TARGET_SIGSEGV;
3053 info.si_errno = 0;
3054 /* XXX: check env->error_code */
3055 info.si_code = TARGET_SEGV_MAPERR;
3056 info._sifields._sigfault._addr = env->mmu.ar;
3057 queue_signal(env, info.si_signo, &info);
3058 }
3059 break;
3060 case EXCP_DEBUG:
3061 {
3062 int sig;
3063
3064 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3065 if (sig)
3066 {
3067 info.si_signo = sig;
3068 info.si_errno = 0;
3069 info.si_code = TARGET_TRAP_BRKPT;
3070 queue_signal(env, info.si_signo, &info);
3071 }
3072 }
3073 break;
3074 default:
3075 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3076 abort();
3077 }
3078 process_pending_signals(env);
3079 }
3080 }
3081 #endif /* TARGET_M68K */
3082
3083 #ifdef TARGET_ALPHA
3084 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3085 {
3086 target_ulong addr, val, tmp;
3087 target_siginfo_t info;
3088 int ret = 0;
3089
3090 addr = env->lock_addr;
3091 tmp = env->lock_st_addr;
3092 env->lock_addr = -1;
3093 env->lock_st_addr = 0;
3094
3095 start_exclusive();
3096 mmap_lock();
3097
3098 if (addr == tmp) {
3099 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3100 goto do_sigsegv;
3101 }
3102
3103 if (val == env->lock_value) {
3104 tmp = env->ir[reg];
3105 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3106 goto do_sigsegv;
3107 }
3108 ret = 1;
3109 }
3110 }
3111 env->ir[reg] = ret;
3112 env->pc += 4;
3113
3114 mmap_unlock();
3115 end_exclusive();
3116 return;
3117
3118 do_sigsegv:
3119 mmap_unlock();
3120 end_exclusive();
3121
3122 info.si_signo = TARGET_SIGSEGV;
3123 info.si_errno = 0;
3124 info.si_code = TARGET_SEGV_MAPERR;
3125 info._sifields._sigfault._addr = addr;
3126 queue_signal(env, TARGET_SIGSEGV, &info);
3127 }
3128
3129 void cpu_loop(CPUAlphaState *env)
3130 {
3131 CPUState *cs = CPU(alpha_env_get_cpu(env));
3132 int trapnr;
3133 target_siginfo_t info;
3134 abi_long sysret;
3135
3136 while (1) {
3137 cpu_exec_start(cs);
3138 trapnr = cpu_alpha_exec(cs);
3139 cpu_exec_end(cs);
3140
3141 /* All of the traps imply a transition through PALcode, which
3142 implies an REI instruction has been executed. Which means
3143 that the intr_flag should be cleared. */
3144 env->intr_flag = 0;
3145
3146 switch (trapnr) {
3147 case EXCP_RESET:
3148 fprintf(stderr, "Reset requested. Exit\n");
3149 exit(EXIT_FAILURE);
3150 break;
3151 case EXCP_MCHK:
3152 fprintf(stderr, "Machine check exception. Exit\n");
3153 exit(EXIT_FAILURE);
3154 break;
3155 case EXCP_SMP_INTERRUPT:
3156 case EXCP_CLK_INTERRUPT:
3157 case EXCP_DEV_INTERRUPT:
3158 fprintf(stderr, "External interrupt. Exit\n");
3159 exit(EXIT_FAILURE);
3160 break;
3161 case EXCP_MMFAULT:
3162 env->lock_addr = -1;
3163 info.si_signo = TARGET_SIGSEGV;
3164 info.si_errno = 0;
3165 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3166 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3167 info._sifields._sigfault._addr = env->trap_arg0;
3168 queue_signal(env, info.si_signo, &info);
3169 break;
3170 case EXCP_UNALIGN:
3171 env->lock_addr = -1;
3172 info.si_signo = TARGET_SIGBUS;
3173 info.si_errno = 0;
3174 info.si_code = TARGET_BUS_ADRALN;
3175 info._sifields._sigfault._addr = env->trap_arg0;
3176 queue_signal(env, info.si_signo, &info);
3177 break;
3178 case EXCP_OPCDEC:
3179 do_sigill:
3180 env->lock_addr = -1;
3181 info.si_signo = TARGET_SIGILL;
3182 info.si_errno = 0;
3183 info.si_code = TARGET_ILL_ILLOPC;
3184 info._sifields._sigfault._addr = env->pc;
3185 queue_signal(env, info.si_signo, &info);
3186 break;
3187 case EXCP_ARITH:
3188 env->lock_addr = -1;
3189 info.si_signo = TARGET_SIGFPE;
3190 info.si_errno = 0;
3191 info.si_code = TARGET_FPE_FLTINV;
3192 info._sifields._sigfault._addr = env->pc;
3193 queue_signal(env, info.si_signo, &info);
3194 break;
3195 case EXCP_FEN:
3196 /* No-op. Linux simply re-enables the FPU. */
3197 break;
3198 case EXCP_CALL_PAL:
3199 env->lock_addr = -1;
3200 switch (env->error_code) {
3201 case 0x80:
3202 /* BPT */
3203 info.si_signo = TARGET_SIGTRAP;
3204 info.si_errno = 0;
3205 info.si_code = TARGET_TRAP_BRKPT;
3206 info._sifields._sigfault._addr = env->pc;
3207 queue_signal(env, info.si_signo, &info);
3208 break;
3209 case 0x81:
3210 /* BUGCHK */
3211 info.si_signo = TARGET_SIGTRAP;
3212 info.si_errno = 0;
3213 info.si_code = 0;
3214 info._sifields._sigfault._addr = env->pc;
3215 queue_signal(env, info.si_signo, &info);
3216 break;
3217 case 0x83:
3218 /* CALLSYS */
3219 trapnr = env->ir[IR_V0];
3220 sysret = do_syscall(env, trapnr,
3221 env->ir[IR_A0], env->ir[IR_A1],
3222 env->ir[IR_A2], env->ir[IR_A3],
3223 env->ir[IR_A4], env->ir[IR_A5],
3224 0, 0);
3225 if (trapnr == TARGET_NR_sigreturn
3226 || trapnr == TARGET_NR_rt_sigreturn) {
3227 break;
3228 }
3229 /* Syscall writes 0 to V0 to bypass error check, similar
3230 to how this is handled internal to Linux kernel.
3231 (Ab)use trapnr temporarily as boolean indicating error. */
3232 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3233 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3234 env->ir[IR_A3] = trapnr;
3235 break;
3236 case 0x86:
3237 /* IMB */
3238 /* ??? We can probably elide the code using page_unprotect
3239 that is checking for self-modifying code. Instead we
3240 could simply call tb_flush here. Until we work out the
3241 changes required to turn off the extra write protection,
3242 this can be a no-op. */
3243 break;
3244 case 0x9E:
3245 /* RDUNIQUE */
3246 /* Handled in the translator for usermode. */
3247 abort();
3248 case 0x9F:
3249 /* WRUNIQUE */
3250 /* Handled in the translator for usermode. */
3251 abort();
3252 case 0xAA:
3253 /* GENTRAP */
3254 info.si_signo = TARGET_SIGFPE;
3255 switch (env->ir[IR_A0]) {
3256 case TARGET_GEN_INTOVF:
3257 info.si_code = TARGET_FPE_INTOVF;
3258 break;
3259 case TARGET_GEN_INTDIV:
3260 info.si_code = TARGET_FPE_INTDIV;
3261 break;
3262 case TARGET_GEN_FLTOVF:
3263 info.si_code = TARGET_FPE_FLTOVF;
3264 break;
3265 case TARGET_GEN_FLTUND:
3266 info.si_code = TARGET_FPE_FLTUND;
3267 break;
3268 case TARGET_GEN_FLTINV:
3269 info.si_code = TARGET_FPE_FLTINV;
3270 break;
3271 case TARGET_GEN_FLTINE:
3272 info.si_code = TARGET_FPE_FLTRES;
3273 break;
3274 case TARGET_GEN_ROPRAND:
3275 info.si_code = 0;
3276 break;
3277 default:
3278 info.si_signo = TARGET_SIGTRAP;
3279 info.si_code = 0;
3280 break;
3281 }
3282 info.si_errno = 0;
3283 info._sifields._sigfault._addr = env->pc;
3284 queue_signal(env, info.si_signo, &info);
3285 break;
3286 default:
3287 goto do_sigill;
3288 }
3289 break;
3290 case EXCP_DEBUG:
3291 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3292 if (info.si_signo) {
3293 env->lock_addr = -1;
3294 info.si_errno = 0;
3295 info.si_code = TARGET_TRAP_BRKPT;
3296 queue_signal(env, info.si_signo, &info);
3297 }
3298 break;
3299 case EXCP_STL_C:
3300 case EXCP_STQ_C:
3301 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3302 break;
3303 case EXCP_INTERRUPT:
3304 /* Just indicate that signals should be handled asap. */
3305 break;
3306 default:
3307 printf ("Unhandled trap: 0x%x\n", trapnr);
3308 cpu_dump_state(cs, stderr, fprintf, 0);
3309 exit(EXIT_FAILURE);
3310 }
3311 process_pending_signals (env);
3312 }
3313 }
3314 #endif /* TARGET_ALPHA */
3315
3316 #ifdef TARGET_S390X
3317 void cpu_loop(CPUS390XState *env)
3318 {
3319 CPUState *cs = CPU(s390_env_get_cpu(env));
3320 int trapnr, n, sig;
3321 target_siginfo_t info;
3322 target_ulong addr;
3323
3324 while (1) {
3325 cpu_exec_start(cs);
3326 trapnr = cpu_s390x_exec(cs);
3327 cpu_exec_end(cs);
3328 switch (trapnr) {
3329 case EXCP_INTERRUPT:
3330 /* Just indicate that signals should be handled asap. */
3331 break;
3332
3333 case EXCP_SVC:
3334 n = env->int_svc_code;
3335 if (!n) {
3336 /* syscalls > 255 */
3337 n = env->regs[1];
3338 }
3339 env->psw.addr += env->int_svc_ilen;
3340 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3341 env->regs[4], env->regs[5],
3342 env->regs[6], env->regs[7], 0, 0);
3343 break;
3344
3345 case EXCP_DEBUG:
3346 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3347 if (sig) {
3348 n = TARGET_TRAP_BRKPT;
3349 goto do_signal_pc;
3350 }
3351 break;
3352 case EXCP_PGM:
3353 n = env->int_pgm_code;
3354 switch (n) {
3355 case PGM_OPERATION:
3356 case PGM_PRIVILEGED:
3357 sig = TARGET_SIGILL;
3358 n = TARGET_ILL_ILLOPC;
3359 goto do_signal_pc;
3360 case PGM_PROTECTION:
3361 case PGM_ADDRESSING:
3362 sig = TARGET_SIGSEGV;
3363 /* XXX: check env->error_code */
3364 n = TARGET_SEGV_MAPERR;
3365 addr = env->__excp_addr;
3366 goto do_signal;
3367 case PGM_EXECUTE:
3368 case PGM_SPECIFICATION:
3369 case PGM_SPECIAL_OP:
3370 case PGM_OPERAND:
3371 do_sigill_opn:
3372 sig = TARGET_SIGILL;
3373 n = TARGET_ILL_ILLOPN;
3374 goto do_signal_pc;
3375
3376 case PGM_FIXPT_OVERFLOW:
3377 sig = TARGET_SIGFPE;
3378 n = TARGET_FPE_INTOVF;
3379 goto do_signal_pc;
3380 case PGM_FIXPT_DIVIDE:
3381 sig = TARGET_SIGFPE;
3382 n = TARGET_FPE_INTDIV;
3383 goto do_signal_pc;
3384
3385 case PGM_DATA:
3386 n = (env->fpc >> 8) & 0xff;
3387 if (n == 0xff) {
3388 /* compare-and-trap */
3389 goto do_sigill_opn;
3390 } else {
3391 /* An IEEE exception, simulated or otherwise. */
3392 if (n & 0x80) {
3393 n = TARGET_FPE_FLTINV;
3394 } else if (n & 0x40) {
3395 n = TARGET_FPE_FLTDIV;
3396 } else if (n & 0x20) {
3397 n = TARGET_FPE_FLTOVF;
3398 } else if (n & 0x10) {
3399 n = TARGET_FPE_FLTUND;
3400 } else if (n & 0x08) {
3401 n = TARGET_FPE_FLTRES;
3402 } else {
3403 /* ??? Quantum exception; BFP, DFP error. */
3404 goto do_sigill_opn;
3405 }
3406 sig = TARGET_SIGFPE;
3407 goto do_signal_pc;
3408 }
3409
3410 default:
3411 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3412 cpu_dump_state(cs, stderr, fprintf, 0);
3413 exit(EXIT_FAILURE);
3414 }
3415 break;
3416
3417 do_signal_pc:
3418 addr = env->psw.addr;
3419 do_signal:
3420 info.si_signo = sig;
3421 info.si_errno = 0;
3422 info.si_code = n;
3423 info._sifields._sigfault._addr = addr;
3424 queue_signal(env, info.si_signo, &info);
3425 break;
3426
3427 default:
3428 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3429 cpu_dump_state(cs, stderr, fprintf, 0);
3430 exit(EXIT_FAILURE);
3431 }
3432 process_pending_signals (env);
3433 }
3434 }
3435
3436 #endif /* TARGET_S390X */
3437
3438 #ifdef TARGET_TILEGX
3439
3440 static void gen_sigill_reg(CPUTLGState *env)
3441 {
3442 target_siginfo_t info;
3443
3444 info.si_signo = TARGET_SIGILL;
3445 info.si_errno = 0;
3446 info.si_code = TARGET_ILL_PRVREG;
3447 info._sifields._sigfault._addr = env->pc;
3448 queue_signal(env, info.si_signo, &info);
3449 }
3450
3451 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3452 {
3453 target_siginfo_t info;
3454
3455 info.si_signo = signo;
3456 info.si_errno = 0;
3457 info._sifields._sigfault._addr = env->pc;
3458
3459 if (signo == TARGET_SIGSEGV) {
3460 /* The passed in sigcode is a dummy; check for a page mapping
3461 and pass either MAPERR or ACCERR. */
3462 target_ulong addr = env->excaddr;
3463 info._sifields._sigfault._addr = addr;
3464 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3465 sigcode = TARGET_SEGV_MAPERR;
3466 } else {
3467 sigcode = TARGET_SEGV_ACCERR;
3468 }
3469 }
3470 info.si_code = sigcode;
3471
3472 queue_signal(env, info.si_signo, &info);
3473 }
3474
3475 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3476 {
3477 env->excaddr = addr;
3478 do_signal(env, TARGET_SIGSEGV, 0);
3479 }
3480
3481 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3482 {
3483 if (unlikely(reg >= TILEGX_R_COUNT)) {
3484 switch (reg) {
3485 case TILEGX_R_SN:
3486 case TILEGX_R_ZERO:
3487 return;
3488 case TILEGX_R_IDN0:
3489 case TILEGX_R_IDN1:
3490 case TILEGX_R_UDN0:
3491 case TILEGX_R_UDN1:
3492 case TILEGX_R_UDN2:
3493 case TILEGX_R_UDN3:
3494 gen_sigill_reg(env);
3495 return;
3496 default:
3497 g_assert_not_reached();
3498 }
3499 }
3500 env->regs[reg] = val;
3501 }
3502
3503 /*
3504 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3505 * memory at the address held in the first source register. If the values are
3506 * not equal, then no memory operation is performed. If the values are equal,
3507 * the 8-byte quantity from the second source register is written into memory
3508 * at the address held in the first source register. In either case, the result
3509 * of the instruction is the value read from memory. The compare and write to
3510 * memory are atomic and thus can be used for synchronization purposes. This
3511 * instruction only operates for addresses aligned to a 8-byte boundary.
3512 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3513 *
3514 * Functional Description (64-bit)
3515 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3516 * rf[Dest] = memVal;
3517 * if (memVal == SPR[CmpValueSPR])
3518 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3519 *
3520 * Functional Description (32-bit)
3521 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3522 * rf[Dest] = memVal;
3523 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3524 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3525 *
3526 *
3527 * This function also processes exch and exch4 which need not process SPR.
3528 */
3529 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3530 {
3531 target_ulong addr;
3532 target_long val, sprval;
3533
3534 start_exclusive();
3535
3536 addr = env->atomic_srca;
3537 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3538 goto sigsegv_maperr;
3539 }
3540
3541 if (cmp) {
3542 if (quad) {
3543 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3544 } else {
3545 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3546 }
3547 }
3548
3549 if (!cmp || val == sprval) {
3550 target_long valb = env->atomic_srcb;
3551 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3552 goto sigsegv_maperr;
3553 }
3554 }
3555
3556 set_regval(env, env->atomic_dstr, val);
3557 end_exclusive();
3558 return;
3559
3560 sigsegv_maperr:
3561 end_exclusive();
3562 gen_sigsegv_maperr(env, addr);
3563 }
3564
3565 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3566 {
3567 int8_t write = 1;
3568 target_ulong addr;
3569 target_long val, valb;
3570
3571 start_exclusive();
3572
3573 addr = env->atomic_srca;
3574 valb = env->atomic_srcb;
3575 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3576 goto sigsegv_maperr;
3577 }
3578
3579 switch (trapnr) {
3580 case TILEGX_EXCP_OPCODE_FETCHADD:
3581 case TILEGX_EXCP_OPCODE_FETCHADD4:
3582 valb += val;
3583 break;
3584 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3585 valb += val;
3586 if (valb < 0) {
3587 write = 0;
3588 }
3589 break;
3590 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3591 valb += val;
3592 if ((int32_t)valb < 0) {
3593 write = 0;
3594 }
3595 break;
3596 case TILEGX_EXCP_OPCODE_FETCHAND:
3597 case TILEGX_EXCP_OPCODE_FETCHAND4:
3598 valb &= val;
3599 break;
3600 case TILEGX_EXCP_OPCODE_FETCHOR:
3601 case TILEGX_EXCP_OPCODE_FETCHOR4:
3602 valb |= val;
3603 break;
3604 default:
3605 g_assert_not_reached();
3606 }
3607
3608 if (write) {
3609 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3610 goto sigsegv_maperr;
3611 }
3612 }
3613
3614 set_regval(env, env->atomic_dstr, val);
3615 end_exclusive();
3616 return;
3617
3618 sigsegv_maperr:
3619 end_exclusive();
3620 gen_sigsegv_maperr(env, addr);
3621 }
3622
3623 void cpu_loop(CPUTLGState *env)
3624 {
3625 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3626 int trapnr;
3627
3628 while (1) {
3629 cpu_exec_start(cs);
3630 trapnr = cpu_tilegx_exec(cs);
3631 cpu_exec_end(cs);
3632 switch (trapnr) {
3633 case TILEGX_EXCP_SYSCALL:
3634 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3635 env->regs[0], env->regs[1],
3636 env->regs[2], env->regs[3],
3637 env->regs[4], env->regs[5],
3638 env->regs[6], env->regs[7]);
3639 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3640 ? - env->regs[TILEGX_R_RE]
3641 : 0;
3642 break;
3643 case TILEGX_EXCP_OPCODE_EXCH:
3644 do_exch(env, true, false);
3645 break;
3646 case TILEGX_EXCP_OPCODE_EXCH4:
3647 do_exch(env, false, false);
3648 break;
3649 case TILEGX_EXCP_OPCODE_CMPEXCH:
3650 do_exch(env, true, true);
3651 break;
3652 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3653 do_exch(env, false, true);
3654 break;
3655 case TILEGX_EXCP_OPCODE_FETCHADD:
3656 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3657 case TILEGX_EXCP_OPCODE_FETCHAND:
3658 case TILEGX_EXCP_OPCODE_FETCHOR:
3659 do_fetch(env, trapnr, true);
3660 break;
3661 case TILEGX_EXCP_OPCODE_FETCHADD4:
3662 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3663 case TILEGX_EXCP_OPCODE_FETCHAND4:
3664 case TILEGX_EXCP_OPCODE_FETCHOR4:
3665 do_fetch(env, trapnr, false);
3666 break;
3667 case TILEGX_EXCP_SIGNAL:
3668 do_signal(env, env->signo, env->sigcode);
3669 break;
3670 case TILEGX_EXCP_REG_IDN_ACCESS:
3671 case TILEGX_EXCP_REG_UDN_ACCESS:
3672 gen_sigill_reg(env);
3673 break;
3674 default:
3675 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3676 g_assert_not_reached();
3677 }
3678 process_pending_signals(env);
3679 }
3680 }
3681
3682 #endif
3683
3684 THREAD CPUState *thread_cpu;
3685
3686 void task_settid(TaskState *ts)
3687 {
3688 if (ts->ts_tid == 0) {
3689 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3690 }
3691 }
3692
3693 void stop_all_tasks(void)
3694 {
3695 /*
3696 * We trust that when using NPTL, start_exclusive()
3697 * handles thread stopping correctly.
3698 */
3699 start_exclusive();
3700 }
3701
3702 /* Assumes contents are already zeroed. */
3703 void init_task_state(TaskState *ts)
3704 {
3705 int i;
3706
3707 ts->used = 1;
3708 ts->first_free = ts->sigqueue_table;
3709 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3710 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3711 }
3712 ts->sigqueue_table[i].next = NULL;
3713 }
3714
3715 CPUArchState *cpu_copy(CPUArchState *env)
3716 {
3717 CPUState *cpu = ENV_GET_CPU(env);
3718 CPUState *new_cpu = cpu_init(cpu_model);
3719 CPUArchState *new_env = new_cpu->env_ptr;
3720 CPUBreakpoint *bp;
3721 CPUWatchpoint *wp;
3722
3723 /* Reset non arch specific state */
3724 cpu_reset(new_cpu);
3725
3726 memcpy(new_env, env, sizeof(CPUArchState));
3727
3728 /* Clone all break/watchpoints.
3729 Note: Once we support ptrace with hw-debug register access, make sure
3730 BP_CPU break/watchpoints are handled correctly on clone. */
3731 QTAILQ_INIT(&new_cpu->breakpoints);
3732 QTAILQ_INIT(&new_cpu->watchpoints);
3733 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3734 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3735 }
3736 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3737 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3738 }
3739
3740 return new_env;
3741 }
3742
3743 static void handle_arg_help(const char *arg)
3744 {
3745 usage(EXIT_SUCCESS);
3746 }
3747
3748 static void handle_arg_log(const char *arg)
3749 {
3750 int mask;
3751
3752 mask = qemu_str_to_log_mask(arg);
3753 if (!mask) {
3754 qemu_print_log_usage(stdout);
3755 exit(EXIT_FAILURE);
3756 }
3757 qemu_set_log(mask);
3758 }
3759
3760 static void handle_arg_log_filename(const char *arg)
3761 {
3762 qemu_set_log_filename(arg);
3763 }
3764
3765 static void handle_arg_set_env(const char *arg)
3766 {
3767 char *r, *p, *token;
3768 r = p = strdup(arg);
3769 while ((token = strsep(&p, ",")) != NULL) {
3770 if (envlist_setenv(envlist, token) != 0) {
3771 usage(EXIT_FAILURE);
3772 }
3773 }
3774 free(r);
3775 }
3776
3777 static void handle_arg_unset_env(const char *arg)
3778 {
3779 char *r, *p, *token;
3780 r = p = strdup(arg);
3781 while ((token = strsep(&p, ",")) != NULL) {
3782 if (envlist_unsetenv(envlist, token) != 0) {
3783 usage(EXIT_FAILURE);
3784 }
3785 }
3786 free(r);
3787 }
3788
3789 static void handle_arg_argv0(const char *arg)
3790 {
3791 argv0 = strdup(arg);
3792 }
3793
3794 static void handle_arg_stack_size(const char *arg)
3795 {
3796 char *p;
3797 guest_stack_size = strtoul(arg, &p, 0);
3798 if (guest_stack_size == 0) {
3799 usage(EXIT_FAILURE);
3800 }
3801
3802 if (*p == 'M') {
3803 guest_stack_size *= 1024 * 1024;
3804 } else if (*p == 'k' || *p == 'K') {
3805 guest_stack_size *= 1024;
3806 }
3807 }
3808
3809 static void handle_arg_ld_prefix(const char *arg)
3810 {
3811 interp_prefix = strdup(arg);
3812 }
3813
3814 static void handle_arg_pagesize(const char *arg)
3815 {
3816 qemu_host_page_size = atoi(arg);
3817 if (qemu_host_page_size == 0 ||
3818 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3819 fprintf(stderr, "page size must be a power of two\n");
3820 exit(EXIT_FAILURE);
3821 }
3822 }
3823
3824 static void handle_arg_randseed(const char *arg)
3825 {
3826 unsigned long long seed;
3827
3828 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3829 fprintf(stderr, "Invalid seed number: %s\n", arg);
3830 exit(EXIT_FAILURE);
3831 }
3832 srand(seed);
3833 }
3834
3835 static void handle_arg_gdb(const char *arg)
3836 {
3837 gdbstub_port = atoi(arg);
3838 }
3839
3840 static void handle_arg_uname(const char *arg)
3841 {
3842 qemu_uname_release = strdup(arg);
3843 }
3844
3845 static void handle_arg_cpu(const char *arg)
3846 {
3847 cpu_model = strdup(arg);
3848 if (cpu_model == NULL || is_help_option(cpu_model)) {
3849 /* XXX: implement xxx_cpu_list for targets that still miss it */
3850 #if defined(cpu_list)
3851 cpu_list(stdout, &fprintf);
3852 #endif
3853 exit(EXIT_FAILURE);
3854 }
3855 }
3856
3857 static void handle_arg_guest_base(const char *arg)
3858 {
3859 guest_base = strtol(arg, NULL, 0);
3860 have_guest_base = 1;
3861 }
3862
3863 static void handle_arg_reserved_va(const char *arg)
3864 {
3865 char *p;
3866 int shift = 0;
3867 reserved_va = strtoul(arg, &p, 0);
3868 switch (*p) {
3869 case 'k':
3870 case 'K':
3871 shift = 10;
3872 break;
3873 case 'M':
3874 shift = 20;
3875 break;
3876 case 'G':
3877 shift = 30;
3878 break;
3879 }
3880 if (shift) {
3881 unsigned long unshifted = reserved_va;
3882 p++;
3883 reserved_va <<= shift;
3884 if (((reserved_va >> shift) != unshifted)
3885 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3886 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3887 #endif
3888 ) {
3889 fprintf(stderr, "Reserved virtual address too big\n");
3890 exit(EXIT_FAILURE);
3891 }
3892 }
3893 if (*p) {
3894 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3895 exit(EXIT_FAILURE);
3896 }
3897 }
3898
3899 static void handle_arg_singlestep(const char *arg)
3900 {
3901 singlestep = 1;
3902 }
3903
3904 static void handle_arg_strace(const char *arg)
3905 {
3906 do_strace = 1;
3907 }
3908
3909 static void handle_arg_version(const char *arg)
3910 {
3911 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3912 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3913 exit(EXIT_SUCCESS);
3914 }
3915
3916 struct qemu_argument {
3917 const char *argv;
3918 const char *env;
3919 bool has_arg;
3920 void (*handle_opt)(const char *arg);
3921 const char *example;
3922 const char *help;
3923 };
3924
3925 static const struct qemu_argument arg_table[] = {
3926 {"h", "", false, handle_arg_help,
3927 "", "print this help"},
3928 {"help", "", false, handle_arg_help,
3929 "", ""},
3930 {"g", "QEMU_GDB", true, handle_arg_gdb,
3931 "port", "wait gdb connection to 'port'"},
3932 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3933 "path", "set the elf interpreter prefix to 'path'"},
3934 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3935 "size", "set the stack size to 'size' bytes"},
3936 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3937 "model", "select CPU (-cpu help for list)"},
3938 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3939 "var=value", "sets targets environment variable (see below)"},
3940 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3941 "var", "unsets targets environment variable (see below)"},
3942 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3943 "argv0", "forces target process argv[0] to be 'argv0'"},
3944 {"r", "QEMU_UNAME", true, handle_arg_uname,
3945 "uname", "set qemu uname release string to 'uname'"},
3946 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3947 "address", "set guest_base address to 'address'"},
3948 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3949 "size", "reserve 'size' bytes for guest virtual address space"},
3950 {"d", "QEMU_LOG", true, handle_arg_log,
3951 "item[,...]", "enable logging of specified items "
3952 "(use '-d help' for a list of items)"},
3953 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3954 "logfile", "write logs to 'logfile' (default stderr)"},
3955 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3956 "pagesize", "set the host page size to 'pagesize'"},
3957 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3958 "", "run in singlestep mode"},
3959 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3960 "", "log system calls"},
3961 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3962 "", "Seed for pseudo-random number generator"},
3963 {"version", "QEMU_VERSION", false, handle_arg_version,
3964 "", "display version information and exit"},
3965 {NULL, NULL, false, NULL, NULL, NULL}
3966 };
3967
3968 static void usage(int exitcode)
3969 {
3970 const struct qemu_argument *arginfo;
3971 int maxarglen;
3972 int maxenvlen;
3973
3974 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3975 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3976 "\n"
3977 "Options and associated environment variables:\n"
3978 "\n");
3979
3980 /* Calculate column widths. We must always have at least enough space
3981 * for the column header.
3982 */
3983 maxarglen = strlen("Argument");
3984 maxenvlen = strlen("Env-variable");
3985
3986 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3987 int arglen = strlen(arginfo->argv);
3988 if (arginfo->has_arg) {
3989 arglen += strlen(arginfo->example) + 1;
3990 }
3991 if (strlen(arginfo->env) > maxenvlen) {
3992 maxenvlen = strlen(arginfo->env);
3993 }
3994 if (arglen > maxarglen) {
3995 maxarglen = arglen;
3996 }
3997 }
3998
3999 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4000 maxenvlen, "Env-variable");
4001
4002 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4003 if (arginfo->has_arg) {
4004 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4005 (int)(maxarglen - strlen(arginfo->argv) - 1),
4006 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4007 } else {
4008 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4009 maxenvlen, arginfo->env,
4010 arginfo->help);
4011 }
4012 }
4013
4014 printf("\n"
4015 "Defaults:\n"
4016 "QEMU_LD_PREFIX = %s\n"
4017 "QEMU_STACK_SIZE = %ld byte\n",
4018 interp_prefix,
4019 guest_stack_size);
4020
4021 printf("\n"
4022 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4023 "QEMU_UNSET_ENV environment variables to set and unset\n"
4024 "environment variables for the target process.\n"
4025 "It is possible to provide several variables by separating them\n"
4026 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4027 "provide the -E and -U options multiple times.\n"
4028 "The following lines are equivalent:\n"
4029 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4030 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4031 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4032 "Note that if you provide several changes to a single variable\n"
4033 "the last change will stay in effect.\n");
4034
4035 exit(exitcode);
4036 }
4037
4038 static int parse_args(int argc, char **argv)
4039 {
4040 const char *r;
4041 int optind;
4042 const struct qemu_argument *arginfo;
4043
4044 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4045 if (arginfo->env == NULL) {
4046 continue;
4047 }
4048
4049 r = getenv(arginfo->env);
4050 if (r != NULL) {
4051 arginfo->handle_opt(r);
4052 }
4053 }
4054
4055 optind = 1;
4056 for (;;) {
4057 if (optind >= argc) {
4058 break;
4059 }
4060 r = argv[optind];
4061 if (r[0] != '-') {
4062 break;
4063 }
4064 optind++;
4065 r++;
4066 if (!strcmp(r, "-")) {
4067 break;
4068 }
4069 /* Treat --foo the same as -foo. */
4070 if (r[0] == '-') {
4071 r++;
4072 }
4073
4074 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4075 if (!strcmp(r, arginfo->argv)) {
4076 if (arginfo->has_arg) {
4077 if (optind >= argc) {
4078 (void) fprintf(stderr,
4079 "qemu: missing argument for option '%s'\n", r);
4080 exit(EXIT_FAILURE);
4081 }
4082 arginfo->handle_opt(argv[optind]);
4083 optind++;
4084 } else {
4085 arginfo->handle_opt(NULL);
4086 }
4087 break;
4088 }
4089 }
4090
4091 /* no option matched the current argv */
4092 if (arginfo->handle_opt == NULL) {
4093 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4094 exit(EXIT_FAILURE);
4095 }
4096 }
4097
4098 if (optind >= argc) {
4099 (void) fprintf(stderr, "qemu: no user program specified\n");
4100 exit(EXIT_FAILURE);
4101 }
4102
4103 filename = argv[optind];
4104 exec_path = argv[optind];
4105
4106 return optind;
4107 }
4108
4109 int main(int argc, char **argv, char **envp)
4110 {
4111 struct target_pt_regs regs1, *regs = &regs1;
4112 struct image_info info1, *info = &info1;
4113 struct linux_binprm bprm;
4114 TaskState *ts;
4115 CPUArchState *env;
4116 CPUState *cpu;
4117 int optind;
4118 char **target_environ, **wrk;
4119 char **target_argv;
4120 int target_argc;
4121 int i;
4122 int ret;
4123 int execfd;
4124
4125 module_call_init(MODULE_INIT_QOM);
4126
4127 if ((envlist = envlist_create()) == NULL) {
4128 (void) fprintf(stderr, "Unable to allocate envlist\n");
4129 exit(EXIT_FAILURE);
4130 }
4131
4132 /* add current environment into the list */
4133 for (wrk = environ; *wrk != NULL; wrk++) {
4134 (void) envlist_setenv(envlist, *wrk);
4135 }
4136
4137 /* Read the stack limit from the kernel. If it's "unlimited",
4138 then we can do little else besides use the default. */
4139 {
4140 struct rlimit lim;
4141 if (getrlimit(RLIMIT_STACK, &lim) == 0
4142 && lim.rlim_cur != RLIM_INFINITY
4143 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4144 guest_stack_size = lim.rlim_cur;
4145 }
4146 }
4147
4148 cpu_model = NULL;
4149 #if defined(cpudef_setup)
4150 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
4151 #endif
4152
4153 srand(time(NULL));
4154
4155 optind = parse_args(argc, argv);
4156
4157 /* Zero out regs */
4158 memset(regs, 0, sizeof(struct target_pt_regs));
4159
4160 /* Zero out image_info */
4161 memset(info, 0, sizeof(struct image_info));
4162
4163 memset(&bprm, 0, sizeof (bprm));
4164
4165 /* Scan interp_prefix dir for replacement files. */
4166 init_paths(interp_prefix);
4167
4168 init_qemu_uname_release();
4169
4170 if (cpu_model == NULL) {
4171 #if defined(TARGET_I386)
4172 #ifdef TARGET_X86_64
4173 cpu_model = "qemu64";
4174 #else
4175 cpu_model = "qemu32";
4176 #endif
4177 #elif defined(TARGET_ARM)
4178 cpu_model = "any";
4179 #elif defined(TARGET_UNICORE32)
4180 cpu_model = "any";
4181 #elif defined(TARGET_M68K)
4182 cpu_model = "any";
4183 #elif defined(TARGET_SPARC)
4184 #ifdef TARGET_SPARC64
4185 cpu_model = "TI UltraSparc II";
4186 #else
4187 cpu_model = "Fujitsu MB86904";
4188 #endif
4189 #elif defined(TARGET_MIPS)
4190 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4191 cpu_model = "5KEf";
4192 #else
4193 cpu_model = "24Kf";
4194 #endif
4195 #elif defined TARGET_OPENRISC
4196 cpu_model = "or1200";
4197 #elif defined(TARGET_PPC)
4198 # ifdef TARGET_PPC64
4199 cpu_model = "POWER8";
4200 # else
4201 cpu_model = "750";
4202 # endif
4203 #elif defined TARGET_SH4
4204 cpu_model = TYPE_SH7785_CPU;
4205 #else
4206 cpu_model = "any";
4207 #endif
4208 }
4209 tcg_exec_init(0);
4210 /* NOTE: we need to init the CPU at this stage to get
4211 qemu_host_page_size */
4212 cpu = cpu_init(cpu_model);
4213 if (!cpu) {
4214 fprintf(stderr, "Unable to find CPU definition\n");
4215 exit(EXIT_FAILURE);
4216 }
4217 env = cpu->env_ptr;
4218 cpu_reset(cpu);
4219
4220 thread_cpu = cpu;
4221
4222 if (getenv("QEMU_STRACE")) {
4223 do_strace = 1;
4224 }
4225
4226 if (getenv("QEMU_RAND_SEED")) {
4227 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4228 }
4229
4230 target_environ = envlist_to_environ(envlist, NULL);
4231 envlist_free(envlist);
4232
4233 /*
4234 * Now that page sizes are configured in cpu_init() we can do
4235 * proper page alignment for guest_base.
4236 */
4237 guest_base = HOST_PAGE_ALIGN(guest_base);
4238
4239 if (reserved_va || have_guest_base) {
4240 guest_base = init_guest_space(guest_base, reserved_va, 0,
4241 have_guest_base);
4242 if (guest_base == (unsigned long)-1) {
4243 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4244 "space for use as guest address space (check your virtual "
4245 "memory ulimit setting or reserve less using -R option)\n",
4246 reserved_va);
4247 exit(EXIT_FAILURE);
4248 }
4249
4250 if (reserved_va) {
4251 mmap_next_start = reserved_va;
4252 }
4253 }
4254
4255 /*
4256 * Read in mmap_min_addr kernel parameter. This value is used
4257 * When loading the ELF image to determine whether guest_base
4258 * is needed. It is also used in mmap_find_vma.
4259 */
4260 {
4261 FILE *fp;
4262
4263 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4264 unsigned long tmp;
4265 if (fscanf(fp, "%lu", &tmp) == 1) {
4266 mmap_min_addr = tmp;
4267 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4268 }
4269 fclose(fp);
4270 }
4271 }
4272
4273 /*
4274 * Prepare copy of argv vector for target.
4275 */
4276 target_argc = argc - optind;
4277 target_argv = calloc(target_argc + 1, sizeof (char *));
4278 if (target_argv == NULL) {
4279 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4280 exit(EXIT_FAILURE);
4281 }
4282
4283 /*
4284 * If argv0 is specified (using '-0' switch) we replace
4285 * argv[0] pointer with the given one.
4286 */
4287 i = 0;
4288 if (argv0 != NULL) {
4289 target_argv[i++] = strdup(argv0);
4290 }
4291 for (; i < target_argc; i++) {
4292 target_argv[i] = strdup(argv[optind + i]);
4293 }
4294 target_argv[target_argc] = NULL;
4295
4296 ts = g_new0(TaskState, 1);
4297 init_task_state(ts);
4298 /* build Task State */
4299 ts->info = info;
4300 ts->bprm = &bprm;
4301 cpu->opaque = ts;
4302 task_settid(ts);
4303
4304 execfd = qemu_getauxval(AT_EXECFD);
4305 if (execfd == 0) {
4306 execfd = open(filename, O_RDONLY);
4307 if (execfd < 0) {
4308 printf("Error while loading %s: %s\n", filename, strerror(errno));
4309 _exit(EXIT_FAILURE);
4310 }
4311 }
4312
4313 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4314 info, &bprm);
4315 if (ret != 0) {
4316 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4317 _exit(EXIT_FAILURE);
4318 }
4319
4320 for (wrk = target_environ; *wrk; wrk++) {
4321 free(*wrk);
4322 }
4323
4324 free(target_environ);
4325
4326 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4327 qemu_log("guest_base 0x%lx\n", guest_base);
4328 log_page_dump();
4329
4330 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4331 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4332 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4333 info->start_code);
4334 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4335 info->start_data);
4336 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4337 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4338 info->start_stack);
4339 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4340 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4341 }
4342
4343 target_set_brk(info->brk);
4344 syscall_init();
4345 signal_init();
4346
4347 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4348 generating the prologue until now so that the prologue can take
4349 the real value of GUEST_BASE into account. */
4350 tcg_prologue_init(&tcg_ctx);
4351
4352 #if defined(TARGET_I386)
4353 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4354 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4355 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4356 env->cr[4] |= CR4_OSFXSR_MASK;
4357 env->hflags |= HF_OSFXSR_MASK;
4358 }
4359 #ifndef TARGET_ABI32
4360 /* enable 64 bit mode if possible */
4361 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4362 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4363 exit(EXIT_FAILURE);
4364 }
4365 env->cr[4] |= CR4_PAE_MASK;
4366 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4367 env->hflags |= HF_LMA_MASK;
4368 #endif
4369
4370 /* flags setup : we activate the IRQs by default as in user mode */
4371 env->eflags |= IF_MASK;
4372
4373 /* linux register setup */
4374 #ifndef TARGET_ABI32
4375 env->regs[R_EAX] = regs->rax;
4376 env->regs[R_EBX] = regs->rbx;
4377 env->regs[R_ECX] = regs->rcx;
4378 env->regs[R_EDX] = regs->rdx;
4379 env->regs[R_ESI] = regs->rsi;
4380 env->regs[R_EDI] = regs->rdi;
4381 env->regs[R_EBP] = regs->rbp;
4382 env->regs[R_ESP] = regs->rsp;
4383 env->eip = regs->rip;
4384 #else
4385 env->regs[R_EAX] = regs->eax;
4386 env->regs[R_EBX] = regs->ebx;
4387 env->regs[R_ECX] = regs->ecx;
4388 env->regs[R_EDX] = regs->edx;
4389 env->regs[R_ESI] = regs->esi;
4390 env->regs[R_EDI] = regs->edi;
4391 env->regs[R_EBP] = regs->ebp;
4392 env->regs[R_ESP] = regs->esp;
4393 env->eip = regs->eip;
4394 #endif
4395
4396 /* linux interrupt setup */
4397 #ifndef TARGET_ABI32
4398 env->idt.limit = 511;
4399 #else
4400 env->idt.limit = 255;
4401 #endif
4402 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4403 PROT_READ|PROT_WRITE,
4404 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4405 idt_table = g2h(env->idt.base);
4406 set_idt(0, 0);
4407 set_idt(1, 0);
4408 set_idt(2, 0);
4409 set_idt(3, 3);
4410 set_idt(4, 3);
4411 set_idt(5, 0);
4412 set_idt(6, 0);
4413 set_idt(7, 0);
4414 set_idt(8, 0);
4415 set_idt(9, 0);
4416 set_idt(10, 0);
4417 set_idt(11, 0);
4418 set_idt(12, 0);
4419 set_idt(13, 0);
4420 set_idt(14, 0);
4421 set_idt(15, 0);
4422 set_idt(16, 0);
4423 set_idt(17, 0);
4424 set_idt(18, 0);
4425 set_idt(19, 0);
4426 set_idt(0x80, 3);
4427
4428 /* linux segment setup */
4429 {
4430 uint64_t *gdt_table;
4431 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4432 PROT_READ|PROT_WRITE,
4433 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4434 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4435 gdt_table = g2h(env->gdt.base);
4436 #ifdef TARGET_ABI32
4437 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4438 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4439 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4440 #else
4441 /* 64 bit code segment */
4442 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4443 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4444 DESC_L_MASK |
4445 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4446 #endif
4447 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4448 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4449 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4450 }
4451 cpu_x86_load_seg(env, R_CS, __USER_CS);
4452 cpu_x86_load_seg(env, R_SS, __USER_DS);
4453 #ifdef TARGET_ABI32
4454 cpu_x86_load_seg(env, R_DS, __USER_DS);
4455 cpu_x86_load_seg(env, R_ES, __USER_DS);
4456 cpu_x86_load_seg(env, R_FS, __USER_DS);
4457 cpu_x86_load_seg(env, R_GS, __USER_DS);
4458 /* This hack makes Wine work... */
4459 env->segs[R_FS].selector = 0;
4460 #else
4461 cpu_x86_load_seg(env, R_DS, 0);
4462 cpu_x86_load_seg(env, R_ES, 0);
4463 cpu_x86_load_seg(env, R_FS, 0);
4464 cpu_x86_load_seg(env, R_GS, 0);
4465 #endif
4466 #elif defined(TARGET_AARCH64)
4467 {
4468 int i;
4469
4470 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4471 fprintf(stderr,
4472 "The selected ARM CPU does not support 64 bit mode\n");
4473 exit(EXIT_FAILURE);
4474 }
4475
4476 for (i = 0; i < 31; i++) {
4477 env->xregs[i] = regs->regs[i];
4478 }
4479 env->pc = regs->pc;
4480 env->xregs[31] = regs->sp;
4481 }
4482 #elif defined(TARGET_ARM)
4483 {
4484 int i;
4485 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4486 CPSRWriteByInstr);
4487 for(i = 0; i < 16; i++) {
4488 env->regs[i] = regs->uregs[i];
4489 }
4490 #ifdef TARGET_WORDS_BIGENDIAN
4491 /* Enable BE8. */
4492 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4493 && (info->elf_flags & EF_ARM_BE8)) {
4494 env->uncached_cpsr |= CPSR_E;
4495 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4496 } else {
4497 env->cp15.sctlr_el[1] |= SCTLR_B;
4498 }
4499 #endif
4500 }
4501 #elif defined(TARGET_UNICORE32)
4502 {
4503 int i;
4504 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4505 for (i = 0; i < 32; i++) {
4506 env->regs[i] = regs->uregs[i];
4507 }
4508 }
4509 #elif defined(TARGET_SPARC)
4510 {
4511 int i;
4512 env->pc = regs->pc;
4513 env->npc = regs->npc;
4514 env->y = regs->y;
4515 for(i = 0; i < 8; i++)
4516 env->gregs[i] = regs->u_regs[i];
4517 for(i = 0; i < 8; i++)
4518 env->regwptr[i] = regs->u_regs[i + 8];
4519 }
4520 #elif defined(TARGET_PPC)
4521 {
4522 int i;
4523
4524 #if defined(TARGET_PPC64)
4525 #if defined(TARGET_ABI32)
4526 env->msr &= ~((target_ulong)1 << MSR_SF);
4527 #else
4528 env->msr |= (target_ulong)1 << MSR_SF;
4529 #endif
4530 #endif
4531 env->nip = regs->nip;
4532 for(i = 0; i < 32; i++) {
4533 env->gpr[i] = regs->gpr[i];
4534 }
4535 }
4536 #elif defined(TARGET_M68K)
4537 {
4538 env->pc = regs->pc;
4539 env->dregs[0] = regs->d0;
4540 env->dregs[1] = regs->d1;
4541 env->dregs[2] = regs->d2;
4542 env->dregs[3] = regs->d3;
4543 env->dregs[4] = regs->d4;
4544 env->dregs[5] = regs->d5;
4545 env->dregs[6] = regs->d6;
4546 env->dregs[7] = regs->d7;
4547 env->aregs[0] = regs->a0;
4548 env->aregs[1] = regs->a1;
4549 env->aregs[2] = regs->a2;
4550 env->aregs[3] = regs->a3;
4551 env->aregs[4] = regs->a4;
4552 env->aregs[5] = regs->a5;
4553 env->aregs[6] = regs->a6;
4554 env->aregs[7] = regs->usp;
4555 env->sr = regs->sr;
4556 ts->sim_syscalls = 1;
4557 }
4558 #elif defined(TARGET_MICROBLAZE)
4559 {
4560 env->regs[0] = regs->r0;
4561 env->regs[1] = regs->r1;
4562 env->regs[2] = regs->r2;
4563 env->regs[3] = regs->r3;
4564 env->regs[4] = regs->r4;
4565 env->regs[5] = regs->r5;
4566 env->regs[6] = regs->r6;
4567 env->regs[7] = regs->r7;
4568 env->regs[8] = regs->r8;
4569 env->regs[9] = regs->r9;
4570 env->regs[10] = regs->r10;
4571 env->regs[11] = regs->r11;
4572 env->regs[12] = regs->r12;
4573 env->regs[13] = regs->r13;
4574 env->regs[14] = regs->r14;
4575 env->regs[15] = regs->r15;
4576 env->regs[16] = regs->r16;
4577 env->regs[17] = regs->r17;
4578 env->regs[18] = regs->r18;
4579 env->regs[19] = regs->r19;
4580 env->regs[20] = regs->r20;
4581 env->regs[21] = regs->r21;
4582 env->regs[22] = regs->r22;
4583 env->regs[23] = regs->r23;
4584 env->regs[24] = regs->r24;
4585 env->regs[25] = regs->r25;
4586 env->regs[26] = regs->r26;
4587 env->regs[27] = regs->r27;
4588 env->regs[28] = regs->r28;
4589 env->regs[29] = regs->r29;
4590 env->regs[30] = regs->r30;
4591 env->regs[31] = regs->r31;
4592 env->sregs[SR_PC] = regs->pc;
4593 }
4594 #elif defined(TARGET_MIPS)
4595 {
4596 int i;
4597
4598 for(i = 0; i < 32; i++) {
4599 env->active_tc.gpr[i] = regs->regs[i];
4600 }
4601 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4602 if (regs->cp0_epc & 1) {
4603 env->hflags |= MIPS_HFLAG_M16;
4604 }
4605 }
4606 #elif defined(TARGET_OPENRISC)
4607 {
4608 int i;
4609
4610 for (i = 0; i < 32; i++) {
4611 env->gpr[i] = regs->gpr[i];
4612 }
4613
4614 env->sr = regs->sr;
4615 env->pc = regs->pc;
4616 }
4617 #elif defined(TARGET_SH4)
4618 {
4619 int i;
4620
4621 for(i = 0; i < 16; i++) {
4622 env->gregs[i] = regs->regs[i];
4623 }
4624 env->pc = regs->pc;
4625 }
4626 #elif defined(TARGET_ALPHA)
4627 {
4628 int i;
4629
4630 for(i = 0; i < 28; i++) {
4631 env->ir[i] = ((abi_ulong *)regs)[i];
4632 }
4633 env->ir[IR_SP] = regs->usp;
4634 env->pc = regs->pc;
4635 }
4636 #elif defined(TARGET_CRIS)
4637 {
4638 env->regs[0] = regs->r0;
4639 env->regs[1] = regs->r1;
4640 env->regs[2] = regs->r2;
4641 env->regs[3] = regs->r3;
4642 env->regs[4] = regs->r4;
4643 env->regs[5] = regs->r5;
4644 env->regs[6] = regs->r6;
4645 env->regs[7] = regs->r7;
4646 env->regs[8] = regs->r8;
4647 env->regs[9] = regs->r9;
4648 env->regs[10] = regs->r10;
4649 env->regs[11] = regs->r11;
4650 env->regs[12] = regs->r12;
4651 env->regs[13] = regs->r13;
4652 env->regs[14] = info->start_stack;
4653 env->regs[15] = regs->acr;
4654 env->pc = regs->erp;
4655 }
4656 #elif defined(TARGET_S390X)
4657 {
4658 int i;
4659 for (i = 0; i < 16; i++) {
4660 env->regs[i] = regs->gprs[i];
4661 }
4662 env->psw.mask = regs->psw.mask;
4663 env->psw.addr = regs->psw.addr;
4664 }
4665 #elif defined(TARGET_TILEGX)
4666 {
4667 int i;
4668 for (i = 0; i < TILEGX_R_COUNT; i++) {
4669 env->regs[i] = regs->regs[i];
4670 }
4671 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4672 env->spregs[i] = 0;
4673 }
4674 env->pc = regs->pc;
4675 }
4676 #else
4677 #error unsupported target CPU
4678 #endif
4679
4680 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4681 ts->stack_base = info->start_stack;
4682 ts->heap_base = info->brk;
4683 /* This will be filled in on the first SYS_HEAPINFO call. */
4684 ts->heap_limit = 0;
4685 #endif
4686
4687 if (gdbstub_port) {
4688 if (gdbserver_start(gdbstub_port) < 0) {
4689 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4690 gdbstub_port);
4691 exit(EXIT_FAILURE);
4692 }
4693 gdb_handlesig(cpu, 0);
4694 }
4695 cpu_loop(env);
4696 /* never exits */
4697 return 0;
4698 }
AR7 emulation for QEMU