2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
98 ICSState
*ics
= spapr
->ics
;
101 assert(ics_valid_irq(ics
, irq
));
103 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
104 error_setg(errp
, "IRQ %d is not free", irq
);
108 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
112 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
)
114 ICSState
*ics
= spapr
->ics
;
115 uint32_t srcno
= irq
- ics
->offset
;
117 assert(ics_valid_irq(ics
, irq
));
119 memset(&ics
->irqs
[srcno
], 0, sizeof(ICSIRQState
));
122 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
127 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
129 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
132 ics_pic_print_info(spapr
->ics
, mon
);
135 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
136 PowerPCCPU
*cpu
, Error
**errp
)
138 Error
*local_err
= NULL
;
140 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
142 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
145 error_propagate(errp
, local_err
);
149 spapr_cpu
->icp
= ICP(obj
);
152 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
154 if (!kvm_irqchip_in_kernel()) {
157 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
158 icp_resend(spapr_cpu_state(cpu
)->icp
);
164 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
166 SpaprMachineState
*spapr
= opaque
;
167 uint32_t srcno
= irq
- spapr
->ics
->offset
;
169 ics_set_irq(spapr
->ics
, srcno
, val
);
172 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
174 Error
*local_err
= NULL
;
176 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
178 error_propagate(errp
, local_err
);
183 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
186 xics_kvm_connect(spapr
, errp
);
190 SpaprIrq spapr_irq_xics
= {
191 .nr_xirqs
= SPAPR_NR_XIRQS
,
192 .nr_msis
= SPAPR_NR_MSIS
,
196 .claim
= spapr_irq_claim_xics
,
197 .free
= spapr_irq_free_xics
,
198 .print_info
= spapr_irq_print_info_xics
,
199 .dt_populate
= spapr_dt_xics
,
200 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
201 .post_load
= spapr_irq_post_load_xics
,
202 .reset
= spapr_irq_reset_xics
,
203 .set_irq
= spapr_irq_set_irq_xics
,
204 .init_kvm
= spapr_irq_init_kvm_xics
,
211 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
214 return spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
, errp
);
217 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
)
219 spapr_xive_irq_free(spapr
->xive
, irq
);
222 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
228 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
230 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
233 spapr_xive_pic_print_info(spapr
->xive
, mon
);
236 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
237 PowerPCCPU
*cpu
, Error
**errp
)
239 Error
*local_err
= NULL
;
241 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
243 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
245 error_propagate(errp
, local_err
);
249 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
252 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
253 * don't beneficiate from the reset of the XIVE IRQ backend
255 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
258 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
260 return spapr_xive_post_load(spapr
->xive
, version_id
);
263 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
266 Error
*local_err
= NULL
;
269 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
271 /* (TCG) Set the OS CAM line of the thread interrupt context. */
272 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
275 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
277 error_propagate(errp
, local_err
);
281 /* Activate the XIVE MMIOs */
282 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
285 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
287 SpaprMachineState
*spapr
= opaque
;
289 if (kvm_irqchip_in_kernel()) {
290 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
292 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
296 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
299 kvmppc_xive_connect(spapr
->xive
, errp
);
303 SpaprIrq spapr_irq_xive
= {
304 .nr_xirqs
= SPAPR_NR_XIRQS
,
305 .nr_msis
= SPAPR_NR_MSIS
,
309 .claim
= spapr_irq_claim_xive
,
310 .free
= spapr_irq_free_xive
,
311 .print_info
= spapr_irq_print_info_xive
,
312 .dt_populate
= spapr_dt_xive
,
313 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
314 .post_load
= spapr_irq_post_load_xive
,
315 .reset
= spapr_irq_reset_xive
,
316 .set_irq
= spapr_irq_set_irq_xive
,
317 .init_kvm
= spapr_irq_init_kvm_xive
,
321 * Dual XIVE and XICS IRQ backend.
323 * Both interrupt mode, XIVE and XICS, objects are created but the
324 * machine starts in legacy interrupt mode (XICS). It can be changed
325 * by the CAS negotiation process and, in that case, the new mode is
326 * activated after an extra machine reset.
330 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
333 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
335 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
336 &spapr_irq_xive
: &spapr_irq_xics
;
339 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
342 Error
*local_err
= NULL
;
345 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
347 error_propagate(errp
, local_err
);
351 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
353 error_propagate(errp
, local_err
);
360 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
)
362 spapr_irq_xics
.free(spapr
, irq
);
363 spapr_irq_xive
.free(spapr
, irq
);
366 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
368 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
371 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
372 uint32_t nr_servers
, void *fdt
,
375 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
378 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
379 PowerPCCPU
*cpu
, Error
**errp
)
381 Error
*local_err
= NULL
;
383 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
385 error_propagate(errp
, local_err
);
389 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
392 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
395 * Force a reset of the XIVE backend after migration. The machine
396 * defaults to XICS at startup.
398 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
399 if (kvm_irqchip_in_kernel()) {
400 xics_kvm_disconnect(spapr
, &error_fatal
);
402 spapr_irq_xive
.reset(spapr
, &error_fatal
);
405 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
408 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
410 Error
*local_err
= NULL
;
413 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
416 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
418 /* Destroy all KVM devices */
419 if (kvm_irqchip_in_kernel()) {
420 xics_kvm_disconnect(spapr
, &local_err
);
422 error_propagate(errp
, local_err
);
423 error_prepend(errp
, "KVM XICS disconnect failed: ");
426 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
428 error_propagate(errp
, local_err
);
429 error_prepend(errp
, "KVM XIVE disconnect failed: ");
434 spapr_irq_current(spapr
)->reset(spapr
, errp
);
437 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
439 SpaprMachineState
*spapr
= opaque
;
441 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
445 * Define values in sync with the XIVE and XICS backend
447 SpaprIrq spapr_irq_dual
= {
448 .nr_xirqs
= SPAPR_NR_XIRQS
,
449 .nr_msis
= SPAPR_NR_MSIS
,
453 .claim
= spapr_irq_claim_dual
,
454 .free
= spapr_irq_free_dual
,
455 .print_info
= spapr_irq_print_info_dual
,
456 .dt_populate
= spapr_irq_dt_populate_dual
,
457 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
458 .post_load
= spapr_irq_post_load_dual
,
459 .reset
= spapr_irq_reset_dual
,
460 .set_irq
= spapr_irq_set_irq_dual
,
461 .init_kvm
= NULL
, /* should not be used */
465 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
467 MachineState
*machine
= MACHINE(spapr
);
470 * Sanity checks on non-P9 machines. On these, XIVE is not
471 * advertised, see spapr_dt_ov5_platform_support()
473 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
474 0, spapr
->max_compat_pvr
)) {
476 * If the 'dual' interrupt mode is selected, force XICS as CAS
477 * negotiation is useless.
479 if (spapr
->irq
== &spapr_irq_dual
) {
480 spapr
->irq
= &spapr_irq_xics
;
485 * Non-P9 machines using only XIVE is a bogus setup. We have two
486 * scenarios to take into account because of the compat mode:
488 * 1. POWER7/8 machines should fail to init later on when creating
489 * the XIVE interrupt presenters because a POWER9 exception
492 * 2. POWER9 machines using the POWER8 compat mode won't fail and
493 * will let the OS boot with a partial XIVE setup : DT
494 * properties but no hcalls.
496 * To cover both and not confuse the OS, add an early failure in
499 if (spapr
->irq
== &spapr_irq_xive
) {
500 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
506 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
507 * re-created. Detect that early to avoid QEMU to exit later when the
511 spapr
->irq
== &spapr_irq_dual
&&
512 machine_kernel_irqchip_required(machine
) &&
513 xics_kvm_has_broken_disconnect(spapr
)) {
514 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
522 * sPAPR IRQ frontend routines for devices
524 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
526 MachineState
*machine
= MACHINE(spapr
);
528 if (machine_kernel_irqchip_split(machine
)) {
529 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
533 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
535 "kernel_irqchip requested but only available with KVM");
539 if (spapr_irq_check(spapr
, errp
) < 0) {
543 /* Initialize the MSI IRQ allocator. */
544 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
545 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
548 if (spapr
->irq
->xics
) {
549 Error
*local_err
= NULL
;
552 obj
= object_new(TYPE_ICS_SPAPR
);
553 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
555 error_propagate(errp
, local_err
);
559 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
562 error_propagate(errp
, local_err
);
566 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
569 error_propagate(errp
, local_err
);
573 object_property_set_bool(obj
, true, "realized", &local_err
);
575 error_propagate(errp
, local_err
);
579 spapr
->ics
= ICS_SPAPR(obj
);
582 if (spapr
->irq
->xive
) {
583 uint32_t nr_servers
= spapr_max_server_number(spapr
);
587 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
588 qdev_prop_set_uint32(dev
, "nr-irqs",
589 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
591 * 8 XIVE END structures per CPU. One for each available
594 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
595 qdev_init_nofail(dev
);
597 spapr
->xive
= SPAPR_XIVE(dev
);
599 /* Enable the CPU IPIs */
600 for (i
= 0; i
< nr_servers
; ++i
) {
601 if (spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
,
607 spapr_xive_hcall_init(spapr
);
610 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
611 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
614 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
616 assert(irq
>= SPAPR_XIRQ_BASE
);
617 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
619 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
622 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
626 assert(irq
>= SPAPR_XIRQ_BASE
);
627 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
629 for (i
= irq
; i
< (irq
+ num
); i
++) {
630 spapr
->irq
->free(spapr
, i
);
634 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
637 * This interface is basically for VIO and PHB devices to find the
638 * right qemu_irq to manipulate, so we only allow access to the
639 * external irqs for now. Currently anything which needs to
640 * access the IPIs most naturally gets there via the guest side
641 * interfaces, we can change this if we need to in future.
643 assert(irq
>= SPAPR_XIRQ_BASE
);
644 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
647 assert(ics_valid_irq(spapr
->ics
, irq
));
650 assert(irq
< spapr
->xive
->nr_irqs
);
651 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
654 return spapr
->qirqs
[irq
];
657 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
659 return spapr
->irq
->post_load(spapr
, version_id
);
662 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
664 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
666 if (spapr
->irq
->reset
) {
667 spapr
->irq
->reset(spapr
, errp
);
671 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
673 const char *nodename
= "interrupt-controller";
676 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
678 error_setg(errp
, "Can't find node \"%s\": %s",
679 nodename
, fdt_strerror(offset
));
683 phandle
= fdt_get_phandle(fdt
, offset
);
685 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
693 * XICS legacy routines - to deprecate one day
696 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
700 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
701 if (num
> (ics
->nr_irqs
- first
)) {
704 for (i
= first
; i
< first
+ num
; ++i
) {
705 if (!ics_irq_free(ics
, i
)) {
709 if (i
== (first
+ num
)) {
717 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
719 ICSState
*ics
= spapr
->ics
;
725 * MSIMesage::data is used for storing VIRQ so
726 * it has to be aligned to num to support multiple
727 * MSI vectors. MSI-X is not affected by this.
728 * The hint is used for the first IRQ, the rest should
729 * be allocated continuously.
732 assert((num
== 1) || (num
== 2) || (num
== 4) ||
733 (num
== 8) || (num
== 16) || (num
== 32));
734 first
= ics_find_free_block(ics
, num
, num
);
736 first
= ics_find_free_block(ics
, num
, 1);
740 error_setg(errp
, "can't find a free %d-IRQ block", num
);
744 return first
+ ics
->offset
;
747 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
749 SpaprIrq spapr_irq_xics_legacy
= {
750 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
751 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
755 .claim
= spapr_irq_claim_xics
,
756 .free
= spapr_irq_free_xics
,
757 .print_info
= spapr_irq_print_info_xics
,
758 .dt_populate
= spapr_dt_xics
,
759 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
760 .post_load
= spapr_irq_post_load_xics
,
761 .reset
= spapr_irq_reset_xics
,
762 .set_irq
= spapr_irq_set_irq_xics
,
763 .init_kvm
= spapr_irq_init_kvm_xics
,