hw/arm/virt-acpi-build.c

   1 /* Support for generating ACPI tables and passing them to Guests
   2  *
   3  * ARM virt ACPI generation
   4  *
   5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   6  * Copyright (C) 2006 Fabrice Bellard
   7  * Copyright (C) 2013 Red Hat Inc
   8  *
   9  * Author: Michael S. Tsirkin <mst@redhat.com>
  10  *
  11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  12  *
  13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "qapi/error.h"
  31 #include "qemu-common.h"
  32 #include "hw/arm/virt-acpi-build.h"
  33 #include "qemu/bitmap.h"
  34 #include "trace.h"
  35 #include "qom/cpu.h"
  36 #include "target-arm/cpu.h"
  37 #include "hw/acpi/acpi-defs.h"
  38 #include "hw/acpi/acpi.h"
  39 #include "hw/nvram/fw_cfg.h"
  40 #include "hw/acpi/bios-linker-loader.h"
  41 #include "hw/loader.h"
  42 #include "hw/hw.h"
  43 #include "hw/acpi/aml-build.h"
  44 #include "hw/pci/pcie_host.h"
  45 #include "hw/pci/pci.h"
  46 #include "sysemu/numa.h"
  47
  48 #define ARM_SPI_BASE 32
  49 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
  50
  51 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
  52 {
  53     uint16_t i;
  54
  55     for (i = 0; i < smp_cpus; i++) {
  56         Aml *dev = aml_device("C%.03X", i);
  57         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  58         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
  59         aml_append(scope, dev);
  60     }
  61 }
  62
  63 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  64                                            uint32_t uart_irq)
  65 {
  66     Aml *dev = aml_device("COM0");
  67     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
  68     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  69
  70     Aml *crs = aml_resource_template();
  71     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  72                                        uart_memmap->size, AML_READ_WRITE));
  73     aml_append(crs,
  74                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  75                              AML_EXCLUSIVE, &uart_irq, 1));
  76     aml_append(dev, aml_name_decl("_CRS", crs));
  77
  78     /* The _ADR entry is used to link this device to the UART described
  79      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
  80      */
  81     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
  82
  83     aml_append(scope, dev);
  84 }
  85
  86 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
  87 {
  88     Aml *dev = aml_device("FWCF");
  89     aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
  90     /* device present, functioning, decoding, not shown in UI */
  91     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
  92
  93     Aml *crs = aml_resource_template();
  94     aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
  95                                        fw_cfg_memmap->size, AML_READ_WRITE));
  96     aml_append(dev, aml_name_decl("_CRS", crs));
  97     aml_append(scope, dev);
  98 }
  99
 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
 101 {
 102     Aml *dev, *crs;
 103     hwaddr base = flash_memmap->base;
 104     hwaddr size = flash_memmap->size / 2;
 105
 106     dev = aml_device("FLS0");
 107     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 108     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 109
 110     crs = aml_resource_template();
 111     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 112     aml_append(dev, aml_name_decl("_CRS", crs));
 113     aml_append(scope, dev);
 114
 115     dev = aml_device("FLS1");
 116     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 117     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
 118     crs = aml_resource_template();
 119     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
 120     aml_append(dev, aml_name_decl("_CRS", crs));
 121     aml_append(scope, dev);
 122 }
 123
 124 static void acpi_dsdt_add_virtio(Aml *scope,
 125                                  const MemMapEntry *virtio_mmio_memmap,
 126                                  uint32_t mmio_irq, int num)
 127 {
 128     hwaddr base = virtio_mmio_memmap->base;
 129     hwaddr size = virtio_mmio_memmap->size;
 130     int i;
 131
 132     for (i = 0; i < num; i++) {
 133         uint32_t irq = mmio_irq + i;
 134         Aml *dev = aml_device("VR%02u", i);
 135         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
 136         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
 137
 138         Aml *crs = aml_resource_template();
 139         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 140         aml_append(crs,
 141                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 142                                  AML_EXCLUSIVE, &irq, 1));
 143         aml_append(dev, aml_name_decl("_CRS", crs));
 144         aml_append(scope, dev);
 145         base += size;
 146     }
 147 }
 148
 149 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
 150                               uint32_t irq, bool use_highmem)
 151 {
 152     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
 153     int i, bus_no;
 154     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
 155     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
 156     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
 157     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
 158     hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
 159     hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
 160     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
 161
 162     Aml *dev = aml_device("%s", "PCI0");
 163     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 164     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 165     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 166     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 167     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 168     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
 169     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 170     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 171
 172     /* Declare the PCI Routing Table. */
 173     Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
 174     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
 175         for (i = 0; i < PCI_NUM_PINS; i++) {
 176             int gsi = (i + bus_no) % PCI_NUM_PINS;
 177             Aml *pkg = aml_package(4);
 178             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
 179             aml_append(pkg, aml_int(i));
 180             aml_append(pkg, aml_name("GSI%d", gsi));
 181             aml_append(pkg, aml_int(0));
 182             aml_append(rt_pkg, pkg);
 183         }
 184     }
 185     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
 186
 187     /* Create GSI link device */
 188     for (i = 0; i < PCI_NUM_PINS; i++) {
 189         uint32_t irqs =  irq + i;
 190         Aml *dev_gsi = aml_device("GSI%d", i);
 191         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
 192         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
 193         crs = aml_resource_template();
 194         aml_append(crs,
 195                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 196                                  AML_EXCLUSIVE, &irqs, 1));
 197         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
 198         crs = aml_resource_template();
 199         aml_append(crs,
 200                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 201                                  AML_EXCLUSIVE, &irqs, 1));
 202         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
 203         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
 204         aml_append(dev_gsi, method);
 205         aml_append(dev, dev_gsi);
 206     }
 207
 208     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 209     aml_append(method, aml_return(aml_int(base_ecam)));
 210     aml_append(dev, method);
 211
 212     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
 213     Aml *rbuf = aml_resource_template();
 214     aml_append(rbuf,
 215         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 216                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 217                             nr_pcie_buses));
 218     aml_append(rbuf,
 219         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 220                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
 221                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
 222     aml_append(rbuf,
 223         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 224                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
 225                      size_pio));
 226
 227     if (use_highmem) {
 228         hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
 229         hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
 230
 231         aml_append(rbuf,
 232             aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 233                              AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 234                              base_mmio_high,
 235                              base_mmio_high + size_mmio_high - 1, 0x0000,
 236                              size_mmio_high));
 237     }
 238
 239     aml_append(method, aml_name_decl("RBUF", rbuf));
 240     aml_append(method, aml_return(rbuf));
 241     aml_append(dev, method);
 242
 243     /* Declare an _OSC (OS Control Handoff) method */
 244     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 245     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
 246     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
 247     aml_append(method,
 248         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 249
 250     /* PCI Firmware Specification 3.0
 251      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
 252      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
 253      * identified by the Universal Unique IDentifier (UUID)
 254      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
 255      */
 256     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
 257     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 258     aml_append(ifctx,
 259         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
 260     aml_append(ifctx,
 261         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 262     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 263     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 264     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
 265                                 aml_name("CTRL")));
 266
 267     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
 268     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
 269                                  aml_name("CDW1")));
 270     aml_append(ifctx, ifctx1);
 271
 272     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
 273     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
 274                                  aml_name("CDW1")));
 275     aml_append(ifctx, ifctx1);
 276
 277     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
 278     aml_append(ifctx, aml_return(aml_arg(3)));
 279     aml_append(method, ifctx);
 280
 281     elsectx = aml_else();
 282     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
 283                                   aml_name("CDW1")));
 284     aml_append(elsectx, aml_return(aml_arg(3)));
 285     aml_append(method, elsectx);
 286     aml_append(dev, method);
 287
 288     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 289
 290     /* PCI Firmware Specification 3.0
 291      * 4.6.1. _DSM for PCI Express Slot Information
 292      * The UUID in _DSM in this context is
 293      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 294      */
 295     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 296     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 297     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 298     uint8_t byte_list[1] = {1};
 299     buf = aml_buffer(1, byte_list);
 300     aml_append(ifctx1, aml_return(buf));
 301     aml_append(ifctx, ifctx1);
 302     aml_append(method, ifctx);
 303
 304     byte_list[0] = 0;
 305     buf = aml_buffer(1, byte_list);
 306     aml_append(method, aml_return(buf));
 307     aml_append(dev, method);
 308
 309     Aml *dev_rp0 = aml_device("%s", "RP0");
 310     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
 311     aml_append(dev, dev_rp0);
 312     aml_append(scope, dev);
 313 }
 314
 315 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
 316                                            uint32_t gpio_irq)
 317 {
 318     Aml *dev = aml_device("GPO0");
 319     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
 320     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 321     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 322
 323     Aml *crs = aml_resource_template();
 324     aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
 325                                        AML_READ_WRITE));
 326     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 327                                   AML_EXCLUSIVE, &gpio_irq, 1));
 328     aml_append(dev, aml_name_decl("_CRS", crs));
 329
 330     Aml *aei = aml_resource_template();
 331     /* Pin 3 for power button */
 332     const uint32_t pin_list[1] = {3};
 333     aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
 334                                  AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
 335                                  "GPO0", NULL, 0));
 336     aml_append(dev, aml_name_decl("_AEI", aei));
 337
 338     /* _E03 is handle for power button */
 339     Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
 340     aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
 341                                   aml_int(0x80)));
 342     aml_append(dev, method);
 343     aml_append(scope, dev);
 344 }
 345
 346 static void acpi_dsdt_add_power_button(Aml *scope)
 347 {
 348     Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
 349     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
 350     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 351     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 352     aml_append(scope, dev);
 353 }
 354
 355 /* RSDP */
 356 static GArray *
 357 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
 358 {
 359     AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
 360     unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
 361     unsigned rsdt_pa_offset =
 362         (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
 363
 364     bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
 365                              true /* fseg memory */);
 366
 367     memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
 368     memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
 369     rsdp->length = cpu_to_le32(sizeof(*rsdp));
 370     rsdp->revision = 0x02;
 371
 372     /* Address to be filled by Guest linker */
 373     bios_linker_loader_add_pointer(linker,
 374         ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
 375         ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
 376
 377     /* Checksum to be filled by Guest linker */
 378     bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
 379         (char *)rsdp - rsdp_table->data, sizeof *rsdp,
 380         (char *)&rsdp->checksum - rsdp_table->data);
 381
 382     return rsdp_table;
 383 }
 384
 385 static void
 386 build_spcr(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 387 {
 388     AcpiSerialPortConsoleRedirection *spcr;
 389     const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
 390     int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
 391
 392     spcr = acpi_data_push(table_data, sizeof(*spcr));
 393
 394     spcr->interface_type = 0x3;    /* ARM PL011 UART */
 395
 396     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
 397     spcr->base_address.bit_width = 8;
 398     spcr->base_address.bit_offset = 0;
 399     spcr->base_address.access_width = 1;
 400     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
 401
 402     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
 403     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
 404
 405     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
 406     spcr->parity = 0;              /* No Parity */
 407     spcr->stopbits = 1;            /* 1 Stop bit */
 408     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
 409     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
 410
 411     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
 412     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
 413
 414     build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
 415                  NULL, NULL);
 416 }
 417
 418 static void
 419 build_srat(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 420 {
 421     AcpiSystemResourceAffinityTable *srat;
 422     AcpiSratProcessorGiccAffinity *core;
 423     AcpiSratMemoryAffinity *numamem;
 424     int i, j, srat_start;
 425     uint64_t mem_base;
 426     uint32_t *cpu_node = g_malloc0(guest_info->smp_cpus * sizeof(uint32_t));
 427
 428     for (i = 0; i < guest_info->smp_cpus; i++) {
 429         for (j = 0; j < nb_numa_nodes; j++) {
 430             if (test_bit(i, numa_info[j].node_cpu)) {
 431                 cpu_node[i] = j;
 432                 break;
 433             }
 434         }
 435     }
 436
 437     srat_start = table_data->len;
 438     srat = acpi_data_push(table_data, sizeof(*srat));
 439     srat->reserved1 = cpu_to_le32(1);
 440
 441     for (i = 0; i < guest_info->smp_cpus; ++i) {
 442         core = acpi_data_push(table_data, sizeof(*core));
 443         core->type = ACPI_SRAT_PROCESSOR_GICC;
 444         core->length = sizeof(*core);
 445         core->proximity = cpu_to_le32(cpu_node[i]);
 446         core->acpi_processor_uid = cpu_to_le32(i);
 447         core->flags = cpu_to_le32(1);
 448     }
 449     g_free(cpu_node);
 450
 451     mem_base = guest_info->memmap[VIRT_MEM].base;
 452     for (i = 0; i < nb_numa_nodes; ++i) {
 453         numamem = acpi_data_push(table_data, sizeof(*numamem));
 454         build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
 455                           MEM_AFFINITY_ENABLED);
 456         mem_base += numa_info[i].node_mem;
 457     }
 458
 459     build_header(linker, table_data, (void *)srat, "SRAT",
 460                  table_data->len - srat_start, 3, NULL, NULL);
 461 }
 462
 463 static void
 464 build_mcfg(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 465 {
 466     AcpiTableMcfg *mcfg;
 467     const MemMapEntry *memmap = guest_info->memmap;
 468     int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
 469
 470     mcfg = acpi_data_push(table_data, len);
 471     mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
 472
 473     /* Only a single allocation so no need to play with segments */
 474     mcfg->allocation[0].pci_segment = cpu_to_le16(0);
 475     mcfg->allocation[0].start_bus_number = 0;
 476     mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
 477                                           / PCIE_MMCFG_SIZE_MIN) - 1;
 478
 479     build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
 480 }
 481
 482 /* GTDT */
 483 static void
 484 build_gtdt(GArray *table_data, BIOSLinker *linker)
 485 {
 486     int gtdt_start = table_data->len;
 487     AcpiGenericTimerTable *gtdt;
 488
 489     gtdt = acpi_data_push(table_data, sizeof *gtdt);
 490     /* The interrupt values are the same with the device tree when adding 16 */
 491     gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
 492     gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
 493
 494     gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
 495     gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON;
 496
 497     gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
 498     gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
 499
 500     gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
 501     gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
 502
 503     build_header(linker, table_data,
 504                  (void *)(table_data->data + gtdt_start), "GTDT",
 505                  table_data->len - gtdt_start, 2, NULL, NULL);
 506 }
 507
 508 /* MADT */
 509 static void
 510 build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 511 {
 512     int madt_start = table_data->len;
 513     const MemMapEntry *memmap = guest_info->memmap;
 514     const int *irqmap = guest_info->irqmap;
 515     AcpiMultipleApicTable *madt;
 516     AcpiMadtGenericDistributor *gicd;
 517     AcpiMadtGenericMsiFrame *gic_msi;
 518     int i;
 519
 520     madt = acpi_data_push(table_data, sizeof *madt);
 521
 522     gicd = acpi_data_push(table_data, sizeof *gicd);
 523     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
 524     gicd->length = sizeof(*gicd);
 525     gicd->base_address = memmap[VIRT_GIC_DIST].base;
 526     gicd->version = guest_info->gic_version;
 527
 528     for (i = 0; i < guest_info->smp_cpus; i++) {
 529         AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
 530                                                      sizeof *gicc);
 531         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 532
 533         gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
 534         gicc->length = sizeof(*gicc);
 535         if (guest_info->gic_version == 2) {
 536             gicc->base_address = memmap[VIRT_GIC_CPU].base;
 537         }
 538         gicc->cpu_interface_number = i;
 539         gicc->arm_mpidr = armcpu->mp_affinity;
 540         gicc->uid = i;
 541         gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 542
 543         if (armcpu->has_pmu) {
 544             gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
 545         }
 546     }
 547
 548     if (guest_info->gic_version == 3) {
 549         AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
 550                                                          sizeof *gicr);
 551
 552         gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
 553         gicr->length = sizeof(*gicr);
 554         gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
 555         gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
 556     } else {
 557         gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
 558         gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
 559         gic_msi->length = sizeof(*gic_msi);
 560         gic_msi->gic_msi_frame_id = 0;
 561         gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
 562         gic_msi->flags = cpu_to_le32(1);
 563         gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
 564         gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
 565     }
 566
 567     build_header(linker, table_data,
 568                  (void *)(table_data->data + madt_start), "APIC",
 569                  table_data->len - madt_start, 3, NULL, NULL);
 570 }
 571
 572 /* FADT */
 573 static void
 574 build_fadt(GArray *table_data, BIOSLinker *linker, unsigned dsdt_tbl_offset)
 575 {
 576     AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
 577     unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
 578
 579     /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
 580     fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
 581     fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
 582                                        (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
 583
 584     /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
 585     fadt->minor_revision = 0x1;
 586
 587     /* DSDT address to be filled by Guest linker */
 588     bios_linker_loader_add_pointer(linker,
 589         ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
 590         ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
 591
 592     build_header(linker, table_data,
 593                  (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL);
 594 }
 595
 596 /* DSDT */
 597 static void
 598 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 599 {
 600     Aml *scope, *dsdt;
 601     const MemMapEntry *memmap = guest_info->memmap;
 602     const int *irqmap = guest_info->irqmap;
 603
 604     dsdt = init_aml_allocator();
 605     /* Reserve space for header */
 606     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
 607
 608     /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
 609      * While UEFI can use libfdt to disable the RTC device node in the DTB that
 610      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
 611      * the RTC ACPI device at all when using UEFI.
 612      */
 613     scope = aml_scope("\\_SB");
 614     acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
 615     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
 616                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
 617     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 618     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
 619     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
 620                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 621     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
 622                       guest_info->use_highmem);
 623     acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
 624                        (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
 625     acpi_dsdt_add_power_button(scope);
 626
 627     aml_append(dsdt, scope);
 628
 629     /* copy AML table into ACPI tables blob and patch header there */
 630     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 631     build_header(linker, table_data,
 632         (void *)(table_data->data + table_data->len - dsdt->buf->len),
 633         "DSDT", dsdt->buf->len, 2, NULL, NULL);
 634     free_aml_allocator();
 635 }
 636
 637 typedef
 638 struct AcpiBuildState {
 639     /* Copy of table in RAM (for patching). */
 640     MemoryRegion *table_mr;
 641     MemoryRegion *rsdp_mr;
 642     MemoryRegion *linker_mr;
 643     /* Is table patched? */
 644     bool patched;
 645     VirtGuestInfo *guest_info;
 646 } AcpiBuildState;
 647
 648 static
 649 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
 650 {
 651     GArray *table_offsets;
 652     unsigned dsdt, rsdt;
 653     GArray *tables_blob = tables->table_data;
 654
 655     table_offsets = g_array_new(false, true /* clear */,
 656                                         sizeof(uint32_t));
 657
 658     bios_linker_loader_alloc(tables->linker,
 659                              ACPI_BUILD_TABLE_FILE, tables_blob,
 660                              64, false /* high memory */);
 661
 662     /*
 663      * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
 664      * RSDP
 665      * RSDT
 666      * FADT
 667      * GTDT
 668      * MADT
 669      * MCFG
 670      * DSDT
 671      */
 672
 673     /* DSDT is pointed to by FADT */
 674     dsdt = tables_blob->len;
 675     build_dsdt(tables_blob, tables->linker, guest_info);
 676
 677     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
 678     acpi_add_table(table_offsets, tables_blob);
 679     build_fadt(tables_blob, tables->linker, dsdt);
 680
 681     acpi_add_table(table_offsets, tables_blob);
 682     build_madt(tables_blob, tables->linker, guest_info);
 683
 684     acpi_add_table(table_offsets, tables_blob);
 685     build_gtdt(tables_blob, tables->linker);
 686
 687     acpi_add_table(table_offsets, tables_blob);
 688     build_mcfg(tables_blob, tables->linker, guest_info);
 689
 690     acpi_add_table(table_offsets, tables_blob);
 691     build_spcr(tables_blob, tables->linker, guest_info);
 692
 693     if (nb_numa_nodes > 0) {
 694         acpi_add_table(table_offsets, tables_blob);
 695         build_srat(tables_blob, tables->linker, guest_info);
 696     }
 697
 698     /* RSDT is pointed to by RSDP */
 699     rsdt = tables_blob->len;
 700     build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
 701
 702     /* RSDP is in FSEG memory, so allocate it separately */
 703     build_rsdp(tables->rsdp, tables->linker, rsdt);
 704
 705     /* Cleanup memory that's no longer used. */
 706     g_array_free(table_offsets, true);
 707 }
 708
 709 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 710 {
 711     uint32_t size = acpi_data_len(data);
 712
 713     /* Make sure RAM size is correct - in case it got changed
 714      * e.g. by migration */
 715     memory_region_ram_resize(mr, size, &error_abort);
 716
 717     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 718     memory_region_set_dirty(mr, 0, size);
 719 }
 720
 721 static void virt_acpi_build_update(void *build_opaque)
 722 {
 723     AcpiBuildState *build_state = build_opaque;
 724     AcpiBuildTables tables;
 725
 726     /* No state to update or already patched? Nothing to do. */
 727     if (!build_state || build_state->patched) {
 728         return;
 729     }
 730     build_state->patched = true;
 731
 732     acpi_build_tables_init(&tables);
 733
 734     virt_acpi_build(build_state->guest_info, &tables);
 735
 736     acpi_ram_update(build_state->table_mr, tables.table_data);
 737     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 738     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
 739
 740
 741     acpi_build_tables_cleanup(&tables, true);
 742 }
 743
 744 static void virt_acpi_build_reset(void *build_opaque)
 745 {
 746     AcpiBuildState *build_state = build_opaque;
 747     build_state->patched = false;
 748 }
 749
 750 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
 751                                        GArray *blob, const char *name,
 752                                        uint64_t max_size)
 753 {
 754     return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
 755                         name, virt_acpi_build_update, build_state);
 756 }
 757
 758 static const VMStateDescription vmstate_virt_acpi_build = {
 759     .name = "virt_acpi_build",
 760     .version_id = 1,
 761     .minimum_version_id = 1,
 762     .fields = (VMStateField[]) {
 763         VMSTATE_BOOL(patched, AcpiBuildState),
 764         VMSTATE_END_OF_LIST()
 765     },
 766 };
 767
 768 void virt_acpi_setup(VirtGuestInfo *guest_info)
 769 {
 770     AcpiBuildTables tables;
 771     AcpiBuildState *build_state;
 772
 773     if (!guest_info->fw_cfg) {
 774         trace_virt_acpi_setup();
 775         return;
 776     }
 777
 778     if (!acpi_enabled) {
 779         trace_virt_acpi_setup();
 780         return;
 781     }
 782
 783     build_state = g_malloc0(sizeof *build_state);
 784     build_state->guest_info = guest_info;
 785
 786     acpi_build_tables_init(&tables);
 787     virt_acpi_build(build_state->guest_info, &tables);
 788
 789     /* Now expose it all to Guest */
 790     build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
 791                                                ACPI_BUILD_TABLE_FILE,
 792                                                ACPI_BUILD_TABLE_MAX_SIZE);
 793     assert(build_state->table_mr != NULL);
 794
 795     build_state->linker_mr =
 796         acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
 797                           "etc/table-loader", 0);
 798
 799     fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
 800                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
 801
 802     build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
 803                                               ACPI_BUILD_RSDP_FILE, 0);
 804
 805     qemu_register_reset(virt_acpi_build_reset, build_state);
 806     virt_acpi_build_reset(build_state);
 807     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 808
 809     /* Cleanup tables but don't free the memory: we track it
 810      * in build_state.
 811      */
 812     acpi_build_tables_cleanup(&tables, false);
 813 }