2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
26 #include "qemu/osdep.h"
28 #include "disas/disas.h"
29 #include "exec/exec-all.h"
30 #include "tcg/tcg-op.h"
31 #include "exec/helper-proto.h"
33 #include "exec/cpu_ldst.h"
34 #include "exec/translator.h"
35 #include "crisv32-decode.h"
36 #include "qemu/qemu-print.h"
38 #include "exec/helper-gen.h"
40 #include "trace-tcg.h"
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 # define LOG_DIS(...) do { } while (0)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
55 /* is_jmp field values */
56 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
57 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
58 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
59 #define DISAS_SWI DISAS_TARGET_3
61 /* Used by the decoder. */
62 #define EXTRACT_FIELD(src, start, end) \
63 (((src) >> start) & ((1 << (end - start + 1)) - 1))
65 #define CC_MASK_NZ 0xc
66 #define CC_MASK_NZV 0xe
67 #define CC_MASK_NZVC 0xf
68 #define CC_MASK_RNZV 0x10e
70 static TCGv cpu_R
[16];
71 static TCGv cpu_PR
[16];
75 static TCGv cc_result
;
80 static TCGv env_btaken
;
81 static TCGv env_btarget
;
84 #include "exec/gen-icount.h"
86 /* This is the state at translation time. */
87 typedef struct DisasContext
{
92 unsigned int (*decoder
)(CPUCRISState
*env
, struct DisasContext
*dc
);
97 unsigned int zsize
, zzsize
;
111 int cc_size_uptodate
; /* -1 invalid or last written value. */
113 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
114 int flags_uptodate
; /* Whether or not $ccs is up-to-date. */
115 int flagx_known
; /* Whether or not flags_x has the x flag known at
119 int clear_x
; /* Clear x after this insn? */
120 int clear_prefix
; /* Clear prefix after this insn? */
121 int clear_locked_irq
; /* Clear the irq lockout. */
122 int cpustate_changed
;
123 unsigned int tb_flags
; /* tb dependent flags. */
128 #define JMP_DIRECT_CC 2
129 #define JMP_INDIRECT 3
130 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
135 TranslationBlock
*tb
;
136 int singlestep_enabled
;
139 static void gen_BUG(DisasContext
*dc
, const char *file
, int line
)
141 cpu_abort(CPU(dc
->cpu
), "%s:%d pc=%x\n", file
, line
, dc
->pc
);
144 static const char *regnames_v32
[] =
146 "$r0", "$r1", "$r2", "$r3",
147 "$r4", "$r5", "$r6", "$r7",
148 "$r8", "$r9", "$r10", "$r11",
149 "$r12", "$r13", "$sp", "$acr",
151 static const char *pregnames_v32
[] =
153 "$bz", "$vr", "$pid", "$srs",
154 "$wz", "$exs", "$eda", "$mof",
155 "$dz", "$ebp", "$erp", "$srp",
156 "$nrp", "$ccs", "$usp", "$spc",
159 /* We need this table to handle preg-moves with implicit width. */
160 static int preg_sizes
[] = {
171 #define t_gen_mov_TN_env(tn, member) \
172 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
173 #define t_gen_mov_env_TN(member, tn) \
174 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
175 #define t_gen_movi_env_TN(member, c) \
177 TCGv tc = tcg_const_tl(c); \
178 t_gen_mov_env_TN(member, tc); \
182 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
184 assert(r
>= 0 && r
<= 15);
185 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
186 tcg_gen_movi_tl(tn
, 0);
187 } else if (r
== PR_VR
) {
188 tcg_gen_movi_tl(tn
, 32);
190 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
193 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
195 assert(r
>= 0 && r
<= 15);
196 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
198 } else if (r
== PR_SRS
) {
199 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
202 gen_helper_tlb_flush_pid(cpu_env
, tn
);
204 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
) {
205 gen_helper_spc_write(cpu_env
, tn
);
206 } else if (r
== PR_CCS
) {
207 dc
->cpustate_changed
= 1;
209 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
213 /* Sign extend at translation time. */
214 static int sign_extend(unsigned int val
, unsigned int width
)
226 static int cris_fetch(CPUCRISState
*env
, DisasContext
*dc
, uint32_t addr
,
227 unsigned int size
, unsigned int sign
)
234 r
= cpu_ldl_code(env
, addr
);
240 r
= cpu_ldsw_code(env
, addr
);
242 r
= cpu_lduw_code(env
, addr
);
249 r
= cpu_ldsb_code(env
, addr
);
251 r
= cpu_ldub_code(env
, addr
);
256 cpu_abort(CPU(dc
->cpu
), "Invalid fetch size %d\n", size
);
262 static void cris_lock_irq(DisasContext
*dc
)
264 dc
->clear_locked_irq
= 0;
265 t_gen_movi_env_TN(locked_irq
, 1);
268 static inline void t_gen_raise_exception(uint32_t index
)
270 TCGv_i32 tmp
= tcg_const_i32(index
);
271 gen_helper_raise_exception(cpu_env
, tmp
);
272 tcg_temp_free_i32(tmp
);
275 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
280 t_31
= tcg_const_tl(31);
281 tcg_gen_shl_tl(d
, a
, b
);
283 tcg_gen_sub_tl(t0
, t_31
, b
);
284 tcg_gen_sar_tl(t0
, t0
, t_31
);
285 tcg_gen_and_tl(t0
, t0
, d
);
286 tcg_gen_xor_tl(d
, d
, t0
);
291 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
296 t_31
= tcg_temp_new();
297 tcg_gen_shr_tl(d
, a
, b
);
299 tcg_gen_movi_tl(t_31
, 31);
300 tcg_gen_sub_tl(t0
, t_31
, b
);
301 tcg_gen_sar_tl(t0
, t0
, t_31
);
302 tcg_gen_and_tl(t0
, t0
, d
);
303 tcg_gen_xor_tl(d
, d
, t0
);
308 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
313 t_31
= tcg_temp_new();
314 tcg_gen_sar_tl(d
, a
, b
);
316 tcg_gen_movi_tl(t_31
, 31);
317 tcg_gen_sub_tl(t0
, t_31
, b
);
318 tcg_gen_sar_tl(t0
, t0
, t_31
);
319 tcg_gen_or_tl(d
, d
, t0
);
324 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
326 TCGv t
= tcg_temp_new();
333 tcg_gen_shli_tl(d
, a
, 1);
334 tcg_gen_sub_tl(t
, d
, b
);
335 tcg_gen_movcond_tl(TCG_COND_GEU
, d
, d
, b
, t
, d
);
339 static void t_gen_cris_mstep(TCGv d
, TCGv a
, TCGv b
, TCGv ccs
)
349 tcg_gen_shli_tl(d
, a
, 1);
350 tcg_gen_shli_tl(t
, ccs
, 31 - 3);
351 tcg_gen_sari_tl(t
, t
, 31);
352 tcg_gen_and_tl(t
, t
, b
);
353 tcg_gen_add_tl(d
, d
, t
);
357 /* Extended arithmetics on CRIS. */
358 static inline void t_gen_add_flag(TCGv d
, int flag
)
363 t_gen_mov_TN_preg(c
, PR_CCS
);
364 /* Propagate carry into d. */
365 tcg_gen_andi_tl(c
, c
, 1 << flag
);
367 tcg_gen_shri_tl(c
, c
, flag
);
369 tcg_gen_add_tl(d
, d
, c
);
373 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
375 if (dc
->flagx_known
) {
380 t_gen_mov_TN_preg(c
, PR_CCS
);
381 /* C flag is already at bit 0. */
382 tcg_gen_andi_tl(c
, c
, C_FLAG
);
383 tcg_gen_add_tl(d
, d
, c
);
391 t_gen_mov_TN_preg(x
, PR_CCS
);
392 tcg_gen_mov_tl(c
, x
);
394 /* Propagate carry into d if X is set. Branch free. */
395 tcg_gen_andi_tl(c
, c
, C_FLAG
);
396 tcg_gen_andi_tl(x
, x
, X_FLAG
);
397 tcg_gen_shri_tl(x
, x
, 4);
399 tcg_gen_and_tl(x
, x
, c
);
400 tcg_gen_add_tl(d
, d
, x
);
406 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
408 if (dc
->flagx_known
) {
413 t_gen_mov_TN_preg(c
, PR_CCS
);
414 /* C flag is already at bit 0. */
415 tcg_gen_andi_tl(c
, c
, C_FLAG
);
416 tcg_gen_sub_tl(d
, d
, c
);
424 t_gen_mov_TN_preg(x
, PR_CCS
);
425 tcg_gen_mov_tl(c
, x
);
427 /* Propagate carry into d if X is set. Branch free. */
428 tcg_gen_andi_tl(c
, c
, C_FLAG
);
429 tcg_gen_andi_tl(x
, x
, X_FLAG
);
430 tcg_gen_shri_tl(x
, x
, 4);
432 tcg_gen_and_tl(x
, x
, c
);
433 tcg_gen_sub_tl(d
, d
, x
);
439 /* Swap the two bytes within each half word of the s operand.
440 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
441 static inline void t_gen_swapb(TCGv d
, TCGv s
)
446 org_s
= tcg_temp_new();
448 /* d and s may refer to the same object. */
449 tcg_gen_mov_tl(org_s
, s
);
450 tcg_gen_shli_tl(t
, org_s
, 8);
451 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
452 tcg_gen_shri_tl(t
, org_s
, 8);
453 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
454 tcg_gen_or_tl(d
, d
, t
);
456 tcg_temp_free(org_s
);
459 /* Swap the halfwords of the s operand. */
460 static inline void t_gen_swapw(TCGv d
, TCGv s
)
463 /* d and s refer the same object. */
465 tcg_gen_mov_tl(t
, s
);
466 tcg_gen_shli_tl(d
, t
, 16);
467 tcg_gen_shri_tl(t
, t
, 16);
468 tcg_gen_or_tl(d
, d
, t
);
472 /* Reverse the within each byte.
473 T0 = (((T0 << 7) & 0x80808080) |
474 ((T0 << 5) & 0x40404040) |
475 ((T0 << 3) & 0x20202020) |
476 ((T0 << 1) & 0x10101010) |
477 ((T0 >> 1) & 0x08080808) |
478 ((T0 >> 3) & 0x04040404) |
479 ((T0 >> 5) & 0x02020202) |
480 ((T0 >> 7) & 0x01010101));
482 static inline void t_gen_swapr(TCGv d
, TCGv s
)
485 int shift
; /* LSL when positive, LSR when negative. */
500 /* d and s refer the same object. */
502 org_s
= tcg_temp_new();
503 tcg_gen_mov_tl(org_s
, s
);
505 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
506 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
507 for (i
= 1; i
< ARRAY_SIZE(bitrev
); i
++) {
508 if (bitrev
[i
].shift
>= 0) {
509 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
511 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
513 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
514 tcg_gen_or_tl(d
, d
, t
);
517 tcg_temp_free(org_s
);
520 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
522 TCGLabel
*l1
= gen_new_label();
524 /* Conditional jmp. */
525 tcg_gen_mov_tl(env_pc
, pc_false
);
526 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
527 tcg_gen_mov_tl(env_pc
, pc_true
);
531 static inline bool use_goto_tb(DisasContext
*dc
, target_ulong dest
)
533 #ifndef CONFIG_USER_ONLY
534 return (dc
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
535 (dc
->ppc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
541 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
543 if (use_goto_tb(dc
, dest
)) {
545 tcg_gen_movi_tl(env_pc
, dest
);
546 tcg_gen_exit_tb(dc
->tb
, n
);
548 tcg_gen_movi_tl(env_pc
, dest
);
549 tcg_gen_exit_tb(NULL
, 0);
553 static inline void cris_clear_x_flag(DisasContext
*dc
)
555 if (dc
->flagx_known
&& dc
->flags_x
) {
556 dc
->flags_uptodate
= 0;
563 static void cris_flush_cc_state(DisasContext
*dc
)
565 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
566 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
567 dc
->cc_size_uptodate
= dc
->cc_size
;
569 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
570 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
573 static void cris_evaluate_flags(DisasContext
*dc
)
575 if (dc
->flags_uptodate
) {
579 cris_flush_cc_state(dc
);
583 gen_helper_evaluate_flags_mcp(cpu_PR
[PR_CCS
], cpu_env
,
584 cpu_PR
[PR_CCS
], cc_src
,
588 gen_helper_evaluate_flags_muls(cpu_PR
[PR_CCS
], cpu_env
,
589 cpu_PR
[PR_CCS
], cc_result
,
593 gen_helper_evaluate_flags_mulu(cpu_PR
[PR_CCS
], cpu_env
,
594 cpu_PR
[PR_CCS
], cc_result
,
604 switch (dc
->cc_size
) {
606 gen_helper_evaluate_flags_move_4(cpu_PR
[PR_CCS
],
607 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
610 gen_helper_evaluate_flags_move_2(cpu_PR
[PR_CCS
],
611 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
614 gen_helper_evaluate_flags(cpu_env
);
623 if (dc
->cc_size
== 4) {
624 gen_helper_evaluate_flags_sub_4(cpu_PR
[PR_CCS
], cpu_env
,
625 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
627 gen_helper_evaluate_flags(cpu_env
);
632 switch (dc
->cc_size
) {
634 gen_helper_evaluate_flags_alu_4(cpu_PR
[PR_CCS
], cpu_env
,
635 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
638 gen_helper_evaluate_flags(cpu_env
);
644 if (dc
->flagx_known
) {
646 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], X_FLAG
);
647 } else if (dc
->cc_op
== CC_OP_FLAGS
) {
648 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
651 dc
->flags_uptodate
= 1;
654 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
663 /* Check if we need to evaluate the condition codes due to
665 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
667 /* TODO: optimize this case. It trigs all the time. */
668 cris_evaluate_flags(dc
);
674 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
678 dc
->flags_uptodate
= 0;
681 static inline void cris_update_cc_x(DisasContext
*dc
)
683 /* Save the x flag state at the time of the cc snapshot. */
684 if (dc
->flagx_known
) {
685 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
)) {
688 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
689 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
691 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
692 dc
->cc_x_uptodate
= 1;
696 /* Update cc prior to executing ALU op. Needs source operands untouched. */
697 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
698 TCGv dst
, TCGv src
, int size
)
701 cris_update_cc_op(dc
, op
, size
);
702 tcg_gen_mov_tl(cc_src
, src
);
710 && op
!= CC_OP_LSL
) {
711 tcg_gen_mov_tl(cc_dest
, dst
);
714 cris_update_cc_x(dc
);
718 /* Update cc after executing ALU op. needs the result. */
719 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
722 tcg_gen_mov_tl(cc_result
, res
);
726 /* Returns one if the write back stage should execute. */
727 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
728 TCGv dst
, TCGv a
, TCGv b
, int size
)
730 /* Emit the ALU insns. */
733 tcg_gen_add_tl(dst
, a
, b
);
734 /* Extended arithmetics. */
735 t_gen_addx_carry(dc
, dst
);
738 tcg_gen_add_tl(dst
, a
, b
);
739 t_gen_add_flag(dst
, 0); /* C_FLAG. */
742 tcg_gen_add_tl(dst
, a
, b
);
743 t_gen_add_flag(dst
, 8); /* R_FLAG. */
746 tcg_gen_sub_tl(dst
, a
, b
);
747 /* Extended arithmetics. */
748 t_gen_subx_carry(dc
, dst
);
751 tcg_gen_mov_tl(dst
, b
);
754 tcg_gen_or_tl(dst
, a
, b
);
757 tcg_gen_and_tl(dst
, a
, b
);
760 tcg_gen_xor_tl(dst
, a
, b
);
763 t_gen_lsl(dst
, a
, b
);
766 t_gen_lsr(dst
, a
, b
);
769 t_gen_asr(dst
, a
, b
);
772 tcg_gen_neg_tl(dst
, b
);
773 /* Extended arithmetics. */
774 t_gen_subx_carry(dc
, dst
);
777 tcg_gen_clzi_tl(dst
, b
, TARGET_LONG_BITS
);
780 tcg_gen_muls2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
783 tcg_gen_mulu2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
786 t_gen_cris_dstep(dst
, a
, b
);
789 t_gen_cris_mstep(dst
, a
, b
, cpu_PR
[PR_CCS
]);
792 tcg_gen_movcond_tl(TCG_COND_LEU
, dst
, a
, b
, a
, b
);
795 tcg_gen_sub_tl(dst
, a
, b
);
796 /* Extended arithmetics. */
797 t_gen_subx_carry(dc
, dst
);
800 qemu_log_mask(LOG_GUEST_ERROR
, "illegal ALU op.\n");
806 tcg_gen_andi_tl(dst
, dst
, 0xff);
807 } else if (size
== 2) {
808 tcg_gen_andi_tl(dst
, dst
, 0xffff);
812 static void cris_alu(DisasContext
*dc
, int op
,
813 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
820 if (op
== CC_OP_CMP
) {
821 tmp
= tcg_temp_new();
823 } else if (size
== 4) {
827 tmp
= tcg_temp_new();
831 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
832 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
833 cris_update_result(dc
, tmp
);
838 tcg_gen_andi_tl(d
, d
, ~0xff);
840 tcg_gen_andi_tl(d
, d
, ~0xffff);
842 tcg_gen_or_tl(d
, d
, tmp
);
849 static int arith_cc(DisasContext
*dc
)
853 case CC_OP_ADDC
: return 1;
854 case CC_OP_ADD
: return 1;
855 case CC_OP_SUB
: return 1;
856 case CC_OP_DSTEP
: return 1;
857 case CC_OP_LSL
: return 1;
858 case CC_OP_LSR
: return 1;
859 case CC_OP_ASR
: return 1;
860 case CC_OP_CMP
: return 1;
861 case CC_OP_NEG
: return 1;
862 case CC_OP_OR
: return 1;
863 case CC_OP_AND
: return 1;
864 case CC_OP_XOR
: return 1;
865 case CC_OP_MULU
: return 1;
866 case CC_OP_MULS
: return 1;
874 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
876 int arith_opt
, move_opt
;
878 /* TODO: optimize more condition codes. */
881 * If the flags are live, we've gotta look into the bits of CCS.
882 * Otherwise, if we just did an arithmetic operation we try to
883 * evaluate the condition code faster.
885 * When this function is done, T0 should be non-zero if the condition
888 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
889 move_opt
= (dc
->cc_op
== CC_OP_MOVE
);
892 if ((arith_opt
|| move_opt
)
893 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
894 tcg_gen_setcondi_tl(TCG_COND_EQ
, cc
, cc_result
, 0);
896 cris_evaluate_flags(dc
);
898 cpu_PR
[PR_CCS
], Z_FLAG
);
902 if ((arith_opt
|| move_opt
)
903 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
904 tcg_gen_mov_tl(cc
, cc_result
);
906 cris_evaluate_flags(dc
);
907 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
909 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
913 cris_evaluate_flags(dc
);
914 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
917 cris_evaluate_flags(dc
);
918 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
919 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
922 cris_evaluate_flags(dc
);
923 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
926 cris_evaluate_flags(dc
);
927 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
929 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
932 if (arith_opt
|| move_opt
) {
935 if (dc
->cc_size
== 1) {
937 } else if (dc
->cc_size
== 2) {
941 tcg_gen_shri_tl(cc
, cc_result
, bits
);
942 tcg_gen_xori_tl(cc
, cc
, 1);
944 cris_evaluate_flags(dc
);
945 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
947 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
951 if (arith_opt
|| move_opt
) {
954 if (dc
->cc_size
== 1) {
956 } else if (dc
->cc_size
== 2) {
960 tcg_gen_shri_tl(cc
, cc_result
, bits
);
961 tcg_gen_andi_tl(cc
, cc
, 1);
963 cris_evaluate_flags(dc
);
964 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
969 cris_evaluate_flags(dc
);
970 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
974 cris_evaluate_flags(dc
);
978 tmp
= tcg_temp_new();
979 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
981 /* Overlay the C flag on top of the Z. */
982 tcg_gen_shli_tl(cc
, tmp
, 2);
983 tcg_gen_and_tl(cc
, tmp
, cc
);
984 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
990 cris_evaluate_flags(dc
);
991 /* Overlay the V flag on top of the N. */
992 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
995 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
996 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
999 cris_evaluate_flags(dc
);
1000 /* Overlay the V flag on top of the N. */
1001 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1003 cpu_PR
[PR_CCS
], cc
);
1004 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1007 cris_evaluate_flags(dc
);
1014 /* To avoid a shift we overlay everything on
1016 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1017 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1019 tcg_gen_xori_tl(z
, z
, 2);
1021 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1022 tcg_gen_xori_tl(n
, n
, 2);
1023 tcg_gen_and_tl(cc
, z
, n
);
1024 tcg_gen_andi_tl(cc
, cc
, 2);
1031 cris_evaluate_flags(dc
);
1038 /* To avoid a shift we overlay everything on
1040 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1041 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1043 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1044 tcg_gen_or_tl(cc
, z
, n
);
1045 tcg_gen_andi_tl(cc
, cc
, 2);
1052 cris_evaluate_flags(dc
);
1053 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1056 tcg_gen_movi_tl(cc
, 1);
1064 static void cris_store_direct_jmp(DisasContext
*dc
)
1066 /* Store the direct jmp state into the cpu-state. */
1067 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1068 if (dc
->jmp
== JMP_DIRECT
) {
1069 tcg_gen_movi_tl(env_btaken
, 1);
1071 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1072 dc
->jmp
= JMP_INDIRECT
;
1076 static void cris_prepare_cc_branch (DisasContext
*dc
,
1077 int offset
, int cond
)
1079 /* This helps us re-schedule the micro-code to insns in delay-slots
1080 before the actual jump. */
1081 dc
->delayed_branch
= 2;
1082 dc
->jmp
= JMP_DIRECT_CC
;
1083 dc
->jmp_pc
= dc
->pc
+ offset
;
1085 gen_tst_cc(dc
, env_btaken
, cond
);
1086 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1090 /* jumps, when the dest is in a live reg for example. Direct should be set
1091 when the dest addr is constant to allow tb chaining. */
1092 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1094 /* This helps us re-schedule the micro-code to insns in delay-slots
1095 before the actual jump. */
1096 dc
->delayed_branch
= 2;
1098 if (type
== JMP_INDIRECT
) {
1099 tcg_gen_movi_tl(env_btaken
, 1);
1103 static void gen_load64(DisasContext
*dc
, TCGv_i64 dst
, TCGv addr
)
1105 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1107 /* If we get a fault on a delayslot we must keep the jmp state in
1108 the cpu-state to be able to re-execute the jmp. */
1109 if (dc
->delayed_branch
== 1) {
1110 cris_store_direct_jmp(dc
);
1113 tcg_gen_qemu_ld_i64(dst
, addr
, mem_index
, MO_TEQ
);
1116 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1117 unsigned int size
, int sign
)
1119 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1121 /* If we get a fault on a delayslot we must keep the jmp state in
1122 the cpu-state to be able to re-execute the jmp. */
1123 if (dc
->delayed_branch
== 1) {
1124 cris_store_direct_jmp(dc
);
1127 tcg_gen_qemu_ld_tl(dst
, addr
, mem_index
,
1128 MO_TE
+ ctz32(size
) + (sign
? MO_SIGN
: 0));
1131 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1134 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1136 /* If we get a fault on a delayslot we must keep the jmp state in
1137 the cpu-state to be able to re-execute the jmp. */
1138 if (dc
->delayed_branch
== 1) {
1139 cris_store_direct_jmp(dc
);
1143 /* Conditional writes. We only support the kind were X and P are known
1144 at translation time. */
1145 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1147 cris_evaluate_flags(dc
);
1148 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1152 tcg_gen_qemu_st_tl(val
, addr
, mem_index
, MO_TE
+ ctz32(size
));
1154 if (dc
->flagx_known
&& dc
->flags_x
) {
1155 cris_evaluate_flags(dc
);
1156 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1160 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1163 tcg_gen_ext8s_i32(d
, s
);
1164 } else if (size
== 2) {
1165 tcg_gen_ext16s_i32(d
, s
);
1167 tcg_gen_mov_tl(d
, s
);
1171 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1174 tcg_gen_ext8u_i32(d
, s
);
1175 } else if (size
== 2) {
1176 tcg_gen_ext16u_i32(d
, s
);
1178 tcg_gen_mov_tl(d
, s
);
1183 static char memsize_char(int size
)
1195 static inline unsigned int memsize_z(DisasContext
*dc
)
1197 return dc
->zsize
+ 1;
1200 static inline unsigned int memsize_zz(DisasContext
*dc
)
1202 switch (dc
->zzsize
) {
1210 static inline void do_postinc (DisasContext
*dc
, int size
)
1213 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1217 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1218 int size
, int s_ext
, TCGv dst
)
1221 t_gen_sext(dst
, cpu_R
[rs
], size
);
1223 t_gen_zext(dst
, cpu_R
[rs
], size
);
1227 /* Prepare T0 and T1 for a register alu operation.
1228 s_ext decides if the operand1 should be sign-extended or zero-extended when
1230 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1231 int size
, int s_ext
, TCGv dst
, TCGv src
)
1233 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1236 t_gen_sext(dst
, cpu_R
[rd
], size
);
1238 t_gen_zext(dst
, cpu_R
[rd
], size
);
1242 static int dec_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
1243 int s_ext
, int memsize
, TCGv dst
)
1251 is_imm
= rs
== 15 && dc
->postinc
;
1253 /* Load [$rs] onto T1. */
1255 insn_len
= 2 + memsize
;
1260 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, memsize
, s_ext
);
1261 tcg_gen_movi_tl(dst
, imm
);
1264 cris_flush_cc_state(dc
);
1265 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1267 t_gen_sext(dst
, dst
, memsize
);
1269 t_gen_zext(dst
, dst
, memsize
);
1275 /* Prepare T0 and T1 for a memory + alu operation.
1276 s_ext decides if the operand1 should be sign-extended or zero-extended when
1278 static int dec_prep_alu_m(CPUCRISState
*env
, DisasContext
*dc
,
1279 int s_ext
, int memsize
, TCGv dst
, TCGv src
)
1283 insn_len
= dec_prep_move_m(env
, dc
, s_ext
, memsize
, src
);
1284 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1289 static const char *cc_name(int cc
)
1291 static const char *cc_names
[16] = {
1292 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1293 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1296 return cc_names
[cc
];
1300 /* Start of insn decoders. */
1302 static int dec_bccq(CPUCRISState
*env
, DisasContext
*dc
)
1306 uint32_t cond
= dc
->op2
;
1308 offset
= EXTRACT_FIELD(dc
->ir
, 1, 7);
1309 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1312 offset
|= sign
<< 8;
1313 offset
= sign_extend(offset
, 8);
1315 LOG_DIS("b%s %x\n", cc_name(cond
), dc
->pc
+ offset
);
1317 /* op2 holds the condition-code. */
1318 cris_cc_mask(dc
, 0);
1319 cris_prepare_cc_branch(dc
, offset
, cond
);
1322 static int dec_addoq(CPUCRISState
*env
, DisasContext
*dc
)
1326 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1327 imm
= sign_extend(dc
->op1
, 7);
1329 LOG_DIS("addoq %d, $r%u\n", imm
, dc
->op2
);
1330 cris_cc_mask(dc
, 0);
1331 /* Fetch register operand, */
1332 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1336 static int dec_addq(CPUCRISState
*env
, DisasContext
*dc
)
1339 LOG_DIS("addq %u, $r%u\n", dc
->op1
, dc
->op2
);
1341 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1343 cris_cc_mask(dc
, CC_MASK_NZVC
);
1345 c
= tcg_const_tl(dc
->op1
);
1346 cris_alu(dc
, CC_OP_ADD
,
1347 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], c
, 4);
1351 static int dec_moveq(CPUCRISState
*env
, DisasContext
*dc
)
1355 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1356 imm
= sign_extend(dc
->op1
, 5);
1357 LOG_DIS("moveq %d, $r%u\n", imm
, dc
->op2
);
1359 tcg_gen_movi_tl(cpu_R
[dc
->op2
], imm
);
1362 static int dec_subq(CPUCRISState
*env
, DisasContext
*dc
)
1365 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1367 LOG_DIS("subq %u, $r%u\n", dc
->op1
, dc
->op2
);
1369 cris_cc_mask(dc
, CC_MASK_NZVC
);
1370 c
= tcg_const_tl(dc
->op1
);
1371 cris_alu(dc
, CC_OP_SUB
,
1372 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], c
, 4);
1376 static int dec_cmpq(CPUCRISState
*env
, DisasContext
*dc
)
1380 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1381 imm
= sign_extend(dc
->op1
, 5);
1383 LOG_DIS("cmpq %d, $r%d\n", imm
, dc
->op2
);
1384 cris_cc_mask(dc
, CC_MASK_NZVC
);
1386 c
= tcg_const_tl(imm
);
1387 cris_alu(dc
, CC_OP_CMP
,
1388 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], c
, 4);
1392 static int dec_andq(CPUCRISState
*env
, DisasContext
*dc
)
1396 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1397 imm
= sign_extend(dc
->op1
, 5);
1399 LOG_DIS("andq %d, $r%d\n", imm
, dc
->op2
);
1400 cris_cc_mask(dc
, CC_MASK_NZ
);
1402 c
= tcg_const_tl(imm
);
1403 cris_alu(dc
, CC_OP_AND
,
1404 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], c
, 4);
1408 static int dec_orq(CPUCRISState
*env
, DisasContext
*dc
)
1412 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1413 imm
= sign_extend(dc
->op1
, 5);
1414 LOG_DIS("orq %d, $r%d\n", imm
, dc
->op2
);
1415 cris_cc_mask(dc
, CC_MASK_NZ
);
1417 c
= tcg_const_tl(imm
);
1418 cris_alu(dc
, CC_OP_OR
,
1419 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], c
, 4);
1423 static int dec_btstq(CPUCRISState
*env
, DisasContext
*dc
)
1426 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1427 LOG_DIS("btstq %u, $r%d\n", dc
->op1
, dc
->op2
);
1429 cris_cc_mask(dc
, CC_MASK_NZ
);
1430 c
= tcg_const_tl(dc
->op1
);
1431 cris_evaluate_flags(dc
);
1432 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1435 cris_alu(dc
, CC_OP_MOVE
,
1436 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1437 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1438 dc
->flags_uptodate
= 1;
1441 static int dec_asrq(CPUCRISState
*env
, DisasContext
*dc
)
1443 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1444 LOG_DIS("asrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1445 cris_cc_mask(dc
, CC_MASK_NZ
);
1447 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1448 cris_alu(dc
, CC_OP_MOVE
,
1450 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1453 static int dec_lslq(CPUCRISState
*env
, DisasContext
*dc
)
1455 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1456 LOG_DIS("lslq %u, $r%d\n", dc
->op1
, dc
->op2
);
1458 cris_cc_mask(dc
, CC_MASK_NZ
);
1460 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1462 cris_alu(dc
, CC_OP_MOVE
,
1464 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1467 static int dec_lsrq(CPUCRISState
*env
, DisasContext
*dc
)
1469 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1470 LOG_DIS("lsrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1472 cris_cc_mask(dc
, CC_MASK_NZ
);
1474 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1475 cris_alu(dc
, CC_OP_MOVE
,
1477 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1481 static int dec_move_r(CPUCRISState
*env
, DisasContext
*dc
)
1483 int size
= memsize_zz(dc
);
1485 LOG_DIS("move.%c $r%u, $r%u\n",
1486 memsize_char(size
), dc
->op1
, dc
->op2
);
1488 cris_cc_mask(dc
, CC_MASK_NZ
);
1490 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1491 cris_cc_mask(dc
, CC_MASK_NZ
);
1492 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1493 cris_update_cc_x(dc
);
1494 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1498 t0
= tcg_temp_new();
1499 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1500 cris_alu(dc
, CC_OP_MOVE
,
1502 cpu_R
[dc
->op2
], t0
, size
);
1508 static int dec_scc_r(CPUCRISState
*env
, DisasContext
*dc
)
1512 LOG_DIS("s%s $r%u\n",
1513 cc_name(cond
), dc
->op1
);
1515 gen_tst_cc(dc
, cpu_R
[dc
->op1
], cond
);
1516 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], 0);
1518 cris_cc_mask(dc
, 0);
1522 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1525 t
[0] = cpu_R
[dc
->op2
];
1526 t
[1] = cpu_R
[dc
->op1
];
1528 t
[0] = tcg_temp_new();
1529 t
[1] = tcg_temp_new();
1533 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1536 tcg_temp_free(t
[0]);
1537 tcg_temp_free(t
[1]);
1541 static int dec_and_r(CPUCRISState
*env
, DisasContext
*dc
)
1544 int size
= memsize_zz(dc
);
1546 LOG_DIS("and.%c $r%u, $r%u\n",
1547 memsize_char(size
), dc
->op1
, dc
->op2
);
1549 cris_cc_mask(dc
, CC_MASK_NZ
);
1551 cris_alu_alloc_temps(dc
, size
, t
);
1552 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1553 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1554 cris_alu_free_temps(dc
, size
, t
);
1558 static int dec_lz_r(CPUCRISState
*env
, DisasContext
*dc
)
1561 LOG_DIS("lz $r%u, $r%u\n",
1563 cris_cc_mask(dc
, CC_MASK_NZ
);
1564 t0
= tcg_temp_new();
1565 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1566 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1571 static int dec_lsl_r(CPUCRISState
*env
, DisasContext
*dc
)
1574 int size
= memsize_zz(dc
);
1576 LOG_DIS("lsl.%c $r%u, $r%u\n",
1577 memsize_char(size
), dc
->op1
, dc
->op2
);
1579 cris_cc_mask(dc
, CC_MASK_NZ
);
1580 cris_alu_alloc_temps(dc
, size
, t
);
1581 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1582 tcg_gen_andi_tl(t
[1], t
[1], 63);
1583 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1584 cris_alu_free_temps(dc
, size
, t
);
1588 static int dec_lsr_r(CPUCRISState
*env
, DisasContext
*dc
)
1591 int size
= memsize_zz(dc
);
1593 LOG_DIS("lsr.%c $r%u, $r%u\n",
1594 memsize_char(size
), dc
->op1
, dc
->op2
);
1596 cris_cc_mask(dc
, CC_MASK_NZ
);
1597 cris_alu_alloc_temps(dc
, size
, t
);
1598 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1599 tcg_gen_andi_tl(t
[1], t
[1], 63);
1600 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1601 cris_alu_free_temps(dc
, size
, t
);
1605 static int dec_asr_r(CPUCRISState
*env
, DisasContext
*dc
)
1608 int size
= memsize_zz(dc
);
1610 LOG_DIS("asr.%c $r%u, $r%u\n",
1611 memsize_char(size
), dc
->op1
, dc
->op2
);
1613 cris_cc_mask(dc
, CC_MASK_NZ
);
1614 cris_alu_alloc_temps(dc
, size
, t
);
1615 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1616 tcg_gen_andi_tl(t
[1], t
[1], 63);
1617 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1618 cris_alu_free_temps(dc
, size
, t
);
1622 static int dec_muls_r(CPUCRISState
*env
, DisasContext
*dc
)
1625 int size
= memsize_zz(dc
);
1627 LOG_DIS("muls.%c $r%u, $r%u\n",
1628 memsize_char(size
), dc
->op1
, dc
->op2
);
1629 cris_cc_mask(dc
, CC_MASK_NZV
);
1630 cris_alu_alloc_temps(dc
, size
, t
);
1631 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1633 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1634 cris_alu_free_temps(dc
, size
, t
);
1638 static int dec_mulu_r(CPUCRISState
*env
, DisasContext
*dc
)
1641 int size
= memsize_zz(dc
);
1643 LOG_DIS("mulu.%c $r%u, $r%u\n",
1644 memsize_char(size
), dc
->op1
, dc
->op2
);
1645 cris_cc_mask(dc
, CC_MASK_NZV
);
1646 cris_alu_alloc_temps(dc
, size
, t
);
1647 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1649 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1650 cris_alu_free_temps(dc
, size
, t
);
1655 static int dec_dstep_r(CPUCRISState
*env
, DisasContext
*dc
)
1657 LOG_DIS("dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
);
1658 cris_cc_mask(dc
, CC_MASK_NZ
);
1659 cris_alu(dc
, CC_OP_DSTEP
,
1660 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1664 static int dec_xor_r(CPUCRISState
*env
, DisasContext
*dc
)
1667 int size
= memsize_zz(dc
);
1668 LOG_DIS("xor.%c $r%u, $r%u\n",
1669 memsize_char(size
), dc
->op1
, dc
->op2
);
1670 BUG_ON(size
!= 4); /* xor is dword. */
1671 cris_cc_mask(dc
, CC_MASK_NZ
);
1672 cris_alu_alloc_temps(dc
, size
, t
);
1673 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1675 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1676 cris_alu_free_temps(dc
, size
, t
);
1680 static int dec_bound_r(CPUCRISState
*env
, DisasContext
*dc
)
1683 int size
= memsize_zz(dc
);
1684 LOG_DIS("bound.%c $r%u, $r%u\n",
1685 memsize_char(size
), dc
->op1
, dc
->op2
);
1686 cris_cc_mask(dc
, CC_MASK_NZ
);
1687 l0
= tcg_temp_local_new();
1688 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1689 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1694 static int dec_cmp_r(CPUCRISState
*env
, DisasContext
*dc
)
1697 int size
= memsize_zz(dc
);
1698 LOG_DIS("cmp.%c $r%u, $r%u\n",
1699 memsize_char(size
), dc
->op1
, dc
->op2
);
1700 cris_cc_mask(dc
, CC_MASK_NZVC
);
1701 cris_alu_alloc_temps(dc
, size
, t
);
1702 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1704 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1705 cris_alu_free_temps(dc
, size
, t
);
1709 static int dec_abs_r(CPUCRISState
*env
, DisasContext
*dc
)
1711 LOG_DIS("abs $r%u, $r%u\n",
1713 cris_cc_mask(dc
, CC_MASK_NZ
);
1715 tcg_gen_abs_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
]);
1716 cris_alu(dc
, CC_OP_MOVE
,
1717 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1721 static int dec_add_r(CPUCRISState
*env
, DisasContext
*dc
)
1724 int size
= memsize_zz(dc
);
1725 LOG_DIS("add.%c $r%u, $r%u\n",
1726 memsize_char(size
), dc
->op1
, dc
->op2
);
1727 cris_cc_mask(dc
, CC_MASK_NZVC
);
1728 cris_alu_alloc_temps(dc
, size
, t
);
1729 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1731 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1732 cris_alu_free_temps(dc
, size
, t
);
1736 static int dec_addc_r(CPUCRISState
*env
, DisasContext
*dc
)
1738 LOG_DIS("addc $r%u, $r%u\n",
1740 cris_evaluate_flags(dc
);
1741 /* Set for this insn. */
1742 dc
->flagx_known
= 1;
1743 dc
->flags_x
= X_FLAG
;
1745 cris_cc_mask(dc
, CC_MASK_NZVC
);
1746 cris_alu(dc
, CC_OP_ADDC
,
1747 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1751 static int dec_mcp_r(CPUCRISState
*env
, DisasContext
*dc
)
1753 LOG_DIS("mcp $p%u, $r%u\n",
1755 cris_evaluate_flags(dc
);
1756 cris_cc_mask(dc
, CC_MASK_RNZV
);
1757 cris_alu(dc
, CC_OP_MCP
,
1758 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1763 static char * swapmode_name(int mode
, char *modename
) {
1766 modename
[i
++] = 'n';
1769 modename
[i
++] = 'w';
1772 modename
[i
++] = 'b';
1775 modename
[i
++] = 'r';
1782 static int dec_swap_r(CPUCRISState
*env
, DisasContext
*dc
)
1788 LOG_DIS("swap%s $r%u\n",
1789 swapmode_name(dc
->op2
, modename
), dc
->op1
);
1791 cris_cc_mask(dc
, CC_MASK_NZ
);
1792 t0
= tcg_temp_new();
1793 tcg_gen_mov_tl(t0
, cpu_R
[dc
->op1
]);
1795 tcg_gen_not_tl(t0
, t0
);
1798 t_gen_swapw(t0
, t0
);
1801 t_gen_swapb(t0
, t0
);
1804 t_gen_swapr(t0
, t0
);
1806 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1811 static int dec_or_r(CPUCRISState
*env
, DisasContext
*dc
)
1814 int size
= memsize_zz(dc
);
1815 LOG_DIS("or.%c $r%u, $r%u\n",
1816 memsize_char(size
), dc
->op1
, dc
->op2
);
1817 cris_cc_mask(dc
, CC_MASK_NZ
);
1818 cris_alu_alloc_temps(dc
, size
, t
);
1819 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1820 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1821 cris_alu_free_temps(dc
, size
, t
);
1825 static int dec_addi_r(CPUCRISState
*env
, DisasContext
*dc
)
1828 LOG_DIS("addi.%c $r%u, $r%u\n",
1829 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1830 cris_cc_mask(dc
, 0);
1831 t0
= tcg_temp_new();
1832 tcg_gen_shli_tl(t0
, cpu_R
[dc
->op2
], dc
->zzsize
);
1833 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1838 static int dec_addi_acr(CPUCRISState
*env
, DisasContext
*dc
)
1841 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1842 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1843 cris_cc_mask(dc
, 0);
1844 t0
= tcg_temp_new();
1845 tcg_gen_shli_tl(t0
, cpu_R
[dc
->op2
], dc
->zzsize
);
1846 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1851 static int dec_neg_r(CPUCRISState
*env
, DisasContext
*dc
)
1854 int size
= memsize_zz(dc
);
1855 LOG_DIS("neg.%c $r%u, $r%u\n",
1856 memsize_char(size
), dc
->op1
, dc
->op2
);
1857 cris_cc_mask(dc
, CC_MASK_NZVC
);
1858 cris_alu_alloc_temps(dc
, size
, t
);
1859 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1861 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1862 cris_alu_free_temps(dc
, size
, t
);
1866 static int dec_btst_r(CPUCRISState
*env
, DisasContext
*dc
)
1868 LOG_DIS("btst $r%u, $r%u\n",
1870 cris_cc_mask(dc
, CC_MASK_NZ
);
1871 cris_evaluate_flags(dc
);
1872 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1873 cpu_R
[dc
->op1
], cpu_PR
[PR_CCS
]);
1874 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
],
1875 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1876 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1877 dc
->flags_uptodate
= 1;
1881 static int dec_sub_r(CPUCRISState
*env
, DisasContext
*dc
)
1884 int size
= memsize_zz(dc
);
1885 LOG_DIS("sub.%c $r%u, $r%u\n",
1886 memsize_char(size
), dc
->op1
, dc
->op2
);
1887 cris_cc_mask(dc
, CC_MASK_NZVC
);
1888 cris_alu_alloc_temps(dc
, size
, t
);
1889 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1890 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1891 cris_alu_free_temps(dc
, size
, t
);
1895 /* Zero extension. From size to dword. */
1896 static int dec_movu_r(CPUCRISState
*env
, DisasContext
*dc
)
1899 int size
= memsize_z(dc
);
1900 LOG_DIS("movu.%c $r%u, $r%u\n",
1904 cris_cc_mask(dc
, CC_MASK_NZ
);
1905 t0
= tcg_temp_new();
1906 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1907 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1912 /* Sign extension. From size to dword. */
1913 static int dec_movs_r(CPUCRISState
*env
, DisasContext
*dc
)
1916 int size
= memsize_z(dc
);
1917 LOG_DIS("movs.%c $r%u, $r%u\n",
1921 cris_cc_mask(dc
, CC_MASK_NZ
);
1922 t0
= tcg_temp_new();
1923 /* Size can only be qi or hi. */
1924 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1925 cris_alu(dc
, CC_OP_MOVE
,
1926 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
1931 /* zero extension. From size to dword. */
1932 static int dec_addu_r(CPUCRISState
*env
, DisasContext
*dc
)
1935 int size
= memsize_z(dc
);
1936 LOG_DIS("addu.%c $r%u, $r%u\n",
1940 cris_cc_mask(dc
, CC_MASK_NZVC
);
1941 t0
= tcg_temp_new();
1942 /* Size can only be qi or hi. */
1943 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1944 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1949 /* Sign extension. From size to dword. */
1950 static int dec_adds_r(CPUCRISState
*env
, DisasContext
*dc
)
1953 int size
= memsize_z(dc
);
1954 LOG_DIS("adds.%c $r%u, $r%u\n",
1958 cris_cc_mask(dc
, CC_MASK_NZVC
);
1959 t0
= tcg_temp_new();
1960 /* Size can only be qi or hi. */
1961 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1962 cris_alu(dc
, CC_OP_ADD
,
1963 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1968 /* Zero extension. From size to dword. */
1969 static int dec_subu_r(CPUCRISState
*env
, DisasContext
*dc
)
1972 int size
= memsize_z(dc
);
1973 LOG_DIS("subu.%c $r%u, $r%u\n",
1977 cris_cc_mask(dc
, CC_MASK_NZVC
);
1978 t0
= tcg_temp_new();
1979 /* Size can only be qi or hi. */
1980 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1981 cris_alu(dc
, CC_OP_SUB
,
1982 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1987 /* Sign extension. From size to dword. */
1988 static int dec_subs_r(CPUCRISState
*env
, DisasContext
*dc
)
1991 int size
= memsize_z(dc
);
1992 LOG_DIS("subs.%c $r%u, $r%u\n",
1996 cris_cc_mask(dc
, CC_MASK_NZVC
);
1997 t0
= tcg_temp_new();
1998 /* Size can only be qi or hi. */
1999 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2000 cris_alu(dc
, CC_OP_SUB
,
2001 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2006 static int dec_setclrf(CPUCRISState
*env
, DisasContext
*dc
)
2009 int set
= (~dc
->opcode
>> 2) & 1;
2012 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
2013 | EXTRACT_FIELD(dc
->ir
, 0, 3);
2014 if (set
&& flags
== 0) {
2017 } else if (!set
&& (flags
& 0x20)) {
2020 LOG_DIS("%sf %x\n", set
? "set" : "clr", flags
);
2023 /* User space is not allowed to touch these. Silently ignore. */
2024 if (dc
->tb_flags
& U_FLAG
) {
2025 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
2028 if (flags
& X_FLAG
) {
2029 dc
->flagx_known
= 1;
2031 dc
->flags_x
= X_FLAG
;
2037 /* Break the TB if any of the SPI flag changes. */
2038 if (flags
& (P_FLAG
| S_FLAG
)) {
2039 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2040 dc
->is_jmp
= DISAS_UPDATE
;
2041 dc
->cpustate_changed
= 1;
2044 /* For the I flag, only act on posedge. */
2045 if ((flags
& I_FLAG
)) {
2046 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2047 dc
->is_jmp
= DISAS_UPDATE
;
2048 dc
->cpustate_changed
= 1;
2052 /* Simply decode the flags. */
2053 cris_evaluate_flags(dc
);
2054 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2055 cris_update_cc_x(dc
);
2056 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2059 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2060 /* Enter user mode. */
2061 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2062 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2063 dc
->cpustate_changed
= 1;
2065 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2067 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2070 dc
->flags_uptodate
= 1;
2075 static int dec_move_rs(CPUCRISState
*env
, DisasContext
*dc
)
2078 LOG_DIS("move $r%u, $s%u\n", dc
->op1
, dc
->op2
);
2079 c1
= tcg_const_tl(dc
->op1
);
2080 c2
= tcg_const_tl(dc
->op2
);
2081 cris_cc_mask(dc
, 0);
2082 gen_helper_movl_sreg_reg(cpu_env
, c2
, c1
);
2087 static int dec_move_sr(CPUCRISState
*env
, DisasContext
*dc
)
2090 LOG_DIS("move $s%u, $r%u\n", dc
->op2
, dc
->op1
);
2091 c1
= tcg_const_tl(dc
->op1
);
2092 c2
= tcg_const_tl(dc
->op2
);
2093 cris_cc_mask(dc
, 0);
2094 gen_helper_movl_reg_sreg(cpu_env
, c1
, c2
);
2100 static int dec_move_rp(CPUCRISState
*env
, DisasContext
*dc
)
2103 LOG_DIS("move $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2104 cris_cc_mask(dc
, 0);
2106 t
[0] = tcg_temp_new();
2107 if (dc
->op2
== PR_CCS
) {
2108 cris_evaluate_flags(dc
);
2109 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2110 if (dc
->tb_flags
& U_FLAG
) {
2111 t
[1] = tcg_temp_new();
2112 /* User space is not allowed to touch all flags. */
2113 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2114 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2115 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2116 tcg_temp_free(t
[1]);
2119 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2122 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2123 if (dc
->op2
== PR_CCS
) {
2124 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2125 dc
->flags_uptodate
= 1;
2127 tcg_temp_free(t
[0]);
2130 static int dec_move_pr(CPUCRISState
*env
, DisasContext
*dc
)
2133 LOG_DIS("move $p%u, $r%u\n", dc
->op2
, dc
->op1
);
2134 cris_cc_mask(dc
, 0);
2136 if (dc
->op2
== PR_CCS
) {
2137 cris_evaluate_flags(dc
);
2140 if (dc
->op2
== PR_DZ
) {
2141 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
2143 t0
= tcg_temp_new();
2144 t_gen_mov_TN_preg(t0
, dc
->op2
);
2145 cris_alu(dc
, CC_OP_MOVE
,
2146 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
,
2147 preg_sizes
[dc
->op2
]);
2153 static int dec_move_mr(CPUCRISState
*env
, DisasContext
*dc
)
2155 int memsize
= memsize_zz(dc
);
2157 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2158 memsize_char(memsize
),
2159 dc
->op1
, dc
->postinc
? "+]" : "]",
2163 insn_len
= dec_prep_move_m(env
, dc
, 0, 4, cpu_R
[dc
->op2
]);
2164 cris_cc_mask(dc
, CC_MASK_NZ
);
2165 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2166 cris_update_cc_x(dc
);
2167 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2171 t0
= tcg_temp_new();
2172 insn_len
= dec_prep_move_m(env
, dc
, 0, memsize
, t0
);
2173 cris_cc_mask(dc
, CC_MASK_NZ
);
2174 cris_alu(dc
, CC_OP_MOVE
,
2175 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2178 do_postinc(dc
, memsize
);
2182 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2184 t
[0] = tcg_temp_new();
2185 t
[1] = tcg_temp_new();
2188 static inline void cris_alu_m_free_temps(TCGv
*t
)
2190 tcg_temp_free(t
[0]);
2191 tcg_temp_free(t
[1]);
2194 static int dec_movs_m(CPUCRISState
*env
, DisasContext
*dc
)
2197 int memsize
= memsize_z(dc
);
2199 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2200 memsize_char(memsize
),
2201 dc
->op1
, dc
->postinc
? "+]" : "]",
2204 cris_alu_m_alloc_temps(t
);
2206 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2207 cris_cc_mask(dc
, CC_MASK_NZ
);
2208 cris_alu(dc
, CC_OP_MOVE
,
2209 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2210 do_postinc(dc
, memsize
);
2211 cris_alu_m_free_temps(t
);
2215 static int dec_addu_m(CPUCRISState
*env
, DisasContext
*dc
)
2218 int memsize
= memsize_z(dc
);
2220 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2221 memsize_char(memsize
),
2222 dc
->op1
, dc
->postinc
? "+]" : "]",
2225 cris_alu_m_alloc_temps(t
);
2227 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2228 cris_cc_mask(dc
, CC_MASK_NZVC
);
2229 cris_alu(dc
, CC_OP_ADD
,
2230 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2231 do_postinc(dc
, memsize
);
2232 cris_alu_m_free_temps(t
);
2236 static int dec_adds_m(CPUCRISState
*env
, DisasContext
*dc
)
2239 int memsize
= memsize_z(dc
);
2241 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2242 memsize_char(memsize
),
2243 dc
->op1
, dc
->postinc
? "+]" : "]",
2246 cris_alu_m_alloc_temps(t
);
2248 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2249 cris_cc_mask(dc
, CC_MASK_NZVC
);
2250 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2251 do_postinc(dc
, memsize
);
2252 cris_alu_m_free_temps(t
);
2256 static int dec_subu_m(CPUCRISState
*env
, DisasContext
*dc
)
2259 int memsize
= memsize_z(dc
);
2261 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2262 memsize_char(memsize
),
2263 dc
->op1
, dc
->postinc
? "+]" : "]",
2266 cris_alu_m_alloc_temps(t
);
2268 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2269 cris_cc_mask(dc
, CC_MASK_NZVC
);
2270 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2271 do_postinc(dc
, memsize
);
2272 cris_alu_m_free_temps(t
);
2276 static int dec_subs_m(CPUCRISState
*env
, DisasContext
*dc
)
2279 int memsize
= memsize_z(dc
);
2281 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2282 memsize_char(memsize
),
2283 dc
->op1
, dc
->postinc
? "+]" : "]",
2286 cris_alu_m_alloc_temps(t
);
2288 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2289 cris_cc_mask(dc
, CC_MASK_NZVC
);
2290 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2291 do_postinc(dc
, memsize
);
2292 cris_alu_m_free_temps(t
);
2296 static int dec_movu_m(CPUCRISState
*env
, DisasContext
*dc
)
2299 int memsize
= memsize_z(dc
);
2302 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2303 memsize_char(memsize
),
2304 dc
->op1
, dc
->postinc
? "+]" : "]",
2307 cris_alu_m_alloc_temps(t
);
2308 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2309 cris_cc_mask(dc
, CC_MASK_NZ
);
2310 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2311 do_postinc(dc
, memsize
);
2312 cris_alu_m_free_temps(t
);
2316 static int dec_cmpu_m(CPUCRISState
*env
, DisasContext
*dc
)
2319 int memsize
= memsize_z(dc
);
2321 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2322 memsize_char(memsize
),
2323 dc
->op1
, dc
->postinc
? "+]" : "]",
2326 cris_alu_m_alloc_temps(t
);
2327 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2328 cris_cc_mask(dc
, CC_MASK_NZVC
);
2329 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2330 do_postinc(dc
, memsize
);
2331 cris_alu_m_free_temps(t
);
2335 static int dec_cmps_m(CPUCRISState
*env
, DisasContext
*dc
)
2338 int memsize
= memsize_z(dc
);
2340 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2341 memsize_char(memsize
),
2342 dc
->op1
, dc
->postinc
? "+]" : "]",
2345 cris_alu_m_alloc_temps(t
);
2346 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2347 cris_cc_mask(dc
, CC_MASK_NZVC
);
2348 cris_alu(dc
, CC_OP_CMP
,
2349 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2351 do_postinc(dc
, memsize
);
2352 cris_alu_m_free_temps(t
);
2356 static int dec_cmp_m(CPUCRISState
*env
, DisasContext
*dc
)
2359 int memsize
= memsize_zz(dc
);
2361 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2362 memsize_char(memsize
),
2363 dc
->op1
, dc
->postinc
? "+]" : "]",
2366 cris_alu_m_alloc_temps(t
);
2367 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2368 cris_cc_mask(dc
, CC_MASK_NZVC
);
2369 cris_alu(dc
, CC_OP_CMP
,
2370 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2372 do_postinc(dc
, memsize
);
2373 cris_alu_m_free_temps(t
);
2377 static int dec_test_m(CPUCRISState
*env
, DisasContext
*dc
)
2380 int memsize
= memsize_zz(dc
);
2382 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2383 memsize_char(memsize
),
2384 dc
->op1
, dc
->postinc
? "+]" : "]",
2387 cris_evaluate_flags(dc
);
2389 cris_alu_m_alloc_temps(t
);
2390 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2391 cris_cc_mask(dc
, CC_MASK_NZ
);
2392 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2394 c
= tcg_const_tl(0);
2395 cris_alu(dc
, CC_OP_CMP
,
2396 cpu_R
[dc
->op2
], t
[1], c
, memsize_zz(dc
));
2398 do_postinc(dc
, memsize
);
2399 cris_alu_m_free_temps(t
);
2403 static int dec_and_m(CPUCRISState
*env
, DisasContext
*dc
)
2406 int memsize
= memsize_zz(dc
);
2408 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2409 memsize_char(memsize
),
2410 dc
->op1
, dc
->postinc
? "+]" : "]",
2413 cris_alu_m_alloc_temps(t
);
2414 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2415 cris_cc_mask(dc
, CC_MASK_NZ
);
2416 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2417 do_postinc(dc
, memsize
);
2418 cris_alu_m_free_temps(t
);
2422 static int dec_add_m(CPUCRISState
*env
, DisasContext
*dc
)
2425 int memsize
= memsize_zz(dc
);
2427 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2428 memsize_char(memsize
),
2429 dc
->op1
, dc
->postinc
? "+]" : "]",
2432 cris_alu_m_alloc_temps(t
);
2433 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2434 cris_cc_mask(dc
, CC_MASK_NZVC
);
2435 cris_alu(dc
, CC_OP_ADD
,
2436 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2437 do_postinc(dc
, memsize
);
2438 cris_alu_m_free_temps(t
);
2442 static int dec_addo_m(CPUCRISState
*env
, DisasContext
*dc
)
2445 int memsize
= memsize_zz(dc
);
2447 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2448 memsize_char(memsize
),
2449 dc
->op1
, dc
->postinc
? "+]" : "]",
2452 cris_alu_m_alloc_temps(t
);
2453 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2454 cris_cc_mask(dc
, 0);
2455 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2456 do_postinc(dc
, memsize
);
2457 cris_alu_m_free_temps(t
);
2461 static int dec_bound_m(CPUCRISState
*env
, DisasContext
*dc
)
2464 int memsize
= memsize_zz(dc
);
2466 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2467 memsize_char(memsize
),
2468 dc
->op1
, dc
->postinc
? "+]" : "]",
2471 l
[0] = tcg_temp_local_new();
2472 l
[1] = tcg_temp_local_new();
2473 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, l
[0], l
[1]);
2474 cris_cc_mask(dc
, CC_MASK_NZ
);
2475 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2476 do_postinc(dc
, memsize
);
2477 tcg_temp_free(l
[0]);
2478 tcg_temp_free(l
[1]);
2482 static int dec_addc_mr(CPUCRISState
*env
, DisasContext
*dc
)
2486 LOG_DIS("addc [$r%u%s, $r%u\n",
2487 dc
->op1
, dc
->postinc
? "+]" : "]",
2490 cris_evaluate_flags(dc
);
2492 /* Set for this insn. */
2493 dc
->flagx_known
= 1;
2494 dc
->flags_x
= X_FLAG
;
2496 cris_alu_m_alloc_temps(t
);
2497 insn_len
= dec_prep_alu_m(env
, dc
, 0, 4, t
[0], t
[1]);
2498 cris_cc_mask(dc
, CC_MASK_NZVC
);
2499 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2501 cris_alu_m_free_temps(t
);
2505 static int dec_sub_m(CPUCRISState
*env
, DisasContext
*dc
)
2508 int memsize
= memsize_zz(dc
);
2510 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2511 memsize_char(memsize
),
2512 dc
->op1
, dc
->postinc
? "+]" : "]",
2513 dc
->op2
, dc
->ir
, dc
->zzsize
);
2515 cris_alu_m_alloc_temps(t
);
2516 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2517 cris_cc_mask(dc
, CC_MASK_NZVC
);
2518 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2519 do_postinc(dc
, memsize
);
2520 cris_alu_m_free_temps(t
);
2524 static int dec_or_m(CPUCRISState
*env
, DisasContext
*dc
)
2527 int memsize
= memsize_zz(dc
);
2529 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2530 memsize_char(memsize
),
2531 dc
->op1
, dc
->postinc
? "+]" : "]",
2534 cris_alu_m_alloc_temps(t
);
2535 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2536 cris_cc_mask(dc
, CC_MASK_NZ
);
2537 cris_alu(dc
, CC_OP_OR
,
2538 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2539 do_postinc(dc
, memsize
);
2540 cris_alu_m_free_temps(t
);
2544 static int dec_move_mp(CPUCRISState
*env
, DisasContext
*dc
)
2547 int memsize
= memsize_zz(dc
);
2550 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2551 memsize_char(memsize
),
2553 dc
->postinc
? "+]" : "]",
2556 cris_alu_m_alloc_temps(t
);
2557 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2558 cris_cc_mask(dc
, 0);
2559 if (dc
->op2
== PR_CCS
) {
2560 cris_evaluate_flags(dc
);
2561 if (dc
->tb_flags
& U_FLAG
) {
2562 /* User space is not allowed to touch all flags. */
2563 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2564 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2565 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2569 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2571 do_postinc(dc
, memsize
);
2572 cris_alu_m_free_temps(t
);
2576 static int dec_move_pm(CPUCRISState
*env
, DisasContext
*dc
)
2581 memsize
= preg_sizes
[dc
->op2
];
2583 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2584 memsize_char(memsize
),
2585 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]");
2587 /* prepare store. Address in T0, value in T1. */
2588 if (dc
->op2
== PR_CCS
) {
2589 cris_evaluate_flags(dc
);
2591 t0
= tcg_temp_new();
2592 t_gen_mov_TN_preg(t0
, dc
->op2
);
2593 cris_flush_cc_state(dc
);
2594 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2597 cris_cc_mask(dc
, 0);
2599 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2604 static int dec_movem_mr(CPUCRISState
*env
, DisasContext
*dc
)
2610 int nr
= dc
->op2
+ 1;
2612 LOG_DIS("movem [$r%u%s, $r%u\n", dc
->op1
,
2613 dc
->postinc
? "+]" : "]", dc
->op2
);
2615 addr
= tcg_temp_new();
2616 /* There are probably better ways of doing this. */
2617 cris_flush_cc_state(dc
);
2618 for (i
= 0; i
< (nr
>> 1); i
++) {
2619 tmp
[i
] = tcg_temp_new_i64();
2620 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2621 gen_load64(dc
, tmp
[i
], addr
);
2624 tmp32
= tcg_temp_new_i32();
2625 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2626 gen_load(dc
, tmp32
, addr
, 4, 0);
2630 tcg_temp_free(addr
);
2632 for (i
= 0; i
< (nr
>> 1); i
++) {
2633 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2634 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2635 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2636 tcg_temp_free_i64(tmp
[i
]);
2639 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp32
);
2640 tcg_temp_free(tmp32
);
2643 /* writeback the updated pointer value. */
2645 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2648 /* gen_load might want to evaluate the previous insns flags. */
2649 cris_cc_mask(dc
, 0);
2653 static int dec_movem_rm(CPUCRISState
*env
, DisasContext
*dc
)
2659 LOG_DIS("movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2660 dc
->postinc
? "+]" : "]");
2662 cris_flush_cc_state(dc
);
2664 tmp
= tcg_temp_new();
2665 addr
= tcg_temp_new();
2666 tcg_gen_movi_tl(tmp
, 4);
2667 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2668 for (i
= 0; i
<= dc
->op2
; i
++) {
2669 /* Displace addr. */
2670 /* Perform the store. */
2671 gen_store(dc
, addr
, cpu_R
[i
], 4);
2672 tcg_gen_add_tl(addr
, addr
, tmp
);
2675 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2677 cris_cc_mask(dc
, 0);
2679 tcg_temp_free(addr
);
2683 static int dec_move_rm(CPUCRISState
*env
, DisasContext
*dc
)
2687 memsize
= memsize_zz(dc
);
2689 LOG_DIS("move.%c $r%u, [$r%u]\n",
2690 memsize_char(memsize
), dc
->op2
, dc
->op1
);
2692 /* prepare store. */
2693 cris_flush_cc_state(dc
);
2694 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2697 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2699 cris_cc_mask(dc
, 0);
2703 static int dec_lapcq(CPUCRISState
*env
, DisasContext
*dc
)
2705 LOG_DIS("lapcq %x, $r%u\n",
2706 dc
->pc
+ dc
->op1
*2, dc
->op2
);
2707 cris_cc_mask(dc
, 0);
2708 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2712 static int dec_lapc_im(CPUCRISState
*env
, DisasContext
*dc
)
2720 cris_cc_mask(dc
, 0);
2721 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2722 LOG_DIS("lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
);
2726 tcg_gen_movi_tl(cpu_R
[rd
], pc
);
2730 /* Jump to special reg. */
2731 static int dec_jump_p(CPUCRISState
*env
, DisasContext
*dc
)
2733 LOG_DIS("jump $p%u\n", dc
->op2
);
2735 if (dc
->op2
== PR_CCS
) {
2736 cris_evaluate_flags(dc
);
2738 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2739 /* rete will often have low bit set to indicate delayslot. */
2740 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2741 cris_cc_mask(dc
, 0);
2742 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2746 /* Jump and save. */
2747 static int dec_jas_r(CPUCRISState
*env
, DisasContext
*dc
)
2750 LOG_DIS("jas $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2751 cris_cc_mask(dc
, 0);
2752 /* Store the return address in Pd. */
2753 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2757 c
= tcg_const_tl(dc
->pc
+ 4);
2758 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2761 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2765 static int dec_jas_im(CPUCRISState
*env
, DisasContext
*dc
)
2770 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2772 LOG_DIS("jas 0x%x\n", imm
);
2773 cris_cc_mask(dc
, 0);
2774 c
= tcg_const_tl(dc
->pc
+ 8);
2775 /* Store the return address in Pd. */
2776 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2780 cris_prepare_jmp(dc
, JMP_DIRECT
);
2784 static int dec_jasc_im(CPUCRISState
*env
, DisasContext
*dc
)
2789 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2791 LOG_DIS("jasc 0x%x\n", imm
);
2792 cris_cc_mask(dc
, 0);
2793 c
= tcg_const_tl(dc
->pc
+ 8 + 4);
2794 /* Store the return address in Pd. */
2795 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2799 cris_prepare_jmp(dc
, JMP_DIRECT
);
2803 static int dec_jasc_r(CPUCRISState
*env
, DisasContext
*dc
)
2806 LOG_DIS("jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2807 cris_cc_mask(dc
, 0);
2808 /* Store the return address in Pd. */
2809 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2810 c
= tcg_const_tl(dc
->pc
+ 4 + 4);
2811 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2813 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2817 static int dec_bcc_im(CPUCRISState
*env
, DisasContext
*dc
)
2820 uint32_t cond
= dc
->op2
;
2822 offset
= cris_fetch(env
, dc
, dc
->pc
+ 2, 2, 1);
2824 LOG_DIS("b%s %d pc=%x dst=%x\n",
2825 cc_name(cond
), offset
,
2826 dc
->pc
, dc
->pc
+ offset
);
2828 cris_cc_mask(dc
, 0);
2829 /* op2 holds the condition-code. */
2830 cris_prepare_cc_branch(dc
, offset
, cond
);
2834 static int dec_bas_im(CPUCRISState
*env
, DisasContext
*dc
)
2839 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2841 LOG_DIS("bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2842 cris_cc_mask(dc
, 0);
2843 c
= tcg_const_tl(dc
->pc
+ 8);
2844 /* Store the return address in Pd. */
2845 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2848 dc
->jmp_pc
= dc
->pc
+ simm
;
2849 cris_prepare_jmp(dc
, JMP_DIRECT
);
2853 static int dec_basc_im(CPUCRISState
*env
, DisasContext
*dc
)
2857 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2859 LOG_DIS("basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2860 cris_cc_mask(dc
, 0);
2861 c
= tcg_const_tl(dc
->pc
+ 12);
2862 /* Store the return address in Pd. */
2863 t_gen_mov_preg_TN(dc
, dc
->op2
, c
);
2866 dc
->jmp_pc
= dc
->pc
+ simm
;
2867 cris_prepare_jmp(dc
, JMP_DIRECT
);
2871 static int dec_rfe_etc(CPUCRISState
*env
, DisasContext
*dc
)
2873 cris_cc_mask(dc
, 0);
2875 if (dc
->op2
== 15) {
2876 tcg_gen_st_i32(tcg_const_i32(1), cpu_env
,
2877 -offsetof(CRISCPU
, env
) + offsetof(CPUState
, halted
));
2878 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2879 t_gen_raise_exception(EXCP_HLT
);
2883 switch (dc
->op2
& 7) {
2887 cris_evaluate_flags(dc
);
2888 gen_helper_rfe(cpu_env
);
2889 dc
->is_jmp
= DISAS_UPDATE
;
2894 cris_evaluate_flags(dc
);
2895 gen_helper_rfn(cpu_env
);
2896 dc
->is_jmp
= DISAS_UPDATE
;
2899 LOG_DIS("break %d\n", dc
->op1
);
2900 cris_evaluate_flags(dc
);
2902 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2904 /* Breaks start at 16 in the exception vector. */
2905 t_gen_movi_env_TN(trap_vector
, dc
->op1
+ 16);
2906 t_gen_raise_exception(EXCP_BREAK
);
2907 dc
->is_jmp
= DISAS_UPDATE
;
2910 printf("op2=%x\n", dc
->op2
);
2918 static int dec_ftag_fidx_d_m(CPUCRISState
*env
, DisasContext
*dc
)
2923 static int dec_ftag_fidx_i_m(CPUCRISState
*env
, DisasContext
*dc
)
2928 static int dec_null(CPUCRISState
*env
, DisasContext
*dc
)
2930 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2931 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2937 static struct decoder_info
{
2942 int (*dec
)(CPUCRISState
*env
, DisasContext
*dc
);
2944 /* Order matters here. */
2945 {DEC_MOVEQ
, dec_moveq
},
2946 {DEC_BTSTQ
, dec_btstq
},
2947 {DEC_CMPQ
, dec_cmpq
},
2948 {DEC_ADDOQ
, dec_addoq
},
2949 {DEC_ADDQ
, dec_addq
},
2950 {DEC_SUBQ
, dec_subq
},
2951 {DEC_ANDQ
, dec_andq
},
2953 {DEC_ASRQ
, dec_asrq
},
2954 {DEC_LSLQ
, dec_lslq
},
2955 {DEC_LSRQ
, dec_lsrq
},
2956 {DEC_BCCQ
, dec_bccq
},
2958 {DEC_BCC_IM
, dec_bcc_im
},
2959 {DEC_JAS_IM
, dec_jas_im
},
2960 {DEC_JAS_R
, dec_jas_r
},
2961 {DEC_JASC_IM
, dec_jasc_im
},
2962 {DEC_JASC_R
, dec_jasc_r
},
2963 {DEC_BAS_IM
, dec_bas_im
},
2964 {DEC_BASC_IM
, dec_basc_im
},
2965 {DEC_JUMP_P
, dec_jump_p
},
2966 {DEC_LAPC_IM
, dec_lapc_im
},
2967 {DEC_LAPCQ
, dec_lapcq
},
2969 {DEC_RFE_ETC
, dec_rfe_etc
},
2970 {DEC_ADDC_MR
, dec_addc_mr
},
2972 {DEC_MOVE_MP
, dec_move_mp
},
2973 {DEC_MOVE_PM
, dec_move_pm
},
2974 {DEC_MOVEM_MR
, dec_movem_mr
},
2975 {DEC_MOVEM_RM
, dec_movem_rm
},
2976 {DEC_MOVE_PR
, dec_move_pr
},
2977 {DEC_SCC_R
, dec_scc_r
},
2978 {DEC_SETF
, dec_setclrf
},
2979 {DEC_CLEARF
, dec_setclrf
},
2981 {DEC_MOVE_SR
, dec_move_sr
},
2982 {DEC_MOVE_RP
, dec_move_rp
},
2983 {DEC_SWAP_R
, dec_swap_r
},
2984 {DEC_ABS_R
, dec_abs_r
},
2985 {DEC_LZ_R
, dec_lz_r
},
2986 {DEC_MOVE_RS
, dec_move_rs
},
2987 {DEC_BTST_R
, dec_btst_r
},
2988 {DEC_ADDC_R
, dec_addc_r
},
2990 {DEC_DSTEP_R
, dec_dstep_r
},
2991 {DEC_XOR_R
, dec_xor_r
},
2992 {DEC_MCP_R
, dec_mcp_r
},
2993 {DEC_CMP_R
, dec_cmp_r
},
2995 {DEC_ADDI_R
, dec_addi_r
},
2996 {DEC_ADDI_ACR
, dec_addi_acr
},
2998 {DEC_ADD_R
, dec_add_r
},
2999 {DEC_SUB_R
, dec_sub_r
},
3001 {DEC_ADDU_R
, dec_addu_r
},
3002 {DEC_ADDS_R
, dec_adds_r
},
3003 {DEC_SUBU_R
, dec_subu_r
},
3004 {DEC_SUBS_R
, dec_subs_r
},
3005 {DEC_LSL_R
, dec_lsl_r
},
3007 {DEC_AND_R
, dec_and_r
},
3008 {DEC_OR_R
, dec_or_r
},
3009 {DEC_BOUND_R
, dec_bound_r
},
3010 {DEC_ASR_R
, dec_asr_r
},
3011 {DEC_LSR_R
, dec_lsr_r
},
3013 {DEC_MOVU_R
, dec_movu_r
},
3014 {DEC_MOVS_R
, dec_movs_r
},
3015 {DEC_NEG_R
, dec_neg_r
},
3016 {DEC_MOVE_R
, dec_move_r
},
3018 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
3019 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
3021 {DEC_MULS_R
, dec_muls_r
},
3022 {DEC_MULU_R
, dec_mulu_r
},
3024 {DEC_ADDU_M
, dec_addu_m
},
3025 {DEC_ADDS_M
, dec_adds_m
},
3026 {DEC_SUBU_M
, dec_subu_m
},
3027 {DEC_SUBS_M
, dec_subs_m
},
3029 {DEC_CMPU_M
, dec_cmpu_m
},
3030 {DEC_CMPS_M
, dec_cmps_m
},
3031 {DEC_MOVU_M
, dec_movu_m
},
3032 {DEC_MOVS_M
, dec_movs_m
},
3034 {DEC_CMP_M
, dec_cmp_m
},
3035 {DEC_ADDO_M
, dec_addo_m
},
3036 {DEC_BOUND_M
, dec_bound_m
},
3037 {DEC_ADD_M
, dec_add_m
},
3038 {DEC_SUB_M
, dec_sub_m
},
3039 {DEC_AND_M
, dec_and_m
},
3040 {DEC_OR_M
, dec_or_m
},
3041 {DEC_MOVE_RM
, dec_move_rm
},
3042 {DEC_TEST_M
, dec_test_m
},
3043 {DEC_MOVE_MR
, dec_move_mr
},
3048 static unsigned int crisv32_decoder(CPUCRISState
*env
, DisasContext
*dc
)
3053 /* Load a halfword onto the instruction register. */
3054 dc
->ir
= cris_fetch(env
, dc
, dc
->pc
, 2, 0);
3056 /* Now decode it. */
3057 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3058 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3059 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3060 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3061 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3062 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3064 /* Large switch for all insns. */
3065 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
3066 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
3067 insn_len
= decinfo
[i
].dec(env
, dc
);
3072 #if !defined(CONFIG_USER_ONLY)
3073 /* Single-stepping ? */
3074 if (dc
->tb_flags
& S_FLAG
) {
3075 TCGLabel
*l1
= gen_new_label();
3076 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3077 /* We treat SPC as a break with an odd trap vector. */
3078 cris_evaluate_flags(dc
);
3079 t_gen_movi_env_TN(trap_vector
, 3);
3080 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3081 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3082 t_gen_raise_exception(EXCP_BREAK
);
3089 #include "translate_v10.c.inc"
3092 * Delay slots on QEMU/CRIS.
3094 * If an exception hits on a delayslot, the core will let ERP (the Exception
3095 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3096 * to give SW a hint that the exception actually hit on the dslot.
3098 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3099 * the core and any jmp to an odd addresses will mask off that lsb. It is
3100 * simply there to let sw know there was an exception on a dslot.
3102 * When the software returns from an exception, the branch will re-execute.
3103 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3104 * and the branch and delayslot don't share pages.
3106 * The TB contaning the branch insn will set up env->btarget and evaluate
3107 * env->btaken. When the translation loop exits we will note that the branch
3108 * sequence is broken and let env->dslot be the size of the branch insn (those
3111 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3112 * set). It will also expect to have env->dslot setup with the size of the
3113 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3114 * will execute the dslot and take the branch, either to btarget or just one
3117 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3118 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3119 * branch and set lsb). Then env->dslot gets cleared so that the exception
3120 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3121 * masked off and we will reexecute the branch insn.
3125 /* generate intermediate code for basic block 'tb'. */
3126 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
3128 CPUCRISState
*env
= cs
->env_ptr
;
3130 unsigned int insn_len
;
3131 struct DisasContext ctx
;
3132 struct DisasContext
*dc
= &ctx
;
3133 uint32_t page_start
;
3137 if (env
->pregs
[PR_VR
] == 32) {
3138 dc
->decoder
= crisv32_decoder
;
3139 dc
->clear_locked_irq
= 0;
3141 dc
->decoder
= crisv10_decoder
;
3142 dc
->clear_locked_irq
= 1;
3145 /* Odd PC indicates that branch is rexecuting due to exception in the
3146 * delayslot, like in real hw.
3148 pc_start
= tb
->pc
& ~1;
3149 dc
->cpu
= env_archcpu(env
);
3152 dc
->is_jmp
= DISAS_NEXT
;
3155 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3156 dc
->flags_uptodate
= 1;
3157 dc
->flagx_known
= 1;
3158 dc
->flags_x
= tb
->flags
& X_FLAG
;
3159 dc
->cc_x_uptodate
= 0;
3162 dc
->clear_prefix
= 0;
3164 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3165 dc
->cc_size_uptodate
= -1;
3167 /* Decode TB flags. */
3168 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG \
3169 | X_FLAG
| PFIX_FLAG
);
3170 dc
->delayed_branch
= !!(tb
->flags
& 7);
3171 if (dc
->delayed_branch
) {
3172 dc
->jmp
= JMP_INDIRECT
;
3174 dc
->jmp
= JMP_NOJMP
;
3177 dc
->cpustate_changed
= 0;
3179 page_start
= pc_start
& TARGET_PAGE_MASK
;
3184 tcg_gen_insn_start(dc
->delayed_branch
== 1
3185 ? dc
->ppc
| 1 : dc
->pc
);
3188 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3189 cris_evaluate_flags(dc
);
3190 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3191 t_gen_raise_exception(EXCP_DEBUG
);
3192 dc
->is_jmp
= DISAS_UPDATE
;
3193 /* The address covered by the breakpoint must be included in
3194 [tb->pc, tb->pc + tb->size) in order to for it to be
3195 properly cleared -- thus we increment the PC here so that
3196 the logic setting tb->size below does the right thing. */
3202 LOG_DIS("%8.8x:\t", dc
->pc
);
3204 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
3209 insn_len
= dc
->decoder(env
, dc
);
3213 cris_clear_x_flag(dc
);
3216 /* Check for delayed branches here. If we do it before
3217 actually generating any host code, the simulator will just
3218 loop doing nothing for on this program location. */
3219 if (dc
->delayed_branch
) {
3220 dc
->delayed_branch
--;
3221 if (dc
->delayed_branch
== 0) {
3222 if (tb
->flags
& 7) {
3223 t_gen_movi_env_TN(dslot
, 0);
3225 if (dc
->cpustate_changed
|| !dc
->flagx_known
3226 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
))) {
3227 cris_store_direct_jmp(dc
);
3230 if (dc
->clear_locked_irq
) {
3231 dc
->clear_locked_irq
= 0;
3232 t_gen_movi_env_TN(locked_irq
, 0);
3235 if (dc
->jmp
== JMP_DIRECT_CC
) {
3236 TCGLabel
*l1
= gen_new_label();
3237 cris_evaluate_flags(dc
);
3239 /* Conditional jmp. */
3240 tcg_gen_brcondi_tl(TCG_COND_EQ
,
3242 gen_goto_tb(dc
, 1, dc
->jmp_pc
);
3244 gen_goto_tb(dc
, 0, dc
->pc
);
3245 dc
->is_jmp
= DISAS_TB_JUMP
;
3246 dc
->jmp
= JMP_NOJMP
;
3247 } else if (dc
->jmp
== JMP_DIRECT
) {
3248 cris_evaluate_flags(dc
);
3249 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
3250 dc
->is_jmp
= DISAS_TB_JUMP
;
3251 dc
->jmp
= JMP_NOJMP
;
3253 TCGv c
= tcg_const_tl(dc
->pc
);
3254 t_gen_cc_jmp(env_btarget
, c
);
3256 dc
->is_jmp
= DISAS_JUMP
;
3262 /* If we are rexecuting a branch due to exceptions on
3263 delay slots don't break. */
3264 if (!(tb
->pc
& 1) && cs
->singlestep_enabled
) {
3267 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3268 && !tcg_op_buf_full()
3270 && (dc
->pc
- page_start
< TARGET_PAGE_SIZE
)
3271 && num_insns
< max_insns
);
3273 if (dc
->clear_locked_irq
) {
3274 t_gen_movi_env_TN(locked_irq
, 0);
3279 /* Force an update if the per-tb cpu state has changed. */
3280 if (dc
->is_jmp
== DISAS_NEXT
3281 && (dc
->cpustate_changed
|| !dc
->flagx_known
3282 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3283 dc
->is_jmp
= DISAS_UPDATE
;
3284 tcg_gen_movi_tl(env_pc
, npc
);
3286 /* Broken branch+delayslot sequence. */
3287 if (dc
->delayed_branch
== 1) {
3288 /* Set env->dslot to the size of the branch insn. */
3289 t_gen_movi_env_TN(dslot
, dc
->pc
- dc
->ppc
);
3290 cris_store_direct_jmp(dc
);
3293 cris_evaluate_flags(dc
);
3295 if (unlikely(cs
->singlestep_enabled
)) {
3296 if (dc
->is_jmp
== DISAS_NEXT
) {
3297 tcg_gen_movi_tl(env_pc
, npc
);
3299 t_gen_raise_exception(EXCP_DEBUG
);
3301 switch (dc
->is_jmp
) {
3303 gen_goto_tb(dc
, 1, npc
);
3308 /* indicate that the hash table must be used
3309 to find the next TB */
3310 tcg_gen_exit_tb(NULL
, 0);
3314 /* nothing more to generate */
3318 gen_tb_end(tb
, num_insns
);
3320 tb
->size
= dc
->pc
- pc_start
;
3321 tb
->icount
= num_insns
;
3325 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3326 && qemu_log_in_addr_range(pc_start
)) {
3327 FILE *logfile
= qemu_log_lock();
3328 qemu_log("--------------\n");
3329 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3330 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
);
3331 qemu_log_unlock(logfile
);
3337 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
3339 CRISCPU
*cpu
= CRIS_CPU(cs
);
3340 CPUCRISState
*env
= &cpu
->env
;
3341 const char **regnames
;
3342 const char **pregnames
;
3348 if (env
->pregs
[PR_VR
] < 32) {
3349 pregnames
= pregnames_v10
;
3350 regnames
= regnames_v10
;
3352 pregnames
= pregnames_v32
;
3353 regnames
= regnames_v32
;
3356 qemu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3357 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3358 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3360 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3363 for (i
= 0; i
< 16; i
++) {
3364 qemu_fprintf(f
, "%s=%8.8x ", regnames
[i
], env
->regs
[i
]);
3365 if ((i
+ 1) % 4 == 0) {
3366 qemu_fprintf(f
, "\n");
3369 qemu_fprintf(f
, "\nspecial regs:\n");
3370 for (i
= 0; i
< 16; i
++) {
3371 qemu_fprintf(f
, "%s=%8.8x ", pregnames
[i
], env
->pregs
[i
]);
3372 if ((i
+ 1) % 4 == 0) {
3373 qemu_fprintf(f
, "\n");
3376 if (env
->pregs
[PR_VR
] >= 32) {
3377 uint32_t srs
= env
->pregs
[PR_SRS
];
3378 qemu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3379 if (srs
< ARRAY_SIZE(env
->sregs
)) {
3380 for (i
= 0; i
< 16; i
++) {
3381 qemu_fprintf(f
, "s%2.2d=%8.8x ",
3382 i
, env
->sregs
[srs
][i
]);
3383 if ((i
+ 1) % 4 == 0) {
3384 qemu_fprintf(f
, "\n");
3389 qemu_fprintf(f
, "\n\n");
3393 void cris_initialize_tcg(void)
3397 cc_x
= tcg_global_mem_new(cpu_env
,
3398 offsetof(CPUCRISState
, cc_x
), "cc_x");
3399 cc_src
= tcg_global_mem_new(cpu_env
,
3400 offsetof(CPUCRISState
, cc_src
), "cc_src");
3401 cc_dest
= tcg_global_mem_new(cpu_env
,
3402 offsetof(CPUCRISState
, cc_dest
),
3404 cc_result
= tcg_global_mem_new(cpu_env
,
3405 offsetof(CPUCRISState
, cc_result
),
3407 cc_op
= tcg_global_mem_new(cpu_env
,
3408 offsetof(CPUCRISState
, cc_op
), "cc_op");
3409 cc_size
= tcg_global_mem_new(cpu_env
,
3410 offsetof(CPUCRISState
, cc_size
),
3412 cc_mask
= tcg_global_mem_new(cpu_env
,
3413 offsetof(CPUCRISState
, cc_mask
),
3416 env_pc
= tcg_global_mem_new(cpu_env
,
3417 offsetof(CPUCRISState
, pc
),
3419 env_btarget
= tcg_global_mem_new(cpu_env
,
3420 offsetof(CPUCRISState
, btarget
),
3422 env_btaken
= tcg_global_mem_new(cpu_env
,
3423 offsetof(CPUCRISState
, btaken
),
3425 for (i
= 0; i
< 16; i
++) {
3426 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
3427 offsetof(CPUCRISState
, regs
[i
]),
3430 for (i
= 0; i
< 16; i
++) {
3431 cpu_PR
[i
] = tcg_global_mem_new(cpu_env
,
3432 offsetof(CPUCRISState
, pregs
[i
]),
3437 void restore_state_to_opc(CPUCRISState
*env
, TranslationBlock
*tb
,