target/mips: Fix TCG temporary leak in gen_cache_operation()
[qemu/ar7.git] / linux-headers / asm-arm64 / sve_context.h
blob1d0e3e1d0950acfa436b081f6b7d09fdd5b265ae
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017-2018 ARM Limited */
4 /*
5 * For use by other UAPI headers only.
6 * Do not make direct use of header or its definitions.
7 */
9 #ifndef __ASM_SVE_CONTEXT_H
10 #define __ASM_SVE_CONTEXT_H
12 #include <linux/types.h>
14 #define __SVE_VQ_BYTES 16 /* number of bytes per quadword */
16 #define __SVE_VQ_MIN 1
17 #define __SVE_VQ_MAX 512
19 #define __SVE_VL_MIN (__SVE_VQ_MIN * __SVE_VQ_BYTES)
20 #define __SVE_VL_MAX (__SVE_VQ_MAX * __SVE_VQ_BYTES)
22 #define __SVE_NUM_ZREGS 32
23 #define __SVE_NUM_PREGS 16
25 #define __sve_vl_valid(vl) \
26 ((vl) % __SVE_VQ_BYTES == 0 && \
27 (vl) >= __SVE_VL_MIN && \
28 (vl) <= __SVE_VL_MAX)
30 #define __sve_vq_from_vl(vl) ((vl) / __SVE_VQ_BYTES)
31 #define __sve_vl_from_vq(vq) ((vq) * __SVE_VQ_BYTES)
33 #define __SVE_ZREG_SIZE(vq) ((__u32)(vq) * __SVE_VQ_BYTES)
34 #define __SVE_PREG_SIZE(vq) ((__u32)(vq) * (__SVE_VQ_BYTES / 8))
35 #define __SVE_FFR_SIZE(vq) __SVE_PREG_SIZE(vq)
37 #define __SVE_ZREGS_OFFSET 0
38 #define __SVE_ZREG_OFFSET(vq, n) \
39 (__SVE_ZREGS_OFFSET + __SVE_ZREG_SIZE(vq) * (n))
40 #define __SVE_ZREGS_SIZE(vq) \
41 (__SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - __SVE_ZREGS_OFFSET)
43 #define __SVE_PREGS_OFFSET(vq) \
44 (__SVE_ZREGS_OFFSET + __SVE_ZREGS_SIZE(vq))
45 #define __SVE_PREG_OFFSET(vq, n) \
46 (__SVE_PREGS_OFFSET(vq) + __SVE_PREG_SIZE(vq) * (n))
47 #define __SVE_PREGS_SIZE(vq) \
48 (__SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - __SVE_PREGS_OFFSET(vq))
50 #define __SVE_FFR_OFFSET(vq) \
51 (__SVE_PREGS_OFFSET(vq) + __SVE_PREGS_SIZE(vq))
53 #endif /* ! _UAPI__ASM_SVE_CONTEXT_H */