2 * ioapic.c IOAPIC emulation logic
4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * Split the ioapic logic from apic.c
7 * Xiantao Zhang <xiantao.zhang@intel.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "monitor/monitor.h"
25 #include "hw/i386/pc.h"
26 #include "hw/i386/ioapic.h"
27 #include "hw/i386/ioapic_internal.h"
28 #include "include/hw/pci/msi.h"
29 #include "sysemu/kvm.h"
31 //#define DEBUG_IOAPIC
34 #define DPRINTF(fmt, ...) \
35 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
40 #define APIC_DELIVERY_MODE_SHIFT 8
41 #define APIC_POLARITY_SHIFT 14
42 #define APIC_TRIG_MODE_SHIFT 15
44 static IOAPICCommonState
*ioapics
[MAX_IOAPICS
];
46 /* global variable from ioapic_common.c */
49 static void ioapic_service(IOAPICCommonState
*s
)
54 uint8_t delivery_mode
;
60 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
65 entry
= s
->ioredtbl
[i
];
66 if (!(entry
& IOAPIC_LVT_MASKED
)) {
67 trig_mode
= ((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1);
68 dest
= entry
>> IOAPIC_LVT_DEST_SHIFT
;
69 dest_mode
= (entry
>> IOAPIC_LVT_DEST_MODE_SHIFT
) & 1;
71 (entry
>> IOAPIC_LVT_DELIV_MODE_SHIFT
) & IOAPIC_DM_MASK
;
72 if (trig_mode
== IOAPIC_TRIGGER_EDGE
) {
75 coalesce
= s
->ioredtbl
[i
] & IOAPIC_LVT_REMOTE_IRR
;
76 s
->ioredtbl
[i
] |= IOAPIC_LVT_REMOTE_IRR
;
78 if (delivery_mode
== IOAPIC_DM_EXTINT
) {
79 vector
= pic_read_irq(isa_pic
);
81 vector
= entry
& IOAPIC_VECTOR_MASK
;
84 if (kvm_irqchip_is_split()) {
85 if (trig_mode
== IOAPIC_TRIGGER_EDGE
) {
86 kvm_set_irq(kvm_state
, i
, 1);
87 kvm_set_irq(kvm_state
, i
, 0);
90 kvm_set_irq(kvm_state
, i
, 1);
98 apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector
,
105 static void ioapic_set_irq(void *opaque
, int vector
, int level
)
107 IOAPICCommonState
*s
= opaque
;
109 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
110 * to GSI 2. GSI maps to ioapic 1-1. This is not
111 * the cleanest way of doing it but it should work. */
113 DPRINTF("%s: %s vec %x\n", __func__
, level
? "raise" : "lower", vector
);
117 if (vector
>= 0 && vector
< IOAPIC_NUM_PINS
) {
118 uint32_t mask
= 1 << vector
;
119 uint64_t entry
= s
->ioredtbl
[vector
];
121 if (((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1) ==
122 IOAPIC_TRIGGER_LEVEL
) {
123 /* level triggered */
126 if (!(entry
& IOAPIC_LVT_REMOTE_IRR
)) {
133 /* According to the 82093AA manual, we must ignore edge requests
134 * if the input pin is masked. */
135 if (level
&& !(entry
& IOAPIC_LVT_MASKED
)) {
143 static void ioapic_update_kvm_routes(IOAPICCommonState
*s
)
148 if (kvm_irqchip_is_split()) {
149 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
150 uint64_t entry
= s
->ioredtbl
[i
];
152 uint8_t delivery_mode
;
155 uint64_t pin_polarity
;
158 trig_mode
= ((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1);
159 dest
= entry
>> IOAPIC_LVT_DEST_SHIFT
;
160 dest_mode
= (entry
>> IOAPIC_LVT_DEST_MODE_SHIFT
) & 1;
161 pin_polarity
= (entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1;
163 (entry
>> IOAPIC_LVT_DELIV_MODE_SHIFT
) & IOAPIC_DM_MASK
;
165 msg
.address
= APIC_DEFAULT_ADDRESS
;
166 msg
.address
|= dest_mode
<< 2;
167 msg
.address
|= dest
<< 12;
169 msg
.data
= entry
& IOAPIC_VECTOR_MASK
;
170 msg
.data
|= delivery_mode
<< APIC_DELIVERY_MODE_SHIFT
;
171 msg
.data
|= pin_polarity
<< APIC_POLARITY_SHIFT
;
172 msg
.data
|= trig_mode
<< APIC_TRIG_MODE_SHIFT
;
174 kvm_irqchip_update_msi_route(kvm_state
, i
, msg
, NULL
);
176 kvm_irqchip_commit_routes(kvm_state
);
181 void ioapic_eoi_broadcast(int vector
)
183 IOAPICCommonState
*s
;
187 for (i
= 0; i
< MAX_IOAPICS
; i
++) {
192 for (n
= 0; n
< IOAPIC_NUM_PINS
; n
++) {
193 entry
= s
->ioredtbl
[n
];
194 if ((entry
& IOAPIC_LVT_REMOTE_IRR
)
195 && (entry
& IOAPIC_VECTOR_MASK
) == vector
) {
196 s
->ioredtbl
[n
] = entry
& ~IOAPIC_LVT_REMOTE_IRR
;
197 if (!(entry
& IOAPIC_LVT_MASKED
) && (s
->irr
& (1 << n
))) {
205 void ioapic_dump_state(Monitor
*mon
, const QDict
*qdict
)
209 for (i
= 0; i
< MAX_IOAPICS
; i
++) {
210 if (ioapics
[i
] != 0) {
211 ioapic_print_redtbl(mon
, ioapics
[i
]);
217 ioapic_mem_read(void *opaque
, hwaddr addr
, unsigned int size
)
219 IOAPICCommonState
*s
= opaque
;
223 switch (addr
& 0xff) {
224 case IOAPIC_IOREGSEL
:
231 switch (s
->ioregsel
) {
234 val
= s
->id
<< IOAPIC_ID_SHIFT
;
237 val
= IOAPIC_VERSION
|
238 ((IOAPIC_NUM_PINS
- 1) << IOAPIC_VER_ENTRIES_SHIFT
);
241 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
242 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
243 if (s
->ioregsel
& 1) {
244 val
= s
->ioredtbl
[index
] >> 32;
246 val
= s
->ioredtbl
[index
] & 0xffffffff;
250 DPRINTF("read: %08x = %08x\n", s
->ioregsel
, val
);
257 ioapic_mem_write(void *opaque
, hwaddr addr
, uint64_t val
,
260 IOAPICCommonState
*s
= opaque
;
263 switch (addr
& 0xff) {
264 case IOAPIC_IOREGSEL
:
271 DPRINTF("write: %08x = %08" PRIx64
"\n", s
->ioregsel
, val
);
272 switch (s
->ioregsel
) {
274 s
->id
= (val
>> IOAPIC_ID_SHIFT
) & IOAPIC_ID_MASK
;
280 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
281 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
282 if (s
->ioregsel
& 1) {
283 s
->ioredtbl
[index
] &= 0xffffffff;
284 s
->ioredtbl
[index
] |= (uint64_t)val
<< 32;
286 s
->ioredtbl
[index
] &= ~0xffffffffULL
;
287 s
->ioredtbl
[index
] |= val
;
295 ioapic_update_kvm_routes(s
);
298 static const MemoryRegionOps ioapic_io_ops
= {
299 .read
= ioapic_mem_read
,
300 .write
= ioapic_mem_write
,
301 .endianness
= DEVICE_NATIVE_ENDIAN
,
304 static void ioapic_realize(DeviceState
*dev
, Error
**errp
)
306 IOAPICCommonState
*s
= IOAPIC_COMMON(dev
);
308 memory_region_init_io(&s
->io_memory
, OBJECT(s
), &ioapic_io_ops
, s
,
311 qdev_init_gpio_in(dev
, ioapic_set_irq
, IOAPIC_NUM_PINS
);
313 ioapics
[ioapic_no
] = s
;
316 static void ioapic_class_init(ObjectClass
*klass
, void *data
)
318 IOAPICCommonClass
*k
= IOAPIC_COMMON_CLASS(klass
);
319 DeviceClass
*dc
= DEVICE_CLASS(klass
);
321 k
->realize
= ioapic_realize
;
322 dc
->reset
= ioapic_reset_common
;
325 static const TypeInfo ioapic_info
= {
327 .parent
= TYPE_IOAPIC_COMMON
,
328 .instance_size
= sizeof(IOAPICCommonState
),
329 .class_init
= ioapic_class_init
,
332 static void ioapic_register_types(void)
334 type_register_static(&ioapic_info
);
337 type_init(ioapic_register_types
)