2 * s390 PCI instructions
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
16 #include "exec/memop.h"
17 #include "exec/memory-internal.h"
18 #include "qemu/error-report.h"
19 #include "sysemu/hw_accel.h"
20 #include "hw/s390x/s390-pci-inst.h"
21 #include "hw/s390x/s390-pci-bus.h"
22 #include "hw/s390x/tod.h"
24 #ifndef DEBUG_S390PCI_INST
25 #define DEBUG_S390PCI_INST 0
28 #define DPRINTF(fmt, ...) \
30 if (DEBUG_S390PCI_INST) { \
31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
35 static inline void inc_dma_avail(S390PCIIOMMU
*iommu
)
37 if (iommu
->dma_limit
) {
38 iommu
->dma_limit
->avail
++;
42 static inline void dec_dma_avail(S390PCIIOMMU
*iommu
)
44 if (iommu
->dma_limit
) {
45 iommu
->dma_limit
->avail
--;
49 static void s390_set_status_code(CPUS390XState
*env
,
50 uint8_t r
, uint64_t status_code
)
52 env
->regs
[r
] &= ~0xff000000ULL
;
53 env
->regs
[r
] |= (status_code
& 0xff) << 24;
56 static int list_pci(ClpReqRspListPci
*rrb
, uint8_t *cc
)
58 S390PCIBusDevice
*pbdev
= NULL
;
59 S390pciState
*s
= s390_get_phb();
60 uint32_t res_code
, initial_l2
, g_l2
;
62 uint64_t resume_token
;
65 if (lduw_p(&rrb
->request
.hdr
.len
) != 32) {
66 res_code
= CLP_RC_LEN
;
71 if ((ldl_p(&rrb
->request
.fmt
) & CLP_MASK_FMT
) != 0) {
72 res_code
= CLP_RC_FMT
;
77 if ((ldl_p(&rrb
->request
.fmt
) & ~CLP_MASK_FMT
) != 0 ||
78 ldq_p(&rrb
->request
.reserved1
) != 0) {
79 res_code
= CLP_RC_RESNOT0
;
84 resume_token
= ldq_p(&rrb
->request
.resume_token
);
87 pbdev
= s390_pci_find_dev_by_idx(s
, resume_token
);
89 res_code
= CLP_RC_LISTPCI_BADRT
;
94 pbdev
= s390_pci_find_next_avail_dev(s
, NULL
);
97 if (lduw_p(&rrb
->response
.hdr
.len
) < 48) {
103 initial_l2
= lduw_p(&rrb
->response
.hdr
.len
);
104 if ((initial_l2
- LIST_PCI_HDR_LEN
) % sizeof(ClpFhListEntry
)
106 res_code
= CLP_RC_LEN
;
112 stl_p(&rrb
->response
.fmt
, 0);
113 stq_p(&rrb
->response
.reserved1
, 0);
114 stl_p(&rrb
->response
.mdd
, FH_MASK_SHM
);
115 stw_p(&rrb
->response
.max_fn
, PCI_MAX_FUNCTIONS
);
116 rrb
->response
.flags
= UID_CHECKING_ENABLED
;
117 rrb
->response
.entry_size
= sizeof(ClpFhListEntry
);
120 g_l2
= LIST_PCI_HDR_LEN
;
121 while (g_l2
< initial_l2
&& pbdev
) {
122 stw_p(&rrb
->response
.fh_list
[i
].device_id
,
123 pci_get_word(pbdev
->pdev
->config
+ PCI_DEVICE_ID
));
124 stw_p(&rrb
->response
.fh_list
[i
].vendor_id
,
125 pci_get_word(pbdev
->pdev
->config
+ PCI_VENDOR_ID
));
126 /* Ignore RESERVED devices. */
127 stl_p(&rrb
->response
.fh_list
[i
].config
,
128 pbdev
->state
== ZPCI_FS_STANDBY
? 0 : 1 << 31);
129 stl_p(&rrb
->response
.fh_list
[i
].fid
, pbdev
->fid
);
130 stl_p(&rrb
->response
.fh_list
[i
].fh
, pbdev
->fh
);
132 g_l2
+= sizeof(ClpFhListEntry
);
133 /* Add endian check for DPRINTF? */
134 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
136 lduw_p(&rrb
->response
.fh_list
[i
].vendor_id
),
137 lduw_p(&rrb
->response
.fh_list
[i
].device_id
),
138 ldl_p(&rrb
->response
.fh_list
[i
].fid
),
139 ldl_p(&rrb
->response
.fh_list
[i
].fh
));
140 pbdev
= s390_pci_find_next_avail_dev(s
, pbdev
);
147 resume_token
= pbdev
->fh
& FH_MASK_INDEX
;
149 stq_p(&rrb
->response
.resume_token
, resume_token
);
150 stw_p(&rrb
->response
.hdr
.len
, g_l2
);
151 stw_p(&rrb
->response
.hdr
.rsp
, CLP_RC_OK
);
154 DPRINTF("list pci failed rc 0x%x\n", rc
);
155 stw_p(&rrb
->response
.hdr
.rsp
, res_code
);
160 int clp_service_call(S390CPU
*cpu
, uint8_t r2
, uintptr_t ra
)
164 S390PCIBusDevice
*pbdev
;
167 uint8_t buffer
[4096 * 2];
169 CPUS390XState
*env
= &cpu
->env
;
170 S390pciState
*s
= s390_get_phb();
173 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
174 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
178 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
, sizeof(*reqh
))) {
179 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
182 reqh
= (ClpReqHdr
*)buffer
;
183 req_len
= lduw_p(&reqh
->len
);
184 if (req_len
< 16 || req_len
> 8184 || (req_len
% 8 != 0)) {
185 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
189 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
190 req_len
+ sizeof(*resh
))) {
191 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
194 resh
= (ClpRspHdr
*)(buffer
+ req_len
);
195 res_len
= lduw_p(&resh
->len
);
196 if (res_len
< 8 || res_len
> 8176 || (res_len
% 8 != 0)) {
197 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
200 if ((req_len
+ res_len
) > 8192) {
201 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
205 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
206 req_len
+ res_len
)) {
207 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
212 stw_p(&resh
->rsp
, CLP_RC_LEN
);
216 switch (lduw_p(&reqh
->cmd
)) {
218 ClpReqRspListPci
*rrb
= (ClpReqRspListPci
*)buffer
;
222 case CLP_SET_PCI_FN
: {
223 ClpReqSetPci
*reqsetpci
= (ClpReqSetPci
*)reqh
;
224 ClpRspSetPci
*ressetpci
= (ClpRspSetPci
*)resh
;
226 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqsetpci
->fh
));
228 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
232 switch (reqsetpci
->oc
) {
233 case CLP_SET_ENABLE_PCI_FN
:
234 switch (reqsetpci
->ndas
) {
236 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_DMAAS
);
241 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_RES
);
245 if (pbdev
->fh
& FH_MASK_ENABLE
) {
246 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
250 pbdev
->fh
|= FH_MASK_ENABLE
;
251 pbdev
->state
= ZPCI_FS_ENABLED
;
252 stl_p(&ressetpci
->fh
, pbdev
->fh
);
253 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
255 case CLP_SET_DISABLE_PCI_FN
:
256 if (!(pbdev
->fh
& FH_MASK_ENABLE
)) {
257 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
260 device_legacy_reset(DEVICE(pbdev
));
261 pbdev
->fh
&= ~FH_MASK_ENABLE
;
262 pbdev
->state
= ZPCI_FS_DISABLED
;
263 stl_p(&ressetpci
->fh
, pbdev
->fh
);
264 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
267 DPRINTF("unknown set pci command\n");
268 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
273 case CLP_QUERY_PCI_FN
: {
274 ClpReqQueryPci
*reqquery
= (ClpReqQueryPci
*)reqh
;
275 ClpRspQueryPci
*resquery
= (ClpRspQueryPci
*)resh
;
277 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqquery
->fh
));
279 DPRINTF("query pci no pci dev\n");
280 stw_p(&resquery
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
284 stq_p(&resquery
->sdma
, pbdev
->zpci_fn
.sdma
);
285 stq_p(&resquery
->edma
, pbdev
->zpci_fn
.edma
);
286 stw_p(&resquery
->pchid
, pbdev
->zpci_fn
.pchid
);
287 stw_p(&resquery
->vfn
, pbdev
->zpci_fn
.vfn
);
288 resquery
->flags
= pbdev
->zpci_fn
.flags
;
289 resquery
->pfgid
= pbdev
->zpci_fn
.pfgid
;
290 resquery
->pft
= pbdev
->zpci_fn
.pft
;
291 resquery
->fmbl
= pbdev
->zpci_fn
.fmbl
;
292 stl_p(&resquery
->fid
, pbdev
->zpci_fn
.fid
);
293 stl_p(&resquery
->uid
, pbdev
->zpci_fn
.uid
);
294 memcpy(resquery
->pfip
, pbdev
->zpci_fn
.pfip
, CLP_PFIP_NR_SEGMENTS
);
295 memcpy(resquery
->util_str
, pbdev
->zpci_fn
.util_str
, CLP_UTIL_STR_LEN
);
297 for (i
= 0; i
< PCI_BAR_COUNT
; i
++) {
298 uint32_t data
= pci_get_long(pbdev
->pdev
->config
+
299 PCI_BASE_ADDRESS_0
+ (i
* 4));
301 stl_p(&resquery
->bar
[i
], data
);
302 resquery
->bar_size
[i
] = pbdev
->pdev
->io_regions
[i
].size
?
303 ctz64(pbdev
->pdev
->io_regions
[i
].size
) : 0;
304 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64
"barsize 0x%x\n", i
,
305 ldl_p(&resquery
->bar
[i
]),
306 pbdev
->pdev
->io_regions
[i
].size
,
307 resquery
->bar_size
[i
]);
310 stw_p(&resquery
->hdr
.rsp
, CLP_RC_OK
);
313 case CLP_QUERY_PCI_FNGRP
: {
314 ClpRspQueryPciGrp
*resgrp
= (ClpRspQueryPciGrp
*)resh
;
316 ClpReqQueryPciGrp
*reqgrp
= (ClpReqQueryPciGrp
*)reqh
;
319 group
= s390_group_find(reqgrp
->g
);
321 /* We do not allow access to unknown groups */
322 /* The group must have been obtained with a vfio device */
323 stw_p(&resgrp
->hdr
.rsp
, CLP_RC_QUERYPCIFG_PFGID
);
326 resgrp
->fr
= group
->zpci_group
.fr
;
327 stq_p(&resgrp
->dasm
, group
->zpci_group
.dasm
);
328 stq_p(&resgrp
->msia
, group
->zpci_group
.msia
);
329 stw_p(&resgrp
->mui
, group
->zpci_group
.mui
);
330 stw_p(&resgrp
->i
, group
->zpci_group
.i
);
331 stw_p(&resgrp
->maxstbl
, group
->zpci_group
.maxstbl
);
332 resgrp
->version
= group
->zpci_group
.version
;
333 stw_p(&resgrp
->hdr
.rsp
, CLP_RC_OK
);
337 DPRINTF("unknown clp command\n");
338 stw_p(&resh
->rsp
, CLP_RC_CMD
);
343 if (s390_cpu_virt_mem_write(cpu
, env
->regs
[r2
], r2
, buffer
,
344 req_len
+ res_len
)) {
345 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
353 * Swap data contained in s390x big endian registers to little endian
356 * @ptr: a pointer to a uint64_t data field
357 * @len: the length of the valid data, must be 1,2,4 or 8
359 static int zpci_endian_swap(uint64_t *ptr
, uint8_t len
)
361 uint64_t data
= *ptr
;
367 data
= bswap16(data
);
370 data
= bswap32(data
);
373 data
= bswap64(data
);
382 static MemoryRegion
*s390_get_subregion(MemoryRegion
*mr
, uint64_t offset
,
385 MemoryRegion
*subregion
;
386 uint64_t subregion_size
;
388 QTAILQ_FOREACH(subregion
, &mr
->subregions
, subregions_link
) {
389 subregion_size
= int128_get64(subregion
->size
);
390 if ((offset
>= subregion
->addr
) &&
391 (offset
+ len
) <= (subregion
->addr
+ subregion_size
)) {
399 static MemTxResult
zpci_read_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
400 uint64_t offset
, uint64_t *data
, uint8_t len
)
404 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
405 mr
= s390_get_subregion(mr
, offset
, len
);
407 return memory_region_dispatch_read(mr
, offset
, data
,
408 size_memop(len
) | MO_BE
,
409 MEMTXATTRS_UNSPECIFIED
);
412 int pcilg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
414 CPUS390XState
*env
= &cpu
->env
;
415 S390PCIBusDevice
*pbdev
;
423 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
424 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
429 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
433 fh
= env
->regs
[r2
] >> 32;
434 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
435 len
= env
->regs
[r2
] & 0xf;
436 offset
= env
->regs
[r2
+ 1];
438 if (!(fh
& FH_MASK_ENABLE
)) {
439 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
443 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
445 DPRINTF("pcilg no pci dev\n");
446 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
450 switch (pbdev
->state
) {
451 case ZPCI_FS_PERMANENT_ERROR
:
453 setcc(cpu
, ZPCI_PCI_LS_ERR
);
454 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
461 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
462 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
463 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
466 result
= zpci_read_bar(pbdev
, pcias
, offset
, &data
, len
);
467 if (result
!= MEMTX_OK
) {
468 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
472 case ZPCI_CONFIG_BAR
:
473 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
474 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
477 data
= pci_host_config_read_common(
478 pbdev
->pdev
, offset
, pci_config_size(pbdev
->pdev
), len
);
480 if (zpci_endian_swap(&data
, len
)) {
481 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
486 DPRINTF("pcilg invalid space\n");
487 setcc(cpu
, ZPCI_PCI_LS_ERR
);
488 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
492 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_LD
]++;
494 env
->regs
[r1
] = data
;
495 setcc(cpu
, ZPCI_PCI_LS_OK
);
499 static MemTxResult
zpci_write_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
500 uint64_t offset
, uint64_t data
, uint8_t len
)
504 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
505 mr
= s390_get_subregion(mr
, offset
, len
);
507 return memory_region_dispatch_write(mr
, offset
, data
,
508 size_memop(len
) | MO_BE
,
509 MEMTXATTRS_UNSPECIFIED
);
512 int pcistg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
514 CPUS390XState
*env
= &cpu
->env
;
515 uint64_t offset
, data
;
516 S390PCIBusDevice
*pbdev
;
522 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
523 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
528 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
532 fh
= env
->regs
[r2
] >> 32;
533 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
534 len
= env
->regs
[r2
] & 0xf;
535 offset
= env
->regs
[r2
+ 1];
536 data
= env
->regs
[r1
];
538 if (!(fh
& FH_MASK_ENABLE
)) {
539 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
543 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
545 DPRINTF("pcistg no pci dev\n");
546 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
550 switch (pbdev
->state
) {
551 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
552 * are already covered by the FH_MASK_ENABLE check above
554 case ZPCI_FS_PERMANENT_ERROR
:
556 setcc(cpu
, ZPCI_PCI_LS_ERR
);
557 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
564 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
565 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
567 * A length of 0 is invalid and length should not cross a double word
569 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
570 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
574 result
= zpci_write_bar(pbdev
, pcias
, offset
, data
, len
);
575 if (result
!= MEMTX_OK
) {
576 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
580 case ZPCI_CONFIG_BAR
:
581 /* ZPCI uses the pseudo BAR number 15 as configuration space */
582 /* possible access lengths are 1,2,4 and must not cross a word */
583 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
584 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
587 /* len = 1,2,4 so we do not need to test */
588 zpci_endian_swap(&data
, len
);
589 pci_host_config_write_common(pbdev
->pdev
, offset
,
590 pci_config_size(pbdev
->pdev
),
594 DPRINTF("pcistg invalid space\n");
595 setcc(cpu
, ZPCI_PCI_LS_ERR
);
596 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
600 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_ST
]++;
602 setcc(cpu
, ZPCI_PCI_LS_OK
);
606 static uint32_t s390_pci_update_iotlb(S390PCIIOMMU
*iommu
,
607 S390IOTLBEntry
*entry
)
609 S390IOTLBEntry
*cache
= g_hash_table_lookup(iommu
->iotlb
, &entry
->iova
);
610 IOMMUTLBEvent event
= {
611 .type
= entry
->perm
? IOMMU_NOTIFIER_MAP
: IOMMU_NOTIFIER_UNMAP
,
613 .target_as
= &address_space_memory
,
615 .translated_addr
= entry
->translated_addr
,
617 .addr_mask
= ~PAGE_MASK
,
621 if (event
.type
== IOMMU_NOTIFIER_UNMAP
) {
625 g_hash_table_remove(iommu
->iotlb
, &entry
->iova
);
626 inc_dma_avail(iommu
);
629 if (cache
->perm
== entry
->perm
&&
630 cache
->translated_addr
== entry
->translated_addr
) {
634 event
.type
= IOMMU_NOTIFIER_UNMAP
;
635 event
.entry
.perm
= IOMMU_NONE
;
636 memory_region_notify_iommu(&iommu
->iommu_mr
, 0, event
);
637 event
.type
= IOMMU_NOTIFIER_MAP
;
638 event
.entry
.perm
= entry
->perm
;
641 cache
= g_new(S390IOTLBEntry
, 1);
642 cache
->iova
= entry
->iova
;
643 cache
->translated_addr
= entry
->translated_addr
;
644 cache
->len
= PAGE_SIZE
;
645 cache
->perm
= entry
->perm
;
646 g_hash_table_replace(iommu
->iotlb
, &cache
->iova
, cache
);
647 dec_dma_avail(iommu
);
650 memory_region_notify_iommu(&iommu
->iommu_mr
, 0, event
);
653 return iommu
->dma_limit
? iommu
->dma_limit
->avail
: 1;
656 int rpcit_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
658 CPUS390XState
*env
= &cpu
->env
;
661 S390PCIBusDevice
*pbdev
;
663 S390IOTLBEntry entry
;
667 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
668 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
673 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
677 fh
= env
->regs
[r1
] >> 32;
678 start
= env
->regs
[r2
];
679 end
= start
+ env
->regs
[r2
+ 1];
681 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
683 DPRINTF("rpcit no pci dev\n");
684 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
688 switch (pbdev
->state
) {
689 case ZPCI_FS_RESERVED
:
690 case ZPCI_FS_STANDBY
:
691 case ZPCI_FS_DISABLED
:
692 case ZPCI_FS_PERMANENT_ERROR
:
693 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
696 setcc(cpu
, ZPCI_PCI_LS_ERR
);
697 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_ERROR_RECOVER
);
703 iommu
= pbdev
->iommu
;
704 if (iommu
->dma_limit
) {
705 dma_avail
= iommu
->dma_limit
->avail
;
709 if (!iommu
->g_iota
) {
710 error
= ERR_EVENT_INVALAS
;
714 if (end
< iommu
->pba
|| start
> iommu
->pal
) {
715 error
= ERR_EVENT_OORANGE
;
719 while (start
< end
) {
720 error
= s390_guest_io_table_walk(iommu
->g_iota
, start
, &entry
);
726 while (entry
.iova
< start
&& entry
.iova
< end
&&
727 (dma_avail
> 0 || entry
.perm
== IOMMU_NONE
)) {
728 dma_avail
= s390_pci_update_iotlb(iommu
, &entry
);
729 entry
.iova
+= PAGE_SIZE
;
730 entry
.translated_addr
+= PAGE_SIZE
;
735 pbdev
->state
= ZPCI_FS_ERROR
;
736 setcc(cpu
, ZPCI_PCI_LS_ERR
);
737 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_FUNC_IN_ERR
);
738 s390_pci_generate_error_event(error
, pbdev
->fh
, pbdev
->fid
, start
, 0);
740 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_RPCIT
]++;
742 setcc(cpu
, ZPCI_PCI_LS_OK
);
744 /* vfio DMA mappings are exhausted, trigger a RPCIT */
745 setcc(cpu
, ZPCI_PCI_LS_ERR
);
746 s390_set_status_code(env
, r1
, ZPCI_RPCIT_ST_INSUFF_RES
);
752 int pcistb_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r3
, uint64_t gaddr
,
753 uint8_t ar
, uintptr_t ra
)
755 CPUS390XState
*env
= &cpu
->env
;
756 S390PCIBusDevice
*pbdev
;
766 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
767 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
771 fh
= env
->regs
[r1
] >> 32;
772 pcias
= (env
->regs
[r1
] >> 16) & 0xf;
773 len
= env
->regs
[r1
] & 0x1fff;
774 offset
= env
->regs
[r3
];
776 if (!(fh
& FH_MASK_ENABLE
)) {
777 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
781 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
783 DPRINTF("pcistb no pci dev fh 0x%x\n", fh
);
784 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
788 switch (pbdev
->state
) {
789 case ZPCI_FS_PERMANENT_ERROR
:
791 setcc(cpu
, ZPCI_PCI_LS_ERR
);
792 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_BLOCKED
);
798 if (pcias
> ZPCI_IO_BAR_MAX
) {
799 DPRINTF("pcistb invalid space\n");
800 setcc(cpu
, ZPCI_PCI_LS_ERR
);
801 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INVAL_AS
);
805 /* Verify the address, offset and length */
806 /* offset must be a multiple of 8 */
808 goto specification_error
;
810 /* Length must be greater than 8, a multiple of 8 */
811 /* and not greater than maxstbl */
812 if ((len
<= 8) || (len
% 8) ||
813 (len
> pbdev
->pci_group
->zpci_group
.maxstbl
)) {
814 goto specification_error
;
816 /* Do not cross a 4K-byte boundary */
817 if (((offset
& 0xfff) + len
) > 0x1000) {
818 goto specification_error
;
820 /* Guest address must be double word aligned */
821 if (gaddr
& 0x07UL
) {
822 goto specification_error
;
825 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
826 mr
= s390_get_subregion(mr
, offset
, len
);
829 for (i
= 0; i
< len
; i
+= 8) {
830 if (!memory_region_access_valid(mr
, offset
+ i
, 8, true,
831 MEMTXATTRS_UNSPECIFIED
)) {
832 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
837 if (s390_cpu_virt_mem_read(cpu
, gaddr
, ar
, buffer
, len
)) {
838 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
842 for (i
= 0; i
< len
/ 8; i
++) {
843 result
= memory_region_dispatch_write(mr
, offset
+ i
* 8,
844 ldq_p(buffer
+ i
* 8),
845 MO_64
, MEMTXATTRS_UNSPECIFIED
);
846 if (result
!= MEMTX_OK
) {
847 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
852 pbdev
->fmb
.counter
[ZPCI_FMB_CNT_STB
]++;
854 setcc(cpu
, ZPCI_PCI_LS_OK
);
858 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
862 static int reg_irqs(CPUS390XState
*env
, S390PCIBusDevice
*pbdev
, ZpciFib fib
)
865 uint8_t isc
= FIB_DATA_ISC(ldl_p(&fib
.data
));
867 pbdev
->routes
.adapter
.adapter_id
= css_get_adapter_id(
868 CSS_IO_ADAPTER_PCI
, isc
);
869 pbdev
->summary_ind
= get_indicator(ldq_p(&fib
.aisb
), sizeof(uint64_t));
870 len
= BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib
.data
))) * sizeof(unsigned long);
871 pbdev
->indicator
= get_indicator(ldq_p(&fib
.aibv
), len
);
873 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
878 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
883 pbdev
->routes
.adapter
.summary_addr
= ldq_p(&fib
.aisb
);
884 pbdev
->routes
.adapter
.summary_offset
= FIB_DATA_AISBO(ldl_p(&fib
.data
));
885 pbdev
->routes
.adapter
.ind_addr
= ldq_p(&fib
.aibv
);
886 pbdev
->routes
.adapter
.ind_offset
= FIB_DATA_AIBVO(ldl_p(&fib
.data
));
888 pbdev
->noi
= FIB_DATA_NOI(ldl_p(&fib
.data
));
889 pbdev
->sum
= FIB_DATA_SUM(ldl_p(&fib
.data
));
891 DPRINTF("reg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
894 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
895 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
896 pbdev
->summary_ind
= NULL
;
897 pbdev
->indicator
= NULL
;
901 int pci_dereg_irqs(S390PCIBusDevice
*pbdev
)
903 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
904 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
906 pbdev
->summary_ind
= NULL
;
907 pbdev
->indicator
= NULL
;
908 pbdev
->routes
.adapter
.summary_addr
= 0;
909 pbdev
->routes
.adapter
.summary_offset
= 0;
910 pbdev
->routes
.adapter
.ind_addr
= 0;
911 pbdev
->routes
.adapter
.ind_offset
= 0;
916 DPRINTF("dereg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
920 static int reg_ioat(CPUS390XState
*env
, S390PCIIOMMU
*iommu
, ZpciFib fib
,
923 uint64_t pba
= ldq_p(&fib
.pba
);
924 uint64_t pal
= ldq_p(&fib
.pal
);
925 uint64_t g_iota
= ldq_p(&fib
.iota
);
926 uint8_t dt
= (g_iota
>> 2) & 0x7;
927 uint8_t t
= (g_iota
>> 11) & 0x1;
931 if (pba
> pal
|| pba
< ZPCI_SDMA_ADDR
|| pal
> ZPCI_EDMA_ADDR
) {
932 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
936 /* currently we only support designation type 1 with translation */
937 if (!(dt
== ZPCI_IOTA_RTTO
&& t
)) {
938 error_report("unsupported ioat dt %d t %d", dt
, t
);
939 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
945 iommu
->g_iota
= g_iota
;
947 s390_pci_iommu_enable(iommu
);
952 void pci_dereg_ioat(S390PCIIOMMU
*iommu
)
954 s390_pci_iommu_disable(iommu
);
960 void fmb_timer_free(S390PCIBusDevice
*pbdev
)
962 if (pbdev
->fmb_timer
) {
963 timer_free(pbdev
->fmb_timer
);
964 pbdev
->fmb_timer
= NULL
;
967 memset(&pbdev
->fmb
, 0, sizeof(ZpciFmb
));
970 static int fmb_do_update(S390PCIBusDevice
*pbdev
, int offset
, uint64_t val
,
974 uint64_t dst
= pbdev
->fmb_addr
+ offset
;
978 address_space_stq_be(&address_space_memory
, dst
, val
,
979 MEMTXATTRS_UNSPECIFIED
,
983 address_space_stl_be(&address_space_memory
, dst
, val
,
984 MEMTXATTRS_UNSPECIFIED
,
988 address_space_stw_be(&address_space_memory
, dst
, val
,
989 MEMTXATTRS_UNSPECIFIED
,
993 address_space_stb(&address_space_memory
, dst
, val
,
994 MEMTXATTRS_UNSPECIFIED
,
1001 if (ret
!= MEMTX_OK
) {
1002 s390_pci_generate_error_event(ERR_EVENT_FMBA
, pbdev
->fh
, pbdev
->fid
,
1003 pbdev
->fmb_addr
, 0);
1004 fmb_timer_free(pbdev
);
1010 static void fmb_update(void *opaque
)
1012 S390PCIBusDevice
*pbdev
= opaque
;
1013 int64_t t
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1017 pbdev
->fmb
.last_update
*= 2;
1018 pbdev
->fmb
.last_update
|= UPDATE_U_BIT
;
1019 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, last_update
),
1020 pbdev
->fmb
.last_update
,
1021 sizeof(pbdev
->fmb
.last_update
))) {
1025 /* Update FMB sample count */
1026 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, sample
),
1027 pbdev
->fmb
.sample
++,
1028 sizeof(pbdev
->fmb
.sample
))) {
1032 /* Update FMB counters */
1033 for (i
= 0; i
< ZPCI_FMB_CNT_MAX
; i
++) {
1034 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, counter
[i
]),
1035 pbdev
->fmb
.counter
[i
],
1036 sizeof(pbdev
->fmb
.counter
[0]))) {
1041 /* Clear U bit and update the time */
1042 pbdev
->fmb
.last_update
= time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
1043 pbdev
->fmb
.last_update
*= 2;
1044 if (fmb_do_update(pbdev
, offsetof(ZpciFmb
, last_update
),
1045 pbdev
->fmb
.last_update
,
1046 sizeof(pbdev
->fmb
.last_update
))) {
1049 timer_mod(pbdev
->fmb_timer
, t
+ DEFAULT_MUI
);
1052 int mpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
1055 CPUS390XState
*env
= &cpu
->env
;
1059 S390PCIBusDevice
*pbdev
;
1060 uint64_t cc
= ZPCI_PCI_LS_OK
;
1062 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
1063 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
1067 oc
= env
->regs
[r1
] & 0xff;
1068 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1069 fh
= env
->regs
[r1
] >> 32;
1072 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
1076 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
1078 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh
);
1079 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1083 switch (pbdev
->state
) {
1084 case ZPCI_FS_RESERVED
:
1085 case ZPCI_FS_STANDBY
:
1086 case ZPCI_FS_DISABLED
:
1087 case ZPCI_FS_PERMANENT_ERROR
:
1088 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1094 if (s390_cpu_virt_mem_read(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1095 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
1100 s390_program_interrupt(env
, PGM_OPERAND
, ra
);
1105 case ZPCI_MOD_FC_REG_INT
:
1106 if (pbdev
->summary_ind
) {
1107 cc
= ZPCI_PCI_LS_ERR
;
1108 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1109 } else if (reg_irqs(env
, pbdev
, fib
)) {
1110 cc
= ZPCI_PCI_LS_ERR
;
1111 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_RES_NOT_AVAIL
);
1114 case ZPCI_MOD_FC_DEREG_INT
:
1115 if (!pbdev
->summary_ind
) {
1116 cc
= ZPCI_PCI_LS_ERR
;
1117 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1119 pci_dereg_irqs(pbdev
);
1122 case ZPCI_MOD_FC_REG_IOAT
:
1124 cc
= ZPCI_PCI_LS_ERR
;
1125 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1126 } else if (pbdev
->iommu
->enabled
) {
1127 cc
= ZPCI_PCI_LS_ERR
;
1128 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1129 } else if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
1130 cc
= ZPCI_PCI_LS_ERR
;
1131 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
1134 case ZPCI_MOD_FC_DEREG_IOAT
:
1136 cc
= ZPCI_PCI_LS_ERR
;
1137 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1138 } else if (!pbdev
->iommu
->enabled
) {
1139 cc
= ZPCI_PCI_LS_ERR
;
1140 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1142 pci_dereg_ioat(pbdev
->iommu
);
1145 case ZPCI_MOD_FC_REREG_IOAT
:
1147 cc
= ZPCI_PCI_LS_ERR
;
1148 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
1149 } else if (!pbdev
->iommu
->enabled
) {
1150 cc
= ZPCI_PCI_LS_ERR
;
1151 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1153 pci_dereg_ioat(pbdev
->iommu
);
1154 if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
1155 cc
= ZPCI_PCI_LS_ERR
;
1156 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
1160 case ZPCI_MOD_FC_RESET_ERROR
:
1161 switch (pbdev
->state
) {
1162 case ZPCI_FS_BLOCKED
:
1164 pbdev
->state
= ZPCI_FS_ENABLED
;
1167 cc
= ZPCI_PCI_LS_ERR
;
1168 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1171 case ZPCI_MOD_FC_RESET_BLOCK
:
1172 switch (pbdev
->state
) {
1174 pbdev
->state
= ZPCI_FS_BLOCKED
;
1177 cc
= ZPCI_PCI_LS_ERR
;
1178 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1181 case ZPCI_MOD_FC_SET_MEASURE
: {
1182 uint64_t fmb_addr
= ldq_p(&fib
.fmb_addr
);
1184 if (fmb_addr
& FMBK_MASK
) {
1185 cc
= ZPCI_PCI_LS_ERR
;
1186 s390_pci_generate_error_event(ERR_EVENT_FMBPRO
, pbdev
->fh
,
1187 pbdev
->fid
, fmb_addr
, 0);
1188 fmb_timer_free(pbdev
);
1193 /* Stop updating FMB. */
1194 fmb_timer_free(pbdev
);
1198 if (!pbdev
->fmb_timer
) {
1199 pbdev
->fmb_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
1201 } else if (timer_pending(pbdev
->fmb_timer
)) {
1202 /* Remove pending timer to update FMB address. */
1203 timer_del(pbdev
->fmb_timer
);
1205 pbdev
->fmb_addr
= fmb_addr
;
1206 timer_mod(pbdev
->fmb_timer
,
1207 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + DEFAULT_MUI
);
1211 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, ra
);
1212 cc
= ZPCI_PCI_LS_ERR
;
1219 int stpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
1222 CPUS390XState
*env
= &cpu
->env
;
1226 S390PCIBusDevice
*pbdev
;
1228 uint64_t cc
= ZPCI_PCI_LS_OK
;
1230 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
1231 s390_program_interrupt(env
, PGM_PRIVILEGED
, ra
);
1235 fh
= env
->regs
[r1
] >> 32;
1236 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1239 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1240 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_INVAL_DMAAS
);
1245 s390_program_interrupt(env
, PGM_SPECIFICATION
, ra
);
1249 pbdev
= s390_pci_find_dev_by_idx(s390_get_phb(), fh
& FH_MASK_INDEX
);
1251 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1255 memset(&fib
, 0, sizeof(fib
));
1257 switch (pbdev
->state
) {
1258 case ZPCI_FS_RESERVED
:
1259 case ZPCI_FS_STANDBY
:
1260 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1262 case ZPCI_FS_DISABLED
:
1263 if (fh
& FH_MASK_ENABLE
) {
1264 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1268 /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1269 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1273 case ZPCI_FS_BLOCKED
:
1276 case ZPCI_FS_ENABLED
:
1278 if (pbdev
->iommu
->enabled
) {
1281 if (!(fh
& FH_MASK_ENABLE
)) {
1282 env
->regs
[r1
] |= 1ULL << 63;
1285 case ZPCI_FS_PERMANENT_ERROR
:
1286 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1287 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_PERM_ERROR
);
1291 stq_p(&fib
.pba
, pbdev
->iommu
->pba
);
1292 stq_p(&fib
.pal
, pbdev
->iommu
->pal
);
1293 stq_p(&fib
.iota
, pbdev
->iommu
->g_iota
);
1294 stq_p(&fib
.aibv
, pbdev
->routes
.adapter
.ind_addr
);
1295 stq_p(&fib
.aisb
, pbdev
->routes
.adapter
.summary_addr
);
1296 stq_p(&fib
.fmb_addr
, pbdev
->fmb_addr
);
1298 data
= ((uint32_t)pbdev
->isc
<< 28) | ((uint32_t)pbdev
->noi
<< 16) |
1299 ((uint32_t)pbdev
->routes
.adapter
.ind_offset
<< 8) |
1300 ((uint32_t)pbdev
->sum
<< 7) | pbdev
->routes
.adapter
.summary_offset
;
1301 stl_p(&fib
.data
, data
);
1304 if (s390_cpu_virt_mem_write(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1305 s390_cpu_virt_mem_handle_exc(cpu
, ra
);