hw/s390x/s390-pci-inst.c

   1 /*
   2  * s390 PCI instructions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "cpu.h"
  16 #include "exec/memop.h"
  17 #include "exec/memory-internal.h"
  18 #include "qemu/error-report.h"
  19 #include "sysemu/hw_accel.h"
  20 #include "hw/s390x/s390-pci-inst.h"
  21 #include "hw/s390x/s390-pci-bus.h"
  22 #include "hw/s390x/tod.h"
  23
  24 #ifndef DEBUG_S390PCI_INST
  25 #define DEBUG_S390PCI_INST  0
  26 #endif
  27
  28 #define DPRINTF(fmt, ...)                                          \
  29     do {                                                           \
  30         if (DEBUG_S390PCI_INST) {                                  \
  31             fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
  32         }                                                          \
  33     } while (0)
  34
  35 static inline void inc_dma_avail(S390PCIIOMMU *iommu)
  36 {
  37     if (iommu->dma_limit) {
  38         iommu->dma_limit->avail++;
  39     }
  40 }
  41
  42 static inline void dec_dma_avail(S390PCIIOMMU *iommu)
  43 {
  44     if (iommu->dma_limit) {
  45         iommu->dma_limit->avail--;
  46     }
  47 }
  48
  49 static void s390_set_status_code(CPUS390XState *env,
  50                                  uint8_t r, uint64_t status_code)
  51 {
  52     env->regs[r] &= ~0xff000000ULL;
  53     env->regs[r] |= (status_code & 0xff) << 24;
  54 }
  55
  56 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
  57 {
  58     S390PCIBusDevice *pbdev = NULL;
  59     S390pciState *s = s390_get_phb();
  60     uint32_t res_code, initial_l2, g_l2;
  61     int rc, i;
  62     uint64_t resume_token;
  63
  64     rc = 0;
  65     if (lduw_p(&rrb->request.hdr.len) != 32) {
  66         res_code = CLP_RC_LEN;
  67         rc = -EINVAL;
  68         goto out;
  69     }
  70
  71     if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
  72         res_code = CLP_RC_FMT;
  73         rc = -EINVAL;
  74         goto out;
  75     }
  76
  77     if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
  78         ldq_p(&rrb->request.reserved1) != 0) {
  79         res_code = CLP_RC_RESNOT0;
  80         rc = -EINVAL;
  81         goto out;
  82     }
  83
  84     resume_token = ldq_p(&rrb->request.resume_token);
  85
  86     if (resume_token) {
  87         pbdev = s390_pci_find_dev_by_idx(s, resume_token);
  88         if (!pbdev) {
  89             res_code = CLP_RC_LISTPCI_BADRT;
  90             rc = -EINVAL;
  91             goto out;
  92         }
  93     } else {
  94         pbdev = s390_pci_find_next_avail_dev(s, NULL);
  95     }
  96
  97     if (lduw_p(&rrb->response.hdr.len) < 48) {
  98         res_code = CLP_RC_8K;
  99         rc = -EINVAL;
 100         goto out;
 101     }
 102
 103     initial_l2 = lduw_p(&rrb->response.hdr.len);
 104     if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
 105         != 0) {
 106         res_code = CLP_RC_LEN;
 107         rc = -EINVAL;
 108         *cc = 3;
 109         goto out;
 110     }
 111
 112     stl_p(&rrb->response.fmt, 0);
 113     stq_p(&rrb->response.reserved1, 0);
 114     stl_p(&rrb->response.mdd, FH_MASK_SHM);
 115     stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
 116     rrb->response.flags = UID_CHECKING_ENABLED;
 117     rrb->response.entry_size = sizeof(ClpFhListEntry);
 118
 119     i = 0;
 120     g_l2 = LIST_PCI_HDR_LEN;
 121     while (g_l2 < initial_l2 && pbdev) {
 122         stw_p(&rrb->response.fh_list[i].device_id,
 123             pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
 124         stw_p(&rrb->response.fh_list[i].vendor_id,
 125             pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
 126         /* Ignore RESERVED devices. */
 127         stl_p(&rrb->response.fh_list[i].config,
 128             pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
 129         stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
 130         stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
 131
 132         g_l2 += sizeof(ClpFhListEntry);
 133         /* Add endian check for DPRINTF? */
 134         DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
 135                 g_l2,
 136                 lduw_p(&rrb->response.fh_list[i].vendor_id),
 137                 lduw_p(&rrb->response.fh_list[i].device_id),
 138                 ldl_p(&rrb->response.fh_list[i].fid),
 139                 ldl_p(&rrb->response.fh_list[i].fh));
 140         pbdev = s390_pci_find_next_avail_dev(s, pbdev);
 141         i++;
 142     }
 143
 144     if (!pbdev) {
 145         resume_token = 0;
 146     } else {
 147         resume_token = pbdev->fh & FH_MASK_INDEX;
 148     }
 149     stq_p(&rrb->response.resume_token, resume_token);
 150     stw_p(&rrb->response.hdr.len, g_l2);
 151     stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
 152 out:
 153     if (rc) {
 154         DPRINTF("list pci failed rc 0x%x\n", rc);
 155         stw_p(&rrb->response.hdr.rsp, res_code);
 156     }
 157     return rc;
 158 }
 159
 160 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
 161 {
 162     ClpReqHdr *reqh;
 163     ClpRspHdr *resh;
 164     S390PCIBusDevice *pbdev;
 165     uint32_t req_len;
 166     uint32_t res_len;
 167     uint8_t buffer[4096 * 2];
 168     uint8_t cc = 0;
 169     CPUS390XState *env = &cpu->env;
 170     S390pciState *s = s390_get_phb();
 171     int i;
 172
 173     if (env->psw.mask & PSW_MASK_PSTATE) {
 174         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
 175         return 0;
 176     }
 177
 178     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
 179         s390_cpu_virt_mem_handle_exc(cpu, ra);
 180         return 0;
 181     }
 182     reqh = (ClpReqHdr *)buffer;
 183     req_len = lduw_p(&reqh->len);
 184     if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
 185         s390_program_interrupt(env, PGM_OPERAND, ra);
 186         return 0;
 187     }
 188
 189     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 190                                req_len + sizeof(*resh))) {
 191         s390_cpu_virt_mem_handle_exc(cpu, ra);
 192         return 0;
 193     }
 194     resh = (ClpRspHdr *)(buffer + req_len);
 195     res_len = lduw_p(&resh->len);
 196     if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
 197         s390_program_interrupt(env, PGM_OPERAND, ra);
 198         return 0;
 199     }
 200     if ((req_len + res_len) > 8192) {
 201         s390_program_interrupt(env, PGM_OPERAND, ra);
 202         return 0;
 203     }
 204
 205     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 206                                req_len + res_len)) {
 207         s390_cpu_virt_mem_handle_exc(cpu, ra);
 208         return 0;
 209     }
 210
 211     if (req_len != 32) {
 212         stw_p(&resh->rsp, CLP_RC_LEN);
 213         goto out;
 214     }
 215
 216     switch (lduw_p(&reqh->cmd)) {
 217     case CLP_LIST_PCI: {
 218         ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
 219         list_pci(rrb, &cc);
 220         break;
 221     }
 222     case CLP_SET_PCI_FN: {
 223         ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
 224         ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
 225
 226         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
 227         if (!pbdev) {
 228                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
 229                 goto out;
 230         }
 231
 232         switch (reqsetpci->oc) {
 233         case CLP_SET_ENABLE_PCI_FN:
 234             switch (reqsetpci->ndas) {
 235             case 0:
 236                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
 237                 goto out;
 238             case 1:
 239                 break;
 240             default:
 241                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
 242                 goto out;
 243             }
 244
 245             if (pbdev->fh & FH_MASK_ENABLE) {
 246                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 247                 goto out;
 248             }
 249
 250             pbdev->fh |= FH_MASK_ENABLE;
 251             pbdev->state = ZPCI_FS_ENABLED;
 252             stl_p(&ressetpci->fh, pbdev->fh);
 253             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 254             break;
 255         case CLP_SET_DISABLE_PCI_FN:
 256             if (!(pbdev->fh & FH_MASK_ENABLE)) {
 257                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 258                 goto out;
 259             }
 260             device_legacy_reset(DEVICE(pbdev));
 261             pbdev->fh &= ~FH_MASK_ENABLE;
 262             pbdev->state = ZPCI_FS_DISABLED;
 263             stl_p(&ressetpci->fh, pbdev->fh);
 264             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 265             break;
 266         default:
 267             DPRINTF("unknown set pci command\n");
 268             stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 269             break;
 270         }
 271         break;
 272     }
 273     case CLP_QUERY_PCI_FN: {
 274         ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
 275         ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
 276
 277         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
 278         if (!pbdev) {
 279             DPRINTF("query pci no pci dev\n");
 280             stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
 281             goto out;
 282         }
 283
 284         stq_p(&resquery->sdma, pbdev->zpci_fn.sdma);
 285         stq_p(&resquery->edma, pbdev->zpci_fn.edma);
 286         stw_p(&resquery->pchid, pbdev->zpci_fn.pchid);
 287         stw_p(&resquery->vfn, pbdev->zpci_fn.vfn);
 288         resquery->flags = pbdev->zpci_fn.flags;
 289         resquery->pfgid = pbdev->zpci_fn.pfgid;
 290         resquery->pft = pbdev->zpci_fn.pft;
 291         resquery->fmbl = pbdev->zpci_fn.fmbl;
 292         stl_p(&resquery->fid, pbdev->zpci_fn.fid);
 293         stl_p(&resquery->uid, pbdev->zpci_fn.uid);
 294         memcpy(resquery->pfip, pbdev->zpci_fn.pfip, CLP_PFIP_NR_SEGMENTS);
 295         memcpy(resquery->util_str, pbdev->zpci_fn.util_str, CLP_UTIL_STR_LEN);
 296
 297         for (i = 0; i < PCI_BAR_COUNT; i++) {
 298             uint32_t data = pci_get_long(pbdev->pdev->config +
 299                 PCI_BASE_ADDRESS_0 + (i * 4));
 300
 301             stl_p(&resquery->bar[i], data);
 302             resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
 303                                     ctz64(pbdev->pdev->io_regions[i].size) : 0;
 304             DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
 305                     ldl_p(&resquery->bar[i]),
 306                     pbdev->pdev->io_regions[i].size,
 307                     resquery->bar_size[i]);
 308         }
 309
 310         stw_p(&resquery->hdr.rsp, CLP_RC_OK);
 311         break;
 312     }
 313     case CLP_QUERY_PCI_FNGRP: {
 314         ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
 315
 316         ClpReqQueryPciGrp *reqgrp = (ClpReqQueryPciGrp *)reqh;
 317         S390PCIGroup *group;
 318
 319         group = s390_group_find(reqgrp->g);
 320         if (!group) {
 321             /* We do not allow access to unknown groups */
 322             /* The group must have been obtained with a vfio device */
 323             stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID);
 324             goto out;
 325         }
 326         resgrp->fr = group->zpci_group.fr;
 327         stq_p(&resgrp->dasm, group->zpci_group.dasm);
 328         stq_p(&resgrp->msia, group->zpci_group.msia);
 329         stw_p(&resgrp->mui, group->zpci_group.mui);
 330         stw_p(&resgrp->i, group->zpci_group.i);
 331         stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl);
 332         resgrp->version = group->zpci_group.version;
 333         stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
 334         break;
 335     }
 336     default:
 337         DPRINTF("unknown clp command\n");
 338         stw_p(&resh->rsp, CLP_RC_CMD);
 339         break;
 340     }
 341
 342 out:
 343     if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
 344                                 req_len + res_len)) {
 345         s390_cpu_virt_mem_handle_exc(cpu, ra);
 346         return 0;
 347     }
 348     setcc(cpu, cc);
 349     return 0;
 350 }
 351
 352 /**
 353  * Swap data contained in s390x big endian registers to little endian
 354  * PCI bars.
 355  *
 356  * @ptr: a pointer to a uint64_t data field
 357  * @len: the length of the valid data, must be 1,2,4 or 8
 358  */
 359 static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
 360 {
 361     uint64_t data = *ptr;
 362
 363     switch (len) {
 364     case 1:
 365         break;
 366     case 2:
 367         data = bswap16(data);
 368         break;
 369     case 4:
 370         data = bswap32(data);
 371         break;
 372     case 8:
 373         data = bswap64(data);
 374         break;
 375     default:
 376         return -EINVAL;
 377     }
 378     *ptr = data;
 379     return 0;
 380 }
 381
 382 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
 383                                         uint8_t len)
 384 {
 385     MemoryRegion *subregion;
 386     uint64_t subregion_size;
 387
 388     QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
 389         subregion_size = int128_get64(subregion->size);
 390         if ((offset >= subregion->addr) &&
 391             (offset + len) <= (subregion->addr + subregion_size)) {
 392             mr = subregion;
 393             break;
 394         }
 395     }
 396     return mr;
 397 }
 398
 399 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
 400                                  uint64_t offset, uint64_t *data, uint8_t len)
 401 {
 402     MemoryRegion *mr;
 403
 404     mr = pbdev->pdev->io_regions[pcias].memory;
 405     mr = s390_get_subregion(mr, offset, len);
 406     offset -= mr->addr;
 407     return memory_region_dispatch_read(mr, offset, data,
 408                                        size_memop(len) | MO_BE,
 409                                        MEMTXATTRS_UNSPECIFIED);
 410 }
 411
 412 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 413 {
 414     CPUS390XState *env = &cpu->env;
 415     S390PCIBusDevice *pbdev;
 416     uint64_t offset;
 417     uint64_t data;
 418     MemTxResult result;
 419     uint8_t len;
 420     uint32_t fh;
 421     uint8_t pcias;
 422
 423     if (env->psw.mask & PSW_MASK_PSTATE) {
 424         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
 425         return 0;
 426     }
 427
 428     if (r2 & 0x1) {
 429         s390_program_interrupt(env, PGM_SPECIFICATION, ra);
 430         return 0;
 431     }
 432
 433     fh = env->regs[r2] >> 32;
 434     pcias = (env->regs[r2] >> 16) & 0xf;
 435     len = env->regs[r2] & 0xf;
 436     offset = env->regs[r2 + 1];
 437
 438     if (!(fh & FH_MASK_ENABLE)) {
 439         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 440         return 0;
 441     }
 442
 443     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 444     if (!pbdev) {
 445         DPRINTF("pcilg no pci dev\n");
 446         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 447         return 0;
 448     }
 449
 450     switch (pbdev->state) {
 451     case ZPCI_FS_PERMANENT_ERROR:
 452     case ZPCI_FS_ERROR:
 453         setcc(cpu, ZPCI_PCI_LS_ERR);
 454         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 455         return 0;
 456     default:
 457         break;
 458     }
 459
 460     switch (pcias) {
 461     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 462         if (!len || (len > (8 - (offset & 0x7)))) {
 463             s390_program_interrupt(env, PGM_OPERAND, ra);
 464             return 0;
 465         }
 466         result = zpci_read_bar(pbdev, pcias, offset, &data, len);
 467         if (result != MEMTX_OK) {
 468             s390_program_interrupt(env, PGM_OPERAND, ra);
 469             return 0;
 470         }
 471         break;
 472     case ZPCI_CONFIG_BAR:
 473         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 474             s390_program_interrupt(env, PGM_OPERAND, ra);
 475             return 0;
 476         }
 477         data =  pci_host_config_read_common(
 478                    pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
 479
 480         if (zpci_endian_swap(&data, len)) {
 481             s390_program_interrupt(env, PGM_OPERAND, ra);
 482             return 0;
 483         }
 484         break;
 485     default:
 486         DPRINTF("pcilg invalid space\n");
 487         setcc(cpu, ZPCI_PCI_LS_ERR);
 488         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 489         return 0;
 490     }
 491
 492     pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++;
 493
 494     env->regs[r1] = data;
 495     setcc(cpu, ZPCI_PCI_LS_OK);
 496     return 0;
 497 }
 498
 499 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
 500                                   uint64_t offset, uint64_t data, uint8_t len)
 501 {
 502     MemoryRegion *mr;
 503
 504     mr = pbdev->pdev->io_regions[pcias].memory;
 505     mr = s390_get_subregion(mr, offset, len);
 506     offset -= mr->addr;
 507     return memory_region_dispatch_write(mr, offset, data,
 508                                         size_memop(len) | MO_BE,
 509                                         MEMTXATTRS_UNSPECIFIED);
 510 }
 511
 512 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 513 {
 514     CPUS390XState *env = &cpu->env;
 515     uint64_t offset, data;
 516     S390PCIBusDevice *pbdev;
 517     MemTxResult result;
 518     uint8_t len;
 519     uint32_t fh;
 520     uint8_t pcias;
 521
 522     if (env->psw.mask & PSW_MASK_PSTATE) {
 523         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
 524         return 0;
 525     }
 526
 527     if (r2 & 0x1) {
 528         s390_program_interrupt(env, PGM_SPECIFICATION, ra);
 529         return 0;
 530     }
 531
 532     fh = env->regs[r2] >> 32;
 533     pcias = (env->regs[r2] >> 16) & 0xf;
 534     len = env->regs[r2] & 0xf;
 535     offset = env->regs[r2 + 1];
 536     data = env->regs[r1];
 537
 538     if (!(fh & FH_MASK_ENABLE)) {
 539         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 540         return 0;
 541     }
 542
 543     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 544     if (!pbdev) {
 545         DPRINTF("pcistg no pci dev\n");
 546         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 547         return 0;
 548     }
 549
 550     switch (pbdev->state) {
 551     /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
 552      * are already covered by the FH_MASK_ENABLE check above
 553      */
 554     case ZPCI_FS_PERMANENT_ERROR:
 555     case ZPCI_FS_ERROR:
 556         setcc(cpu, ZPCI_PCI_LS_ERR);
 557         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 558         return 0;
 559     default:
 560         break;
 561     }
 562
 563     switch (pcias) {
 564         /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
 565     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 566         /* Check length:
 567          * A length of 0 is invalid and length should not cross a double word
 568          */
 569         if (!len || (len > (8 - (offset & 0x7)))) {
 570             s390_program_interrupt(env, PGM_OPERAND, ra);
 571             return 0;
 572         }
 573
 574         result = zpci_write_bar(pbdev, pcias, offset, data, len);
 575         if (result != MEMTX_OK) {
 576             s390_program_interrupt(env, PGM_OPERAND, ra);
 577             return 0;
 578         }
 579         break;
 580     case ZPCI_CONFIG_BAR:
 581         /* ZPCI uses the pseudo BAR number 15 as configuration space */
 582         /* possible access lengths are 1,2,4 and must not cross a word */
 583         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 584             s390_program_interrupt(env, PGM_OPERAND, ra);
 585             return 0;
 586         }
 587         /* len = 1,2,4 so we do not need to test */
 588         zpci_endian_swap(&data, len);
 589         pci_host_config_write_common(pbdev->pdev, offset,
 590                                      pci_config_size(pbdev->pdev),
 591                                      data, len);
 592         break;
 593     default:
 594         DPRINTF("pcistg invalid space\n");
 595         setcc(cpu, ZPCI_PCI_LS_ERR);
 596         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 597         return 0;
 598     }
 599
 600     pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++;
 601
 602     setcc(cpu, ZPCI_PCI_LS_OK);
 603     return 0;
 604 }
 605
 606 static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu,
 607                                       S390IOTLBEntry *entry)
 608 {
 609     S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova);
 610     IOMMUTLBEvent event = {
 611         .type = entry->perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP,
 612         .entry = {
 613             .target_as = &address_space_memory,
 614             .iova = entry->iova,
 615             .translated_addr = entry->translated_addr,
 616             .perm = entry->perm,
 617             .addr_mask = ~PAGE_MASK,
 618         },
 619     };
 620
 621     if (event.type == IOMMU_NOTIFIER_UNMAP) {
 622         if (!cache) {
 623             goto out;
 624         }
 625         g_hash_table_remove(iommu->iotlb, &entry->iova);
 626         inc_dma_avail(iommu);
 627     } else {
 628         if (cache) {
 629             if (cache->perm == entry->perm &&
 630                 cache->translated_addr == entry->translated_addr) {
 631                 goto out;
 632             }
 633
 634             event.type = IOMMU_NOTIFIER_UNMAP;
 635             event.entry.perm = IOMMU_NONE;
 636             memory_region_notify_iommu(&iommu->iommu_mr, 0, event);
 637             event.type = IOMMU_NOTIFIER_MAP;
 638             event.entry.perm = entry->perm;
 639         }
 640
 641         cache = g_new(S390IOTLBEntry, 1);
 642         cache->iova = entry->iova;
 643         cache->translated_addr = entry->translated_addr;
 644         cache->len = PAGE_SIZE;
 645         cache->perm = entry->perm;
 646         g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
 647         dec_dma_avail(iommu);
 648     }
 649
 650     memory_region_notify_iommu(&iommu->iommu_mr, 0, event);
 651
 652 out:
 653     return iommu->dma_limit ? iommu->dma_limit->avail : 1;
 654 }
 655
 656 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 657 {
 658     CPUS390XState *env = &cpu->env;
 659     uint32_t fh;
 660     uint16_t error = 0;
 661     S390PCIBusDevice *pbdev;
 662     S390PCIIOMMU *iommu;
 663     S390IOTLBEntry entry;
 664     hwaddr start, end;
 665     uint32_t dma_avail;
 666
 667     if (env->psw.mask & PSW_MASK_PSTATE) {
 668         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
 669         return 0;
 670     }
 671
 672     if (r2 & 0x1) {
 673         s390_program_interrupt(env, PGM_SPECIFICATION, ra);
 674         return 0;
 675     }
 676
 677     fh = env->regs[r1] >> 32;
 678     start = env->regs[r2];
 679     end = start + env->regs[r2 + 1];
 680
 681     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 682     if (!pbdev) {
 683         DPRINTF("rpcit no pci dev\n");
 684         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 685         return 0;
 686     }
 687
 688     switch (pbdev->state) {
 689     case ZPCI_FS_RESERVED:
 690     case ZPCI_FS_STANDBY:
 691     case ZPCI_FS_DISABLED:
 692     case ZPCI_FS_PERMANENT_ERROR:
 693         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 694         return 0;
 695     case ZPCI_FS_ERROR:
 696         setcc(cpu, ZPCI_PCI_LS_ERR);
 697         s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
 698         return 0;
 699     default:
 700         break;
 701     }
 702
 703     iommu = pbdev->iommu;
 704     if (iommu->dma_limit) {
 705         dma_avail = iommu->dma_limit->avail;
 706     } else {
 707         dma_avail = 1;
 708     }
 709     if (!iommu->g_iota) {
 710         error = ERR_EVENT_INVALAS;
 711         goto err;
 712     }
 713
 714     if (end < iommu->pba || start > iommu->pal) {
 715         error = ERR_EVENT_OORANGE;
 716         goto err;
 717     }
 718
 719     while (start < end) {
 720         error = s390_guest_io_table_walk(iommu->g_iota, start, &entry);
 721         if (error) {
 722             break;
 723         }
 724
 725         start += entry.len;
 726         while (entry.iova < start && entry.iova < end &&
 727                (dma_avail > 0 || entry.perm == IOMMU_NONE)) {
 728             dma_avail = s390_pci_update_iotlb(iommu, &entry);
 729             entry.iova += PAGE_SIZE;
 730             entry.translated_addr += PAGE_SIZE;
 731         }
 732     }
 733 err:
 734     if (error) {
 735         pbdev->state = ZPCI_FS_ERROR;
 736         setcc(cpu, ZPCI_PCI_LS_ERR);
 737         s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR);
 738         s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0);
 739     } else {
 740         pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++;
 741         if (dma_avail > 0) {
 742             setcc(cpu, ZPCI_PCI_LS_OK);
 743         } else {
 744             /* vfio DMA mappings are exhausted, trigger a RPCIT */
 745             setcc(cpu, ZPCI_PCI_LS_ERR);
 746             s390_set_status_code(env, r1, ZPCI_RPCIT_ST_INSUFF_RES);
 747         }
 748     }
 749     return 0;
 750 }
 751
 752 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 753                         uint8_t ar, uintptr_t ra)
 754 {
 755     CPUS390XState *env = &cpu->env;
 756     S390PCIBusDevice *pbdev;
 757     MemoryRegion *mr;
 758     MemTxResult result;
 759     uint64_t offset;
 760     int i;
 761     uint32_t fh;
 762     uint8_t pcias;
 763     uint16_t len;
 764     uint8_t buffer[128];
 765
 766     if (env->psw.mask & PSW_MASK_PSTATE) {
 767         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
 768         return 0;
 769     }
 770
 771     fh = env->regs[r1] >> 32;
 772     pcias = (env->regs[r1] >> 16) & 0xf;
 773     len = env->regs[r1] & 0x1fff;
 774     offset = env->regs[r3];
 775
 776     if (!(fh & FH_MASK_ENABLE)) {
 777         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 778         return 0;
 779     }
 780
 781     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 782     if (!pbdev) {
 783         DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
 784         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 785         return 0;
 786     }
 787
 788     switch (pbdev->state) {
 789     case ZPCI_FS_PERMANENT_ERROR:
 790     case ZPCI_FS_ERROR:
 791         setcc(cpu, ZPCI_PCI_LS_ERR);
 792         s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
 793         return 0;
 794     default:
 795         break;
 796     }
 797
 798     if (pcias > ZPCI_IO_BAR_MAX) {
 799         DPRINTF("pcistb invalid space\n");
 800         setcc(cpu, ZPCI_PCI_LS_ERR);
 801         s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
 802         return 0;
 803     }
 804
 805     /* Verify the address, offset and length */
 806     /* offset must be a multiple of 8 */
 807     if (offset % 8) {
 808         goto specification_error;
 809     }
 810     /* Length must be greater than 8, a multiple of 8 */
 811     /* and not greater than maxstbl */
 812     if ((len <= 8) || (len % 8) ||
 813         (len > pbdev->pci_group->zpci_group.maxstbl)) {
 814         goto specification_error;
 815     }
 816     /* Do not cross a 4K-byte boundary */
 817     if (((offset & 0xfff) + len) > 0x1000) {
 818         goto specification_error;
 819     }
 820     /* Guest address must be double word aligned */
 821     if (gaddr & 0x07UL) {
 822         goto specification_error;
 823     }
 824
 825     mr = pbdev->pdev->io_regions[pcias].memory;
 826     mr = s390_get_subregion(mr, offset, len);
 827     offset -= mr->addr;
 828
 829     for (i = 0; i < len; i += 8) {
 830         if (!memory_region_access_valid(mr, offset + i, 8, true,
 831                                         MEMTXATTRS_UNSPECIFIED)) {
 832             s390_program_interrupt(env, PGM_OPERAND, ra);
 833             return 0;
 834         }
 835     }
 836
 837     if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
 838         s390_cpu_virt_mem_handle_exc(cpu, ra);
 839         return 0;
 840     }
 841
 842     for (i = 0; i < len / 8; i++) {
 843         result = memory_region_dispatch_write(mr, offset + i * 8,
 844                                               ldq_p(buffer + i * 8),
 845                                               MO_64, MEMTXATTRS_UNSPECIFIED);
 846         if (result != MEMTX_OK) {
 847             s390_program_interrupt(env, PGM_OPERAND, ra);
 848             return 0;
 849         }
 850     }
 851
 852     pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++;
 853
 854     setcc(cpu, ZPCI_PCI_LS_OK);
 855     return 0;
 856
 857 specification_error:
 858     s390_program_interrupt(env, PGM_SPECIFICATION, ra);
 859     return 0;
 860 }
 861
 862 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 863 {
 864     int ret, len;
 865     uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
 866
 867     pbdev->routes.adapter.adapter_id = css_get_adapter_id(
 868                                        CSS_IO_ADAPTER_PCI, isc);
 869     pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
 870     len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
 871     pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
 872
 873     ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 874     if (ret) {
 875         goto out;
 876     }
 877
 878     ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
 879     if (ret) {
 880         goto out;
 881     }
 882
 883     pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
 884     pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
 885     pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
 886     pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
 887     pbdev->isc = isc;
 888     pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
 889     pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
 890
 891     DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 892     return 0;
 893 out:
 894     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 895     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 896     pbdev->summary_ind = NULL;
 897     pbdev->indicator = NULL;
 898     return ret;
 899 }
 900
 901 int pci_dereg_irqs(S390PCIBusDevice *pbdev)
 902 {
 903     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 904     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 905
 906     pbdev->summary_ind = NULL;
 907     pbdev->indicator = NULL;
 908     pbdev->routes.adapter.summary_addr = 0;
 909     pbdev->routes.adapter.summary_offset = 0;
 910     pbdev->routes.adapter.ind_addr = 0;
 911     pbdev->routes.adapter.ind_offset = 0;
 912     pbdev->isc = 0;
 913     pbdev->noi = 0;
 914     pbdev->sum = 0;
 915
 916     DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 917     return 0;
 918 }
 919
 920 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
 921                     uintptr_t ra)
 922 {
 923     uint64_t pba = ldq_p(&fib.pba);
 924     uint64_t pal = ldq_p(&fib.pal);
 925     uint64_t g_iota = ldq_p(&fib.iota);
 926     uint8_t dt = (g_iota >> 2) & 0x7;
 927     uint8_t t = (g_iota >> 11) & 0x1;
 928
 929     pba &= ~0xfff;
 930     pal |= 0xfff;
 931     if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
 932         s390_program_interrupt(env, PGM_OPERAND, ra);
 933         return -EINVAL;
 934     }
 935
 936     /* currently we only support designation type 1 with translation */
 937     if (!(dt == ZPCI_IOTA_RTTO && t)) {
 938         error_report("unsupported ioat dt %d t %d", dt, t);
 939         s390_program_interrupt(env, PGM_OPERAND, ra);
 940         return -EINVAL;
 941     }
 942
 943     iommu->pba = pba;
 944     iommu->pal = pal;
 945     iommu->g_iota = g_iota;
 946
 947     s390_pci_iommu_enable(iommu);
 948
 949     return 0;
 950 }
 951
 952 void pci_dereg_ioat(S390PCIIOMMU *iommu)
 953 {
 954     s390_pci_iommu_disable(iommu);
 955     iommu->pba = 0;
 956     iommu->pal = 0;
 957     iommu->g_iota = 0;
 958 }
 959
 960 void fmb_timer_free(S390PCIBusDevice *pbdev)
 961 {
 962     if (pbdev->fmb_timer) {
 963         timer_free(pbdev->fmb_timer);
 964         pbdev->fmb_timer = NULL;
 965     }
 966     pbdev->fmb_addr = 0;
 967     memset(&pbdev->fmb, 0, sizeof(ZpciFmb));
 968 }
 969
 970 static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val,
 971                          int len)
 972 {
 973     MemTxResult ret;
 974     uint64_t dst = pbdev->fmb_addr + offset;
 975
 976     switch (len) {
 977     case 8:
 978         address_space_stq_be(&address_space_memory, dst, val,
 979                              MEMTXATTRS_UNSPECIFIED,
 980                              &ret);
 981         break;
 982     case 4:
 983         address_space_stl_be(&address_space_memory, dst, val,
 984                              MEMTXATTRS_UNSPECIFIED,
 985                              &ret);
 986         break;
 987     case 2:
 988         address_space_stw_be(&address_space_memory, dst, val,
 989                              MEMTXATTRS_UNSPECIFIED,
 990                              &ret);
 991         break;
 992     case 1:
 993         address_space_stb(&address_space_memory, dst, val,
 994                           MEMTXATTRS_UNSPECIFIED,
 995                           &ret);
 996         break;
 997     default:
 998         ret = MEMTX_ERROR;
 999         break;
1000     }
1001     if (ret != MEMTX_OK) {
1002         s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid,
1003                                       pbdev->fmb_addr, 0);
1004         fmb_timer_free(pbdev);
1005     }
1006
1007     return ret;
1008 }
1009
1010 static void fmb_update(void *opaque)
1011 {
1012     S390PCIBusDevice *pbdev = opaque;
1013     int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1014     int i;
1015
1016     /* Update U bit */
1017     pbdev->fmb.last_update *= 2;
1018     pbdev->fmb.last_update |= UPDATE_U_BIT;
1019     if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
1020                       pbdev->fmb.last_update,
1021                       sizeof(pbdev->fmb.last_update))) {
1022         return;
1023     }
1024
1025     /* Update FMB sample count */
1026     if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample),
1027                       pbdev->fmb.sample++,
1028                       sizeof(pbdev->fmb.sample))) {
1029         return;
1030     }
1031
1032     /* Update FMB counters */
1033     for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) {
1034         if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]),
1035                           pbdev->fmb.counter[i],
1036                           sizeof(pbdev->fmb.counter[0]))) {
1037             return;
1038         }
1039     }
1040
1041     /* Clear U bit and update the time */
1042     pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
1043     pbdev->fmb.last_update *= 2;
1044     if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
1045                       pbdev->fmb.last_update,
1046                       sizeof(pbdev->fmb.last_update))) {
1047         return;
1048     }
1049     timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI);
1050 }
1051
1052 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1053                         uintptr_t ra)
1054 {
1055     CPUS390XState *env = &cpu->env;
1056     uint8_t oc, dmaas;
1057     uint32_t fh;
1058     ZpciFib fib;
1059     S390PCIBusDevice *pbdev;
1060     uint64_t cc = ZPCI_PCI_LS_OK;
1061
1062     if (env->psw.mask & PSW_MASK_PSTATE) {
1063         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
1064         return 0;
1065     }
1066
1067     oc = env->regs[r1] & 0xff;
1068     dmaas = (env->regs[r1] >> 16) & 0xff;
1069     fh = env->regs[r1] >> 32;
1070
1071     if (fiba & 0x7) {
1072         s390_program_interrupt(env, PGM_SPECIFICATION, ra);
1073         return 0;
1074     }
1075
1076     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
1077     if (!pbdev) {
1078         DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
1079         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1080         return 0;
1081     }
1082
1083     switch (pbdev->state) {
1084     case ZPCI_FS_RESERVED:
1085     case ZPCI_FS_STANDBY:
1086     case ZPCI_FS_DISABLED:
1087     case ZPCI_FS_PERMANENT_ERROR:
1088         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1089         return 0;
1090     default:
1091         break;
1092     }
1093
1094     if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1095         s390_cpu_virt_mem_handle_exc(cpu, ra);
1096         return 0;
1097     }
1098
1099     if (fib.fmt != 0) {
1100         s390_program_interrupt(env, PGM_OPERAND, ra);
1101         return 0;
1102     }
1103
1104     switch (oc) {
1105     case ZPCI_MOD_FC_REG_INT:
1106         if (pbdev->summary_ind) {
1107             cc = ZPCI_PCI_LS_ERR;
1108             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1109         } else if (reg_irqs(env, pbdev, fib)) {
1110             cc = ZPCI_PCI_LS_ERR;
1111             s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
1112         }
1113         break;
1114     case ZPCI_MOD_FC_DEREG_INT:
1115         if (!pbdev->summary_ind) {
1116             cc = ZPCI_PCI_LS_ERR;
1117             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1118         } else {
1119             pci_dereg_irqs(pbdev);
1120         }
1121         break;
1122     case ZPCI_MOD_FC_REG_IOAT:
1123         if (dmaas != 0) {
1124             cc = ZPCI_PCI_LS_ERR;
1125             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1126         } else if (pbdev->iommu->enabled) {
1127             cc = ZPCI_PCI_LS_ERR;
1128             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1129         } else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1130             cc = ZPCI_PCI_LS_ERR;
1131             s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1132         }
1133         break;
1134     case ZPCI_MOD_FC_DEREG_IOAT:
1135         if (dmaas != 0) {
1136             cc = ZPCI_PCI_LS_ERR;
1137             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1138         } else if (!pbdev->iommu->enabled) {
1139             cc = ZPCI_PCI_LS_ERR;
1140             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1141         } else {
1142             pci_dereg_ioat(pbdev->iommu);
1143         }
1144         break;
1145     case ZPCI_MOD_FC_REREG_IOAT:
1146         if (dmaas != 0) {
1147             cc = ZPCI_PCI_LS_ERR;
1148             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1149         } else if (!pbdev->iommu->enabled) {
1150             cc = ZPCI_PCI_LS_ERR;
1151             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1152         } else {
1153             pci_dereg_ioat(pbdev->iommu);
1154             if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1155                 cc = ZPCI_PCI_LS_ERR;
1156                 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1157             }
1158         }
1159         break;
1160     case ZPCI_MOD_FC_RESET_ERROR:
1161         switch (pbdev->state) {
1162         case ZPCI_FS_BLOCKED:
1163         case ZPCI_FS_ERROR:
1164             pbdev->state = ZPCI_FS_ENABLED;
1165             break;
1166         default:
1167             cc = ZPCI_PCI_LS_ERR;
1168             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1169         }
1170         break;
1171     case ZPCI_MOD_FC_RESET_BLOCK:
1172         switch (pbdev->state) {
1173         case ZPCI_FS_ERROR:
1174             pbdev->state = ZPCI_FS_BLOCKED;
1175             break;
1176         default:
1177             cc = ZPCI_PCI_LS_ERR;
1178             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1179         }
1180         break;
1181     case ZPCI_MOD_FC_SET_MEASURE: {
1182         uint64_t fmb_addr = ldq_p(&fib.fmb_addr);
1183
1184         if (fmb_addr & FMBK_MASK) {
1185             cc = ZPCI_PCI_LS_ERR;
1186             s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh,
1187                                           pbdev->fid, fmb_addr, 0);
1188             fmb_timer_free(pbdev);
1189             break;
1190         }
1191
1192         if (!fmb_addr) {
1193             /* Stop updating FMB. */
1194             fmb_timer_free(pbdev);
1195             break;
1196         }
1197
1198         if (!pbdev->fmb_timer) {
1199             pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
1200                                             fmb_update, pbdev);
1201         } else if (timer_pending(pbdev->fmb_timer)) {
1202             /* Remove pending timer to update FMB address. */
1203             timer_del(pbdev->fmb_timer);
1204         }
1205         pbdev->fmb_addr = fmb_addr;
1206         timer_mod(pbdev->fmb_timer,
1207                   qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI);
1208         break;
1209     }
1210     default:
1211         s390_program_interrupt(&cpu->env, PGM_OPERAND, ra);
1212         cc = ZPCI_PCI_LS_ERR;
1213     }
1214
1215     setcc(cpu, cc);
1216     return 0;
1217 }
1218
1219 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1220                          uintptr_t ra)
1221 {
1222     CPUS390XState *env = &cpu->env;
1223     uint8_t dmaas;
1224     uint32_t fh;
1225     ZpciFib fib;
1226     S390PCIBusDevice *pbdev;
1227     uint32_t data;
1228     uint64_t cc = ZPCI_PCI_LS_OK;
1229
1230     if (env->psw.mask & PSW_MASK_PSTATE) {
1231         s390_program_interrupt(env, PGM_PRIVILEGED, ra);
1232         return 0;
1233     }
1234
1235     fh = env->regs[r1] >> 32;
1236     dmaas = (env->regs[r1] >> 16) & 0xff;
1237
1238     if (dmaas) {
1239         setcc(cpu, ZPCI_PCI_LS_ERR);
1240         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
1241         return 0;
1242     }
1243
1244     if (fiba & 0x7) {
1245         s390_program_interrupt(env, PGM_SPECIFICATION, ra);
1246         return 0;
1247     }
1248
1249     pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1250     if (!pbdev) {
1251         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1252         return 0;
1253     }
1254
1255     memset(&fib, 0, sizeof(fib));
1256
1257     switch (pbdev->state) {
1258     case ZPCI_FS_RESERVED:
1259     case ZPCI_FS_STANDBY:
1260         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1261         return 0;
1262     case ZPCI_FS_DISABLED:
1263         if (fh & FH_MASK_ENABLE) {
1264             setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1265             return 0;
1266         }
1267         goto out;
1268     /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1269      * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1270     case ZPCI_FS_ERROR:
1271         fib.fc |= 0x20;
1272         /* fallthrough */
1273     case ZPCI_FS_BLOCKED:
1274         fib.fc |= 0x40;
1275         /* fallthrough */
1276     case ZPCI_FS_ENABLED:
1277         fib.fc |= 0x80;
1278         if (pbdev->iommu->enabled) {
1279             fib.fc |= 0x10;
1280         }
1281         if (!(fh & FH_MASK_ENABLE)) {
1282             env->regs[r1] |= 1ULL << 63;
1283         }
1284         break;
1285     case ZPCI_FS_PERMANENT_ERROR:
1286         setcc(cpu, ZPCI_PCI_LS_ERR);
1287         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1288         return 0;
1289     }
1290
1291     stq_p(&fib.pba, pbdev->iommu->pba);
1292     stq_p(&fib.pal, pbdev->iommu->pal);
1293     stq_p(&fib.iota, pbdev->iommu->g_iota);
1294     stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1295     stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1296     stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1297
1298     data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1299            ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1300            ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1301     stl_p(&fib.data, data);
1302
1303 out:
1304     if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1305         s390_cpu_virt_mem_handle_exc(cpu, ra);
1306         return 0;
1307     }
1308
1309     setcc(cpu, cc);
1310     return 0;
1311 }