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hw/elf_ops: Fix a typo
[qemu/ar7.git] / hw / mips / gt64xxx_pci.c
blob588e6f993017d1d2804634858ae5752252bda85b
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu/units.h"
28 #include "qemu/log.h"
29 #include "hw/mips/mips.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_host.h"
32 #include "hw/southbridge/piix.h"
33 #include "migration/vmstate.h"
34 #include "hw/intc/i8259.h"
35 #include "hw/irq.h"
36 #include "exec/address-spaces.h"
37 #include "trace.h"
38 #include "qom/object.h"
39
40 #define GT_REGS (0x1000 >> 2)
41
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
45
46 /* CPU Address Decode */
47 #define GT_SCS10LD (0x008 >> 2)
48 #define GT_SCS10HD (0x010 >> 2)
49 #define GT_SCS32LD (0x018 >> 2)
50 #define GT_SCS32HD (0x020 >> 2)
51 #define GT_CS20LD (0x028 >> 2)
52 #define GT_CS20HD (0x030 >> 2)
53 #define GT_CS3BOOTLD (0x038 >> 2)
54 #define GT_CS3BOOTHD (0x040 >> 2)
55 #define GT_PCI0IOLD (0x048 >> 2)
56 #define GT_PCI0IOHD (0x050 >> 2)
57 #define GT_PCI0M0LD (0x058 >> 2)
58 #define GT_PCI0M0HD (0x060 >> 2)
59 #define GT_PCI0M1LD (0x080 >> 2)
60 #define GT_PCI0M1HD (0x088 >> 2)
61 #define GT_PCI1IOLD (0x090 >> 2)
62 #define GT_PCI1IOHD (0x098 >> 2)
63 #define GT_PCI1M0LD (0x0a0 >> 2)
64 #define GT_PCI1M0HD (0x0a8 >> 2)
65 #define GT_PCI1M1LD (0x0b0 >> 2)
66 #define GT_PCI1M1HD (0x0b8 >> 2)
67 #define GT_ISD (0x068 >> 2)
68
69 #define GT_SCS10AR (0x0d0 >> 2)
70 #define GT_SCS32AR (0x0d8 >> 2)
71 #define GT_CS20R (0x0e0 >> 2)
72 #define GT_CS3BOOTR (0x0e8 >> 2)
73
74 #define GT_PCI0IOREMAP (0x0f0 >> 2)
75 #define GT_PCI0M0REMAP (0x0f8 >> 2)
76 #define GT_PCI0M1REMAP (0x100 >> 2)
77 #define GT_PCI1IOREMAP (0x108 >> 2)
78 #define GT_PCI1M0REMAP (0x110 >> 2)
79 #define GT_PCI1M1REMAP (0x118 >> 2)
80
81 /* CPU Error Report */
82 #define GT_CPUERR_ADDRLO (0x070 >> 2)
83 #define GT_CPUERR_ADDRHI (0x078 >> 2)
84 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
87
88 /* CPU Sync Barrier */
89 #define GT_PCI0SYNC (0x0c0 >> 2)
90 #define GT_PCI1SYNC (0x0c8 >> 2)
91
92 /* SDRAM and Device Address Decode */
93 #define GT_SCS0LD (0x400 >> 2)
94 #define GT_SCS0HD (0x404 >> 2)
95 #define GT_SCS1LD (0x408 >> 2)
96 #define GT_SCS1HD (0x40c >> 2)
97 #define GT_SCS2LD (0x410 >> 2)
98 #define GT_SCS2HD (0x414 >> 2)
99 #define GT_SCS3LD (0x418 >> 2)
100 #define GT_SCS3HD (0x41c >> 2)
101 #define GT_CS0LD (0x420 >> 2)
102 #define GT_CS0HD (0x424 >> 2)
103 #define GT_CS1LD (0x428 >> 2)
104 #define GT_CS1HD (0x42c >> 2)
105 #define GT_CS2LD (0x430 >> 2)
106 #define GT_CS2HD (0x434 >> 2)
107 #define GT_CS3LD (0x438 >> 2)
108 #define GT_CS3HD (0x43c >> 2)
109 #define GT_BOOTLD (0x440 >> 2)
110 #define GT_BOOTHD (0x444 >> 2)
111 #define GT_ADERR (0x470 >> 2)
112
113 /* SDRAM Configuration */
114 #define GT_SDRAM_CFG (0x448 >> 2)
115 #define GT_SDRAM_OPMODE (0x474 >> 2)
116 #define GT_SDRAM_BM (0x478 >> 2)
117 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118
119 /* SDRAM Parameters */
120 #define GT_SDRAM_B0 (0x44c >> 2)
121 #define GT_SDRAM_B1 (0x450 >> 2)
122 #define GT_SDRAM_B2 (0x454 >> 2)
123 #define GT_SDRAM_B3 (0x458 >> 2)
124
125 /* Device Parameters */
126 #define GT_DEV_B0 (0x45c >> 2)
127 #define GT_DEV_B1 (0x460 >> 2)
128 #define GT_DEV_B2 (0x464 >> 2)
129 #define GT_DEV_B3 (0x468 >> 2)
130 #define GT_DEV_BOOT (0x46c >> 2)
131
132 /* ECC */
133 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
135 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
136 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138
139 /* DMA Record */
140 #define GT_DMA0_CNT (0x800 >> 2)
141 #define GT_DMA1_CNT (0x804 >> 2)
142 #define GT_DMA2_CNT (0x808 >> 2)
143 #define GT_DMA3_CNT (0x80c >> 2)
144 #define GT_DMA0_SA (0x810 >> 2)
145 #define GT_DMA1_SA (0x814 >> 2)
146 #define GT_DMA2_SA (0x818 >> 2)
147 #define GT_DMA3_SA (0x81c >> 2)
148 #define GT_DMA0_DA (0x820 >> 2)
149 #define GT_DMA1_DA (0x824 >> 2)
150 #define GT_DMA2_DA (0x828 >> 2)
151 #define GT_DMA3_DA (0x82c >> 2)
152 #define GT_DMA0_NEXT (0x830 >> 2)
153 #define GT_DMA1_NEXT (0x834 >> 2)
154 #define GT_DMA2_NEXT (0x838 >> 2)
155 #define GT_DMA3_NEXT (0x83c >> 2)
156 #define GT_DMA0_CUR (0x870 >> 2)
157 #define GT_DMA1_CUR (0x874 >> 2)
158 #define GT_DMA2_CUR (0x878 >> 2)
159 #define GT_DMA3_CUR (0x87c >> 2)
160
161 /* DMA Channel Control */
162 #define GT_DMA0_CTRL (0x840 >> 2)
163 #define GT_DMA1_CTRL (0x844 >> 2)
164 #define GT_DMA2_CTRL (0x848 >> 2)
165 #define GT_DMA3_CTRL (0x84c >> 2)
166
167 /* DMA Arbiter */
168 #define GT_DMA_ARB (0x860 >> 2)
169
170 /* Timer/Counter */
171 #define GT_TC0 (0x850 >> 2)
172 #define GT_TC1 (0x854 >> 2)
173 #define GT_TC2 (0x858 >> 2)
174 #define GT_TC3 (0x85c >> 2)
175 #define GT_TC_CONTROL (0x864 >> 2)
176
177 /* PCI Internal */
178 #define GT_PCI0_CMD (0xc00 >> 2)
179 #define GT_PCI0_TOR (0xc04 >> 2)
180 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
183 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184 #define GT_PCI1_IACK (0xc30 >> 2)
185 #define GT_PCI0_IACK (0xc34 >> 2)
186 #define GT_PCI0_BARE (0xc3c >> 2)
187 #define GT_PCI0_PREFMBR (0xc40 >> 2)
188 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
191 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195 #define GT_PCI1_CMD (0xc80 >> 2)
196 #define GT_PCI1_TOR (0xc84 >> 2)
197 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
200 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201 #define GT_PCI1_BARE (0xcbc >> 2)
202 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
203 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
205 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
211 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
212 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
213 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214
215 /* Interrupts */
216 #define GT_INTRCAUSE (0xc18 >> 2)
217 #define GT_INTRMASK (0xc1c >> 2)
218 #define GT_PCI0_ICMASK (0xc24 >> 2)
219 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
220 #define GT_CPU_INTSEL (0xc70 >> 2)
221 #define GT_PCI0_INTSEL (0xc74 >> 2)
222 #define GT_HINTRCAUSE (0xc98 >> 2)
223 #define GT_HINTRMASK (0xc9c >> 2)
224 #define GT_PCI0_HICMASK (0xca4 >> 2)
225 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226
227 #define PCI_MAPPING_ENTRY(regname) \
228 hwaddr regname ##_start; \
229 hwaddr regname ##_length; \
230 MemoryRegion regname ##_mem
231
232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
233
234 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
235
236 struct GT64120State {
237 PCIHostState parent_obj;
238
239 uint32_t regs[GT_REGS];
240 PCI_MAPPING_ENTRY(PCI0IO);
241 PCI_MAPPING_ENTRY(PCI0M0);
242 PCI_MAPPING_ENTRY(PCI0M1);
243 PCI_MAPPING_ENTRY(ISD);
244 MemoryRegion pci0_mem;
245 AddressSpace pci0_mem_as;
246 };
247
248 /* Adjust range to avoid touching space which isn't mappable via PCI */
249 /*
250 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
251 * 0x1fc00000 - 0x1fd00000
252 */
253 static void check_reserved_space(hwaddr *start, hwaddr *length)
254 {
255 hwaddr begin = *start;
256 hwaddr end = *start + *length;
257
258 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
259 end = 0x1e000000LL;
260 }
261 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
262 begin = 0x1f100000LL;
263 }
264 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
265 end = 0x1fc00000LL;
266 }
267 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
268 begin = 0x1fd00000LL;
269 }
270 /* XXX: This is broken when a reserved range splits the requested range */
271 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
272 end = 0x1e000000LL;
273 }
274 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
275 end = 0x1fc00000LL;
276 }
277
278 *start = begin;
279 *length = end - begin;
280 }
281
282 static void gt64120_isd_mapping(GT64120State *s)
283 {
284 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
285 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
286 hwaddr length = 0x1000;
287
288 if (s->ISD_length) {
289 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
290 }
291 check_reserved_space(&start, &length);
292 length = 0x1000;
293 /* Map new address */
294 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
295 s->ISD_start = start;
296 s->ISD_length = length;
297 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
298 }
299
300 static void gt64120_pci_mapping(GT64120State *s)
301 {
302 /* Update PCI0IO mapping */
303 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
304 /* Unmap old IO address */
305 if (s->PCI0IO_length) {
306 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
307 object_unparent(OBJECT(&s->PCI0IO_mem));
308 }
309 /* Map new IO address */
310 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
311 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
312 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
313 if (s->PCI0IO_length) {
314 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
315 get_system_io(), 0, s->PCI0IO_length);
316 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
317 &s->PCI0IO_mem);
318 }
319 }
320
321 /* Update PCI0M0 mapping */
322 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
323 /* Unmap old MEM address */
324 if (s->PCI0M0_length) {
325 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
326 object_unparent(OBJECT(&s->PCI0M0_mem));
327 }
328 /* Map new mem address */
329 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
330 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
331 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
332 if (s->PCI0M0_length) {
333 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
334 &s->pci0_mem, s->PCI0M0_start,
335 s->PCI0M0_length);
336 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
337 &s->PCI0M0_mem);
338 }
339 }
340
341 /* Update PCI0M1 mapping */
342 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
343 /* Unmap old MEM address */
344 if (s->PCI0M1_length) {
345 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
346 object_unparent(OBJECT(&s->PCI0M1_mem));
347 }
348 /* Map new mem address */
349 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
350 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
351 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
352 if (s->PCI0M1_length) {
353 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
354 &s->pci0_mem, s->PCI0M1_start,
355 s->PCI0M1_length);
356 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
357 &s->PCI0M1_mem);
358 }
359 }
360 }
361
362 static int gt64120_post_load(void *opaque, int version_id)
363 {
364 GT64120State *s = opaque;
365
366 gt64120_isd_mapping(s);
367 gt64120_pci_mapping(s);
368
369 return 0;
370 }
371
372 static const VMStateDescription vmstate_gt64120 = {
373 .name = "gt64120",
374 .version_id = 1,
375 .minimum_version_id = 1,
376 .post_load = gt64120_post_load,
377 .fields = (VMStateField[]) {
378 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
379 VMSTATE_END_OF_LIST()
380 }
381 };
382
383 static void gt64120_writel(void *opaque, hwaddr addr,
384 uint64_t val, unsigned size)
385 {
386 GT64120State *s = opaque;
387 PCIHostState *phb = PCI_HOST_BRIDGE(s);
388 uint32_t saddr;
389
390 if (!(s->regs[GT_CPU] & 0x00001000)) {
391 val = bswap32(val);
392 }
393
394 saddr = (addr & 0xfff) >> 2;
395 switch (saddr) {
396
397 /* CPU Configuration */
398 case GT_CPU:
399 s->regs[GT_CPU] = val;
400 break;
401 case GT_MULTI:
402 /* Read-only register as only one GT64xxx is present on the CPU bus */
403 break;
404
405 /* CPU Address Decode */
406 case GT_PCI0IOLD:
407 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
408 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
409 gt64120_pci_mapping(s);
410 break;
411 case GT_PCI0M0LD:
412 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
413 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
414 gt64120_pci_mapping(s);
415 break;
416 case GT_PCI0M1LD:
417 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
418 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
419 gt64120_pci_mapping(s);
420 break;
421 case GT_PCI1IOLD:
422 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
423 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
424 break;
425 case GT_PCI1M0LD:
426 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
427 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
428 break;
429 case GT_PCI1M1LD:
430 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
431 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
432 break;
433 case GT_PCI0M0HD:
434 case GT_PCI0M1HD:
435 case GT_PCI0IOHD:
436 s->regs[saddr] = val & 0x0000007f;
437 gt64120_pci_mapping(s);
438 break;
439 case GT_PCI1IOHD:
440 case GT_PCI1M0HD:
441 case GT_PCI1M1HD:
442 s->regs[saddr] = val & 0x0000007f;
443 break;
444 case GT_ISD:
445 s->regs[saddr] = val & 0x00007fff;
446 gt64120_isd_mapping(s);
447 break;
448
449 case GT_PCI0IOREMAP:
450 case GT_PCI0M0REMAP:
451 case GT_PCI0M1REMAP:
452 case GT_PCI1IOREMAP:
453 case GT_PCI1M0REMAP:
454 case GT_PCI1M1REMAP:
455 s->regs[saddr] = val & 0x000007ff;
456 break;
457
458 /* CPU Error Report */
459 case GT_CPUERR_ADDRLO:
460 case GT_CPUERR_ADDRHI:
461 case GT_CPUERR_DATALO:
462 case GT_CPUERR_DATAHI:
463 case GT_CPUERR_PARITY:
464 /* Read-only registers, do nothing */
465 qemu_log_mask(LOG_GUEST_ERROR,
466 "gt64120: Read-only register write "
467 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
468 saddr << 2, size, size << 1, val);
469 break;
470
471 /* CPU Sync Barrier */
472 case GT_PCI0SYNC:
473 case GT_PCI1SYNC:
474 /* Read-only registers, do nothing */
475 qemu_log_mask(LOG_GUEST_ERROR,
476 "gt64120: Read-only register write "
477 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
478 saddr << 2, size, size << 1, val);
479 break;
480
481 /* SDRAM and Device Address Decode */
482 case GT_SCS0LD:
483 case GT_SCS0HD:
484 case GT_SCS1LD:
485 case GT_SCS1HD:
486 case GT_SCS2LD:
487 case GT_SCS2HD:
488 case GT_SCS3LD:
489 case GT_SCS3HD:
490 case GT_CS0LD:
491 case GT_CS0HD:
492 case GT_CS1LD:
493 case GT_CS1HD:
494 case GT_CS2LD:
495 case GT_CS2HD:
496 case GT_CS3LD:
497 case GT_CS3HD:
498 case GT_BOOTLD:
499 case GT_BOOTHD:
500 case GT_ADERR:
501 /* SDRAM Configuration */
502 case GT_SDRAM_CFG:
503 case GT_SDRAM_OPMODE:
504 case GT_SDRAM_BM:
505 case GT_SDRAM_ADDRDECODE:
506 /* Accept and ignore SDRAM interleave configuration */
507 s->regs[saddr] = val;
508 break;
509
510 /* Device Parameters */
511 case GT_DEV_B0:
512 case GT_DEV_B1:
513 case GT_DEV_B2:
514 case GT_DEV_B3:
515 case GT_DEV_BOOT:
516 /* Not implemented */
517 qemu_log_mask(LOG_UNIMP,
518 "gt64120: Unimplemented device register write "
519 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
520 saddr << 2, size, size << 1, val);
521 break;
522
523 /* ECC */
524 case GT_ECC_ERRDATALO:
525 case GT_ECC_ERRDATAHI:
526 case GT_ECC_MEM:
527 case GT_ECC_CALC:
528 case GT_ECC_ERRADDR:
529 /* Read-only registers, do nothing */
530 qemu_log_mask(LOG_GUEST_ERROR,
531 "gt64120: Read-only register write "
532 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
533 saddr << 2, size, size << 1, val);
534 break;
535
536 /* DMA Record */
537 case GT_DMA0_CNT:
538 case GT_DMA1_CNT:
539 case GT_DMA2_CNT:
540 case GT_DMA3_CNT:
541 case GT_DMA0_SA:
542 case GT_DMA1_SA:
543 case GT_DMA2_SA:
544 case GT_DMA3_SA:
545 case GT_DMA0_DA:
546 case GT_DMA1_DA:
547 case GT_DMA2_DA:
548 case GT_DMA3_DA:
549 case GT_DMA0_NEXT:
550 case GT_DMA1_NEXT:
551 case GT_DMA2_NEXT:
552 case GT_DMA3_NEXT:
553 case GT_DMA0_CUR:
554 case GT_DMA1_CUR:
555 case GT_DMA2_CUR:
556 case GT_DMA3_CUR:
557
558 /* DMA Channel Control */
559 case GT_DMA0_CTRL:
560 case GT_DMA1_CTRL:
561 case GT_DMA2_CTRL:
562 case GT_DMA3_CTRL:
563
564 /* DMA Arbiter */
565 case GT_DMA_ARB:
566 /* Not implemented */
567 qemu_log_mask(LOG_UNIMP,
568 "gt64120: Unimplemented DMA register write "
569 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
570 saddr << 2, size, size << 1, val);
571 break;
572
573 /* Timer/Counter */
574 case GT_TC0:
575 case GT_TC1:
576 case GT_TC2:
577 case GT_TC3:
578 case GT_TC_CONTROL:
579 /* Not implemented */
580 qemu_log_mask(LOG_UNIMP,
581 "gt64120: Unimplemented timer register write "
582 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
583 saddr << 2, size, size << 1, val);
584 break;
585
586 /* PCI Internal */
587 case GT_PCI0_CMD:
588 case GT_PCI1_CMD:
589 s->regs[saddr] = val & 0x0401fc0f;
590 break;
591 case GT_PCI0_TOR:
592 case GT_PCI0_BS_SCS10:
593 case GT_PCI0_BS_SCS32:
594 case GT_PCI0_BS_CS20:
595 case GT_PCI0_BS_CS3BT:
596 case GT_PCI1_IACK:
597 case GT_PCI0_IACK:
598 case GT_PCI0_BARE:
599 case GT_PCI0_PREFMBR:
600 case GT_PCI0_SCS10_BAR:
601 case GT_PCI0_SCS32_BAR:
602 case GT_PCI0_CS20_BAR:
603 case GT_PCI0_CS3BT_BAR:
604 case GT_PCI0_SSCS10_BAR:
605 case GT_PCI0_SSCS32_BAR:
606 case GT_PCI0_SCS3BT_BAR:
607 case GT_PCI1_TOR:
608 case GT_PCI1_BS_SCS10:
609 case GT_PCI1_BS_SCS32:
610 case GT_PCI1_BS_CS20:
611 case GT_PCI1_BS_CS3BT:
612 case GT_PCI1_BARE:
613 case GT_PCI1_PREFMBR:
614 case GT_PCI1_SCS10_BAR:
615 case GT_PCI1_SCS32_BAR:
616 case GT_PCI1_CS20_BAR:
617 case GT_PCI1_CS3BT_BAR:
618 case GT_PCI1_SSCS10_BAR:
619 case GT_PCI1_SSCS32_BAR:
620 case GT_PCI1_SCS3BT_BAR:
621 case GT_PCI1_CFGADDR:
622 case GT_PCI1_CFGDATA:
623 /* not implemented */
624 qemu_log_mask(LOG_UNIMP,
625 "gt64120: Unimplemented timer register write "
626 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
627 saddr << 2, size, size << 1, val);
628 break;
629 case GT_PCI0_CFGADDR:
630 phb->config_reg = val & 0x80fffffc;
631 break;
632 case GT_PCI0_CFGDATA:
633 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
634 val = bswap32(val);
635 }
636 if (phb->config_reg & (1u << 31)) {
637 pci_data_write(phb->bus, phb->config_reg, val, 4);
638 }
639 break;
640
641 /* Interrupts */
642 case GT_INTRCAUSE:
643 /* not really implemented */
644 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
645 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
646 trace_gt64120_write("INTRCAUSE", size, val);
647 break;
648 case GT_INTRMASK:
649 s->regs[saddr] = val & 0x3c3ffffe;
650 trace_gt64120_write("INTRMASK", size, val);
651 break;
652 case GT_PCI0_ICMASK:
653 s->regs[saddr] = val & 0x03fffffe;
654 trace_gt64120_write("ICMASK", size, val);
655 break;
656 case GT_PCI0_SERR0MASK:
657 s->regs[saddr] = val & 0x0000003f;
658 trace_gt64120_write("SERR0MASK", size, val);
659 break;
660
661 /* Reserved when only PCI_0 is configured. */
662 case GT_HINTRCAUSE:
663 case GT_CPU_INTSEL:
664 case GT_PCI0_INTSEL:
665 case GT_HINTRMASK:
666 case GT_PCI0_HICMASK:
667 case GT_PCI1_SERR1MASK:
668 /* not implemented */
669 break;
670
671 /* SDRAM Parameters */
672 case GT_SDRAM_B0:
673 case GT_SDRAM_B1:
674 case GT_SDRAM_B2:
675 case GT_SDRAM_B3:
676 /*
677 * We don't simulate electrical parameters of the SDRAM.
678 * Accept, but ignore the values.
679 */
680 s->regs[saddr] = val;
681 break;
682
683 default:
684 qemu_log_mask(LOG_GUEST_ERROR,
685 "gt64120: Illegal register write "
686 "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
687 saddr << 2, size, size << 1, val);
688 break;
689 }
690 }
691
692 static uint64_t gt64120_readl(void *opaque,
693 hwaddr addr, unsigned size)
694 {
695 GT64120State *s = opaque;
696 PCIHostState *phb = PCI_HOST_BRIDGE(s);
697 uint32_t val;
698 uint32_t saddr;
699
700 saddr = (addr & 0xfff) >> 2;
701 switch (saddr) {
702
703 /* CPU Configuration */
704 case GT_MULTI:
705 /*
706 * Only one GT64xxx is present on the CPU bus, return
707 * the initial value.
708 */
709 val = s->regs[saddr];
710 break;
711
712 /* CPU Error Report */
713 case GT_CPUERR_ADDRLO:
714 case GT_CPUERR_ADDRHI:
715 case GT_CPUERR_DATALO:
716 case GT_CPUERR_DATAHI:
717 case GT_CPUERR_PARITY:
718 /* Emulated memory has no error, always return the initial values. */
719 val = s->regs[saddr];
720 break;
721
722 /* CPU Sync Barrier */
723 case GT_PCI0SYNC:
724 case GT_PCI1SYNC:
725 /*
726 * Reading those register should empty all FIFO on the PCI
727 * bus, which are not emulated. The return value should be
728 * a random value that should be ignored.
729 */
730 val = 0xc000ffee;
731 break;
732
733 /* ECC */
734 case GT_ECC_ERRDATALO:
735 case GT_ECC_ERRDATAHI:
736 case GT_ECC_MEM:
737 case GT_ECC_CALC:
738 case GT_ECC_ERRADDR:
739 /* Emulated memory has no error, always return the initial values. */
740 val = s->regs[saddr];
741 break;
742
743 case GT_CPU:
744 case GT_SCS10LD:
745 case GT_SCS10HD:
746 case GT_SCS32LD:
747 case GT_SCS32HD:
748 case GT_CS20LD:
749 case GT_CS20HD:
750 case GT_CS3BOOTLD:
751 case GT_CS3BOOTHD:
752 case GT_SCS10AR:
753 case GT_SCS32AR:
754 case GT_CS20R:
755 case GT_CS3BOOTR:
756 case GT_PCI0IOLD:
757 case GT_PCI0M0LD:
758 case GT_PCI0M1LD:
759 case GT_PCI1IOLD:
760 case GT_PCI1M0LD:
761 case GT_PCI1M1LD:
762 case GT_PCI0IOHD:
763 case GT_PCI0M0HD:
764 case GT_PCI0M1HD:
765 case GT_PCI1IOHD:
766 case GT_PCI1M0HD:
767 case GT_PCI1M1HD:
768 case GT_PCI0IOREMAP:
769 case GT_PCI0M0REMAP:
770 case GT_PCI0M1REMAP:
771 case GT_PCI1IOREMAP:
772 case GT_PCI1M0REMAP:
773 case GT_PCI1M1REMAP:
774 case GT_ISD:
775 val = s->regs[saddr];
776 break;
777 case GT_PCI0_IACK:
778 /* Read the IRQ number */
779 val = pic_read_irq(isa_pic);
780 break;
781
782 /* SDRAM and Device Address Decode */
783 case GT_SCS0LD:
784 case GT_SCS0HD:
785 case GT_SCS1LD:
786 case GT_SCS1HD:
787 case GT_SCS2LD:
788 case GT_SCS2HD:
789 case GT_SCS3LD:
790 case GT_SCS3HD:
791 case GT_CS0LD:
792 case GT_CS0HD:
793 case GT_CS1LD:
794 case GT_CS1HD:
795 case GT_CS2LD:
796 case GT_CS2HD:
797 case GT_CS3LD:
798 case GT_CS3HD:
799 case GT_BOOTLD:
800 case GT_BOOTHD:
801 case GT_ADERR:
802 val = s->regs[saddr];
803 break;
804
805 /* SDRAM Configuration */
806 case GT_SDRAM_CFG:
807 case GT_SDRAM_OPMODE:
808 case GT_SDRAM_BM:
809 case GT_SDRAM_ADDRDECODE:
810 val = s->regs[saddr];
811 break;
812
813 /* SDRAM Parameters */
814 case GT_SDRAM_B0:
815 case GT_SDRAM_B1:
816 case GT_SDRAM_B2:
817 case GT_SDRAM_B3:
818 /*
819 * We don't simulate electrical parameters of the SDRAM.
820 * Just return the last written value.
821 */
822 val = s->regs[saddr];
823 break;
824
825 /* Device Parameters */
826 case GT_DEV_B0:
827 case GT_DEV_B1:
828 case GT_DEV_B2:
829 case GT_DEV_B3:
830 case GT_DEV_BOOT:
831 val = s->regs[saddr];
832 break;
833
834 /* DMA Record */
835 case GT_DMA0_CNT:
836 case GT_DMA1_CNT:
837 case GT_DMA2_CNT:
838 case GT_DMA3_CNT:
839 case GT_DMA0_SA:
840 case GT_DMA1_SA:
841 case GT_DMA2_SA:
842 case GT_DMA3_SA:
843 case GT_DMA0_DA:
844 case GT_DMA1_DA:
845 case GT_DMA2_DA:
846 case GT_DMA3_DA:
847 case GT_DMA0_NEXT:
848 case GT_DMA1_NEXT:
849 case GT_DMA2_NEXT:
850 case GT_DMA3_NEXT:
851 case GT_DMA0_CUR:
852 case GT_DMA1_CUR:
853 case GT_DMA2_CUR:
854 case GT_DMA3_CUR:
855 val = s->regs[saddr];
856 break;
857
858 /* DMA Channel Control */
859 case GT_DMA0_CTRL:
860 case GT_DMA1_CTRL:
861 case GT_DMA2_CTRL:
862 case GT_DMA3_CTRL:
863 val = s->regs[saddr];
864 break;
865
866 /* DMA Arbiter */
867 case GT_DMA_ARB:
868 val = s->regs[saddr];
869 break;
870
871 /* Timer/Counter */
872 case GT_TC0:
873 case GT_TC1:
874 case GT_TC2:
875 case GT_TC3:
876 case GT_TC_CONTROL:
877 val = s->regs[saddr];
878 break;
879
880 /* PCI Internal */
881 case GT_PCI0_CFGADDR:
882 val = phb->config_reg;
883 break;
884 case GT_PCI0_CFGDATA:
885 if (!(phb->config_reg & (1 << 31))) {
886 val = 0xffffffff;
887 } else {
888 val = pci_data_read(phb->bus, phb->config_reg, 4);
889 }
890 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
891 val = bswap32(val);
892 }
893 break;
894
895 case GT_PCI0_CMD:
896 case GT_PCI0_TOR:
897 case GT_PCI0_BS_SCS10:
898 case GT_PCI0_BS_SCS32:
899 case GT_PCI0_BS_CS20:
900 case GT_PCI0_BS_CS3BT:
901 case GT_PCI1_IACK:
902 case GT_PCI0_BARE:
903 case GT_PCI0_PREFMBR:
904 case GT_PCI0_SCS10_BAR:
905 case GT_PCI0_SCS32_BAR:
906 case GT_PCI0_CS20_BAR:
907 case GT_PCI0_CS3BT_BAR:
908 case GT_PCI0_SSCS10_BAR:
909 case GT_PCI0_SSCS32_BAR:
910 case GT_PCI0_SCS3BT_BAR:
911 case GT_PCI1_CMD:
912 case GT_PCI1_TOR:
913 case GT_PCI1_BS_SCS10:
914 case GT_PCI1_BS_SCS32:
915 case GT_PCI1_BS_CS20:
916 case GT_PCI1_BS_CS3BT:
917 case GT_PCI1_BARE:
918 case GT_PCI1_PREFMBR:
919 case GT_PCI1_SCS10_BAR:
920 case GT_PCI1_SCS32_BAR:
921 case GT_PCI1_CS20_BAR:
922 case GT_PCI1_CS3BT_BAR:
923 case GT_PCI1_SSCS10_BAR:
924 case GT_PCI1_SSCS32_BAR:
925 case GT_PCI1_SCS3BT_BAR:
926 case GT_PCI1_CFGADDR:
927 case GT_PCI1_CFGDATA:
928 val = s->regs[saddr];
929 break;
930
931 /* Interrupts */
932 case GT_INTRCAUSE:
933 val = s->regs[saddr];
934 trace_gt64120_read("INTRCAUSE", size, val);
935 break;
936 case GT_INTRMASK:
937 val = s->regs[saddr];
938 trace_gt64120_read("INTRMASK", size, val);
939 break;
940 case GT_PCI0_ICMASK:
941 val = s->regs[saddr];
942 trace_gt64120_read("ICMASK", size, val);
943 break;
944 case GT_PCI0_SERR0MASK:
945 val = s->regs[saddr];
946 trace_gt64120_read("SERR0MASK", size, val);
947 break;
948
949 /* Reserved when only PCI_0 is configured. */
950 case GT_HINTRCAUSE:
951 case GT_CPU_INTSEL:
952 case GT_PCI0_INTSEL:
953 case GT_HINTRMASK:
954 case GT_PCI0_HICMASK:
955 case GT_PCI1_SERR1MASK:
956 val = s->regs[saddr];
957 break;
958
959 default:
960 val = s->regs[saddr];
961 qemu_log_mask(LOG_GUEST_ERROR,
962 "gt64120: Illegal register read "
963 "reg:0x03%x size:%u value:0x%0*x\n",
964 saddr << 2, size, size << 1, val);
965 break;
966 }
967
968 if (!(s->regs[GT_CPU] & 0x00001000)) {
969 val = bswap32(val);
970 }
971
972 return val;
973 }
974
975 static const MemoryRegionOps isd_mem_ops = {
976 .read = gt64120_readl,
977 .write = gt64120_writel,
978 .endianness = DEVICE_NATIVE_ENDIAN,
979 };
980
981 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
982 {
983 int slot;
984
985 slot = PCI_SLOT(pci_dev->devfn);
986
987 switch (slot) {
988 /* PIIX4 USB */
989 case 10:
990 return 3;
991 /* AMD 79C973 Ethernet */
992 case 11:
993 return 1;
994 /* Crystal 4281 Sound */
995 case 12:
996 return 2;
997 /* PCI slot 1 to 4 */
998 case 18 ... 21:
999 return ((slot - 18) + irq_num) & 0x03;
1000 /* Unknown device, don't do any translation */
1001 default:
1002 return irq_num;
1003 }
1004 }
1005
1006 static int pci_irq_levels[4];
1007
1008 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
1009 {
1010 int i, pic_irq, pic_level;
1011 qemu_irq *pic = opaque;
1012
1013 pci_irq_levels[irq_num] = level;
1014
1015 /* now we change the pic irq level according to the piix irq mappings */
1016 /* XXX: optimize */
1017 pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
1018 if (pic_irq < 16) {
1019 /* The pic level is the logical OR of all the PCI irqs mapped to it. */
1020 pic_level = 0;
1021 for (i = 0; i < 4; i++) {
1022 if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
1023 pic_level |= pci_irq_levels[i];
1024 }
1025 }
1026 qemu_set_irq(pic[pic_irq], pic_level);
1027 }
1028 }
1029
1030
1031 static void gt64120_reset(DeviceState *dev)
1032 {
1033 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1034
1035 /* FIXME: Malta specific hw assumptions ahead */
1036
1037 /* CPU Configuration */
1038 #ifdef TARGET_WORDS_BIGENDIAN
1039 s->regs[GT_CPU] = 0x00000000;
1040 #else
1041 s->regs[GT_CPU] = 0x00001000;
1042 #endif
1043 s->regs[GT_MULTI] = 0x00000003;
1044
1045 /* CPU Address decode */
1046 s->regs[GT_SCS10LD] = 0x00000000;
1047 s->regs[GT_SCS10HD] = 0x00000007;
1048 s->regs[GT_SCS32LD] = 0x00000008;
1049 s->regs[GT_SCS32HD] = 0x0000000f;
1050 s->regs[GT_CS20LD] = 0x000000e0;
1051 s->regs[GT_CS20HD] = 0x00000070;
1052 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1053 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1054
1055 s->regs[GT_PCI0IOLD] = 0x00000080;
1056 s->regs[GT_PCI0IOHD] = 0x0000000f;
1057 s->regs[GT_PCI0M0LD] = 0x00000090;
1058 s->regs[GT_PCI0M0HD] = 0x0000001f;
1059 s->regs[GT_ISD] = 0x000000a0;
1060 s->regs[GT_PCI0M1LD] = 0x00000790;
1061 s->regs[GT_PCI0M1HD] = 0x0000001f;
1062 s->regs[GT_PCI1IOLD] = 0x00000100;
1063 s->regs[GT_PCI1IOHD] = 0x0000000f;
1064 s->regs[GT_PCI1M0LD] = 0x00000110;
1065 s->regs[GT_PCI1M0HD] = 0x0000001f;
1066 s->regs[GT_PCI1M1LD] = 0x00000120;
1067 s->regs[GT_PCI1M1HD] = 0x0000002f;
1068
1069 s->regs[GT_SCS10AR] = 0x00000000;
1070 s->regs[GT_SCS32AR] = 0x00000008;
1071 s->regs[GT_CS20R] = 0x000000e0;
1072 s->regs[GT_CS3BOOTR] = 0x000000f8;
1073
1074 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1075 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1076 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1077 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1078 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1079 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1080
1081 /* CPU Error Report */
1082 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1083 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1084 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1085 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1086 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1087
1088 /* CPU Sync Barrier */
1089 s->regs[GT_PCI0SYNC] = 0x00000000;
1090 s->regs[GT_PCI1SYNC] = 0x00000000;
1091
1092 /* SDRAM and Device Address Decode */
1093 s->regs[GT_SCS0LD] = 0x00000000;
1094 s->regs[GT_SCS0HD] = 0x00000007;
1095 s->regs[GT_SCS1LD] = 0x00000008;
1096 s->regs[GT_SCS1HD] = 0x0000000f;
1097 s->regs[GT_SCS2LD] = 0x00000010;
1098 s->regs[GT_SCS2HD] = 0x00000017;
1099 s->regs[GT_SCS3LD] = 0x00000018;
1100 s->regs[GT_SCS3HD] = 0x0000001f;
1101 s->regs[GT_CS0LD] = 0x000000c0;
1102 s->regs[GT_CS0HD] = 0x000000c7;
1103 s->regs[GT_CS1LD] = 0x000000c8;
1104 s->regs[GT_CS1HD] = 0x000000cf;
1105 s->regs[GT_CS2LD] = 0x000000d0;
1106 s->regs[GT_CS2HD] = 0x000000df;
1107 s->regs[GT_CS3LD] = 0x000000f0;
1108 s->regs[GT_CS3HD] = 0x000000fb;
1109 s->regs[GT_BOOTLD] = 0x000000fc;
1110 s->regs[GT_BOOTHD] = 0x000000ff;
1111 s->regs[GT_ADERR] = 0xffffffff;
1112
1113 /* SDRAM Configuration */
1114 s->regs[GT_SDRAM_CFG] = 0x00000200;
1115 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1116 s->regs[GT_SDRAM_BM] = 0x00000007;
1117 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1118
1119 /* SDRAM Parameters */
1120 s->regs[GT_SDRAM_B0] = 0x00000005;
1121 s->regs[GT_SDRAM_B1] = 0x00000005;
1122 s->regs[GT_SDRAM_B2] = 0x00000005;
1123 s->regs[GT_SDRAM_B3] = 0x00000005;
1124
1125 /* ECC */
1126 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1127 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1128 s->regs[GT_ECC_MEM] = 0x00000000;
1129 s->regs[GT_ECC_CALC] = 0x00000000;
1130 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1131
1132 /* Device Parameters */
1133 s->regs[GT_DEV_B0] = 0x386fffff;
1134 s->regs[GT_DEV_B1] = 0x386fffff;
1135 s->regs[GT_DEV_B2] = 0x386fffff;
1136 s->regs[GT_DEV_B3] = 0x386fffff;
1137 s->regs[GT_DEV_BOOT] = 0x146fffff;
1138
1139 /* DMA registers are all zeroed at reset */
1140
1141 /* Timer/Counter */
1142 s->regs[GT_TC0] = 0xffffffff;
1143 s->regs[GT_TC1] = 0x00ffffff;
1144 s->regs[GT_TC2] = 0x00ffffff;
1145 s->regs[GT_TC3] = 0x00ffffff;
1146 s->regs[GT_TC_CONTROL] = 0x00000000;
1147
1148 /* PCI Internal */
1149 #ifdef TARGET_WORDS_BIGENDIAN
1150 s->regs[GT_PCI0_CMD] = 0x00000000;
1151 #else
1152 s->regs[GT_PCI0_CMD] = 0x00010001;
1153 #endif
1154 s->regs[GT_PCI0_TOR] = 0x0000070f;
1155 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1156 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1157 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1158 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1159 s->regs[GT_PCI1_IACK] = 0x00000000;
1160 s->regs[GT_PCI0_IACK] = 0x00000000;
1161 s->regs[GT_PCI0_BARE] = 0x0000000f;
1162 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1163 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1164 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1165 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1166 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1167 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1168 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1169 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1170 #ifdef TARGET_WORDS_BIGENDIAN
1171 s->regs[GT_PCI1_CMD] = 0x00000000;
1172 #else
1173 s->regs[GT_PCI1_CMD] = 0x00010001;
1174 #endif
1175 s->regs[GT_PCI1_TOR] = 0x0000070f;
1176 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1177 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1178 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1179 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1180 s->regs[GT_PCI1_BARE] = 0x0000000f;
1181 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1182 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1183 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1184 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1185 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1186 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1187 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1188 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1189 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1190 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1191 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1192
1193 /* Interrupt registers are all zeroed at reset */
1194
1195 gt64120_isd_mapping(s);
1196 gt64120_pci_mapping(s);
1197 }
1198
1199 PCIBus *gt64120_register(qemu_irq *pic)
1200 {
1201 GT64120State *d;
1202 PCIHostState *phb;
1203 DeviceState *dev;
1204
1205 dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE);
1206 d = GT64120_PCI_HOST_BRIDGE(dev);
1207 phb = PCI_HOST_BRIDGE(dev);
1208 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1209 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1210 phb->bus = pci_register_root_bus(dev, "pci",
1211 gt64120_pci_set_irq, gt64120_pci_map_irq,
1212 pic,
1213 &d->pci0_mem,
1214 get_system_io(),
1215 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1216 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1217 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
1218 "isd-mem", 0x1000);
1219
1220 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1221 return phb->bus;
1222 }
1223
1224 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1225 {
1226 /* FIXME: Malta specific hw assumptions ahead */
1227 pci_set_word(d->config + PCI_COMMAND, 0);
1228 pci_set_word(d->config + PCI_STATUS,
1229 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1230 pci_config_set_prog_interface(d->config, 0);
1231 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1232 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1233 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1234 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1235 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1236 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1237 pci_set_byte(d->config + 0x3d, 0x01);
1238 }
1239
1240 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1241 {
1242 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1243 DeviceClass *dc = DEVICE_CLASS(klass);
1244
1245 k->realize = gt64120_pci_realize;
1246 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1247 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1248 k->revision = 0x10;
1249 k->class_id = PCI_CLASS_BRIDGE_HOST;
1250 /*
1251 * PCI-facing part of the host bridge, not usable without the
1252 * host-facing part, which can't be device_add'ed, yet.
1253 */
1254 dc->user_creatable = false;
1255 }
1256
1257 static const TypeInfo gt64120_pci_info = {
1258 .name = "gt64120_pci",
1259 .parent = TYPE_PCI_DEVICE,
1260 .instance_size = sizeof(PCIDevice),
1261 .class_init = gt64120_pci_class_init,
1262 .interfaces = (InterfaceInfo[]) {
1263 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1264 { },
1265 },
1266 };
1267
1268 static void gt64120_class_init(ObjectClass *klass, void *data)
1269 {
1270 DeviceClass *dc = DEVICE_CLASS(klass);
1271
1272 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1273 dc->reset = gt64120_reset;
1274 dc->vmsd = &vmstate_gt64120;
1275 }
1276
1277 static const TypeInfo gt64120_info = {
1278 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1279 .parent = TYPE_PCI_HOST_BRIDGE,
1280 .instance_size = sizeof(GT64120State),
1281 .class_init = gt64120_class_init,
1282 };
1283
1284 static void gt64120_pci_register_types(void)
1285 {
1286 type_register_static(&gt64120_info);
1287 type_register_static(&gt64120_pci_info);
1288 }
1289
1290 type_init(gt64120_pci_register_types)
AR7 emulation for QEMU