hw/mips/boston.c

   1 /*
   2  * MIPS Boston development board emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22
  23 #include "exec/address-spaces.h"
  24 #include "hw/boards.h"
  25 #include "hw/char/serial.h"
  26 #include "hw/ide/pci.h"
  27 #include "hw/ide/ahci.h"
  28 #include "hw/loader.h"
  29 #include "hw/loader-fit.h"
  30 #include "hw/mips/bootloader.h"
  31 #include "hw/mips/cps.h"
  32 #include "hw/pci-host/xilinx-pcie.h"
  33 #include "hw/qdev-clock.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qapi/error.h"
  36 #include "qemu/error-report.h"
  37 #include "qemu/log.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/device_tree.h"
  40 #include "sysemu/sysemu.h"
  41 #include "sysemu/qtest.h"
  42 #include "sysemu/runstate.h"
  43
  44 #include <libfdt.h>
  45 #include "qom/object.h"
  46
  47 #define TYPE_BOSTON "mips-boston"
  48 typedef struct BostonState BostonState;
  49 DECLARE_INSTANCE_CHECKER(BostonState, BOSTON,
  50                          TYPE_BOSTON)
  51
  52 struct BostonState {
  53     SysBusDevice parent_obj;
  54
  55     MachineState *mach;
  56     MIPSCPSState cps;
  57     SerialMM *uart;
  58     Clock *cpuclk;
  59
  60     CharBackend lcd_display;
  61     char lcd_content[8];
  62     bool lcd_inited;
  63
  64     hwaddr kernel_entry;
  65     hwaddr fdt_base;
  66 };
  67
  68 enum boston_plat_reg {
  69     PLAT_FPGA_BUILD     = 0x00,
  70     PLAT_CORE_CL        = 0x04,
  71     PLAT_WRAPPER_CL     = 0x08,
  72     PLAT_SYSCLK_STATUS  = 0x0c,
  73     PLAT_SOFTRST_CTL    = 0x10,
  74 #define PLAT_SOFTRST_CTL_SYSRESET       (1 << 4)
  75     PLAT_DDR3_STATUS    = 0x14,
  76 #define PLAT_DDR3_STATUS_LOCKED         (1 << 0)
  77 #define PLAT_DDR3_STATUS_CALIBRATED     (1 << 2)
  78     PLAT_PCIE_STATUS    = 0x18,
  79 #define PLAT_PCIE_STATUS_PCIE0_LOCKED   (1 << 0)
  80 #define PLAT_PCIE_STATUS_PCIE1_LOCKED   (1 << 8)
  81 #define PLAT_PCIE_STATUS_PCIE2_LOCKED   (1 << 16)
  82     PLAT_FLASH_CTL      = 0x1c,
  83     PLAT_SPARE0         = 0x20,
  84     PLAT_SPARE1         = 0x24,
  85     PLAT_SPARE2         = 0x28,
  86     PLAT_SPARE3         = 0x2c,
  87     PLAT_MMCM_DIV       = 0x30,
  88 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT     0
  89 #define PLAT_MMCM_DIV_INPUT_SHIFT       8
  90 #define PLAT_MMCM_DIV_MUL_SHIFT         16
  91 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT     24
  92     PLAT_BUILD_CFG      = 0x34,
  93 #define PLAT_BUILD_CFG_IOCU_EN          (1 << 0)
  94 #define PLAT_BUILD_CFG_PCIE0_EN         (1 << 1)
  95 #define PLAT_BUILD_CFG_PCIE1_EN         (1 << 2)
  96 #define PLAT_BUILD_CFG_PCIE2_EN         (1 << 3)
  97     PLAT_DDR_CFG        = 0x38,
  98 #define PLAT_DDR_CFG_SIZE               (0xf << 0)
  99 #define PLAT_DDR_CFG_MHZ                (0xfff << 4)
 100     PLAT_NOC_PCIE0_ADDR = 0x3c,
 101     PLAT_NOC_PCIE1_ADDR = 0x40,
 102     PLAT_NOC_PCIE2_ADDR = 0x44,
 103     PLAT_SYS_CTL        = 0x48,
 104 };
 105
 106 static void boston_lcd_event(void *opaque, QEMUChrEvent event)
 107 {
 108     BostonState *s = opaque;
 109     if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
 110         qemu_chr_fe_printf(&s->lcd_display, "        ");
 111         s->lcd_inited = true;
 112     }
 113 }
 114
 115 static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
 116                                 unsigned size)
 117 {
 118     BostonState *s = opaque;
 119     uint64_t val = 0;
 120
 121     switch (size) {
 122     case 8:
 123         val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
 124         val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
 125         val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
 126         val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
 127         /* fall through */
 128     case 4:
 129         val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
 130         val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
 131         /* fall through */
 132     case 2:
 133         val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
 134         /* fall through */
 135     case 1:
 136         val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
 137         break;
 138     }
 139
 140     return val;
 141 }
 142
 143 static void boston_lcd_write(void *opaque, hwaddr addr,
 144                              uint64_t val, unsigned size)
 145 {
 146     BostonState *s = opaque;
 147
 148     switch (size) {
 149     case 8:
 150         s->lcd_content[(addr + 7) & 0x7] = val >> 56;
 151         s->lcd_content[(addr + 6) & 0x7] = val >> 48;
 152         s->lcd_content[(addr + 5) & 0x7] = val >> 40;
 153         s->lcd_content[(addr + 4) & 0x7] = val >> 32;
 154         /* fall through */
 155     case 4:
 156         s->lcd_content[(addr + 3) & 0x7] = val >> 24;
 157         s->lcd_content[(addr + 2) & 0x7] = val >> 16;
 158         /* fall through */
 159     case 2:
 160         s->lcd_content[(addr + 1) & 0x7] = val >> 8;
 161         /* fall through */
 162     case 1:
 163         s->lcd_content[(addr + 0) & 0x7] = val;
 164         break;
 165     }
 166
 167     qemu_chr_fe_printf(&s->lcd_display,
 168                        "\r%-8.8s", s->lcd_content);
 169 }
 170
 171 static const MemoryRegionOps boston_lcd_ops = {
 172     .read = boston_lcd_read,
 173     .write = boston_lcd_write,
 174     .endianness = DEVICE_NATIVE_ENDIAN,
 175 };
 176
 177 static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
 178                                     unsigned size)
 179 {
 180     BostonState *s = opaque;
 181     uint32_t gic_freq, val;
 182
 183     if (size != 4) {
 184         qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
 185         return 0;
 186     }
 187
 188     switch (addr & 0xffff) {
 189     case PLAT_FPGA_BUILD:
 190     case PLAT_CORE_CL:
 191     case PLAT_WRAPPER_CL:
 192         return 0;
 193     case PLAT_DDR3_STATUS:
 194         return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
 195     case PLAT_MMCM_DIV:
 196         gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
 197         val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
 198         val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
 199         val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
 200         val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT;
 201         return val;
 202     case PLAT_BUILD_CFG:
 203         val = PLAT_BUILD_CFG_PCIE0_EN;
 204         val |= PLAT_BUILD_CFG_PCIE1_EN;
 205         val |= PLAT_BUILD_CFG_PCIE2_EN;
 206         return val;
 207     case PLAT_DDR_CFG:
 208         val = s->mach->ram_size / GiB;
 209         assert(!(val & ~PLAT_DDR_CFG_SIZE));
 210         val |= PLAT_DDR_CFG_MHZ;
 211         return val;
 212     default:
 213         qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
 214                       addr & 0xffff);
 215         return 0;
 216     }
 217 }
 218
 219 static void boston_platreg_write(void *opaque, hwaddr addr,
 220                                  uint64_t val, unsigned size)
 221 {
 222     if (size != 4) {
 223         qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
 224         return;
 225     }
 226
 227     switch (addr & 0xffff) {
 228     case PLAT_FPGA_BUILD:
 229     case PLAT_CORE_CL:
 230     case PLAT_WRAPPER_CL:
 231     case PLAT_DDR3_STATUS:
 232     case PLAT_PCIE_STATUS:
 233     case PLAT_MMCM_DIV:
 234     case PLAT_BUILD_CFG:
 235     case PLAT_DDR_CFG:
 236         /* read only */
 237         break;
 238     case PLAT_SOFTRST_CTL:
 239         if (val & PLAT_SOFTRST_CTL_SYSRESET) {
 240             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 241         }
 242         break;
 243     default:
 244         qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
 245                       " = 0x%" PRIx64 "\n", addr & 0xffff, val);
 246         break;
 247     }
 248 }
 249
 250 static const MemoryRegionOps boston_platreg_ops = {
 251     .read = boston_platreg_read,
 252     .write = boston_platreg_write,
 253     .endianness = DEVICE_NATIVE_ENDIAN,
 254 };
 255
 256 static void mips_boston_instance_init(Object *obj)
 257 {
 258     BostonState *s = BOSTON(obj);
 259
 260     s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
 261     clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */
 262 }
 263
 264 static const TypeInfo boston_device = {
 265     .name          = TYPE_BOSTON,
 266     .parent        = TYPE_SYS_BUS_DEVICE,
 267     .instance_size = sizeof(BostonState),
 268     .instance_init = mips_boston_instance_init,
 269 };
 270
 271 static void boston_register_types(void)
 272 {
 273     type_register_static(&boston_device);
 274 }
 275 type_init(boston_register_types)
 276
 277 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
 278 {
 279     const uint32_t cm_base = 0x16100000;
 280     const uint32_t gic_base = 0x16120000;
 281     const uint32_t cpc_base = 0x16200000;
 282
 283     /* Move CM GCRs */
 284     bl_gen_write_ulong(&p,
 285                        cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
 286                        cm_base);
 287
 288     /* Move & enable GIC GCRs */
 289     bl_gen_write_ulong(&p,
 290                        cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS),
 291                        gic_base | GCR_GIC_BASE_GICEN_MSK);
 292
 293     /* Move & enable CPC GCRs */
 294     bl_gen_write_ulong(&p,
 295                        cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS),
 296                        cpc_base | GCR_CPC_BASE_CPCEN_MSK);
 297
 298     /*
 299      * Setup argument registers to follow the UHI boot protocol:
 300      *
 301      * a0/$4 = -2
 302      * a1/$5 = virtual address of FDT
 303      * a2/$6 = 0
 304      * a3/$7 = 0
 305      */
 306     bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
 307 }
 308
 309 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
 310                                      const void *match_data, hwaddr *load_addr)
 311 {
 312     BostonState *s = BOSTON(opaque);
 313     MachineState *machine = s->mach;
 314     const char *cmdline;
 315     int err;
 316     size_t ram_low_sz, ram_high_sz;
 317     size_t fdt_sz = fdt_totalsize(fdt_orig) * 2;
 318     g_autofree void *fdt = g_malloc0(fdt_sz);
 319
 320     err = fdt_open_into(fdt_orig, fdt, fdt_sz);
 321     if (err) {
 322         fprintf(stderr, "unable to open FDT\n");
 323         return NULL;
 324     }
 325
 326     cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])
 327             ? machine->kernel_cmdline : " ";
 328     err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 329     if (err < 0) {
 330         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 331         return NULL;
 332     }
 333
 334     ram_low_sz = MIN(256 * MiB, machine->ram_size);
 335     ram_high_sz = machine->ram_size - ram_low_sz;
 336     qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
 337                                  1, 0x00000000, 1, ram_low_sz,
 338                                  1, 0x90000000, 1, ram_high_sz);
 339
 340     fdt = g_realloc(fdt, fdt_totalsize(fdt));
 341     qemu_fdt_dumpdtb(fdt, fdt_sz);
 342
 343     s->fdt_base = *load_addr;
 344
 345     return g_steal_pointer(&fdt);
 346 }
 347
 348 static const void *boston_kernel_filter(void *opaque, const void *kernel,
 349                                         hwaddr *load_addr, hwaddr *entry_addr)
 350 {
 351     BostonState *s = BOSTON(opaque);
 352
 353     s->kernel_entry = *entry_addr;
 354
 355     return kernel;
 356 }
 357
 358 static const struct fit_loader_match boston_matches[] = {
 359     { "img,boston" },
 360     { NULL },
 361 };
 362
 363 static const struct fit_loader boston_fit_loader = {
 364     .matches = boston_matches,
 365     .addr_to_phys = cpu_mips_kseg0_to_phys,
 366     .fdt_filter = boston_fdt_filter,
 367     .kernel_filter = boston_kernel_filter,
 368 };
 369
 370 static inline XilinxPCIEHost *
 371 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
 372                  hwaddr cfg_base, uint64_t cfg_size,
 373                  hwaddr mmio_base, uint64_t mmio_size,
 374                  qemu_irq irq, bool link_up)
 375 {
 376     DeviceState *dev;
 377     MemoryRegion *cfg, *mmio;
 378
 379     dev = qdev_new(TYPE_XILINX_PCIE_HOST);
 380
 381     qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
 382     qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
 383     qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
 384     qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
 385     qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
 386     qdev_prop_set_bit(dev, "link_up", link_up);
 387
 388     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 389
 390     cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 391     memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
 392
 393     mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 394     memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
 395
 396     qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
 397
 398     return XILINX_PCIE_HOST(dev);
 399 }
 400
 401 static void boston_mach_init(MachineState *machine)
 402 {
 403     DeviceState *dev;
 404     BostonState *s;
 405     MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
 406     MemoryRegion *sys_mem = get_system_memory();
 407     XilinxPCIEHost *pcie2;
 408     PCIDevice *ahci;
 409     DriveInfo *hd[6];
 410     Chardev *chr;
 411     int fw_size, fit_err;
 412
 413     if ((machine->ram_size % GiB) ||
 414         (machine->ram_size > (2 * GiB))) {
 415         error_report("Memory size must be 1GB or 2GB");
 416         exit(1);
 417     }
 418
 419     dev = qdev_new(TYPE_BOSTON);
 420     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 421
 422     s = BOSTON(dev);
 423     s->mach = machine;
 424
 425     if (!cpu_type_supports_cps_smp(machine->cpu_type)) {
 426         error_report("Boston requires CPUs which support CPS");
 427         exit(1);
 428     }
 429
 430     object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
 431     object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
 432                             &error_fatal);
 433     object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
 434                             &error_fatal);
 435     qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
 436                           qdev_get_clock_out(dev, "cpu-refclk"));
 437     sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
 438
 439     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
 440
 441     flash =  g_new(MemoryRegion, 1);
 442     memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
 443                            &error_fatal);
 444     memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
 445
 446     memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
 447
 448     ddr_low_alias = g_new(MemoryRegion, 1);
 449     memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
 450                              machine->ram, 0,
 451                              MIN(machine->ram_size, (256 * MiB)));
 452     memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
 453
 454     xilinx_pcie_init(sys_mem, 0,
 455                      0x10000000, 32 * MiB,
 456                      0x40000000, 1 * GiB,
 457                      get_cps_irq(&s->cps, 2), false);
 458
 459     xilinx_pcie_init(sys_mem, 1,
 460                      0x12000000, 32 * MiB,
 461                      0x20000000, 512 * MiB,
 462                      get_cps_irq(&s->cps, 1), false);
 463
 464     pcie2 = xilinx_pcie_init(sys_mem, 2,
 465                              0x14000000, 32 * MiB,
 466                              0x16000000, 1 * MiB,
 467                              get_cps_irq(&s->cps, 0), true);
 468
 469     platreg = g_new(MemoryRegion, 1);
 470     memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
 471                           "boston-platregs", 0x1000);
 472     memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
 473
 474     s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
 475                              get_cps_irq(&s->cps, 3), 10000000,
 476                              serial_hd(0), DEVICE_NATIVE_ENDIAN);
 477
 478     lcd = g_new(MemoryRegion, 1);
 479     memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
 480     memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
 481
 482     chr = qemu_chr_new("lcd", "vc:320x240", NULL);
 483     qemu_chr_fe_init(&s->lcd_display, chr, NULL);
 484     qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
 485                              boston_lcd_event, NULL, s, NULL, true);
 486
 487     ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
 488                                            PCI_DEVFN(0, 0),
 489                                            true, TYPE_ICH9_AHCI);
 490     g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
 491     ide_drive_get(hd, ahci_get_num_ports(ahci));
 492     ahci_ide_create_devs(ahci, hd);
 493
 494     if (machine->firmware) {
 495         fw_size = load_image_targphys(machine->firmware,
 496                                       0x1fc00000, 4 * MiB);
 497         if (fw_size == -1) {
 498             error_report("unable to load firmware image '%s'",
 499                           machine->firmware);
 500             exit(1);
 501         }
 502     } else if (machine->kernel_filename) {
 503         fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
 504         if (fit_err) {
 505             error_report("unable to load FIT image");
 506             exit(1);
 507         }
 508
 509         gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
 510                      s->kernel_entry, s->fdt_base);
 511     } else if (!qtest_enabled()) {
 512         error_report("Please provide either a -kernel or -bios argument");
 513         exit(1);
 514     }
 515 }
 516
 517 static void boston_mach_class_init(MachineClass *mc)
 518 {
 519     mc->desc = "MIPS Boston";
 520     mc->init = boston_mach_init;
 521     mc->block_default_type = IF_IDE;
 522     mc->default_ram_size = 1 * GiB;
 523     mc->default_ram_id = "boston.ddr";
 524     mc->max_cpus = 16;
 525     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
 526 }
 527
 528 DEFINE_MACHINE("boston", boston_mach_class_init)