hw/gpio/omap_gpio.c

   1 /*
   2  * TI OMAP processors GPIO emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/irq.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/arm/omap.h"
  25 #include "hw/sysbus.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/module.h"
  28 #include "qapi/error.h"
  29
  30 struct omap_gpio_s {
  31     qemu_irq irq;
  32     qemu_irq handler[16];
  33
  34     uint16_t inputs;
  35     uint16_t outputs;
  36     uint16_t dir;
  37     uint16_t edge;
  38     uint16_t mask;
  39     uint16_t ints;
  40     uint16_t pins;
  41 };
  42
  43 struct omap_gpif_s {
  44     SysBusDevice parent_obj;
  45
  46     MemoryRegion iomem;
  47     int mpu_model;
  48     void *clk;
  49     struct omap_gpio_s omap1;
  50 };
  51
  52 /* General-Purpose I/O of OMAP1 */
  53 static void omap_gpio_set(void *opaque, int line, int level)
  54 {
  55     struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
  56     uint16_t prev = s->inputs;
  57
  58     if (level)
  59         s->inputs |= 1 << line;
  60     else
  61         s->inputs &= ~(1 << line);
  62
  63     if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
  64                     (1 << line) & s->dir & ~s->mask) {
  65         s->ints |= 1 << line;
  66         qemu_irq_raise(s->irq);
  67     }
  68 }
  69
  70 static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
  71                                unsigned size)
  72 {
  73     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
  74     int offset = addr & OMAP_MPUI_REG_MASK;
  75
  76     if (size != 2) {
  77         return omap_badwidth_read16(opaque, addr);
  78     }
  79
  80     switch (offset) {
  81     case 0x00:  /* DATA_INPUT */
  82         return s->inputs & s->pins;
  83
  84     case 0x04:  /* DATA_OUTPUT */
  85         return s->outputs;
  86
  87     case 0x08:  /* DIRECTION_CONTROL */
  88         return s->dir;
  89
  90     case 0x0c:  /* INTERRUPT_CONTROL */
  91         return s->edge;
  92
  93     case 0x10:  /* INTERRUPT_MASK */
  94         return s->mask;
  95
  96     case 0x14:  /* INTERRUPT_STATUS */
  97         return s->ints;
  98
  99     case 0x18:  /* PIN_CONTROL (not in OMAP310) */
 100         OMAP_BAD_REG(addr);
 101         return s->pins;
 102     }
 103
 104     OMAP_BAD_REG(addr);
 105     return 0;
 106 }
 107
 108 static void omap_gpio_write(void *opaque, hwaddr addr,
 109                             uint64_t value, unsigned size)
 110 {
 111     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
 112     int offset = addr & OMAP_MPUI_REG_MASK;
 113     uint16_t diff;
 114     int ln;
 115
 116     if (size != 2) {
 117         omap_badwidth_write16(opaque, addr, value);
 118         return;
 119     }
 120
 121     switch (offset) {
 122     case 0x00:  /* DATA_INPUT */
 123         OMAP_RO_REG(addr);
 124         return;
 125
 126     case 0x04:  /* DATA_OUTPUT */
 127         diff = (s->outputs ^ value) & ~s->dir;
 128         s->outputs = value;
 129         while ((ln = ctz32(diff)) != 32) {
 130             if (s->handler[ln])
 131                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 132             diff &= ~(1 << ln);
 133         }
 134         break;
 135
 136     case 0x08:  /* DIRECTION_CONTROL */
 137         diff = s->outputs & (s->dir ^ value);
 138         s->dir = value;
 139
 140         value = s->outputs & ~s->dir;
 141         while ((ln = ctz32(diff)) != 32) {
 142             if (s->handler[ln])
 143                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 144             diff &= ~(1 << ln);
 145         }
 146         break;
 147
 148     case 0x0c:  /* INTERRUPT_CONTROL */
 149         s->edge = value;
 150         break;
 151
 152     case 0x10:  /* INTERRUPT_MASK */
 153         s->mask = value;
 154         break;
 155
 156     case 0x14:  /* INTERRUPT_STATUS */
 157         s->ints &= ~value;
 158         if (!s->ints)
 159             qemu_irq_lower(s->irq);
 160         break;
 161
 162     case 0x18:  /* PIN_CONTROL (not in OMAP310 TRM) */
 163         OMAP_BAD_REG(addr);
 164         s->pins = value;
 165         break;
 166
 167     default:
 168         OMAP_BAD_REG(addr);
 169         return;
 170     }
 171 }
 172
 173 /* *Some* sources say the memory region is 32-bit.  */
 174 static const MemoryRegionOps omap_gpio_ops = {
 175     .read = omap_gpio_read,
 176     .write = omap_gpio_write,
 177     .endianness = DEVICE_NATIVE_ENDIAN,
 178 };
 179
 180 static void omap_gpio_reset(struct omap_gpio_s *s)
 181 {
 182     s->inputs = 0;
 183     s->outputs = ~0;
 184     s->dir = ~0;
 185     s->edge = ~0;
 186     s->mask = ~0;
 187     s->ints = 0;
 188     s->pins = ~0;
 189 }
 190
 191 struct omap2_gpio_s {
 192     qemu_irq irq[2];
 193     qemu_irq wkup;
 194     qemu_irq *handler;
 195     MemoryRegion iomem;
 196
 197     uint8_t revision;
 198     uint8_t config[2];
 199     uint32_t inputs;
 200     uint32_t outputs;
 201     uint32_t dir;
 202     uint32_t level[2];
 203     uint32_t edge[2];
 204     uint32_t mask[2];
 205     uint32_t wumask;
 206     uint32_t ints[2];
 207     uint32_t debounce;
 208     uint8_t delay;
 209 };
 210
 211 struct omap2_gpif_s {
 212     SysBusDevice parent_obj;
 213
 214     MemoryRegion iomem;
 215     int mpu_model;
 216     void *iclk;
 217     void *fclk[6];
 218     int modulecount;
 219     struct omap2_gpio_s *modules;
 220     qemu_irq *handler;
 221     int autoidle;
 222     int gpo;
 223 };
 224
 225 /* General-Purpose Interface of OMAP2/3 */
 226 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
 227                                                 int line)
 228 {
 229     qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
 230 }
 231
 232 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
 233 {
 234     if (!(s->config[0] & (1 << 2)))                     /* ENAWAKEUP */
 235         return;
 236     if (!(s->config[0] & (3 << 3)))                     /* Force Idle */
 237         return;
 238     if (!(s->wumask & (1 << line)))
 239         return;
 240
 241     qemu_irq_raise(s->wkup);
 242 }
 243
 244 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
 245                 uint32_t diff)
 246 {
 247     int ln;
 248
 249     s->outputs ^= diff;
 250     diff &= ~s->dir;
 251     while ((ln = ctz32(diff)) != 32) {
 252         qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
 253         diff &= ~(1 << ln);
 254     }
 255 }
 256
 257 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
 258 {
 259     s->ints[line] |= s->dir &
 260             ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
 261     omap2_gpio_module_int_update(s, line);
 262 }
 263
 264 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
 265 {
 266     s->ints[0] |= 1 << line;
 267     omap2_gpio_module_int_update(s, 0);
 268     s->ints[1] |= 1 << line;
 269     omap2_gpio_module_int_update(s, 1);
 270     omap2_gpio_module_wake(s, line);
 271 }
 272
 273 static void omap2_gpio_set(void *opaque, int line, int level)
 274 {
 275     struct omap2_gpif_s *p = opaque;
 276     struct omap2_gpio_s *s = &p->modules[line >> 5];
 277
 278     line &= 31;
 279     if (level) {
 280         if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
 281             omap2_gpio_module_int(s, line);
 282         s->inputs |= 1 << line;
 283     } else {
 284         if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
 285             omap2_gpio_module_int(s, line);
 286         s->inputs &= ~(1 << line);
 287     }
 288 }
 289
 290 static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
 291 {
 292     s->config[0] = 0;
 293     s->config[1] = 2;
 294     s->ints[0] = 0;
 295     s->ints[1] = 0;
 296     s->mask[0] = 0;
 297     s->mask[1] = 0;
 298     s->wumask = 0;
 299     s->dir = ~0;
 300     s->level[0] = 0;
 301     s->level[1] = 0;
 302     s->edge[0] = 0;
 303     s->edge[1] = 0;
 304     s->debounce = 0;
 305     s->delay = 0;
 306 }
 307
 308 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
 309 {
 310     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 311
 312     switch (addr) {
 313     case 0x00:  /* GPIO_REVISION */
 314         return s->revision;
 315
 316     case 0x10:  /* GPIO_SYSCONFIG */
 317         return s->config[0];
 318
 319     case 0x14:  /* GPIO_SYSSTATUS */
 320         return 0x01;
 321
 322     case 0x18:  /* GPIO_IRQSTATUS1 */
 323         return s->ints[0];
 324
 325     case 0x1c:  /* GPIO_IRQENABLE1 */
 326     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 327     case 0x64:  /* GPIO_SETIRQENABLE1 */
 328         return s->mask[0];
 329
 330     case 0x20:  /* GPIO_WAKEUPENABLE */
 331     case 0x80:  /* GPIO_CLEARWKUENA */
 332     case 0x84:  /* GPIO_SETWKUENA */
 333         return s->wumask;
 334
 335     case 0x28:  /* GPIO_IRQSTATUS2 */
 336         return s->ints[1];
 337
 338     case 0x2c:  /* GPIO_IRQENABLE2 */
 339     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 340     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 341         return s->mask[1];
 342
 343     case 0x30:  /* GPIO_CTRL */
 344         return s->config[1];
 345
 346     case 0x34:  /* GPIO_OE */
 347         return s->dir;
 348
 349     case 0x38:  /* GPIO_DATAIN */
 350         return s->inputs;
 351
 352     case 0x3c:  /* GPIO_DATAOUT */
 353     case 0x90:  /* GPIO_CLEARDATAOUT */
 354     case 0x94:  /* GPIO_SETDATAOUT */
 355         return s->outputs;
 356
 357     case 0x40:  /* GPIO_LEVELDETECT0 */
 358         return s->level[0];
 359
 360     case 0x44:  /* GPIO_LEVELDETECT1 */
 361         return s->level[1];
 362
 363     case 0x48:  /* GPIO_RISINGDETECT */
 364         return s->edge[0];
 365
 366     case 0x4c:  /* GPIO_FALLINGDETECT */
 367         return s->edge[1];
 368
 369     case 0x50:  /* GPIO_DEBOUNCENABLE */
 370         return s->debounce;
 371
 372     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 373         return s->delay;
 374     }
 375
 376     OMAP_BAD_REG(addr);
 377     return 0;
 378 }
 379
 380 static void omap2_gpio_module_write(void *opaque, hwaddr addr,
 381                 uint32_t value)
 382 {
 383     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 384     uint32_t diff;
 385     int ln;
 386
 387     switch (addr) {
 388     case 0x00:  /* GPIO_REVISION */
 389     case 0x14:  /* GPIO_SYSSTATUS */
 390     case 0x38:  /* GPIO_DATAIN */
 391         OMAP_RO_REG(addr);
 392         break;
 393
 394     case 0x10:  /* GPIO_SYSCONFIG */
 395         if (((value >> 3) & 3) == 3) {
 396             qemu_log_mask(LOG_GUEST_ERROR,
 397                           "%s: Illegal IDLEMODE value: 3\n", __func__);
 398         }
 399         if (value & 2)
 400             omap2_gpio_module_reset(s);
 401         s->config[0] = value & 0x1d;
 402         break;
 403
 404     case 0x18:  /* GPIO_IRQSTATUS1 */
 405         if (s->ints[0] & value) {
 406             s->ints[0] &= ~value;
 407             omap2_gpio_module_level_update(s, 0);
 408         }
 409         break;
 410
 411     case 0x1c:  /* GPIO_IRQENABLE1 */
 412         s->mask[0] = value;
 413         omap2_gpio_module_int_update(s, 0);
 414         break;
 415
 416     case 0x20:  /* GPIO_WAKEUPENABLE */
 417         s->wumask = value;
 418         break;
 419
 420     case 0x28:  /* GPIO_IRQSTATUS2 */
 421         if (s->ints[1] & value) {
 422             s->ints[1] &= ~value;
 423             omap2_gpio_module_level_update(s, 1);
 424         }
 425         break;
 426
 427     case 0x2c:  /* GPIO_IRQENABLE2 */
 428         s->mask[1] = value;
 429         omap2_gpio_module_int_update(s, 1);
 430         break;
 431
 432     case 0x30:  /* GPIO_CTRL */
 433         s->config[1] = value & 7;
 434         break;
 435
 436     case 0x34:  /* GPIO_OE */
 437         diff = s->outputs & (s->dir ^ value);
 438         s->dir = value;
 439
 440         value = s->outputs & ~s->dir;
 441         while ((ln = ctz32(diff)) != 32) {
 442             diff &= ~(1 << ln);
 443             qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 444         }
 445
 446         omap2_gpio_module_level_update(s, 0);
 447         omap2_gpio_module_level_update(s, 1);
 448         break;
 449
 450     case 0x3c:  /* GPIO_DATAOUT */
 451         omap2_gpio_module_out_update(s, s->outputs ^ value);
 452         break;
 453
 454     case 0x40:  /* GPIO_LEVELDETECT0 */
 455         s->level[0] = value;
 456         omap2_gpio_module_level_update(s, 0);
 457         omap2_gpio_module_level_update(s, 1);
 458         break;
 459
 460     case 0x44:  /* GPIO_LEVELDETECT1 */
 461         s->level[1] = value;
 462         omap2_gpio_module_level_update(s, 0);
 463         omap2_gpio_module_level_update(s, 1);
 464         break;
 465
 466     case 0x48:  /* GPIO_RISINGDETECT */
 467         s->edge[0] = value;
 468         break;
 469
 470     case 0x4c:  /* GPIO_FALLINGDETECT */
 471         s->edge[1] = value;
 472         break;
 473
 474     case 0x50:  /* GPIO_DEBOUNCENABLE */
 475         s->debounce = value;
 476         break;
 477
 478     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 479         s->delay = value;
 480         break;
 481
 482     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 483         s->mask[0] &= ~value;
 484         omap2_gpio_module_int_update(s, 0);
 485         break;
 486
 487     case 0x64:  /* GPIO_SETIRQENABLE1 */
 488         s->mask[0] |= value;
 489         omap2_gpio_module_int_update(s, 0);
 490         break;
 491
 492     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 493         s->mask[1] &= ~value;
 494         omap2_gpio_module_int_update(s, 1);
 495         break;
 496
 497     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 498         s->mask[1] |= value;
 499         omap2_gpio_module_int_update(s, 1);
 500         break;
 501
 502     case 0x80:  /* GPIO_CLEARWKUENA */
 503         s->wumask &= ~value;
 504         break;
 505
 506     case 0x84:  /* GPIO_SETWKUENA */
 507         s->wumask |= value;
 508         break;
 509
 510     case 0x90:  /* GPIO_CLEARDATAOUT */
 511         omap2_gpio_module_out_update(s, s->outputs & value);
 512         break;
 513
 514     case 0x94:  /* GPIO_SETDATAOUT */
 515         omap2_gpio_module_out_update(s, ~s->outputs & value);
 516         break;
 517
 518     default:
 519         OMAP_BAD_REG(addr);
 520         return;
 521     }
 522 }
 523
 524 static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
 525                                         unsigned size)
 526 {
 527     return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
 528 }
 529
 530 static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
 531                                      uint64_t value, unsigned size)
 532 {
 533     uint32_t cur = 0;
 534     uint32_t mask = 0xffff;
 535
 536     if (size == 4) {
 537         omap2_gpio_module_write(opaque, addr, value);
 538         return;
 539     }
 540
 541     switch (addr & ~3) {
 542     case 0x00:  /* GPIO_REVISION */
 543     case 0x14:  /* GPIO_SYSSTATUS */
 544     case 0x38:  /* GPIO_DATAIN */
 545         OMAP_RO_REG(addr);
 546         break;
 547
 548     case 0x10:  /* GPIO_SYSCONFIG */
 549     case 0x1c:  /* GPIO_IRQENABLE1 */
 550     case 0x20:  /* GPIO_WAKEUPENABLE */
 551     case 0x2c:  /* GPIO_IRQENABLE2 */
 552     case 0x30:  /* GPIO_CTRL */
 553     case 0x34:  /* GPIO_OE */
 554     case 0x3c:  /* GPIO_DATAOUT */
 555     case 0x40:  /* GPIO_LEVELDETECT0 */
 556     case 0x44:  /* GPIO_LEVELDETECT1 */
 557     case 0x48:  /* GPIO_RISINGDETECT */
 558     case 0x4c:  /* GPIO_FALLINGDETECT */
 559     case 0x50:  /* GPIO_DEBOUNCENABLE */
 560     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 561         cur = omap2_gpio_module_read(opaque, addr & ~3) &
 562                 ~(mask << ((addr & 3) << 3));
 563
 564         /* Fall through.  */
 565     case 0x18:  /* GPIO_IRQSTATUS1 */
 566     case 0x28:  /* GPIO_IRQSTATUS2 */
 567     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 568     case 0x64:  /* GPIO_SETIRQENABLE1 */
 569     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 570     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 571     case 0x80:  /* GPIO_CLEARWKUENA */
 572     case 0x84:  /* GPIO_SETWKUENA */
 573     case 0x90:  /* GPIO_CLEARDATAOUT */
 574     case 0x94:  /* GPIO_SETDATAOUT */
 575         value <<= (addr & 3) << 3;
 576         omap2_gpio_module_write(opaque, addr, cur | value);
 577         break;
 578
 579     default:
 580         OMAP_BAD_REG(addr);
 581         return;
 582     }
 583 }
 584
 585 static const MemoryRegionOps omap2_gpio_module_ops = {
 586     .read = omap2_gpio_module_readp,
 587     .write = omap2_gpio_module_writep,
 588     .valid.min_access_size = 1,
 589     .valid.max_access_size = 4,
 590     .endianness = DEVICE_NATIVE_ENDIAN,
 591 };
 592
 593 static void omap_gpif_reset(DeviceState *dev)
 594 {
 595     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 596
 597     omap_gpio_reset(&s->omap1);
 598 }
 599
 600 static void omap2_gpif_reset(DeviceState *dev)
 601 {
 602     struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 603     int i;
 604
 605     for (i = 0; i < s->modulecount; i++) {
 606         omap2_gpio_module_reset(&s->modules[i]);
 607     }
 608     s->autoidle = 0;
 609     s->gpo = 0;
 610 }
 611
 612 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
 613                                     unsigned size)
 614 {
 615     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 616
 617     switch (addr) {
 618     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 619         return 0x18;
 620
 621     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 622         return s->autoidle;
 623
 624     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 625         return 0x01;
 626
 627     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 628         return 0x00;
 629
 630     case 0x40:  /* IPGENERICOCPSPL_GPO */
 631         return s->gpo;
 632
 633     case 0x50:  /* IPGENERICOCPSPL_GPI */
 634         return 0x00;
 635     }
 636
 637     OMAP_BAD_REG(addr);
 638     return 0;
 639 }
 640
 641 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
 642                                  uint64_t value, unsigned size)
 643 {
 644     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 645
 646     switch (addr) {
 647     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 648     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 649     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 650     case 0x50:  /* IPGENERICOCPSPL_GPI */
 651         OMAP_RO_REG(addr);
 652         break;
 653
 654     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 655         if (value & (1 << 1))                                   /* SOFTRESET */
 656             omap2_gpif_reset(DEVICE(s));
 657         s->autoidle = value & 1;
 658         break;
 659
 660     case 0x40:  /* IPGENERICOCPSPL_GPO */
 661         s->gpo = value & 1;
 662         break;
 663
 664     default:
 665         OMAP_BAD_REG(addr);
 666         return;
 667     }
 668 }
 669
 670 static const MemoryRegionOps omap2_gpif_top_ops = {
 671     .read = omap2_gpif_top_read,
 672     .write = omap2_gpif_top_write,
 673     .endianness = DEVICE_NATIVE_ENDIAN,
 674 };
 675
 676 static void omap_gpio_init(Object *obj)
 677 {
 678     DeviceState *dev = DEVICE(obj);
 679     struct omap_gpif_s *s = OMAP1_GPIO(obj);
 680     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 681
 682     qdev_init_gpio_in(dev, omap_gpio_set, 16);
 683     qdev_init_gpio_out(dev, s->omap1.handler, 16);
 684     sysbus_init_irq(sbd, &s->omap1.irq);
 685     memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1,
 686                           "omap.gpio", 0x1000);
 687     sysbus_init_mmio(sbd, &s->iomem);
 688 }
 689
 690 static void omap_gpio_realize(DeviceState *dev, Error **errp)
 691 {
 692     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 693
 694     if (!s->clk) {
 695         error_setg(errp, "omap-gpio: clk not connected");
 696     }
 697 }
 698
 699 static void omap2_gpio_realize(DeviceState *dev, Error **errp)
 700 {
 701     struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 702     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 703     int i;
 704
 705     if (!s->iclk) {
 706         error_setg(errp, "omap2-gpio: iclk not connected");
 707         return;
 708     }
 709
 710     s->modulecount = s->mpu_model < omap2430 ? 4
 711         : s->mpu_model < omap3430 ? 5
 712         : 6;
 713
 714     if (s->mpu_model < omap3430) {
 715         memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s,
 716                               "omap2.gpio", 0x1000);
 717         sysbus_init_mmio(sbd, &s->iomem);
 718     }
 719
 720     s->modules = g_new0(struct omap2_gpio_s, s->modulecount);
 721     s->handler = g_new0(qemu_irq, s->modulecount * 32);
 722     qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
 723     qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
 724
 725     for (i = 0; i < s->modulecount; i++) {
 726         struct omap2_gpio_s *m = &s->modules[i];
 727
 728         if (!s->fclk[i]) {
 729             error_setg(errp, "omap2-gpio: fclk%d not connected", i);
 730             return;
 731         }
 732
 733         m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
 734         m->handler = &s->handler[i * 32];
 735         sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
 736         sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
 737         sysbus_init_irq(sbd, &m->wkup);
 738         memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m,
 739                               "omap.gpio-module", 0x1000);
 740         sysbus_init_mmio(sbd, &m->iomem);
 741     }
 742 }
 743
 744 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
 745 {
 746     gpio->clk = clk;
 747 }
 748
 749 static Property omap_gpio_properties[] = {
 750     DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
 751     DEFINE_PROP_END_OF_LIST(),
 752 };
 753
 754 static void omap_gpio_class_init(ObjectClass *klass, void *data)
 755 {
 756     DeviceClass *dc = DEVICE_CLASS(klass);
 757
 758     dc->realize = omap_gpio_realize;
 759     dc->reset = omap_gpif_reset;
 760     device_class_set_props(dc, omap_gpio_properties);
 761     /* Reason: pointer property "clk" */
 762     dc->user_creatable = false;
 763 }
 764
 765 static const TypeInfo omap_gpio_info = {
 766     .name          = TYPE_OMAP1_GPIO,
 767     .parent        = TYPE_SYS_BUS_DEVICE,
 768     .instance_size = sizeof(struct omap_gpif_s),
 769     .instance_init = omap_gpio_init,
 770     .class_init    = omap_gpio_class_init,
 771 };
 772
 773 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
 774 {
 775     gpio->iclk = clk;
 776 }
 777
 778 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
 779 {
 780     assert(i <= 5);
 781     gpio->fclk[i] = clk;
 782 }
 783
 784 static Property omap2_gpio_properties[] = {
 785     DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
 786     DEFINE_PROP_END_OF_LIST(),
 787 };
 788
 789 static void omap2_gpio_class_init(ObjectClass *klass, void *data)
 790 {
 791     DeviceClass *dc = DEVICE_CLASS(klass);
 792
 793     dc->realize = omap2_gpio_realize;
 794     dc->reset = omap2_gpif_reset;
 795     device_class_set_props(dc, omap2_gpio_properties);
 796     /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
 797     dc->user_creatable = false;
 798 }
 799
 800 static const TypeInfo omap2_gpio_info = {
 801     .name          = TYPE_OMAP2_GPIO,
 802     .parent        = TYPE_SYS_BUS_DEVICE,
 803     .instance_size = sizeof(struct omap2_gpif_s),
 804     .class_init    = omap2_gpio_class_init,
 805 };
 806
 807 static void omap_gpio_register_types(void)
 808 {
 809     type_register_static(&omap_gpio_info);
 810     type_register_static(&omap2_gpio_info);
 811 }
 812
 813 type_init(omap_gpio_register_types)