hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2.1 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/southbridge/piix.h"
  25 #include "hw/irq.h"
  26 #include "hw/isa/apm.h"
  27 #include "hw/i2c/pm_smbus.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/acpi/acpi.h"
  31 #include "sysemu/runstate.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/xen.h"
  34 #include "qapi/error.h"
  35 #include "qemu/range.h"
  36 #include "exec/address-spaces.h"
  37 #include "hw/acpi/pcihp.h"
  38 #include "hw/acpi/cpu_hotplug.h"
  39 #include "hw/acpi/cpu.h"
  40 #include "hw/hotplug.h"
  41 #include "hw/mem/pc-dimm.h"
  42 #include "hw/mem/nvdimm.h"
  43 #include "hw/acpi/memory_hotplug.h"
  44 #include "hw/acpi/acpi_dev_interface.h"
  45 #include "migration/vmstate.h"
  46 #include "hw/core/cpu.h"
  47 #include "trace.h"
  48 #include "qom/object.h"
  49
  50 #define GPE_BASE 0xafe0
  51 #define GPE_LEN 4
  52
  53 struct pci_status {
  54     uint32_t up; /* deprecated, maintained for migration compatibility */
  55     uint32_t down;
  56 };
  57
  58 struct PIIX4PMState {
  59     /*< private >*/
  60     PCIDevice parent_obj;
  61     /*< public >*/
  62
  63     MemoryRegion io;
  64     uint32_t io_base;
  65
  66     MemoryRegion io_gpe;
  67     ACPIREGS ar;
  68
  69     APMState apm;
  70
  71     PMSMBus smb;
  72     uint32_t smb_io_base;
  73
  74     qemu_irq irq;
  75     qemu_irq smi_irq;
  76     int smm_enabled;
  77     bool smm_compat;
  78     Notifier machine_ready;
  79     Notifier powerdown_notifier;
  80
  81     AcpiPciHpState acpi_pci_hotplug;
  82     bool use_acpi_hotplug_bridge;
  83     bool use_acpi_root_pci_hotplug;
  84
  85     uint8_t disable_s3;
  86     uint8_t disable_s4;
  87     uint8_t s4_val;
  88
  89     bool cpu_hotplug_legacy;
  90     AcpiCpuHotplug gpe_cpu;
  91     CPUHotplugState cpuhp_state;
  92
  93     MemHotplugState acpi_memory_hotplug;
  94 };
  95
  96 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
  97
  98 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  99                                            PCIBus *bus, PIIX4PMState *s);
 100
 101 #define ACPI_ENABLE 0xf1
 102 #define ACPI_DISABLE 0xf0
 103
 104 static void pm_tmr_timer(ACPIREGS *ar)
 105 {
 106     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 107     acpi_update_sci(&s->ar, s->irq);
 108 }
 109
 110 static void apm_ctrl_changed(uint32_t val, void *arg)
 111 {
 112     PIIX4PMState *s = arg;
 113     PCIDevice *d = PCI_DEVICE(s);
 114
 115     /* ACPI specs 3.0, 4.7.2.5 */
 116     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 117     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 118         return;
 119     }
 120
 121     if (d->config[0x5b] & (1 << 1)) {
 122         if (s->smi_irq) {
 123             qemu_irq_raise(s->smi_irq);
 124         }
 125     }
 126 }
 127
 128 static void pm_io_space_update(PIIX4PMState *s)
 129 {
 130     PCIDevice *d = PCI_DEVICE(s);
 131
 132     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 133     s->io_base &= 0xffc0;
 134
 135     memory_region_transaction_begin();
 136     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 137     memory_region_set_address(&s->io, s->io_base);
 138     memory_region_transaction_commit();
 139 }
 140
 141 static void smbus_io_space_update(PIIX4PMState *s)
 142 {
 143     PCIDevice *d = PCI_DEVICE(s);
 144
 145     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 146     s->smb_io_base &= 0xffc0;
 147
 148     memory_region_transaction_begin();
 149     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 150     memory_region_set_address(&s->smb.io, s->smb_io_base);
 151     memory_region_transaction_commit();
 152 }
 153
 154 static void pm_write_config(PCIDevice *d,
 155                             uint32_t address, uint32_t val, int len)
 156 {
 157     pci_default_write_config(d, address, val, len);
 158     if (range_covers_byte(address, len, 0x80) ||
 159         ranges_overlap(address, len, 0x40, 4)) {
 160         pm_io_space_update((PIIX4PMState *)d);
 161     }
 162     if (range_covers_byte(address, len, 0xd2) ||
 163         ranges_overlap(address, len, 0x90, 4)) {
 164         smbus_io_space_update((PIIX4PMState *)d);
 165     }
 166 }
 167
 168 static int vmstate_acpi_post_load(void *opaque, int version_id)
 169 {
 170     PIIX4PMState *s = opaque;
 171
 172     pm_io_space_update(s);
 173     smbus_io_space_update(s);
 174     return 0;
 175 }
 176
 177 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 178  {                                                                   \
 179      .name       = (stringify(_field)),                              \
 180      .version_id = 0,                                                \
 181      .info       = &vmstate_info_uint16,                             \
 182      .size       = sizeof(uint16_t),                                 \
 183      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 184      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 185  }
 186
 187 static const VMStateDescription vmstate_gpe = {
 188     .name = "gpe",
 189     .version_id = 1,
 190     .minimum_version_id = 1,
 191     .fields = (VMStateField[]) {
 192         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 193         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static const VMStateDescription vmstate_pci_status = {
 199     .name = "pci_status",
 200     .version_id = 1,
 201     .minimum_version_id = 1,
 202     .fields = (VMStateField[]) {
 203         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 204         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 205         VMSTATE_END_OF_LIST()
 206     }
 207 };
 208
 209 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id)
 210 {
 211     PIIX4PMState *s = opaque;
 212     return s->use_acpi_hotplug_bridge;
 213 }
 214
 215 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque,
 216                                                     int version_id)
 217 {
 218     PIIX4PMState *s = opaque;
 219     return !s->use_acpi_hotplug_bridge;
 220 }
 221
 222 static bool vmstate_test_use_memhp(void *opaque)
 223 {
 224     PIIX4PMState *s = opaque;
 225     return s->acpi_memory_hotplug.is_enabled;
 226 }
 227
 228 static const VMStateDescription vmstate_memhp_state = {
 229     .name = "piix4_pm/memhp",
 230     .version_id = 1,
 231     .minimum_version_id = 1,
 232     .minimum_version_id_old = 1,
 233     .needed = vmstate_test_use_memhp,
 234     .fields      = (VMStateField[]) {
 235         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 236         VMSTATE_END_OF_LIST()
 237     }
 238 };
 239
 240 static bool vmstate_test_use_cpuhp(void *opaque)
 241 {
 242     PIIX4PMState *s = opaque;
 243     return !s->cpu_hotplug_legacy;
 244 }
 245
 246 static int vmstate_cpuhp_pre_load(void *opaque)
 247 {
 248     Object *obj = OBJECT(opaque);
 249     object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
 250     return 0;
 251 }
 252
 253 static const VMStateDescription vmstate_cpuhp_state = {
 254     .name = "piix4_pm/cpuhp",
 255     .version_id = 1,
 256     .minimum_version_id = 1,
 257     .minimum_version_id_old = 1,
 258     .needed = vmstate_test_use_cpuhp,
 259     .pre_load = vmstate_cpuhp_pre_load,
 260     .fields      = (VMStateField[]) {
 261         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 262         VMSTATE_END_OF_LIST()
 263     }
 264 };
 265
 266 static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
 267 {
 268     return pm_smbus_vmstate_needed();
 269 }
 270
 271 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 272  * To support incoming qemu-kvm 1.2 migration, change version_id
 273  * and minimum_version_id to 2 below (which breaks migration from
 274  * qemu 1.2).
 275  *
 276  */
 277 static const VMStateDescription vmstate_acpi = {
 278     .name = "piix4_pm",
 279     .version_id = 3,
 280     .minimum_version_id = 3,
 281     .post_load = vmstate_acpi_post_load,
 282     .fields = (VMStateField[]) {
 283         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 284         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 285         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 286         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 287         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 288         VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
 289                             pmsmb_vmstate, PMSMBus),
 290         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 291         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 292         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 293         VMSTATE_STRUCT_TEST(
 294             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 295             PIIX4PMState,
 296             vmstate_test_no_use_acpi_hotplug_bridge,
 297             2, vmstate_pci_status,
 298             struct AcpiPciHpPciStatus),
 299         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 300                             vmstate_test_use_acpi_hotplug_bridge),
 301         VMSTATE_END_OF_LIST()
 302     },
 303     .subsections = (const VMStateDescription*[]) {
 304          &vmstate_memhp_state,
 305          &vmstate_cpuhp_state,
 306          NULL
 307     }
 308 };
 309
 310 static void piix4_pm_reset(DeviceState *dev)
 311 {
 312     PIIX4PMState *s = PIIX4_PM(dev);
 313     PCIDevice *d = PCI_DEVICE(s);
 314     uint8_t *pci_conf = d->config;
 315
 316     pci_conf[0x58] = 0;
 317     pci_conf[0x59] = 0;
 318     pci_conf[0x5a] = 0;
 319     pci_conf[0x5b] = 0;
 320
 321     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 322     pci_conf[0x80] = 0;
 323
 324     if (!s->smm_enabled) {
 325         /* Mark SMM as already inited (until KVM supports SMM). */
 326         pci_conf[0x5B] = 0x02;
 327     }
 328     pm_io_space_update(s);
 329     acpi_pcihp_reset(&s->acpi_pci_hotplug, !s->use_acpi_root_pci_hotplug);
 330 }
 331
 332 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 333 {
 334     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 335
 336     assert(s != NULL);
 337     acpi_pm1_evt_power_down(&s->ar);
 338 }
 339
 340 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
 341                                     DeviceState *dev, Error **errp)
 342 {
 343     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 344
 345     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 346         acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
 347     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 348         if (!s->acpi_memory_hotplug.is_enabled) {
 349             error_setg(errp,
 350                 "memory hotplug is not enabled: %s.memory-hotplug-support "
 351                 "is not set", object_get_typename(OBJECT(s)));
 352         }
 353     } else if (
 354                !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 355         error_setg(errp, "acpi: device pre plug request for not supported"
 356                    " device type: %s", object_get_typename(OBJECT(dev)));
 357     }
 358 }
 359
 360 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 361                                  DeviceState *dev, Error **errp)
 362 {
 363     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 364
 365     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 366         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 367             nvdimm_acpi_plug_cb(hotplug_dev, dev);
 368         } else {
 369             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 370                                 dev, errp);
 371         }
 372     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 373         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 374     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 375         if (s->cpu_hotplug_legacy) {
 376             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 377         } else {
 378             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 379         }
 380     } else {
 381         g_assert_not_reached();
 382     }
 383 }
 384
 385 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 386                                            DeviceState *dev, Error **errp)
 387 {
 388     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 389
 390     if (s->acpi_memory_hotplug.is_enabled &&
 391         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 392         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 393                                       dev, errp);
 394     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 395         acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
 396                                             dev, errp);
 397     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 398                !s->cpu_hotplug_legacy) {
 399         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 400     } else {
 401         error_setg(errp, "acpi: device unplug request for not supported device"
 402                    " type: %s", object_get_typename(OBJECT(dev)));
 403     }
 404 }
 405
 406 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 407                                    DeviceState *dev, Error **errp)
 408 {
 409     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 410
 411     if (s->acpi_memory_hotplug.is_enabled &&
 412         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 413         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 414     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 415         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 416                                     errp);
 417     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 418                !s->cpu_hotplug_legacy) {
 419         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 420     } else {
 421         error_setg(errp, "acpi: device unplug for not supported device"
 422                    " type: %s", object_get_typename(OBJECT(dev)));
 423     }
 424 }
 425
 426 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 427 {
 428     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 429     PCIDevice *d = PCI_DEVICE(s);
 430     MemoryRegion *io_as = pci_address_space_io(d);
 431     uint8_t *pci_conf;
 432
 433     pci_conf = d->config;
 434     pci_conf[0x5f] = 0x10 |
 435         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 436     pci_conf[0x63] = 0x60;
 437     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 438         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 439 }
 440
 441 static void piix4_pm_add_properties(PIIX4PMState *s)
 442 {
 443     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 444     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 445     static const uint32_t gpe0_blk = GPE_BASE;
 446     static const uint32_t gpe0_blk_len = GPE_LEN;
 447     static const uint16_t sci_int = 9;
 448
 449     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 450                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
 451     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 452                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
 453     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 454                                   &gpe0_blk, OBJ_PROP_FLAG_READ);
 455     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 456                                   &gpe0_blk_len, OBJ_PROP_FLAG_READ);
 457     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 458                                   &sci_int, OBJ_PROP_FLAG_READ);
 459     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 460                                   &s->io_base, OBJ_PROP_FLAG_READ);
 461 }
 462
 463 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 464 {
 465     PIIX4PMState *s = PIIX4_PM(dev);
 466     uint8_t *pci_conf;
 467
 468     pci_conf = dev->config;
 469     pci_conf[0x06] = 0x80;
 470     pci_conf[0x07] = 0x02;
 471     pci_conf[0x09] = 0x00;
 472     pci_conf[0x3d] = 0x01; // interrupt pin 1
 473
 474     /* APM */
 475     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 476
 477     if (!s->smm_enabled) {
 478         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 479          * support SMM mode. */
 480         pci_conf[0x5B] = 0x02;
 481     }
 482
 483     /* XXX: which specification is used ? The i82731AB has different
 484        mappings */
 485     pci_conf[0x90] = s->smb_io_base | 1;
 486     pci_conf[0x91] = s->smb_io_base >> 8;
 487     pci_conf[0xd2] = 0x09;
 488     pm_smbus_init(DEVICE(dev), &s->smb, true);
 489     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 490     memory_region_add_subregion(pci_address_space_io(dev),
 491                                 s->smb_io_base, &s->smb.io);
 492
 493     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 494     memory_region_set_enabled(&s->io, false);
 495     memory_region_add_subregion(pci_address_space_io(dev),
 496                                 0, &s->io);
 497
 498     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 499     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 500     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val,
 501                       !s->smm_compat && !s->smm_enabled);
 502     acpi_gpe_init(&s->ar, GPE_LEN);
 503
 504     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 505     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 506
 507     s->machine_ready.notify = piix4_pm_machine_ready;
 508     qemu_add_machine_init_done_notifier(&s->machine_ready);
 509
 510     piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
 511                                    pci_get_bus(dev), s);
 512     qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s));
 513
 514     piix4_pm_add_properties(s);
 515 }
 516
 517 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 518                       qemu_irq sci_irq, qemu_irq smi_irq,
 519                       int smm_enabled, DeviceState **piix4_pm)
 520 {
 521     PCIDevice *pci_dev;
 522     DeviceState *dev;
 523     PIIX4PMState *s;
 524
 525     pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
 526     dev = DEVICE(pci_dev);
 527     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 528     if (piix4_pm) {
 529         *piix4_pm = dev;
 530     }
 531
 532     s = PIIX4_PM(dev);
 533     s->irq = sci_irq;
 534     s->smi_irq = smi_irq;
 535     s->smm_enabled = smm_enabled;
 536     if (xen_enabled()) {
 537         s->use_acpi_hotplug_bridge = false;
 538     }
 539
 540     pci_realize_and_unref(pci_dev, bus, &error_fatal);
 541
 542     return s->smb.smbus;
 543 }
 544
 545 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 546 {
 547     PIIX4PMState *s = opaque;
 548     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 549
 550     trace_piix4_gpe_readb(addr, width, val);
 551     return val;
 552 }
 553
 554 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 555                        unsigned width)
 556 {
 557     PIIX4PMState *s = opaque;
 558
 559     trace_piix4_gpe_writeb(addr, width, val);
 560     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 561     acpi_update_sci(&s->ar, s->irq);
 562 }
 563
 564 static const MemoryRegionOps piix4_gpe_ops = {
 565     .read = gpe_readb,
 566     .write = gpe_writeb,
 567     .valid.min_access_size = 1,
 568     .valid.max_access_size = 4,
 569     .impl.min_access_size = 1,
 570     .impl.max_access_size = 1,
 571     .endianness = DEVICE_LITTLE_ENDIAN,
 572 };
 573
 574
 575 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 576 {
 577     PIIX4PMState *s = PIIX4_PM(obj);
 578
 579     return s->cpu_hotplug_legacy;
 580 }
 581
 582 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 583 {
 584     PIIX4PMState *s = PIIX4_PM(obj);
 585
 586     assert(!value);
 587     if (s->cpu_hotplug_legacy && value == false) {
 588         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 589                                    PIIX4_CPU_HOTPLUG_IO_BASE);
 590     }
 591     s->cpu_hotplug_legacy = value;
 592 }
 593
 594 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 595                                            PCIBus *bus, PIIX4PMState *s)
 596 {
 597     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 598                           "acpi-gpe0", GPE_LEN);
 599     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 600
 601     if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) {
 602         acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 603                         s->use_acpi_hotplug_bridge);
 604     }
 605
 606     s->cpu_hotplug_legacy = true;
 607     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 608                              piix4_get_cpu_hotplug_legacy,
 609                              piix4_set_cpu_hotplug_legacy);
 610     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 611                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 612
 613     if (s->acpi_memory_hotplug.is_enabled) {
 614         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
 615                                  ACPI_MEMORY_HOTPLUG_BASE);
 616     }
 617 }
 618
 619 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 620 {
 621     PIIX4PMState *s = PIIX4_PM(adev);
 622
 623     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 624     if (!s->cpu_hotplug_legacy) {
 625         acpi_cpu_ospm_status(&s->cpuhp_state, list);
 626     }
 627 }
 628
 629 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 630 {
 631     PIIX4PMState *s = PIIX4_PM(adev);
 632
 633     acpi_send_gpe_event(&s->ar, s->irq, ev);
 634 }
 635
 636 static Property piix4_pm_properties[] = {
 637     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 638     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 639     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 640     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 641     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 642                      use_acpi_hotplug_bridge, true),
 643     DEFINE_PROP_BOOL("acpi-root-pci-hotplug", PIIX4PMState,
 644                      use_acpi_root_pci_hotplug, true),
 645     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 646                      acpi_memory_hotplug.is_enabled, true),
 647     DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
 648     DEFINE_PROP_END_OF_LIST(),
 649 };
 650
 651 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 652 {
 653     DeviceClass *dc = DEVICE_CLASS(klass);
 654     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 655     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 656     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 657
 658     k->realize = piix4_pm_realize;
 659     k->config_write = pm_write_config;
 660     k->vendor_id = PCI_VENDOR_ID_INTEL;
 661     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 662     k->revision = 0x03;
 663     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 664     dc->reset = piix4_pm_reset;
 665     dc->desc = "PM";
 666     dc->vmsd = &vmstate_acpi;
 667     device_class_set_props(dc, piix4_pm_properties);
 668     /*
 669      * Reason: part of PIIX4 southbridge, needs to be wired up,
 670      * e.g. by mips_malta_init()
 671      */
 672     dc->user_creatable = false;
 673     dc->hotpluggable = false;
 674     hc->pre_plug = piix4_device_pre_plug_cb;
 675     hc->plug = piix4_device_plug_cb;
 676     hc->unplug_request = piix4_device_unplug_request_cb;
 677     hc->unplug = piix4_device_unplug_cb;
 678     adevc->ospm_status = piix4_ospm_status;
 679     adevc->send_event = piix4_send_gpe;
 680     adevc->madt_cpu = pc_madt_cpu_entry;
 681 }
 682
 683 static const TypeInfo piix4_pm_info = {
 684     .name          = TYPE_PIIX4_PM,
 685     .parent        = TYPE_PCI_DEVICE,
 686     .instance_size = sizeof(PIIX4PMState),
 687     .class_init    = piix4_pm_class_init,
 688     .interfaces = (InterfaceInfo[]) {
 689         { TYPE_HOTPLUG_HANDLER },
 690         { TYPE_ACPI_DEVICE_IF },
 691         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 692         { }
 693     }
 694 };
 695
 696 static void piix4_pm_register_types(void)
 697 {
 698     type_register_static(&piix4_pm_info);
 699 }
 700
 701 type_init(piix4_pm_register_types)