2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* Debug EEPRO100 card. */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
68 #define INT 1 /* interrupt related actions */
69 #define MDI 1 /* mdi related actions */
72 #define EEPROM 1 /* eeprom related actions */
74 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78 #define MAX_ETH_FRAME_SIZE 1514
80 /* This driver supports several different devices which are declared here. */
81 #define i82550 0x82550
82 #define i82551 0x82551
83 #define i82557A 0x82557a
84 #define i82557B 0x82557b
85 #define i82557C 0x82557c
86 #define i82558A 0x82558a
87 #define i82558B 0x82558b
88 #define i82559A 0x82559a
89 #define i82559B 0x82559b
90 #define i82559C 0x82559c
91 #define i82559ER 0x82559e
92 #define i82562 0x82562
94 /* Use 64 word EEPROM. TODO: could be a runtime option. */
95 #define EEPROM_SIZE 64
97 #define PCI_MEM_SIZE (4 * KiB)
98 #define PCI_IO_SIZE 64
99 #define PCI_FLASH_SIZE (128 * KiB)
101 #define BIT(n) (1 << (n))
102 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104 /* The SCB accepts the following controls for the Tx and Rx units: */
105 #define CU_NOP 0x0000 /* No operation. */
106 #define CU_START 0x0010 /* CU start. */
107 #define CU_RESUME 0x0020 /* CU resume. */
108 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
109 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
111 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112 #define CU_SRESUME 0x00a0 /* CU static resume. */
114 #define RU_NOP 0x0000
115 #define RX_START 0x0001
116 #define RX_RESUME 0x0002
117 #define RX_ABORT 0x0004
118 #define RX_ADDR_LOAD 0x0006
119 #define RX_RESUMENR 0x0007
120 #define INT_MASK 0x0100
121 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123 /* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125 enum speedo_offsets
{
128 SCBCmd
= 2, /* Rx/Command Unit command and status. */
130 SCBPointer
= 4, /* General purpose pointer. */
131 SCBPort
= 8, /* Misc. commands and operands. */
132 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI
= 16, /* MDI interface control. */
134 SCBEarlyRx
= 20, /* Early receive byte count. */
138 /* A speedo3 transmit buffer descriptor with two buffers... */
142 uint32_t link
; /* void * */
143 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold
; /* transmit threshold */
146 uint8_t tbd_count
; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
154 /* Receive frame descriptor. */
158 uint32_t link
; /* struct RxFD * */
159 uint32_t rx_buf_addr
; /* void * */
162 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
166 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
167 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
168 tx_multiple_collisions
, tx_total_collisions
;
169 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
170 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
171 rx_short_frame_errors
;
172 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
173 uint16_t xmt_tco_frames
, rcv_tco_frames
;
174 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
175 uint32_t reserved
[4];
195 uint8_t mult
[8]; /* multicast mask array */
199 uint8_t scb_stat
; /* SCB stat/ack byte */
200 uint8_t int_stat
; /* PCI interrupt status */
201 /* region must not be saved by nic_save. */
202 uint32_t region
[3]; /* PCI region addresses */
205 uint32_t device
; /* device variant */
207 /* (cu_base + cu_offset) address the next command block in the command block list. */
208 uint32_t cu_base
; /* CU base address */
209 uint32_t cu_offset
; /* CU address offset */
210 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
211 uint32_t ru_base
; /* RU base address */
212 uint32_t ru_offset
; /* RU address offset */
213 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
215 /* Temporary status information (no need to save these values),
216 * used while processing CU commands. */
217 eepro100_tx_t tx
; /* transmit buffer descriptor */
218 uint32_t cb_address
; /* = cu_base + cu_offset */
220 /* Statistical counters. Also used for wake-up packet (i82559). */
221 eepro100_stats_t statistics
;
227 /* Configuration bytes. */
228 uint8_t configuration
[22];
230 /* Data in mem is always in the byte order of the controller (le). */
231 uint8_t mem
[PCI_MEM_SIZE
];
232 /* vmstate for each particular nic */
233 VMStateDescription
*vmstate
;
235 /* Quasi static device properties (no need to save them). */
237 bool has_extended_tcb_support
;
240 /* Default values for MDI (PHY) registers */
241 static const uint16_t eepro100_mdi_default
[] = {
242 /* MDI Registers 0 - 6, 7 */
243 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
244 /* MDI Registers 8 - 15 */
245 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 /* MDI Registers 16 - 31 */
247 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251 /* Readonly mask for MDI (PHY) registers */
252 static const uint16_t eepro100_mdi_mask
[] = {
253 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
254 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
255 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
256 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
260 static void stl_le_phys(target_phys_addr_t addr
, uint32_t val
)
262 val
= cpu_to_le32(val
);
263 cpu_physical_memory_write(addr
, (const uint8_t *)&val
, sizeof(val
));
266 #define POLYNOMIAL 0x04c11db6
270 static int compute_mcast_idx(const uint8_t * ep
)
277 for (i
= 0; i
< 6; i
++) {
279 for (j
= 0; j
< 8; j
++) {
280 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
284 crc
= ((crc
^ POLYNOMIAL
) | carry
);
291 #if defined(DEBUG_EEPRO100)
292 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
294 static char dump
[3 * 16 + 1];
300 p
+= sprintf(p
, " %02x", *buf
++);
304 #endif /* DEBUG_EEPRO100 */
307 stat_ack_not_ours
= 0x00,
308 stat_ack_sw_gen
= 0x04,
310 stat_ack_cu_idle
= 0x20,
311 stat_ack_frame_rx
= 0x40,
312 stat_ack_cu_cmd_done
= 0x80,
313 stat_ack_not_present
= 0xFF,
314 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
315 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
318 static void disable_interrupt(EEPRO100State
* s
)
321 TRACE(INT
, logout("interrupt disabled\n"));
322 qemu_irq_lower(s
->dev
.irq
[0]);
327 static void enable_interrupt(EEPRO100State
* s
)
330 TRACE(INT
, logout("interrupt enabled\n"));
331 qemu_irq_raise(s
->dev
.irq
[0]);
336 static void eepro100_acknowledge(EEPRO100State
* s
)
338 s
->scb_stat
&= ~s
->mem
[SCBAck
];
339 s
->mem
[SCBAck
] = s
->scb_stat
;
340 if (s
->scb_stat
== 0) {
341 disable_interrupt(s
);
345 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
347 uint8_t mask
= ~s
->mem
[SCBIntmask
];
348 s
->mem
[SCBAck
] |= stat
;
349 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
350 stat
&= (mask
| 0x0f);
351 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
352 if (stat
&& (mask
& 0x01)) {
353 /* SCB mask and SCB Bit M do not disable interrupt. */
355 } else if (s
->int_stat
) {
356 disable_interrupt(s
);
360 static void eepro100_cx_interrupt(EEPRO100State
* s
)
362 /* CU completed action command. */
363 /* Transmit not ok (82557 only, not in emulation). */
364 eepro100_interrupt(s
, 0x80);
367 static void eepro100_cna_interrupt(EEPRO100State
* s
)
369 /* CU left the active state. */
370 eepro100_interrupt(s
, 0x20);
373 static void eepro100_fr_interrupt(EEPRO100State
* s
)
375 /* RU received a complete frame. */
376 eepro100_interrupt(s
, 0x40);
380 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
382 /* RU is not ready. */
383 eepro100_interrupt(s
, 0x10);
387 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
389 /* MDI completed read or write cycle. */
390 eepro100_interrupt(s
, 0x08);
393 static void eepro100_swi_interrupt(EEPRO100State
* s
)
395 /* Software has requested an interrupt. */
396 eepro100_interrupt(s
, 0x04);
400 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
402 /* Flow control pause interrupt (82558 and later). */
403 eepro100_interrupt(s
, 0x01);
407 static void pci_reset(EEPRO100State
* s
)
409 uint32_t device
= s
->device
;
410 uint8_t *pci_conf
= s
->dev
.config
;
411 bool power_management
= 1;
413 TRACE(OTHER
, logout("%p\n", s
));
416 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
417 /* PCI Device ID depends on device and is set below. */
419 /* TODO: this is the default, do not override. */
420 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
422 /* TODO: Value at RST# should be 0. */
423 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
| PCI_STATUS_FAST_BACK
);
424 /* PCI Revision ID */
425 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
426 /* TODO: this is the default, do not override. */
428 PCI_CONFIG_8(PCI_CLASS_PROG
, 0x00);
429 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
430 /* PCI Cache Line Size */
431 /* check cache line size!!! */
432 //~ PCI_CONFIG_8(0x0c, 0x00);
433 /* PCI Latency Timer */
434 PCI_CONFIG_8(PCI_LATENCY_TIMER
, 0x20); // latency timer = 32 clocks
435 /* PCI Header Type */
436 /* BIST (built-in self test) */
437 #if defined(TARGET_I386)
438 // !!! workaround for buggy bios
439 //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
442 /* PCI Base Address Registers */
443 /* CSR Memory Mapped Base Address */
444 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
445 PCI_BASE_ADDRESS_SPACE_MEMORY
|
446 PCI_BASE_ADDRESS_MEM_PREFETCH
);
447 /* CSR I/O Mapped Base Address */
448 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_BASE_ADDRESS_SPACE_IO
);
450 /* Flash Memory Mapped Base Address */
451 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
,
452 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY
);
455 /* Expansion ROM Base Address (depends on boot disable!!!) */
456 /* TODO: not needed, set when BAR is registered */
457 PCI_CONFIG_32(PCI_ROM_ADDRESS
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
458 /* Capability Pointer */
459 /* TODO: revisions with power_management 1 use this but
460 * do not set new capability list bit in status register. */
461 PCI_CONFIG_8(PCI_CAPABILITY_LIST
, 0xdc);
464 /* TODO: RST# value should be 0 */
465 PCI_CONFIG_8(PCI_INTERRUPT_PIN
, 1); // interrupt pin 0
467 PCI_CONFIG_8(PCI_MIN_GNT
, 0x08);
468 /* Maximum Latency */
469 PCI_CONFIG_8(PCI_MAX_LAT
, 0x18);
473 // TODO: check device id.
474 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
475 /* Revision ID: 0x0c, 0x0d, 0x0e. */
476 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0e);
477 // TODO: check size of statistical counters.
479 // TODO: check extended tcb support.
480 s
->has_extended_tcb_support
= 1;
483 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
484 /* Revision ID: 0x0f, 0x10. */
485 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
486 // TODO: check size of statistical counters.
488 s
->has_extended_tcb_support
= 1;
491 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
492 PCI_CONFIG_8(PCI_REVISION_ID
, 0x01);
493 PCI_CONFIG_8(PCI_CAPABILITY_LIST
, 0x00);
494 power_management
= 0;
497 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
498 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
499 PCI_CONFIG_8(PCI_CAPABILITY_LIST
, 0x00);
500 power_management
= 0;
503 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
504 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
505 PCI_CONFIG_8(PCI_CAPABILITY_LIST
, 0x00);
506 power_management
= 0;
509 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
510 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
511 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
512 PCI_CONFIG_8(PCI_REVISION_ID
, 0x04);
514 s
->has_extended_tcb_support
= 1;
517 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
518 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
519 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
520 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
522 s
->has_extended_tcb_support
= 1;
525 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
526 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
527 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
528 PCI_CONFIG_8(PCI_REVISION_ID
, 0x06);
530 s
->has_extended_tcb_support
= 1;
533 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
534 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
535 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
536 PCI_CONFIG_8(PCI_REVISION_ID
, 0x07);
538 s
->has_extended_tcb_support
= 1;
541 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
542 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
543 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
544 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
545 // TODO: Windows wants revision id 0x0c.
546 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0c);
548 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID
, 0x8086);
549 PCI_CONFIG_16(PCI_SUBSYSTEM_ID
, 0x0040);
552 s
->has_extended_tcb_support
= 1;
555 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
556 PCI_CONFIG_16(PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
557 PCI_STATUS_FAST_BACK
| PCI_STATUS_CAP_LIST
);
558 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
560 s
->has_extended_tcb_support
= 1;
563 // TODO: check device id.
564 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
565 /* TODO: wrong revision id. */
566 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0e);
568 s
->has_extended_tcb_support
= 1;
571 logout("Device %X is undefined!\n", device
);
574 s
->configuration
[6] |= BIT(5);
576 if (s
->stats_size
== 80) {
577 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
578 if (s
->configuration
[6] & BIT(2)) {
579 /* TCO statistical counters. */
580 assert(s
->configuration
[6] & BIT(5));
582 if (s
->configuration
[6] & BIT(5)) {
583 /* No extended statistical counters, i82557 compatible. */
586 /* i82558 compatible. */
591 if (s
->configuration
[6] & BIT(5)) {
592 /* No extended statistical counters. */
596 assert(s
->stats_size
> 0 && s
->stats_size
<= sizeof(s
->statistics
));
598 if (power_management
) {
599 /* Power Management Capabilities */
600 PCI_CONFIG_8(0xdc, 0x01);
601 /* Next Item Pointer */
603 PCI_CONFIG_16(0xde, 0x7e21);
604 /* TODO: Power Management Control / Status. */
605 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
609 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
610 // TODO: get vendor id from EEPROM for i82557C or later.
611 // TODO: get device id from EEPROM for i82557C or later.
612 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
613 // TODO: header type is determined by EEPROM for i82559.
614 // TODO: get subsystem id from EEPROM for i82557C or later.
615 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
616 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
617 // TODO: capability pointer depends on EEPROM for i82558.
618 logout("Get device id and revision from EEPROM!!!\n");
620 #endif /* EEPROM_SIZE > 0 */
623 static void nic_selective_reset(EEPRO100State
* s
)
626 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
627 //~ eeprom93xx_reset(s->eeprom);
628 memcpy(eeprom_contents
, s
->conf
.macaddr
.a
, 6);
629 eeprom_contents
[0xa] = 0x4000;
630 if (s
->device
== i82557B
|| s
->device
== i82557C
)
631 eeprom_contents
[5] = 0x0100;
633 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
634 sum
+= eeprom_contents
[i
];
636 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
637 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
639 memset(s
->mem
, 0, sizeof(s
->mem
));
640 uint32_t val
= BIT(21);
641 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
643 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
644 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
647 static void nic_reset(void *opaque
)
649 EEPRO100State
*s
= opaque
;
650 TRACE(OTHER
, logout("%p\n", s
));
651 nic_selective_reset(s
);
654 #if defined(DEBUG_EEPRO100)
655 static const char * const e100_reg
[PCI_IO_SIZE
/ 4] = {
659 "EEPROM/Flash Control",
661 "Receive DMA Byte Count",
663 "General Status/Control"
666 static char *regname(uint32_t addr
)
669 if (addr
< PCI_IO_SIZE
) {
670 const char *r
= e100_reg
[addr
/ 4];
672 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
674 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
677 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
681 #endif /* DEBUG_EEPRO100 */
684 static uint16_t eepro100_read_status(EEPRO100State
* s
)
686 uint16_t val
= s
->status
;
687 TRACE(OTHER
, logout("val=0x%04x\n", val
));
691 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
693 TRACE(OTHER
, logout("val=0x%04x\n", val
));
698 /*****************************************************************************
702 ****************************************************************************/
705 static uint16_t eepro100_read_command(EEPRO100State
* s
)
707 uint16_t val
= 0xffff;
708 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
713 /* Commands that can be put in a command list entry. */
718 CmdMulticastList
= 3,
720 CmdTDR
= 5, /* load microcode */
724 /* And some extra flags: */
725 CmdSuspend
= 0x4000, /* Suspend after completion. */
726 CmdIntr
= 0x2000, /* Interrupt after completion. */
727 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
730 static cu_state_t
get_cu_state(EEPRO100State
* s
)
732 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
735 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
737 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
740 static ru_state_t
get_ru_state(EEPRO100State
* s
)
742 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
745 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
747 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
750 static void dump_statistics(EEPRO100State
* s
)
752 /* Dump statistical data. Most data is never changed by the emulation
753 * and always 0, so we first just copy the whole block and then those
754 * values which really matter.
755 * Number of data should check configuration!!!
757 cpu_physical_memory_write(s
->statsaddr
,
758 (uint8_t *) & s
->statistics
, s
->stats_size
);
759 stl_le_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
760 stl_le_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
761 stl_le_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
762 stl_le_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
763 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
764 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
765 //~ missing("CU dump statistical counters");
768 static void tx_command(EEPRO100State
*s
)
770 uint32_t tbd_array
= le32_to_cpu(s
->tx
.tx_desc_addr
);
771 uint16_t tcb_bytes
= (le16_to_cpu(s
->tx
.tcb_bytes
) & 0x3fff);
772 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
775 uint32_t tbd_address
= s
->cb_address
+ 0x10;
777 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
778 tbd_array
, tcb_bytes
, s
->tx
.tbd_count
));
780 if (tcb_bytes
> 2600) {
781 logout("TCB byte count too large, using 2600\n");
784 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
786 ("illegal values of TBD array address and TCB byte count!\n");
788 assert(tcb_bytes
<= sizeof(buf
));
789 while (size
< tcb_bytes
) {
790 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
791 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
792 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
795 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
796 tx_buffer_address
, tx_buffer_size
));
797 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
798 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
800 size
+= tx_buffer_size
;
802 if (tbd_array
== 0xffffffff) {
803 /* Simplified mode. Was already handled by code above. */
806 uint8_t tbd_count
= 0;
807 if (s
->has_extended_tcb_support
&& !(s
->configuration
[6] & BIT(4))) {
808 /* Extended Flexible TCB. */
809 for (; tbd_count
< 2; tbd_count
++) {
810 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
811 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
812 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
815 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
816 tx_buffer_address
, tx_buffer_size
));
817 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
818 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
820 size
+= tx_buffer_size
;
821 if (tx_buffer_el
& 1) {
826 tbd_address
= tbd_array
;
827 for (; tbd_count
< s
->tx
.tbd_count
; tbd_count
++) {
828 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
829 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
830 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
833 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
834 tx_buffer_address
, tx_buffer_size
));
835 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
836 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
838 size
+= tx_buffer_size
;
839 if (tx_buffer_el
& 1) {
844 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
845 qemu_send_packet(&s
->nic
->nc
, buf
, size
);
846 s
->statistics
.tx_good_frames
++;
847 /* Transmit with bad status would raise an CX/TNO interrupt.
848 * (82557 only). Emulation never has bad status. */
849 //~ eepro100_cx_interrupt(s);
852 static void action_command(EEPRO100State
*s
)
855 s
->cb_address
= s
->cu_base
+ s
->cu_offset
;
856 cpu_physical_memory_read(s
->cb_address
, (uint8_t *)&s
->tx
, sizeof(s
->tx
));
857 uint16_t status
= le16_to_cpu(s
->tx
.status
);
858 uint16_t command
= le16_to_cpu(s
->tx
.command
);
860 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
861 val
, status
, command
, s
->tx
.link
);
862 bool bit_el
= ((command
& 0x8000) != 0);
863 bool bit_s
= ((command
& 0x4000) != 0);
864 bool bit_i
= ((command
& 0x2000) != 0);
865 bool bit_nc
= ((command
& 0x0010) != 0);
867 //~ bool bit_sf = ((command & 0x0008) != 0);
868 uint16_t cmd
= command
& 0x0007;
869 s
->cu_offset
= le32_to_cpu(s
->tx
.link
);
875 cpu_physical_memory_read(s
->cb_address
+ 8, &s
->conf
.macaddr
.a
[0], 6);
876 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6)));
879 cpu_physical_memory_read(s
->cb_address
+ 8, &s
->configuration
[0],
880 sizeof(s
->configuration
));
881 TRACE(OTHER
, logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16)));
883 case CmdMulticastList
:
884 //~ missing("multicast list");
888 missing("CmdTx: NC = 0");
895 TRACE(OTHER
, logout("load microcode\n"));
896 /* Starting with offset 8, the command contains
897 * 64 dwords microcode which we just ignore here. */
900 missing("undefined command");
904 /* Write new status. */
905 stw_phys(s
->cb_address
, status
| 0x8000 | (success
? 0x2000 : 0));
907 /* CU completed action. */
908 eepro100_cx_interrupt(s
);
911 /* CU becomes idle. Terminate command loop. */
912 set_cu_state(s
, cu_idle
);
913 eepro100_cna_interrupt(s
);
916 /* CU becomes suspended. Terminate command loop. */
917 set_cu_state(s
, cu_suspended
);
918 eepro100_cna_interrupt(s
);
921 /* More entries in list. */
922 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
925 TRACE(OTHER
, logout("CU list empty\n"));
926 /* List is empty. Now CU is idle or suspended. */
929 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
936 if (get_cu_state(s
) != cu_idle
) {
937 /* Intel documentation says that CU must be idle for the CU
938 * start command. Intel driver for Linux also starts the CU
939 * from suspended state. */
940 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
941 //~ assert(!"wrong CU state");
943 set_cu_state(s
, cu_active
);
944 s
->cu_offset
= s
->pointer
;
948 if (get_cu_state(s
) != cu_suspended
) {
949 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
950 /* Workaround for bad Linux eepro100 driver which resumes
951 * from idle state. */
952 //~ missing("cu resume");
953 set_cu_state(s
, cu_suspended
);
955 if (get_cu_state(s
) == cu_suspended
) {
956 TRACE(OTHER
, logout("CU resuming\n"));
957 set_cu_state(s
, cu_active
);
962 /* Load dump counters address. */
963 s
->statsaddr
= s
->pointer
;
964 TRACE(OTHER
, logout("val=0x%02x (status address)\n", val
));
967 /* Dump statistical counters. */
968 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
970 stl_le_phys(s
->statsaddr
+ s
->stats_size
, 0xa005);
974 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
975 s
->cu_base
= s
->pointer
;
978 /* Dump and reset statistical counters. */
979 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
981 stl_le_phys(s
->statsaddr
+ s
->stats_size
, 0xa007);
982 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
985 /* CU static resume. */
986 missing("CU static resume");
989 missing("Undefined CU command");
993 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
1001 if (get_ru_state(s
) != ru_idle
) {
1002 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
1003 //~ assert(!"wrong RU state");
1005 set_ru_state(s
, ru_ready
);
1006 s
->ru_offset
= s
->pointer
;
1007 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
1011 if (get_ru_state(s
) != ru_suspended
) {
1012 logout("RU state is %u, should be %u\n", get_ru_state(s
),
1014 //~ assert(!"wrong RU state");
1016 set_ru_state(s
, ru_ready
);
1020 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
1021 s
->ru_base
= s
->pointer
;
1024 logout("val=0x%02x (undefined RU command)\n", val
);
1025 missing("Undefined SU command");
1029 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
1031 eepro100_ru_command(s
, val
& 0x0f);
1032 eepro100_cu_command(s
, val
& 0xf0);
1034 TRACE(OTHER
, logout("val=0x%02x\n", val
));
1036 /* Clear command byte after command was accepted. */
1040 /*****************************************************************************
1044 ****************************************************************************/
1046 #define EEPROM_CS 0x02
1047 #define EEPROM_SK 0x01
1048 #define EEPROM_DI 0x04
1049 #define EEPROM_DO 0x08
1051 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
1054 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
1055 if (eeprom93xx_read(s
->eeprom
)) {
1060 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
1064 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
1066 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
1068 /* mask unwriteable bits */
1069 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1071 int eecs
= ((val
& EEPROM_CS
) != 0);
1072 int eesk
= ((val
& EEPROM_SK
) != 0);
1073 int eedi
= ((val
& EEPROM_DI
) != 0);
1074 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
1077 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
1079 s
->pointer
= le32_to_cpu(val
);
1080 TRACE(OTHER
, logout("val=0x%08x\n", val
));
1083 /*****************************************************************************
1087 ****************************************************************************/
1089 #if defined(DEBUG_EEPRO100)
1090 static const char * const mdi_op_name
[] = {
1097 static const char * const mdi_reg_name
[] = {
1100 "PHY Identification (Word 1)",
1101 "PHY Identification (Word 2)",
1102 "Auto-Negotiation Advertisement",
1103 "Auto-Negotiation Link Partner Ability",
1104 "Auto-Negotiation Expansion"
1107 static const char *reg2name(uint8_t reg
)
1109 static char buffer
[10];
1110 const char *p
= buffer
;
1111 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
1112 p
= mdi_reg_name
[reg
];
1114 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
1118 #endif /* DEBUG_EEPRO100 */
1120 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
1123 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
1125 #ifdef DEBUG_EEPRO100
1126 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1127 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1128 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1129 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1130 uint16_t data
= (val
& BITS(15, 0));
1132 /* Emulation takes no time to finish MDI transaction. */
1134 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1135 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1136 reg2name(reg
), data
));
1140 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
1142 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1143 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1144 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1145 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1146 uint16_t data
= (val
& BITS(15, 0));
1147 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1148 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1150 /* Unsupported PHY address. */
1151 //~ logout("phy must be 1 but is %u\n", phy);
1153 } else if (opcode
!= 1 && opcode
!= 2) {
1154 /* Unsupported opcode. */
1155 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1157 } else if (reg
> 6) {
1158 /* Unsupported register. */
1159 logout("register must be 0...6 but is %u\n", reg
);
1162 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1163 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1164 reg2name(reg
), data
));
1168 case 0: /* Control Register */
1169 if (data
& 0x8000) {
1170 /* Reset status and control registers to default. */
1171 s
->mdimem
[0] = eepro100_mdi_default
[0];
1172 s
->mdimem
[1] = eepro100_mdi_default
[1];
1173 data
= s
->mdimem
[reg
];
1175 /* Restart Auto Configuration = Normal Operation */
1179 case 1: /* Status Register */
1180 missing("not writable");
1181 data
= s
->mdimem
[reg
];
1183 case 2: /* PHY Identification Register (Word 1) */
1184 case 3: /* PHY Identification Register (Word 2) */
1185 missing("not implemented");
1187 case 4: /* Auto-Negotiation Advertisement Register */
1188 case 5: /* Auto-Negotiation Link Partner Ability Register */
1190 case 6: /* Auto-Negotiation Expansion Register */
1192 missing("not implemented");
1194 s
->mdimem
[reg
] = data
;
1195 } else if (opcode
== 2) {
1198 case 0: /* Control Register */
1199 if (data
& 0x8000) {
1200 /* Reset status and control registers to default. */
1201 s
->mdimem
[0] = eepro100_mdi_default
[0];
1202 s
->mdimem
[1] = eepro100_mdi_default
[1];
1205 case 1: /* Status Register */
1206 s
->mdimem
[reg
] |= 0x0020;
1208 case 2: /* PHY Identification Register (Word 1) */
1209 case 3: /* PHY Identification Register (Word 2) */
1210 case 4: /* Auto-Negotiation Advertisement Register */
1212 case 5: /* Auto-Negotiation Link Partner Ability Register */
1213 s
->mdimem
[reg
] = 0x41fe;
1215 case 6: /* Auto-Negotiation Expansion Register */
1216 s
->mdimem
[reg
] = 0x0001;
1219 data
= s
->mdimem
[reg
];
1221 /* Emulation takes no time to finish MDI transaction.
1222 * Set MDI bit in SCB status register. */
1223 s
->mem
[SCBAck
] |= 0x08;
1226 eepro100_mdi_interrupt(s
);
1229 val
= (val
& 0xffff0000) + data
;
1230 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1233 /*****************************************************************************
1237 ****************************************************************************/
1239 #define PORT_SOFTWARE_RESET 0
1240 #define PORT_SELFTEST 1
1241 #define PORT_SELECTIVE_RESET 2
1243 #define PORT_SELECTION_MASK 3
1246 uint32_t st_sign
; /* Self Test Signature */
1247 uint32_t st_result
; /* Self Test Results */
1248 } eepro100_selftest_t
;
1250 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1255 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1257 val
= le32_to_cpu(val
);
1258 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1259 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1260 switch (selection
) {
1261 case PORT_SOFTWARE_RESET
:
1265 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1266 eepro100_selftest_t data
;
1267 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1268 data
.st_sign
= 0xffffffff;
1270 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1272 case PORT_SELECTIVE_RESET
:
1273 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1274 nic_selective_reset(s
);
1277 logout("val=0x%08x\n", val
);
1278 missing("unknown port selection");
1282 /*****************************************************************************
1284 * General hardware emulation.
1286 ****************************************************************************/
1288 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1291 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1292 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1297 //~ val = eepro100_read_status(s);
1298 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1301 //~ val = eepro100_read_status(s);
1302 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1305 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1306 //~ val = eepro100_read_command(s);
1309 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1312 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1315 val
= eepro100_read_eeprom(s
);
1317 case 0x1b: /* PMDR (power management driver register) */
1319 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1321 case 0x1d: /* general status register */
1322 /* 100 Mbps full duplex, valid link */
1324 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1327 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1328 missing("unknown byte read");
1333 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1336 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1337 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1342 //~ val = eepro100_read_status(s);
1344 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1347 val
= eepro100_read_eeprom(s
);
1348 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1351 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1352 missing("unknown word read");
1357 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1360 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1361 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1366 //~ val = eepro100_read_status(s);
1367 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1370 //~ val = eepro100_read_pointer(s);
1371 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1374 val
= eepro100_read_port(s
);
1375 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1378 val
= eepro100_read_mdi(s
);
1381 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1382 missing("unknown longword read");
1387 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1389 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1390 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1393 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1397 //~ eepro100_write_status(s, val);
1400 eepro100_acknowledge(s
);
1403 eepro100_write_command(s
, val
);
1407 eepro100_swi_interrupt(s
);
1409 eepro100_interrupt(s
, 0);
1412 case SCBFlow
: /* does not exist on 82557 */
1416 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1419 eepro100_write_eeprom(s
->eeprom
, val
);
1422 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1423 missing("unknown byte write");
1427 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1429 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1430 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1433 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1437 //~ eepro100_write_status(s, val);
1438 eepro100_acknowledge(s
);
1441 eepro100_write_command(s
, val
);
1442 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1445 eepro100_write_eeprom(s
->eeprom
, val
);
1448 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1449 missing("unknown word write");
1453 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1455 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1456 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1461 eepro100_write_pointer(s
, val
);
1464 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1465 eepro100_write_port(s
, val
);
1468 eepro100_write_mdi(s
, val
);
1471 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1472 missing("unknown longword write");
1476 /*****************************************************************************
1480 ****************************************************************************/
1482 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1484 EEPRO100State
*s
= opaque
;
1485 //~ logout("addr=%s\n", regname(addr));
1486 return eepro100_read1(s
, addr
- s
->region
[1]);
1489 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1491 EEPRO100State
*s
= opaque
;
1492 return eepro100_read2(s
, addr
- s
->region
[1]);
1495 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1497 EEPRO100State
*s
= opaque
;
1498 return eepro100_read4(s
, addr
- s
->region
[1]);
1501 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1503 EEPRO100State
*s
= opaque
;
1504 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1505 eepro100_write1(s
, addr
- s
->region
[1], val
);
1508 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1510 EEPRO100State
*s
= opaque
;
1511 eepro100_write2(s
, addr
- s
->region
[1], val
);
1514 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1516 EEPRO100State
*s
= opaque
;
1517 eepro100_write4(s
, addr
- s
->region
[1], val
);
1520 /***********************************************************/
1521 /* PCI EEPRO100 definitions */
1523 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1524 pcibus_t addr
, pcibus_t size
, int type
)
1526 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1528 TRACE(OTHER
, logout("region %d, addr=0x%08"FMT_PCIBUS
", "
1529 "size=0x%08"FMT_PCIBUS
", type=%d\n",
1530 region_num
, addr
, size
, type
));
1532 assert(region_num
== 1);
1533 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1534 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1535 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1536 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1537 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1538 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1540 s
->region
[region_num
] = addr
;
1543 /*****************************************************************************
1545 * Memory mapped I/O.
1547 ****************************************************************************/
1549 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1551 EEPRO100State
*s
= opaque
;
1552 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1553 eepro100_write1(s
, addr
, val
);
1556 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1558 EEPRO100State
*s
= opaque
;
1559 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1560 eepro100_write2(s
, addr
, val
);
1563 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1565 EEPRO100State
*s
= opaque
;
1566 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1567 eepro100_write4(s
, addr
, val
);
1570 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1572 EEPRO100State
*s
= opaque
;
1573 //~ logout("addr=%s\n", regname(addr));
1574 return eepro100_read1(s
, addr
);
1577 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1579 EEPRO100State
*s
= opaque
;
1580 //~ logout("addr=%s\n", regname(addr));
1581 return eepro100_read2(s
, addr
);
1584 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1586 EEPRO100State
*s
= opaque
;
1587 //~ logout("addr=%s\n", regname(addr));
1588 return eepro100_read4(s
, addr
);
1591 static CPUWriteMemoryFunc
* const pci_mmio_write
[] = {
1597 static CPUReadMemoryFunc
* const pci_mmio_read
[] = {
1603 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1604 pcibus_t addr
, pcibus_t size
, int type
)
1606 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1608 TRACE(OTHER
, logout("region %d, addr=0x%08"FMT_PCIBUS
", "
1609 "size=0x%08"FMT_PCIBUS
", type=%d\n",
1610 region_num
, addr
, size
, type
));
1612 if (region_num
== 0) {
1613 /* Map control / status registers. */
1614 cpu_register_physical_memory(addr
, size
, s
->mmio_index
);
1615 s
->region
[region_num
] = addr
;
1619 static int nic_can_receive(VLANClientState
*nc
)
1621 EEPRO100State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
1622 TRACE(RXTX
, logout("%p\n", s
));
1623 return get_ru_state(s
) == ru_ready
;
1624 //~ return !eepro100_buffer_full(s);
1627 static ssize_t
nic_receive(VLANClientState
*nc
, const uint8_t * buf
, size_t size
)
1630 * - Magic packets should set bit 30 in power management driver register.
1631 * - Interesting packets should set bit 29 in power management driver register.
1633 EEPRO100State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
1634 uint16_t rfd_status
= 0xa000;
1635 static const uint8_t broadcast_macaddr
[6] =
1636 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1638 /* TODO: check multiple IA bit. */
1639 if (s
->configuration
[20] & BIT(6)) {
1640 missing("Multiple IA bit");
1644 if (s
->configuration
[8] & 0x80) {
1645 /* CSMA is disabled. */
1646 logout("%p received while CSMA is disabled\n", s
);
1648 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1649 /* Short frame and configuration byte 7/0 (discard short receive) set:
1650 * Short frame is discarded */
1651 logout("%p received short frame (%zu byte)\n", s
, size
);
1652 s
->statistics
.rx_short_frame_errors
++;
1654 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1655 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1656 * Long frames are discarded. */
1657 logout("%p received long frame (%zu byte), ignored\n", s
, size
);
1659 } else if (memcmp(buf
, s
->conf
.macaddr
.a
, 6) == 0) { // !!!
1660 /* Frame matches individual address. */
1661 /* TODO: check configuration byte 15/4 (ignore U/L). */
1662 TRACE(RXTX
, logout("%p received frame for me, len=%zu\n", s
, size
));
1663 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1664 /* Broadcast frame. */
1665 TRACE(RXTX
, logout("%p received broadcast, len=%zu\n", s
, size
));
1666 rfd_status
|= 0x0002;
1667 } else if (buf
[0] & 0x01) { // !!!
1668 /* Multicast frame. */
1669 TRACE(RXTX
, logout("%p received multicast, len=%zu\n", s
, size
));
1670 /* TODO: check multicast all bit. */
1671 if (s
->configuration
[21] & BIT(3)) {
1672 missing("Multicast All bit");
1674 int mcast_idx
= compute_mcast_idx(buf
);
1675 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1678 rfd_status
|= 0x0002;
1679 } else if (s
->configuration
[15] & 1) {
1680 /* Promiscuous: receive all. */
1681 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%zu\n", s
, size
));
1682 rfd_status
|= 0x0004;
1684 TRACE(RXTX
, logout("%p received frame, ignored, len=%zu,%s\n", s
, size
,
1685 nic_dump(buf
, size
)));
1689 if (get_ru_state(s
) != ru_ready
) {
1690 /* No resources available. */
1691 logout("no resources, state=%u\n", get_ru_state(s
));
1692 s
->statistics
.rx_resource_errors
++;
1693 //~ assert(!"no resources");
1697 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1699 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1700 offsetof(eepro100_rx_t
, packet
));
1701 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1702 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1704 if (size
> rfd_size
) {
1705 logout("Receive buffer (%" PRId16
" bytes) too small for data "
1706 "(%zu bytes); data truncated\n", rfd_size
, size
);
1710 rfd_status
|= 0x0080;
1712 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1713 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1714 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1716 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1717 /* Early receive interrupt not supported. */
1718 //~ eepro100_er_interrupt(s);
1719 /* Receive CRC Transfer not supported. */
1720 if (s
->configuration
[18] & 4) {
1721 missing("Receive CRC Transfer");
1724 /* TODO: check stripping enable bit. */
1725 //~ assert(!(s->configuration[17] & 1));
1726 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1727 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1728 s
->statistics
.rx_good_frames
++;
1729 eepro100_fr_interrupt(s
);
1730 s
->ru_offset
= le32_to_cpu(rx
.link
);
1731 if (rfd_command
& 0x8000) {
1732 /* EL bit is set, so this was the last frame. */
1733 logout("receive: Running out of frames\n");
1734 set_ru_state(s
, ru_suspended
);
1736 if (rfd_command
& 0x4000) {
1738 set_ru_state(s
, ru_suspended
);
1743 static const VMStateDescription vmstate_eepro100
= {
1745 .minimum_version_id
= 2,
1746 .minimum_version_id_old
= 2,
1747 .fields
= (VMStateField
[]) {
1748 VMSTATE_PCI_DEVICE(dev
, EEPRO100State
),
1750 VMSTATE_BUFFER(mult
, EEPRO100State
),
1751 VMSTATE_BUFFER(mem
, EEPRO100State
),
1752 /* Save all members of struct between scb_stat and mem. */
1753 VMSTATE_UINT8(scb_stat
, EEPRO100State
),
1754 VMSTATE_UINT8(int_stat
, EEPRO100State
),
1755 VMSTATE_UNUSED(3*4),
1756 VMSTATE_MACADDR(conf
.macaddr
, EEPRO100State
),
1757 VMSTATE_UNUSED(19*4),
1758 VMSTATE_UINT16_ARRAY(mdimem
, EEPRO100State
, 32),
1759 /* The eeprom should be saved and restored by its own routines. */
1760 VMSTATE_UINT32(device
, EEPRO100State
),
1761 /* TODO check device. */
1762 VMSTATE_UINT32(pointer
, EEPRO100State
),
1763 VMSTATE_UINT32(cu_base
, EEPRO100State
),
1764 VMSTATE_UINT32(cu_offset
, EEPRO100State
),
1765 VMSTATE_UINT32(ru_base
, EEPRO100State
),
1766 VMSTATE_UINT32(ru_offset
, EEPRO100State
),
1767 VMSTATE_UINT32(statsaddr
, EEPRO100State
),
1768 /* Save eepro100_stats_t statistics. */
1769 VMSTATE_UINT32(statistics
.tx_good_frames
, EEPRO100State
),
1770 VMSTATE_UINT32(statistics
.tx_max_collisions
, EEPRO100State
),
1771 VMSTATE_UINT32(statistics
.tx_late_collisions
, EEPRO100State
),
1772 VMSTATE_UINT32(statistics
.tx_underruns
, EEPRO100State
),
1773 VMSTATE_UINT32(statistics
.tx_lost_crs
, EEPRO100State
),
1774 VMSTATE_UINT32(statistics
.tx_deferred
, EEPRO100State
),
1775 VMSTATE_UINT32(statistics
.tx_single_collisions
, EEPRO100State
),
1776 VMSTATE_UINT32(statistics
.tx_multiple_collisions
, EEPRO100State
),
1777 VMSTATE_UINT32(statistics
.tx_total_collisions
, EEPRO100State
),
1778 VMSTATE_UINT32(statistics
.rx_good_frames
, EEPRO100State
),
1779 VMSTATE_UINT32(statistics
.rx_crc_errors
, EEPRO100State
),
1780 VMSTATE_UINT32(statistics
.rx_alignment_errors
, EEPRO100State
),
1781 VMSTATE_UINT32(statistics
.rx_resource_errors
, EEPRO100State
),
1782 VMSTATE_UINT32(statistics
.rx_overrun_errors
, EEPRO100State
),
1783 VMSTATE_UINT32(statistics
.rx_cdt_errors
, EEPRO100State
),
1784 VMSTATE_UINT32(statistics
.rx_short_frame_errors
, EEPRO100State
),
1785 VMSTATE_UINT32(statistics
.fc_xmt_pause
, EEPRO100State
),
1786 VMSTATE_UINT32(statistics
.fc_rcv_pause
, EEPRO100State
),
1787 VMSTATE_UINT32(statistics
.fc_rcv_unsupported
, EEPRO100State
),
1788 VMSTATE_UINT16(statistics
.xmt_tco_frames
, EEPRO100State
),
1789 VMSTATE_UINT16(statistics
.rcv_tco_frames
, EEPRO100State
),
1791 VMSTATE_UINT16(status
, EEPRO100State
),
1793 /* Configuration bytes. */
1794 VMSTATE_BUFFER(configuration
, EEPRO100State
),
1795 VMSTATE_END_OF_LIST()
1799 static void nic_cleanup(VLANClientState
*nc
)
1801 EEPRO100State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
1806 static int pci_nic_uninit(PCIDevice
*pci_dev
)
1808 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1810 cpu_unregister_io_memory(s
->mmio_index
);
1811 vmstate_unregister(s
->vmstate
, s
);
1812 eeprom93xx_free(s
->eeprom
);
1813 qemu_del_vlan_client(&s
->nic
->nc
);
1817 static NetClientInfo net_eepro100_info
= {
1818 .type
= NET_CLIENT_TYPE_NIC
,
1819 .size
= sizeof(NICState
),
1820 .can_receive
= nic_can_receive
,
1821 .receive
= nic_receive
,
1822 .cleanup
= nic_cleanup
,
1825 static int nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1827 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1829 TRACE(OTHER
, logout("\n"));
1835 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1836 * i82559 and later support 64 or 256 word EEPROM. */
1837 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1839 /* Handler for memory-mapped I/O */
1841 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1843 pci_register_bar(&s
->dev
, 0, PCI_MEM_SIZE
,
1844 PCI_BASE_ADDRESS_SPACE_MEMORY
|
1845 PCI_BASE_ADDRESS_MEM_PREFETCH
, pci_mmio_map
);
1846 pci_register_bar(&s
->dev
, 1, PCI_IO_SIZE
, PCI_BASE_ADDRESS_SPACE_IO
,
1848 pci_register_bar(&s
->dev
, 2, PCI_FLASH_SIZE
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1851 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1852 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1853 assert(s
->region
[1] == 0);
1857 s
->nic
= qemu_new_nic(&net_eepro100_info
, &s
->conf
,
1858 pci_dev
->qdev
.info
->name
, pci_dev
->qdev
.id
, s
);
1860 qemu_format_nic_info_str(&s
->nic
->nc
, s
->conf
.macaddr
.a
);
1861 TRACE(OTHER
, logout("%s\n", s
->nic
->nc
.info_str
));
1863 qemu_register_reset(nic_reset
, s
);
1865 s
->vmstate
= qemu_malloc(sizeof(vmstate_eepro100
));
1866 memcpy(s
->vmstate
, &vmstate_eepro100
, sizeof(vmstate_eepro100
));
1867 s
->vmstate
->name
= s
->nic
->nc
.model
;
1868 vmstate_register(-1, s
->vmstate
, s
);
1873 static int pci_i82550_init(PCIDevice
*pci_dev
)
1875 return nic_init(pci_dev
, i82550
);
1878 static int pci_i82551_init(PCIDevice
*pci_dev
)
1880 return nic_init(pci_dev
, i82551
);
1883 static int pci_i82557a_init(PCIDevice
*pci_dev
)
1885 return nic_init(pci_dev
, i82557A
);
1888 static int pci_i82557b_init(PCIDevice
*pci_dev
)
1890 return nic_init(pci_dev
, i82557B
);
1893 static int pci_i82557c_init(PCIDevice
*pci_dev
)
1895 return nic_init(pci_dev
, i82557C
);
1898 static int pci_i82558a_init(PCIDevice
*pci_dev
)
1900 return nic_init(pci_dev
, i82558A
);
1903 static int pci_i82558b_init(PCIDevice
*pci_dev
)
1905 return nic_init(pci_dev
, i82558B
);
1908 static int pci_i82559a_init(PCIDevice
*pci_dev
)
1910 return nic_init(pci_dev
, i82559A
);
1913 static int pci_i82559b_init(PCIDevice
*pci_dev
)
1915 return nic_init(pci_dev
, i82559B
);
1918 static int pci_i82559c_init(PCIDevice
*pci_dev
)
1920 return nic_init(pci_dev
, i82559C
);
1923 static int pci_i82559er_init(PCIDevice
*pci_dev
)
1925 return nic_init(pci_dev
, i82559ER
);
1928 static int pci_i82562_init(PCIDevice
*pci_dev
)
1930 return nic_init(pci_dev
, i82562
);
1933 static PCIDeviceInfo eepro100_info
[] = {
1935 .qdev
.name
= "i82550",
1936 .qdev
.size
= sizeof(EEPRO100State
),
1937 .init
= pci_i82550_init
,
1938 .exit
= pci_nic_uninit
,
1939 .qdev
.props
= (Property
[]) {
1940 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1941 DEFINE_PROP_END_OF_LIST(),
1944 .qdev
.name
= "i82551",
1945 .qdev
.size
= sizeof(EEPRO100State
),
1946 .init
= pci_i82551_init
,
1947 .exit
= pci_nic_uninit
,
1948 .qdev
.props
= (Property
[]) {
1949 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1950 DEFINE_PROP_END_OF_LIST(),
1953 .qdev
.name
= "i82557a",
1954 .qdev
.size
= sizeof(EEPRO100State
),
1955 .init
= pci_i82557a_init
,
1956 .exit
= pci_nic_uninit
,
1957 .qdev
.props
= (Property
[]) {
1958 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1959 DEFINE_PROP_END_OF_LIST(),
1962 .qdev
.name
= "i82557b",
1963 .qdev
.size
= sizeof(EEPRO100State
),
1964 .init
= pci_i82557b_init
,
1965 .exit
= pci_nic_uninit
,
1966 .qdev
.props
= (Property
[]) {
1967 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1968 DEFINE_PROP_END_OF_LIST(),
1971 .qdev
.name
= "i82557c",
1972 .qdev
.size
= sizeof(EEPRO100State
),
1973 .init
= pci_i82557c_init
,
1974 .exit
= pci_nic_uninit
,
1975 .qdev
.props
= (Property
[]) {
1976 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1977 DEFINE_PROP_END_OF_LIST(),
1980 .qdev
.name
= "i82558a",
1981 .qdev
.size
= sizeof(EEPRO100State
),
1982 .init
= pci_i82558a_init
,
1983 .exit
= pci_nic_uninit
,
1984 .qdev
.props
= (Property
[]) {
1985 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1986 DEFINE_PROP_END_OF_LIST(),
1989 .qdev
.name
= "i82558b",
1990 .qdev
.size
= sizeof(EEPRO100State
),
1991 .init
= pci_i82558b_init
,
1992 .exit
= pci_nic_uninit
,
1993 .qdev
.props
= (Property
[]) {
1994 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
1995 DEFINE_PROP_END_OF_LIST(),
1998 .qdev
.name
= "i82559a",
1999 .qdev
.size
= sizeof(EEPRO100State
),
2000 .init
= pci_i82559a_init
,
2001 .exit
= pci_nic_uninit
,
2002 .qdev
.props
= (Property
[]) {
2003 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2004 DEFINE_PROP_END_OF_LIST(),
2007 .qdev
.name
= "i82559b",
2008 .qdev
.size
= sizeof(EEPRO100State
),
2009 .init
= pci_i82559b_init
,
2010 .exit
= pci_nic_uninit
,
2011 .qdev
.props
= (Property
[]) {
2012 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2013 DEFINE_PROP_END_OF_LIST(),
2016 .qdev
.name
= "i82559c",
2017 .qdev
.size
= sizeof(EEPRO100State
),
2018 .init
= pci_i82559c_init
,
2019 .exit
= pci_nic_uninit
,
2020 .qdev
.props
= (Property
[]) {
2021 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2022 DEFINE_PROP_END_OF_LIST(),
2025 .qdev
.name
= "i82559er",
2026 .qdev
.size
= sizeof(EEPRO100State
),
2027 .init
= pci_i82559er_init
,
2028 .exit
= pci_nic_uninit
,
2029 .romfile
= "pxe-i82559er.bin",
2030 .qdev
.props
= (Property
[]) {
2031 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2032 DEFINE_PROP_END_OF_LIST(),
2035 .qdev
.name
= "i82562",
2036 .qdev
.size
= sizeof(EEPRO100State
),
2037 .init
= pci_i82562_init
,
2038 .exit
= pci_nic_uninit
,
2039 .qdev
.props
= (Property
[]) {
2040 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2041 DEFINE_PROP_END_OF_LIST(),
2048 static void eepro100_register_devices(void)
2050 pci_qdev_register_many(eepro100_info
);
2053 device_init(eepro100_register_devices
)