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s390: remove misleading comment
[qemu/ar7.git] / target-xtensa / translate.c
blob9eac56e2a5bc42909e1d75f5f133ac7fafcf8bbd
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41
42 #include "exec/helper-proto.h"
43 #include "exec/helper-gen.h"
44
45 #include "trace-tcg.h"
46 #include "exec/log.h"
47
48
49 typedef struct DisasContext {
50 const XtensaConfig *config;
51 TranslationBlock *tb;
52 uint32_t pc;
53 uint32_t next_pc;
54 int cring;
55 int ring;
56 uint32_t lbeg;
57 uint32_t lend;
58 TCGv_i32 litbase;
59 int is_jmp;
60 int singlestep_enabled;
61
62 bool sar_5bit;
63 bool sar_m32_5bit;
64 bool sar_m32_allocated;
65 TCGv_i32 sar_m32;
66
67 uint32_t ccount_delta;
68 unsigned window;
69
70 bool debug;
71 bool icount;
72 TCGv_i32 next_icount;
73
74 unsigned cpenable;
75 } DisasContext;
76
77 static TCGv_env cpu_env;
78 static TCGv_i32 cpu_pc;
79 static TCGv_i32 cpu_R[16];
80 static TCGv_i32 cpu_FR[16];
81 static TCGv_i32 cpu_SR[256];
82 static TCGv_i32 cpu_UR[256];
83
84 #include "exec/gen-icount.h"
85
86 typedef struct XtensaReg {
87 const char *name;
88 uint64_t opt_bits;
89 enum {
90 SR_R = 1,
91 SR_W = 2,
92 SR_X = 4,
93 SR_RW = 3,
94 SR_RWX = 7,
95 } access;
96 } XtensaReg;
97
98 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
99 .name = (regname), \
100 .opt_bits = XTENSA_OPTION_BIT(opt), \
101 .access = (acc), \
102 }
103
104 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
105
106 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
107 .name = (regname), \
108 .opt_bits = (opt), \
109 .access = (acc), \
110 }
111
112 #define XTENSA_REG_BITS(regname, opt) \
113 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
114
115 static const XtensaReg sregnames[256] = {
116 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
117 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
118 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
119 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
120 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
121 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
122 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
123 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
124 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
125 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
126 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
127 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
128 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
129 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
130 [WINDOW_START] = XTENSA_REG("WINDOW_START",
131 XTENSA_OPTION_WINDOWED_REGISTER),
132 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
133 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
134 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
135 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
136 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
137 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
138 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
139 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
140 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
141 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
142 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
143 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
144 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
145 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
146 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
147 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
154 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
161 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
162 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
165 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
166 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
168 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
170 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
172 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
174 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
175 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
176 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
177 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
178 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
179 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
180 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
181 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
182 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
183 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
184 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
185 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
186 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
187 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
188 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
189 XTENSA_OPTION_TIMER_INTERRUPT),
190 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
191 XTENSA_OPTION_TIMER_INTERRUPT),
192 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
193 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
194 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
195 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
196 };
197
198 static const XtensaReg uregnames[256] = {
199 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
200 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
201 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
202 };
203
204 void xtensa_translate_init(void)
205 {
206 static const char * const regnames[] = {
207 "ar0", "ar1", "ar2", "ar3",
208 "ar4", "ar5", "ar6", "ar7",
209 "ar8", "ar9", "ar10", "ar11",
210 "ar12", "ar13", "ar14", "ar15",
211 };
212 static const char * const fregnames[] = {
213 "f0", "f1", "f2", "f3",
214 "f4", "f5", "f6", "f7",
215 "f8", "f9", "f10", "f11",
216 "f12", "f13", "f14", "f15",
217 };
218 int i;
219
220 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
221 cpu_pc = tcg_global_mem_new_i32(cpu_env,
222 offsetof(CPUXtensaState, pc), "pc");
223
224 for (i = 0; i < 16; i++) {
225 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
226 offsetof(CPUXtensaState, regs[i]),
227 regnames[i]);
228 }
229
230 for (i = 0; i < 16; i++) {
231 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
232 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
233 fregnames[i]);
234 }
235
236 for (i = 0; i < 256; ++i) {
237 if (sregnames[i].name) {
238 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
239 offsetof(CPUXtensaState, sregs[i]),
240 sregnames[i].name);
241 }
242 }
243
244 for (i = 0; i < 256; ++i) {
245 if (uregnames[i].name) {
246 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
247 offsetof(CPUXtensaState, uregs[i]),
248 uregnames[i].name);
249 }
250 }
251 }
252
253 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
254 {
255 return xtensa_option_bits_enabled(dc->config, opt);
256 }
257
258 static inline bool option_enabled(DisasContext *dc, int opt)
259 {
260 return xtensa_option_enabled(dc->config, opt);
261 }
262
263 static void init_litbase(DisasContext *dc)
264 {
265 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
266 dc->litbase = tcg_temp_local_new_i32();
267 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
268 }
269 }
270
271 static void reset_litbase(DisasContext *dc)
272 {
273 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
274 tcg_temp_free(dc->litbase);
275 }
276 }
277
278 static void init_sar_tracker(DisasContext *dc)
279 {
280 dc->sar_5bit = false;
281 dc->sar_m32_5bit = false;
282 dc->sar_m32_allocated = false;
283 }
284
285 static void reset_sar_tracker(DisasContext *dc)
286 {
287 if (dc->sar_m32_allocated) {
288 tcg_temp_free(dc->sar_m32);
289 }
290 }
291
292 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
293 {
294 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
295 if (dc->sar_m32_5bit) {
296 tcg_gen_discard_i32(dc->sar_m32);
297 }
298 dc->sar_5bit = true;
299 dc->sar_m32_5bit = false;
300 }
301
302 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
303 {
304 TCGv_i32 tmp = tcg_const_i32(32);
305 if (!dc->sar_m32_allocated) {
306 dc->sar_m32 = tcg_temp_local_new_i32();
307 dc->sar_m32_allocated = true;
308 }
309 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
310 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
311 dc->sar_5bit = false;
312 dc->sar_m32_5bit = true;
313 tcg_temp_free(tmp);
314 }
315
316 static void gen_advance_ccount(DisasContext *dc)
317 {
318 if (dc->ccount_delta > 0) {
319 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
320 gen_helper_advance_ccount(cpu_env, tmp);
321 tcg_temp_free(tmp);
322 }
323 dc->ccount_delta = 0;
324 }
325
326 static void gen_exception(DisasContext *dc, int excp)
327 {
328 TCGv_i32 tmp = tcg_const_i32(excp);
329 gen_advance_ccount(dc);
330 gen_helper_exception(cpu_env, tmp);
331 tcg_temp_free(tmp);
332 }
333
334 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
335 {
336 TCGv_i32 tpc = tcg_const_i32(dc->pc);
337 TCGv_i32 tcause = tcg_const_i32(cause);
338 gen_advance_ccount(dc);
339 gen_helper_exception_cause(cpu_env, tpc, tcause);
340 tcg_temp_free(tpc);
341 tcg_temp_free(tcause);
342 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
343 cause == SYSCALL_CAUSE) {
344 dc->is_jmp = DISAS_UPDATE;
345 }
346 }
347
348 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
349 TCGv_i32 vaddr)
350 {
351 TCGv_i32 tpc = tcg_const_i32(dc->pc);
352 TCGv_i32 tcause = tcg_const_i32(cause);
353 gen_advance_ccount(dc);
354 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
355 tcg_temp_free(tpc);
356 tcg_temp_free(tcause);
357 }
358
359 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
360 {
361 TCGv_i32 tpc = tcg_const_i32(dc->pc);
362 TCGv_i32 tcause = tcg_const_i32(cause);
363 gen_advance_ccount(dc);
364 gen_helper_debug_exception(cpu_env, tpc, tcause);
365 tcg_temp_free(tpc);
366 tcg_temp_free(tcause);
367 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
368 dc->is_jmp = DISAS_UPDATE;
369 }
370 }
371
372 static bool gen_check_privilege(DisasContext *dc)
373 {
374 if (dc->cring) {
375 gen_exception_cause(dc, PRIVILEGED_CAUSE);
376 dc->is_jmp = DISAS_UPDATE;
377 return false;
378 }
379 return true;
380 }
381
382 static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
383 {
384 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
385 !(dc->cpenable & (1 << cp))) {
386 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
387 dc->is_jmp = DISAS_UPDATE;
388 return false;
389 }
390 return true;
391 }
392
393 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
394 {
395 tcg_gen_mov_i32(cpu_pc, dest);
396 gen_advance_ccount(dc);
397 if (dc->icount) {
398 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
399 }
400 if (dc->singlestep_enabled) {
401 gen_exception(dc, EXCP_DEBUG);
402 } else {
403 if (slot >= 0) {
404 tcg_gen_goto_tb(slot);
405 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
406 } else {
407 tcg_gen_exit_tb(0);
408 }
409 }
410 dc->is_jmp = DISAS_UPDATE;
411 }
412
413 static void gen_jump(DisasContext *dc, TCGv dest)
414 {
415 gen_jump_slot(dc, dest, -1);
416 }
417
418 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
419 {
420 TCGv_i32 tmp = tcg_const_i32(dest);
421 #ifndef CONFIG_USER_ONLY
422 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
423 slot = -1;
424 }
425 #endif
426 gen_jump_slot(dc, tmp, slot);
427 tcg_temp_free(tmp);
428 }
429
430 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
431 int slot)
432 {
433 TCGv_i32 tcallinc = tcg_const_i32(callinc);
434
435 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
436 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
437 tcg_temp_free(tcallinc);
438 tcg_gen_movi_i32(cpu_R[callinc << 2],
439 (callinc << 30) | (dc->next_pc & 0x3fffffff));
440 gen_jump_slot(dc, dest, slot);
441 }
442
443 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
444 {
445 gen_callw_slot(dc, callinc, dest, -1);
446 }
447
448 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
449 {
450 TCGv_i32 tmp = tcg_const_i32(dest);
451 #ifndef CONFIG_USER_ONLY
452 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
453 slot = -1;
454 }
455 #endif
456 gen_callw_slot(dc, callinc, tmp, slot);
457 tcg_temp_free(tmp);
458 }
459
460 static bool gen_check_loop_end(DisasContext *dc, int slot)
461 {
462 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
463 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
464 dc->next_pc == dc->lend) {
465 TCGLabel *label = gen_new_label();
466
467 gen_advance_ccount(dc);
468 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
469 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
470 gen_jumpi(dc, dc->lbeg, slot);
471 gen_set_label(label);
472 gen_jumpi(dc, dc->next_pc, -1);
473 return true;
474 }
475 return false;
476 }
477
478 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
479 {
480 if (!gen_check_loop_end(dc, slot)) {
481 gen_jumpi(dc, dc->next_pc, slot);
482 }
483 }
484
485 static void gen_brcond(DisasContext *dc, TCGCond cond,
486 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
487 {
488 TCGLabel *label = gen_new_label();
489
490 gen_advance_ccount(dc);
491 tcg_gen_brcond_i32(cond, t0, t1, label);
492 gen_jumpi_check_loop_end(dc, 0);
493 gen_set_label(label);
494 gen_jumpi(dc, dc->pc + offset, 1);
495 }
496
497 static void gen_brcondi(DisasContext *dc, TCGCond cond,
498 TCGv_i32 t0, uint32_t t1, uint32_t offset)
499 {
500 TCGv_i32 tmp = tcg_const_i32(t1);
501 gen_brcond(dc, cond, t0, tmp, offset);
502 tcg_temp_free(tmp);
503 }
504
505 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
506 {
507 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
508 if (sregnames[sr].name) {
509 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
510 } else {
511 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
512 }
513 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
514 return false;
515 } else if (!(sregnames[sr].access & access)) {
516 static const char * const access_text[] = {
517 [SR_R] = "rsr",
518 [SR_W] = "wsr",
519 [SR_X] = "xsr",
520 };
521 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
522 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
523 access_text[access]);
524 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
525 return false;
526 }
527 return true;
528 }
529
530 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
531 {
532 gen_advance_ccount(dc);
533 tcg_gen_mov_i32(d, cpu_SR[sr]);
534 }
535
536 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
537 {
538 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
539 tcg_gen_or_i32(d, d, cpu_SR[sr]);
540 tcg_gen_andi_i32(d, d, 0xfffffffc);
541 }
542
543 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
544 {
545 static void (* const rsr_handler[256])(DisasContext *dc,
546 TCGv_i32 d, uint32_t sr) = {
547 [CCOUNT] = gen_rsr_ccount,
548 [PTEVADDR] = gen_rsr_ptevaddr,
549 };
550
551 if (rsr_handler[sr]) {
552 rsr_handler[sr](dc, d, sr);
553 } else {
554 tcg_gen_mov_i32(d, cpu_SR[sr]);
555 }
556 }
557
558 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
559 {
560 gen_helper_wsr_lbeg(cpu_env, s);
561 gen_jumpi_check_loop_end(dc, 0);
562 }
563
564 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
565 {
566 gen_helper_wsr_lend(cpu_env, s);
567 gen_jumpi_check_loop_end(dc, 0);
568 }
569
570 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
571 {
572 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
573 if (dc->sar_m32_5bit) {
574 tcg_gen_discard_i32(dc->sar_m32);
575 }
576 dc->sar_5bit = false;
577 dc->sar_m32_5bit = false;
578 }
579
580 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
581 {
582 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
583 }
584
585 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
586 {
587 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
588 /* This can change tb->flags, so exit tb */
589 gen_jumpi_check_loop_end(dc, -1);
590 }
591
592 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
593 {
594 tcg_gen_ext8s_i32(cpu_SR[sr], s);
595 }
596
597 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
598 {
599 gen_helper_wsr_windowbase(cpu_env, v);
600 /* This can change tb->flags, so exit tb */
601 gen_jumpi_check_loop_end(dc, -1);
602 }
603
604 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
605 {
606 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
607 /* This can change tb->flags, so exit tb */
608 gen_jumpi_check_loop_end(dc, -1);
609 }
610
611 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
612 {
613 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
614 }
615
616 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
617 {
618 gen_helper_wsr_rasid(cpu_env, v);
619 /* This can change tb->flags, so exit tb */
620 gen_jumpi_check_loop_end(dc, -1);
621 }
622
623 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
624 {
625 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
626 }
627
628 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
629 {
630 gen_helper_wsr_ibreakenable(cpu_env, v);
631 gen_jumpi_check_loop_end(dc, 0);
632 }
633
634 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635 {
636 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
637 }
638
639 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
640 {
641 unsigned id = sr - IBREAKA;
642
643 if (id < dc->config->nibreak) {
644 TCGv_i32 tmp = tcg_const_i32(id);
645 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
646 tcg_temp_free(tmp);
647 gen_jumpi_check_loop_end(dc, 0);
648 }
649 }
650
651 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
652 {
653 unsigned id = sr - DBREAKA;
654
655 if (id < dc->config->ndbreak) {
656 TCGv_i32 tmp = tcg_const_i32(id);
657 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
658 tcg_temp_free(tmp);
659 }
660 }
661
662 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
663 {
664 unsigned id = sr - DBREAKC;
665
666 if (id < dc->config->ndbreak) {
667 TCGv_i32 tmp = tcg_const_i32(id);
668 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
669 tcg_temp_free(tmp);
670 }
671 }
672
673 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
674 {
675 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
676 /* This can change tb->flags, so exit tb */
677 gen_jumpi_check_loop_end(dc, -1);
678 }
679
680 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
681 {
682 tcg_gen_andi_i32(cpu_SR[sr], v,
683 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
684 gen_helper_check_interrupts(cpu_env);
685 gen_jumpi_check_loop_end(dc, 0);
686 }
687
688 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
689 {
690 TCGv_i32 tmp = tcg_temp_new_i32();
691
692 tcg_gen_andi_i32(tmp, v,
693 dc->config->inttype_mask[INTTYPE_EDGE] |
694 dc->config->inttype_mask[INTTYPE_NMI] |
695 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
696 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
697 tcg_temp_free(tmp);
698 gen_helper_check_interrupts(cpu_env);
699 }
700
701 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
702 {
703 tcg_gen_mov_i32(cpu_SR[sr], v);
704 gen_helper_check_interrupts(cpu_env);
705 gen_jumpi_check_loop_end(dc, 0);
706 }
707
708 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
709 {
710 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
711 PS_UM | PS_EXCM | PS_INTLEVEL;
712
713 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
714 mask |= PS_RING;
715 }
716 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
717 gen_helper_check_interrupts(cpu_env);
718 /* This can change mmu index and tb->flags, so exit tb */
719 gen_jumpi_check_loop_end(dc, -1);
720 }
721
722 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
723 {
724 if (dc->icount) {
725 tcg_gen_mov_i32(dc->next_icount, v);
726 } else {
727 tcg_gen_mov_i32(cpu_SR[sr], v);
728 }
729 }
730
731 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
732 {
733 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
734 /* This can change tb->flags, so exit tb */
735 gen_jumpi_check_loop_end(dc, -1);
736 }
737
738 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
739 {
740 uint32_t id = sr - CCOMPARE;
741 if (id < dc->config->nccompare) {
742 uint32_t int_bit = 1 << dc->config->timerint[id];
743 gen_advance_ccount(dc);
744 tcg_gen_mov_i32(cpu_SR[sr], v);
745 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
746 gen_helper_check_interrupts(cpu_env);
747 }
748 }
749
750 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
751 {
752 static void (* const wsr_handler[256])(DisasContext *dc,
753 uint32_t sr, TCGv_i32 v) = {
754 [LBEG] = gen_wsr_lbeg,
755 [LEND] = gen_wsr_lend,
756 [SAR] = gen_wsr_sar,
757 [BR] = gen_wsr_br,
758 [LITBASE] = gen_wsr_litbase,
759 [ACCHI] = gen_wsr_acchi,
760 [WINDOW_BASE] = gen_wsr_windowbase,
761 [WINDOW_START] = gen_wsr_windowstart,
762 [PTEVADDR] = gen_wsr_ptevaddr,
763 [RASID] = gen_wsr_rasid,
764 [ITLBCFG] = gen_wsr_tlbcfg,
765 [DTLBCFG] = gen_wsr_tlbcfg,
766 [IBREAKENABLE] = gen_wsr_ibreakenable,
767 [ATOMCTL] = gen_wsr_atomctl,
768 [IBREAKA] = gen_wsr_ibreaka,
769 [IBREAKA + 1] = gen_wsr_ibreaka,
770 [DBREAKA] = gen_wsr_dbreaka,
771 [DBREAKA + 1] = gen_wsr_dbreaka,
772 [DBREAKC] = gen_wsr_dbreakc,
773 [DBREAKC + 1] = gen_wsr_dbreakc,
774 [CPENABLE] = gen_wsr_cpenable,
775 [INTSET] = gen_wsr_intset,
776 [INTCLEAR] = gen_wsr_intclear,
777 [INTENABLE] = gen_wsr_intenable,
778 [PS] = gen_wsr_ps,
779 [ICOUNT] = gen_wsr_icount,
780 [ICOUNTLEVEL] = gen_wsr_icountlevel,
781 [CCOMPARE] = gen_wsr_ccompare,
782 [CCOMPARE + 1] = gen_wsr_ccompare,
783 [CCOMPARE + 2] = gen_wsr_ccompare,
784 };
785
786 if (wsr_handler[sr]) {
787 wsr_handler[sr](dc, sr, s);
788 } else {
789 tcg_gen_mov_i32(cpu_SR[sr], s);
790 }
791 }
792
793 static void gen_wur(uint32_t ur, TCGv_i32 s)
794 {
795 switch (ur) {
796 case FCR:
797 gen_helper_wur_fcr(cpu_env, s);
798 break;
799
800 case FSR:
801 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
802 break;
803
804 default:
805 tcg_gen_mov_i32(cpu_UR[ur], s);
806 break;
807 }
808 }
809
810 static void gen_load_store_alignment(DisasContext *dc, int shift,
811 TCGv_i32 addr, bool no_hw_alignment)
812 {
813 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
814 tcg_gen_andi_i32(addr, addr, ~0 << shift);
815 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
816 no_hw_alignment) {
817 TCGLabel *label = gen_new_label();
818 TCGv_i32 tmp = tcg_temp_new_i32();
819 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
820 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
821 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
822 gen_set_label(label);
823 tcg_temp_free(tmp);
824 }
825 }
826
827 static void gen_waiti(DisasContext *dc, uint32_t imm4)
828 {
829 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
830 TCGv_i32 intlevel = tcg_const_i32(imm4);
831 gen_advance_ccount(dc);
832 gen_helper_waiti(cpu_env, pc, intlevel);
833 tcg_temp_free(pc);
834 tcg_temp_free(intlevel);
835 }
836
837 static bool gen_window_check1(DisasContext *dc, unsigned r1)
838 {
839 if (r1 / 4 > dc->window) {
840 TCGv_i32 pc = tcg_const_i32(dc->pc);
841 TCGv_i32 w = tcg_const_i32(r1 / 4);
842
843 gen_advance_ccount(dc);
844 gen_helper_window_check(cpu_env, pc, w);
845 dc->is_jmp = DISAS_UPDATE;
846 return false;
847 }
848 return true;
849 }
850
851 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
852 {
853 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
854 }
855
856 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
857 unsigned r3)
858 {
859 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
860 }
861
862 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
863 {
864 TCGv_i32 m = tcg_temp_new_i32();
865
866 if (hi) {
867 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
868 } else {
869 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
870 }
871 return m;
872 }
873
874 static inline unsigned xtensa_op0_insn_len(unsigned op0)
875 {
876 return op0 >= 8 ? 2 : 3;
877 }
878
879 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
880 {
881 #define HAS_OPTION_BITS(opt) do { \
882 if (!option_bits_enabled(dc, opt)) { \
883 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
884 __FILE__, __LINE__); \
885 goto invalid_opcode; \
886 } \
887 } while (0)
888
889 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
890
891 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
892 #define RESERVED() do { \
893 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
894 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
895 goto invalid_opcode; \
896 } while (0)
897
898
899 #ifdef TARGET_WORDS_BIGENDIAN
900 #define OP0 (((b0) & 0xf0) >> 4)
901 #define OP1 (((b2) & 0xf0) >> 4)
902 #define OP2 ((b2) & 0xf)
903 #define RRR_R ((b1) & 0xf)
904 #define RRR_S (((b1) & 0xf0) >> 4)
905 #define RRR_T ((b0) & 0xf)
906 #else
907 #define OP0 (((b0) & 0xf))
908 #define OP1 (((b2) & 0xf))
909 #define OP2 (((b2) & 0xf0) >> 4)
910 #define RRR_R (((b1) & 0xf0) >> 4)
911 #define RRR_S (((b1) & 0xf))
912 #define RRR_T (((b0) & 0xf0) >> 4)
913 #endif
914 #define RRR_X ((RRR_R & 0x4) >> 2)
915 #define RRR_Y ((RRR_T & 0x4) >> 2)
916 #define RRR_W (RRR_R & 0x3)
917
918 #define RRRN_R RRR_R
919 #define RRRN_S RRR_S
920 #define RRRN_T RRR_T
921
922 #define RRI4_R RRR_R
923 #define RRI4_S RRR_S
924 #define RRI4_T RRR_T
925 #ifdef TARGET_WORDS_BIGENDIAN
926 #define RRI4_IMM4 ((b2) & 0xf)
927 #else
928 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
929 #endif
930
931 #define RRI8_R RRR_R
932 #define RRI8_S RRR_S
933 #define RRI8_T RRR_T
934 #define RRI8_IMM8 (b2)
935 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
936
937 #ifdef TARGET_WORDS_BIGENDIAN
938 #define RI16_IMM16 (((b1) << 8) | (b2))
939 #else
940 #define RI16_IMM16 (((b2) << 8) | (b1))
941 #endif
942
943 #ifdef TARGET_WORDS_BIGENDIAN
944 #define CALL_N (((b0) & 0xc) >> 2)
945 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
946 #else
947 #define CALL_N (((b0) & 0x30) >> 4)
948 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
949 #endif
950 #define CALL_OFFSET_SE \
951 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
952
953 #define CALLX_N CALL_N
954 #ifdef TARGET_WORDS_BIGENDIAN
955 #define CALLX_M ((b0) & 0x3)
956 #else
957 #define CALLX_M (((b0) & 0xc0) >> 6)
958 #endif
959 #define CALLX_S RRR_S
960
961 #define BRI12_M CALLX_M
962 #define BRI12_S RRR_S
963 #ifdef TARGET_WORDS_BIGENDIAN
964 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
965 #else
966 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
967 #endif
968 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
969
970 #define BRI8_M BRI12_M
971 #define BRI8_R RRI8_R
972 #define BRI8_S RRI8_S
973 #define BRI8_IMM8 RRI8_IMM8
974 #define BRI8_IMM8_SE RRI8_IMM8_SE
975
976 #define RSR_SR (b1)
977
978 uint8_t b0 = cpu_ldub_code(env, dc->pc);
979 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
980 uint8_t b2 = 0;
981 unsigned len = xtensa_op0_insn_len(OP0);
982
983 static const uint32_t B4CONST[] = {
984 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
985 };
986
987 static const uint32_t B4CONSTU[] = {
988 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
989 };
990
991 switch (len) {
992 case 2:
993 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
994 break;
995
996 case 3:
997 b2 = cpu_ldub_code(env, dc->pc + 2);
998 break;
999
1000 default:
1001 RESERVED();
1002 }
1003 dc->next_pc = dc->pc + len;
1004
1005 switch (OP0) {
1006 case 0: /*QRST*/
1007 switch (OP1) {
1008 case 0: /*RST0*/
1009 switch (OP2) {
1010 case 0: /*ST0*/
1011 if ((RRR_R & 0xc) == 0x8) {
1012 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1013 }
1014
1015 switch (RRR_R) {
1016 case 0: /*SNM0*/
1017 switch (CALLX_M) {
1018 case 0: /*ILL*/
1019 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1020 break;
1021
1022 case 1: /*reserved*/
1023 RESERVED();
1024 break;
1025
1026 case 2: /*JR*/
1027 switch (CALLX_N) {
1028 case 0: /*RET*/
1029 case 2: /*JX*/
1030 if (gen_window_check1(dc, CALLX_S)) {
1031 gen_jump(dc, cpu_R[CALLX_S]);
1032 }
1033 break;
1034
1035 case 1: /*RETWw*/
1036 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1037 {
1038 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1039 gen_advance_ccount(dc);
1040 gen_helper_retw(tmp, cpu_env, tmp);
1041 gen_jump(dc, tmp);
1042 tcg_temp_free(tmp);
1043 }
1044 break;
1045
1046 case 3: /*reserved*/
1047 RESERVED();
1048 break;
1049 }
1050 break;
1051
1052 case 3: /*CALLX*/
1053 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1054 break;
1055 }
1056 switch (CALLX_N) {
1057 case 0: /*CALLX0*/
1058 {
1059 TCGv_i32 tmp = tcg_temp_new_i32();
1060 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1061 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1062 gen_jump(dc, tmp);
1063 tcg_temp_free(tmp);
1064 }
1065 break;
1066
1067 case 1: /*CALLX4w*/
1068 case 2: /*CALLX8w*/
1069 case 3: /*CALLX12w*/
1070 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1071 {
1072 TCGv_i32 tmp = tcg_temp_new_i32();
1073
1074 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1075 gen_callw(dc, CALLX_N, tmp);
1076 tcg_temp_free(tmp);
1077 }
1078 break;
1079 }
1080 break;
1081 }
1082 break;
1083
1084 case 1: /*MOVSPw*/
1085 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1086 if (gen_window_check2(dc, RRR_T, RRR_S)) {
1087 TCGv_i32 pc = tcg_const_i32(dc->pc);
1088 gen_advance_ccount(dc);
1089 gen_helper_movsp(cpu_env, pc);
1090 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1091 tcg_temp_free(pc);
1092 }
1093 break;
1094
1095 case 2: /*SYNC*/
1096 switch (RRR_T) {
1097 case 0: /*ISYNC*/
1098 break;
1099
1100 case 1: /*RSYNC*/
1101 break;
1102
1103 case 2: /*ESYNC*/
1104 break;
1105
1106 case 3: /*DSYNC*/
1107 break;
1108
1109 case 8: /*EXCW*/
1110 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1111 break;
1112
1113 case 12: /*MEMW*/
1114 break;
1115
1116 case 13: /*EXTW*/
1117 break;
1118
1119 case 15: /*NOP*/
1120 break;
1121
1122 default: /*reserved*/
1123 RESERVED();
1124 break;
1125 }
1126 break;
1127
1128 case 3: /*RFEIx*/
1129 switch (RRR_T) {
1130 case 0: /*RFETx*/
1131 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1132 switch (RRR_S) {
1133 case 0: /*RFEx*/
1134 if (gen_check_privilege(dc)) {
1135 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1136 gen_helper_check_interrupts(cpu_env);
1137 gen_jump(dc, cpu_SR[EPC1]);
1138 }
1139 break;
1140
1141 case 1: /*RFUEx*/
1142 RESERVED();
1143 break;
1144
1145 case 2: /*RFDEx*/
1146 if (gen_check_privilege(dc)) {
1147 gen_jump(dc, cpu_SR[
1148 dc->config->ndepc ? DEPC : EPC1]);
1149 }
1150 break;
1151
1152 case 4: /*RFWOw*/
1153 case 5: /*RFWUw*/
1154 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1155 if (gen_check_privilege(dc)) {
1156 TCGv_i32 tmp = tcg_const_i32(1);
1157
1158 tcg_gen_andi_i32(
1159 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1160 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1161
1162 if (RRR_S == 4) {
1163 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1164 cpu_SR[WINDOW_START], tmp);
1165 } else {
1166 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1167 cpu_SR[WINDOW_START], tmp);
1168 }
1169
1170 gen_helper_restore_owb(cpu_env);
1171 gen_helper_check_interrupts(cpu_env);
1172 gen_jump(dc, cpu_SR[EPC1]);
1173
1174 tcg_temp_free(tmp);
1175 }
1176 break;
1177
1178 default: /*reserved*/
1179 RESERVED();
1180 break;
1181 }
1182 break;
1183
1184 case 1: /*RFIx*/
1185 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1186 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1187 if (gen_check_privilege(dc)) {
1188 tcg_gen_mov_i32(cpu_SR[PS],
1189 cpu_SR[EPS2 + RRR_S - 2]);
1190 gen_helper_check_interrupts(cpu_env);
1191 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1192 }
1193 } else {
1194 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
1195 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1196 }
1197 break;
1198
1199 case 2: /*RFME*/
1200 TBD();
1201 break;
1202
1203 default: /*reserved*/
1204 RESERVED();
1205 break;
1206
1207 }
1208 break;
1209
1210 case 4: /*BREAKx*/
1211 HAS_OPTION(XTENSA_OPTION_DEBUG);
1212 if (dc->debug) {
1213 gen_debug_exception(dc, DEBUGCAUSE_BI);
1214 }
1215 break;
1216
1217 case 5: /*SYSCALLx*/
1218 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1219 switch (RRR_S) {
1220 case 0: /*SYSCALLx*/
1221 gen_exception_cause(dc, SYSCALL_CAUSE);
1222 break;
1223
1224 case 1: /*SIMCALL*/
1225 if (semihosting_enabled()) {
1226 if (gen_check_privilege(dc)) {
1227 gen_helper_simcall(cpu_env);
1228 }
1229 } else {
1230 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
1231 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1232 }
1233 break;
1234
1235 default:
1236 RESERVED();
1237 break;
1238 }
1239 break;
1240
1241 case 6: /*RSILx*/
1242 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1243 if (gen_check_privilege(dc) &&
1244 gen_window_check1(dc, RRR_T)) {
1245 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1246 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1247 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1248 gen_helper_check_interrupts(cpu_env);
1249 gen_jumpi_check_loop_end(dc, 0);
1250 }
1251 break;
1252
1253 case 7: /*WAITIx*/
1254 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1255 if (gen_check_privilege(dc)) {
1256 gen_waiti(dc, RRR_S);
1257 }
1258 break;
1259
1260 case 8: /*ANY4p*/
1261 case 9: /*ALL4p*/
1262 case 10: /*ANY8p*/
1263 case 11: /*ALL8p*/
1264 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1265 {
1266 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1267 TCGv_i32 mask = tcg_const_i32(
1268 ((1 << shift) - 1) << RRR_S);
1269 TCGv_i32 tmp = tcg_temp_new_i32();
1270
1271 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1272 if (RRR_R & 1) { /*ALL*/
1273 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1274 } else { /*ANY*/
1275 tcg_gen_add_i32(tmp, tmp, mask);
1276 }
1277 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1278 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1279 tmp, RRR_T, 1);
1280 tcg_temp_free(mask);
1281 tcg_temp_free(tmp);
1282 }
1283 break;
1284
1285 default: /*reserved*/
1286 RESERVED();
1287 break;
1288
1289 }
1290 break;
1291
1292 case 1: /*AND*/
1293 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1294 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1295 }
1296 break;
1297
1298 case 2: /*OR*/
1299 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1300 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1301 }
1302 break;
1303
1304 case 3: /*XOR*/
1305 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1306 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1307 }
1308 break;
1309
1310 case 4: /*ST1*/
1311 switch (RRR_R) {
1312 case 0: /*SSR*/
1313 if (gen_window_check1(dc, RRR_S)) {
1314 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1315 }
1316 break;
1317
1318 case 1: /*SSL*/
1319 if (gen_window_check1(dc, RRR_S)) {
1320 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1321 }
1322 break;
1323
1324 case 2: /*SSA8L*/
1325 if (gen_window_check1(dc, RRR_S)) {
1326 TCGv_i32 tmp = tcg_temp_new_i32();
1327 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1328 gen_right_shift_sar(dc, tmp);
1329 tcg_temp_free(tmp);
1330 }
1331 break;
1332
1333 case 3: /*SSA8B*/
1334 if (gen_window_check1(dc, RRR_S)) {
1335 TCGv_i32 tmp = tcg_temp_new_i32();
1336 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1337 gen_left_shift_sar(dc, tmp);
1338 tcg_temp_free(tmp);
1339 }
1340 break;
1341
1342 case 4: /*SSAI*/
1343 {
1344 TCGv_i32 tmp = tcg_const_i32(
1345 RRR_S | ((RRR_T & 1) << 4));
1346 gen_right_shift_sar(dc, tmp);
1347 tcg_temp_free(tmp);
1348 }
1349 break;
1350
1351 case 6: /*RER*/
1352 TBD();
1353 break;
1354
1355 case 7: /*WER*/
1356 TBD();
1357 break;
1358
1359 case 8: /*ROTWw*/
1360 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1361 if (gen_check_privilege(dc)) {
1362 TCGv_i32 tmp = tcg_const_i32(
1363 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1364 gen_helper_rotw(cpu_env, tmp);
1365 tcg_temp_free(tmp);
1366 /* This can change tb->flags, so exit tb */
1367 gen_jumpi_check_loop_end(dc, -1);
1368 }
1369 break;
1370
1371 case 14: /*NSAu*/
1372 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1373 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1374 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1375 }
1376 break;
1377
1378 case 15: /*NSAUu*/
1379 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1380 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1381 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1382 }
1383 break;
1384
1385 default: /*reserved*/
1386 RESERVED();
1387 break;
1388 }
1389 break;
1390
1391 case 5: /*TLB*/
1392 HAS_OPTION_BITS(
1393 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1394 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1395 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1396 if (gen_check_privilege(dc) &&
1397 gen_window_check2(dc, RRR_S, RRR_T)) {
1398 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1399
1400 switch (RRR_R & 7) {
1401 case 3: /*RITLB0*/ /*RDTLB0*/
1402 gen_helper_rtlb0(cpu_R[RRR_T],
1403 cpu_env, cpu_R[RRR_S], dtlb);
1404 break;
1405
1406 case 4: /*IITLB*/ /*IDTLB*/
1407 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1408 /* This could change memory mapping, so exit tb */
1409 gen_jumpi_check_loop_end(dc, -1);
1410 break;
1411
1412 case 5: /*PITLB*/ /*PDTLB*/
1413 tcg_gen_movi_i32(cpu_pc, dc->pc);
1414 gen_helper_ptlb(cpu_R[RRR_T],
1415 cpu_env, cpu_R[RRR_S], dtlb);
1416 break;
1417
1418 case 6: /*WITLB*/ /*WDTLB*/
1419 gen_helper_wtlb(
1420 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1421 /* This could change memory mapping, so exit tb */
1422 gen_jumpi_check_loop_end(dc, -1);
1423 break;
1424
1425 case 7: /*RITLB1*/ /*RDTLB1*/
1426 gen_helper_rtlb1(cpu_R[RRR_T],
1427 cpu_env, cpu_R[RRR_S], dtlb);
1428 break;
1429
1430 default:
1431 tcg_temp_free(dtlb);
1432 RESERVED();
1433 break;
1434 }
1435 tcg_temp_free(dtlb);
1436 }
1437 break;
1438
1439 case 6: /*RT0*/
1440 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1441 break;
1442 }
1443 switch (RRR_S) {
1444 case 0: /*NEG*/
1445 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1446 break;
1447
1448 case 1: /*ABS*/
1449 {
1450 TCGv_i32 zero = tcg_const_i32(0);
1451 TCGv_i32 neg = tcg_temp_new_i32();
1452
1453 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1454 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1455 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1456 tcg_temp_free(neg);
1457 tcg_temp_free(zero);
1458 }
1459 break;
1460
1461 default: /*reserved*/
1462 RESERVED();
1463 break;
1464 }
1465 break;
1466
1467 case 7: /*reserved*/
1468 RESERVED();
1469 break;
1470
1471 case 8: /*ADD*/
1472 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1473 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1474 }
1475 break;
1476
1477 case 9: /*ADD**/
1478 case 10:
1479 case 11:
1480 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1481 TCGv_i32 tmp = tcg_temp_new_i32();
1482 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1483 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1484 tcg_temp_free(tmp);
1485 }
1486 break;
1487
1488 case 12: /*SUB*/
1489 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1490 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1491 }
1492 break;
1493
1494 case 13: /*SUB**/
1495 case 14:
1496 case 15:
1497 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1498 TCGv_i32 tmp = tcg_temp_new_i32();
1499 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1500 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1501 tcg_temp_free(tmp);
1502 }
1503 break;
1504 }
1505 break;
1506
1507 case 1: /*RST1*/
1508 switch (OP2) {
1509 case 0: /*SLLI*/
1510 case 1:
1511 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1512 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1513 32 - (RRR_T | ((OP2 & 1) << 4)));
1514 }
1515 break;
1516
1517 case 2: /*SRAI*/
1518 case 3:
1519 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1520 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1521 RRR_S | ((OP2 & 1) << 4));
1522 }
1523 break;
1524
1525 case 4: /*SRLI*/
1526 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1527 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1528 }
1529 break;
1530
1531 case 6: /*XSR*/
1532 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1533 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1534 gen_window_check1(dc, RRR_T)) {
1535 TCGv_i32 tmp = tcg_temp_new_i32();
1536
1537 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1538 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1539 gen_wsr(dc, RSR_SR, tmp);
1540 tcg_temp_free(tmp);
1541 }
1542 break;
1543
1544 /*
1545 * Note: 64 bit ops are used here solely because SAR values
1546 * have range 0..63
1547 */
1548 #define gen_shift_reg(cmd, reg) do { \
1549 TCGv_i64 tmp = tcg_temp_new_i64(); \
1550 tcg_gen_extu_i32_i64(tmp, reg); \
1551 tcg_gen_##cmd##_i64(v, v, tmp); \
1552 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1553 tcg_temp_free_i64(v); \
1554 tcg_temp_free_i64(tmp); \
1555 } while (0)
1556
1557 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1558
1559 case 8: /*SRC*/
1560 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1561 TCGv_i64 v = tcg_temp_new_i64();
1562 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1563 gen_shift(shr);
1564 }
1565 break;
1566
1567 case 9: /*SRL*/
1568 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1569 break;
1570 }
1571 if (dc->sar_5bit) {
1572 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1573 } else {
1574 TCGv_i64 v = tcg_temp_new_i64();
1575 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1576 gen_shift(shr);
1577 }
1578 break;
1579
1580 case 10: /*SLL*/
1581 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1582 break;
1583 }
1584 if (dc->sar_m32_5bit) {
1585 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1586 } else {
1587 TCGv_i64 v = tcg_temp_new_i64();
1588 TCGv_i32 s = tcg_const_i32(32);
1589 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1590 tcg_gen_andi_i32(s, s, 0x3f);
1591 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1592 gen_shift_reg(shl, s);
1593 tcg_temp_free(s);
1594 }
1595 break;
1596
1597 case 11: /*SRA*/
1598 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1599 break;
1600 }
1601 if (dc->sar_5bit) {
1602 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1603 } else {
1604 TCGv_i64 v = tcg_temp_new_i64();
1605 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1606 gen_shift(sar);
1607 }
1608 break;
1609 #undef gen_shift
1610 #undef gen_shift_reg
1611
1612 case 12: /*MUL16U*/
1613 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1614 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1615 TCGv_i32 v1 = tcg_temp_new_i32();
1616 TCGv_i32 v2 = tcg_temp_new_i32();
1617 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1618 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1619 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1620 tcg_temp_free(v2);
1621 tcg_temp_free(v1);
1622 }
1623 break;
1624
1625 case 13: /*MUL16S*/
1626 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1627 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1628 TCGv_i32 v1 = tcg_temp_new_i32();
1629 TCGv_i32 v2 = tcg_temp_new_i32();
1630 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1631 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1632 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1633 tcg_temp_free(v2);
1634 tcg_temp_free(v1);
1635 }
1636 break;
1637
1638 default: /*reserved*/
1639 RESERVED();
1640 break;
1641 }
1642 break;
1643
1644 case 2: /*RST2*/
1645 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1646 break;
1647 }
1648
1649 if (OP2 >= 12) {
1650 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1651 TCGLabel *label = gen_new_label();
1652 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1653 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1654 gen_set_label(label);
1655 }
1656
1657 switch (OP2) {
1658 #define BOOLEAN_LOGIC(fn, r, s, t) \
1659 do { \
1660 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1661 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1662 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1663 \
1664 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1665 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1666 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1667 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1668 tcg_temp_free(tmp1); \
1669 tcg_temp_free(tmp2); \
1670 } while (0)
1671
1672 case 0: /*ANDBp*/
1673 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1674 break;
1675
1676 case 1: /*ANDBCp*/
1677 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1678 break;
1679
1680 case 2: /*ORBp*/
1681 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1682 break;
1683
1684 case 3: /*ORBCp*/
1685 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1686 break;
1687
1688 case 4: /*XORBp*/
1689 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1690 break;
1691
1692 #undef BOOLEAN_LOGIC
1693
1694 case 8: /*MULLi*/
1695 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1696 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1697 break;
1698
1699 case 10: /*MULUHi*/
1700 case 11: /*MULSHi*/
1701 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1702 {
1703 TCGv lo = tcg_temp_new();
1704
1705 if (OP2 == 10) {
1706 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1707 cpu_R[RRR_S], cpu_R[RRR_T]);
1708 } else {
1709 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1710 cpu_R[RRR_S], cpu_R[RRR_T]);
1711 }
1712 tcg_temp_free(lo);
1713 }
1714 break;
1715
1716 case 12: /*QUOUi*/
1717 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1718 break;
1719
1720 case 13: /*QUOSi*/
1721 case 15: /*REMSi*/
1722 {
1723 TCGLabel *label1 = gen_new_label();
1724 TCGLabel *label2 = gen_new_label();
1725
1726 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1727 label1);
1728 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1729 label1);
1730 tcg_gen_movi_i32(cpu_R[RRR_R],
1731 OP2 == 13 ? 0x80000000 : 0);
1732 tcg_gen_br(label2);
1733 gen_set_label(label1);
1734 if (OP2 == 13) {
1735 tcg_gen_div_i32(cpu_R[RRR_R],
1736 cpu_R[RRR_S], cpu_R[RRR_T]);
1737 } else {
1738 tcg_gen_rem_i32(cpu_R[RRR_R],
1739 cpu_R[RRR_S], cpu_R[RRR_T]);
1740 }
1741 gen_set_label(label2);
1742 }
1743 break;
1744
1745 case 14: /*REMUi*/
1746 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1747 break;
1748
1749 default: /*reserved*/
1750 RESERVED();
1751 break;
1752 }
1753 break;
1754
1755 case 3: /*RST3*/
1756 switch (OP2) {
1757 case 0: /*RSR*/
1758 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1759 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1760 gen_window_check1(dc, RRR_T)) {
1761 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1762 }
1763 break;
1764
1765 case 1: /*WSR*/
1766 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1767 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1768 gen_window_check1(dc, RRR_T)) {
1769 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1770 }
1771 break;
1772
1773 case 2: /*SEXTu*/
1774 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1775 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1776 int shift = 24 - RRR_T;
1777
1778 if (shift == 24) {
1779 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1780 } else if (shift == 16) {
1781 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1782 } else {
1783 TCGv_i32 tmp = tcg_temp_new_i32();
1784 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1785 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1786 tcg_temp_free(tmp);
1787 }
1788 }
1789 break;
1790
1791 case 3: /*CLAMPSu*/
1792 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1793 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1794 TCGv_i32 tmp1 = tcg_temp_new_i32();
1795 TCGv_i32 tmp2 = tcg_temp_new_i32();
1796 TCGv_i32 zero = tcg_const_i32(0);
1797
1798 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1799 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1800 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1801
1802 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1803 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1804
1805 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1806 cpu_R[RRR_S], tmp1);
1807 tcg_temp_free(tmp1);
1808 tcg_temp_free(tmp2);
1809 tcg_temp_free(zero);
1810 }
1811 break;
1812
1813 case 4: /*MINu*/
1814 case 5: /*MAXu*/
1815 case 6: /*MINUu*/
1816 case 7: /*MAXUu*/
1817 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1818 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1819 static const TCGCond cond[] = {
1820 TCG_COND_LE,
1821 TCG_COND_GE,
1822 TCG_COND_LEU,
1823 TCG_COND_GEU
1824 };
1825 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1826 cpu_R[RRR_S], cpu_R[RRR_T],
1827 cpu_R[RRR_S], cpu_R[RRR_T]);
1828 }
1829 break;
1830
1831 case 8: /*MOVEQZ*/
1832 case 9: /*MOVNEZ*/
1833 case 10: /*MOVLTZ*/
1834 case 11: /*MOVGEZ*/
1835 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1836 static const TCGCond cond[] = {
1837 TCG_COND_EQ,
1838 TCG_COND_NE,
1839 TCG_COND_LT,
1840 TCG_COND_GE,
1841 };
1842 TCGv_i32 zero = tcg_const_i32(0);
1843
1844 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1845 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1846 tcg_temp_free(zero);
1847 }
1848 break;
1849
1850 case 12: /*MOVFp*/
1851 case 13: /*MOVTp*/
1852 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1853 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1854 TCGv_i32 zero = tcg_const_i32(0);
1855 TCGv_i32 tmp = tcg_temp_new_i32();
1856
1857 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1858 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1859 cpu_R[RRR_R], tmp, zero,
1860 cpu_R[RRR_S], cpu_R[RRR_R]);
1861
1862 tcg_temp_free(tmp);
1863 tcg_temp_free(zero);
1864 }
1865 break;
1866
1867 case 14: /*RUR*/
1868 if (gen_window_check1(dc, RRR_R)) {
1869 int st = (RRR_S << 4) + RRR_T;
1870 if (uregnames[st].name) {
1871 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1872 } else {
1873 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
1874 TBD();
1875 }
1876 }
1877 break;
1878
1879 case 15: /*WUR*/
1880 if (gen_window_check1(dc, RRR_T)) {
1881 if (uregnames[RSR_SR].name) {
1882 gen_wur(RSR_SR, cpu_R[RRR_T]);
1883 } else {
1884 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
1885 TBD();
1886 }
1887 }
1888 break;
1889
1890 }
1891 break;
1892
1893 case 4: /*EXTUI*/
1894 case 5:
1895 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1896 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1897 int maskimm = (1 << (OP2 + 1)) - 1;
1898
1899 TCGv_i32 tmp = tcg_temp_new_i32();
1900 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1901 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1902 tcg_temp_free(tmp);
1903 }
1904 break;
1905
1906 case 6: /*CUST0*/
1907 RESERVED();
1908 break;
1909
1910 case 7: /*CUST1*/
1911 RESERVED();
1912 break;
1913
1914 case 8: /*LSCXp*/
1915 switch (OP2) {
1916 case 0: /*LSXf*/
1917 case 1: /*LSXUf*/
1918 case 4: /*SSXf*/
1919 case 5: /*SSXUf*/
1920 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1921 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1922 gen_check_cpenable(dc, 0)) {
1923 TCGv_i32 addr = tcg_temp_new_i32();
1924 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1925 gen_load_store_alignment(dc, 2, addr, false);
1926 if (OP2 & 0x4) {
1927 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1928 } else {
1929 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1930 }
1931 if (OP2 & 0x1) {
1932 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1933 }
1934 tcg_temp_free(addr);
1935 }
1936 break;
1937
1938 default: /*reserved*/
1939 RESERVED();
1940 break;
1941 }
1942 break;
1943
1944 case 9: /*LSC4*/
1945 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1946 break;
1947 }
1948 switch (OP2) {
1949 case 0: /*L32E*/
1950 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1951 if (gen_check_privilege(dc) &&
1952 gen_window_check2(dc, RRR_S, RRR_T)) {
1953 TCGv_i32 addr = tcg_temp_new_i32();
1954 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1955 (0xffffffc0 | (RRR_R << 2)));
1956 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1957 tcg_temp_free(addr);
1958 }
1959 break;
1960
1961 case 4: /*S32E*/
1962 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1963 if (gen_check_privilege(dc) &&
1964 gen_window_check2(dc, RRR_S, RRR_T)) {
1965 TCGv_i32 addr = tcg_temp_new_i32();
1966 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1967 (0xffffffc0 | (RRR_R << 2)));
1968 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1969 tcg_temp_free(addr);
1970 }
1971 break;
1972
1973 case 5: /*S32N*/
1974 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
1975 TCGv_i32 addr = tcg_temp_new_i32();
1976
1977 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
1978 gen_load_store_alignment(dc, 2, addr, false);
1979 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
1980 tcg_temp_free(addr);
1981 }
1982 break;
1983
1984 default:
1985 RESERVED();
1986 break;
1987 }
1988 break;
1989
1990 case 10: /*FP0*/
1991 /*DEPBITS*/
1992 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
1993 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1994 break;
1995 }
1996 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
1997 OP2, RRR_R + 1);
1998 break;
1999 }
2000
2001 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2002 switch (OP2) {
2003 case 0: /*ADD.Sf*/
2004 if (gen_check_cpenable(dc, 0)) {
2005 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2006 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2007 }
2008 break;
2009
2010 case 1: /*SUB.Sf*/
2011 if (gen_check_cpenable(dc, 0)) {
2012 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2013 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2014 }
2015 break;
2016
2017 case 2: /*MUL.Sf*/
2018 if (gen_check_cpenable(dc, 0)) {
2019 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2020 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2021 }
2022 break;
2023
2024 case 4: /*MADD.Sf*/
2025 if (gen_check_cpenable(dc, 0)) {
2026 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2027 cpu_FR[RRR_R], cpu_FR[RRR_S],
2028 cpu_FR[RRR_T]);
2029 }
2030 break;
2031
2032 case 5: /*MSUB.Sf*/
2033 if (gen_check_cpenable(dc, 0)) {
2034 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2035 cpu_FR[RRR_R], cpu_FR[RRR_S],
2036 cpu_FR[RRR_T]);
2037 }
2038 break;
2039
2040 case 8: /*ROUND.Sf*/
2041 case 9: /*TRUNC.Sf*/
2042 case 10: /*FLOOR.Sf*/
2043 case 11: /*CEIL.Sf*/
2044 case 14: /*UTRUNC.Sf*/
2045 if (gen_window_check1(dc, RRR_R) &&
2046 gen_check_cpenable(dc, 0)) {
2047 static const unsigned rounding_mode_const[] = {
2048 float_round_nearest_even,
2049 float_round_to_zero,
2050 float_round_down,
2051 float_round_up,
2052 [6] = float_round_to_zero,
2053 };
2054 TCGv_i32 rounding_mode = tcg_const_i32(
2055 rounding_mode_const[OP2 & 7]);
2056 TCGv_i32 scale = tcg_const_i32(RRR_T);
2057
2058 if (OP2 == 14) {
2059 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2060 rounding_mode, scale);
2061 } else {
2062 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2063 rounding_mode, scale);
2064 }
2065
2066 tcg_temp_free(rounding_mode);
2067 tcg_temp_free(scale);
2068 }
2069 break;
2070
2071 case 12: /*FLOAT.Sf*/
2072 case 13: /*UFLOAT.Sf*/
2073 if (gen_window_check1(dc, RRR_S) &&
2074 gen_check_cpenable(dc, 0)) {
2075 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2076
2077 if (OP2 == 13) {
2078 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2079 cpu_R[RRR_S], scale);
2080 } else {
2081 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2082 cpu_R[RRR_S], scale);
2083 }
2084 tcg_temp_free(scale);
2085 }
2086 break;
2087
2088 case 15: /*FP1OP*/
2089 switch (RRR_T) {
2090 case 0: /*MOV.Sf*/
2091 if (gen_check_cpenable(dc, 0)) {
2092 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2093 }
2094 break;
2095
2096 case 1: /*ABS.Sf*/
2097 if (gen_check_cpenable(dc, 0)) {
2098 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2099 }
2100 break;
2101
2102 case 4: /*RFRf*/
2103 if (gen_window_check1(dc, RRR_R) &&
2104 gen_check_cpenable(dc, 0)) {
2105 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2106 }
2107 break;
2108
2109 case 5: /*WFRf*/
2110 if (gen_window_check1(dc, RRR_S) &&
2111 gen_check_cpenable(dc, 0)) {
2112 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2113 }
2114 break;
2115
2116 case 6: /*NEG.Sf*/
2117 if (gen_check_cpenable(dc, 0)) {
2118 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2119 }
2120 break;
2121
2122 default: /*reserved*/
2123 RESERVED();
2124 break;
2125 }
2126 break;
2127
2128 default: /*reserved*/
2129 RESERVED();
2130 break;
2131 }
2132 break;
2133
2134 case 11: /*FP1*/
2135 /*DEPBITS*/
2136 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2137 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2138 break;
2139 }
2140 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2141 OP2 + 16, RRR_R + 1);
2142 break;
2143 }
2144
2145 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2146
2147 #define gen_compare(rel, br, a, b) \
2148 do { \
2149 if (gen_check_cpenable(dc, 0)) { \
2150 TCGv_i32 bit = tcg_const_i32(1 << br); \
2151 \
2152 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2153 tcg_temp_free(bit); \
2154 } \
2155 } while (0)
2156
2157 switch (OP2) {
2158 case 1: /*UN.Sf*/
2159 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2160 break;
2161
2162 case 2: /*OEQ.Sf*/
2163 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2164 break;
2165
2166 case 3: /*UEQ.Sf*/
2167 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2168 break;
2169
2170 case 4: /*OLT.Sf*/
2171 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2172 break;
2173
2174 case 5: /*ULT.Sf*/
2175 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2176 break;
2177
2178 case 6: /*OLE.Sf*/
2179 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2180 break;
2181
2182 case 7: /*ULE.Sf*/
2183 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2184 break;
2185
2186 #undef gen_compare
2187
2188 case 8: /*MOVEQZ.Sf*/
2189 case 9: /*MOVNEZ.Sf*/
2190 case 10: /*MOVLTZ.Sf*/
2191 case 11: /*MOVGEZ.Sf*/
2192 if (gen_window_check1(dc, RRR_T) &&
2193 gen_check_cpenable(dc, 0)) {
2194 static const TCGCond cond[] = {
2195 TCG_COND_EQ,
2196 TCG_COND_NE,
2197 TCG_COND_LT,
2198 TCG_COND_GE,
2199 };
2200 TCGv_i32 zero = tcg_const_i32(0);
2201
2202 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2203 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2204 tcg_temp_free(zero);
2205 }
2206 break;
2207
2208 case 12: /*MOVF.Sf*/
2209 case 13: /*MOVT.Sf*/
2210 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2211 if (gen_check_cpenable(dc, 0)) {
2212 TCGv_i32 zero = tcg_const_i32(0);
2213 TCGv_i32 tmp = tcg_temp_new_i32();
2214
2215 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2216 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2217 cpu_FR[RRR_R], tmp, zero,
2218 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2219
2220 tcg_temp_free(tmp);
2221 tcg_temp_free(zero);
2222 }
2223 break;
2224
2225 default: /*reserved*/
2226 RESERVED();
2227 break;
2228 }
2229 break;
2230
2231 default: /*reserved*/
2232 RESERVED();
2233 break;
2234 }
2235 break;
2236
2237 case 1: /*L32R*/
2238 if (gen_window_check1(dc, RRR_T)) {
2239 TCGv_i32 tmp = tcg_const_i32(
2240 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2241 0 : ((dc->pc + 3) & ~3)) +
2242 (0xfffc0000 | (RI16_IMM16 << 2)));
2243
2244 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2245 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2246 }
2247 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2248 tcg_temp_free(tmp);
2249 }
2250 break;
2251
2252 case 2: /*LSAI*/
2253 #define gen_load_store(type, shift) do { \
2254 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2255 TCGv_i32 addr = tcg_temp_new_i32(); \
2256 \
2257 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2258 if (shift) { \
2259 gen_load_store_alignment(dc, shift, addr, false); \
2260 } \
2261 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2262 tcg_temp_free(addr); \
2263 } \
2264 } while (0)
2265
2266 switch (RRI8_R) {
2267 case 0: /*L8UI*/
2268 gen_load_store(ld8u, 0);
2269 break;
2270
2271 case 1: /*L16UI*/
2272 gen_load_store(ld16u, 1);
2273 break;
2274
2275 case 2: /*L32I*/
2276 gen_load_store(ld32u, 2);
2277 break;
2278
2279 case 4: /*S8I*/
2280 gen_load_store(st8, 0);
2281 break;
2282
2283 case 5: /*S16I*/
2284 gen_load_store(st16, 1);
2285 break;
2286
2287 case 6: /*S32I*/
2288 gen_load_store(st32, 2);
2289 break;
2290
2291 #define gen_dcache_hit_test(w, shift) do { \
2292 if (gen_window_check1(dc, RRI##w##_S)) { \
2293 TCGv_i32 addr = tcg_temp_new_i32(); \
2294 TCGv_i32 res = tcg_temp_new_i32(); \
2295 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2296 RRI##w##_IMM##w << shift); \
2297 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2298 tcg_temp_free(addr); \
2299 tcg_temp_free(res); \
2300 } \
2301 } while (0)
2302
2303 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2304 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2305
2306 case 7: /*CACHEc*/
2307 if (RRI8_T < 8) {
2308 HAS_OPTION(XTENSA_OPTION_DCACHE);
2309 }
2310
2311 switch (RRI8_T) {
2312 case 0: /*DPFRc*/
2313 gen_window_check1(dc, RRI8_S);
2314 break;
2315
2316 case 1: /*DPFWc*/
2317 gen_window_check1(dc, RRI8_S);
2318 break;
2319
2320 case 2: /*DPFROc*/
2321 gen_window_check1(dc, RRI8_S);
2322 break;
2323
2324 case 3: /*DPFWOc*/
2325 gen_window_check1(dc, RRI8_S);
2326 break;
2327
2328 case 4: /*DHWBc*/
2329 gen_dcache_hit_test8();
2330 break;
2331
2332 case 5: /*DHWBIc*/
2333 gen_dcache_hit_test8();
2334 break;
2335
2336 case 6: /*DHIc*/
2337 if (gen_check_privilege(dc)) {
2338 gen_dcache_hit_test8();
2339 }
2340 break;
2341
2342 case 7: /*DIIc*/
2343 if (gen_check_privilege(dc)) {
2344 gen_window_check1(dc, RRI8_S);
2345 }
2346 break;
2347
2348 case 8: /*DCEc*/
2349 switch (OP1) {
2350 case 0: /*DPFLl*/
2351 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2352 if (gen_check_privilege(dc)) {
2353 gen_dcache_hit_test4();
2354 }
2355 break;
2356
2357 case 2: /*DHUl*/
2358 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2359 if (gen_check_privilege(dc)) {
2360 gen_dcache_hit_test4();
2361 }
2362 break;
2363
2364 case 3: /*DIUl*/
2365 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2366 if (gen_check_privilege(dc)) {
2367 gen_window_check1(dc, RRI4_S);
2368 }
2369 break;
2370
2371 case 4: /*DIWBc*/
2372 HAS_OPTION(XTENSA_OPTION_DCACHE);
2373 if (gen_check_privilege(dc)) {
2374 gen_window_check1(dc, RRI4_S);
2375 }
2376 break;
2377
2378 case 5: /*DIWBIc*/
2379 HAS_OPTION(XTENSA_OPTION_DCACHE);
2380 if (gen_check_privilege(dc)) {
2381 gen_window_check1(dc, RRI4_S);
2382 }
2383 break;
2384
2385 default: /*reserved*/
2386 RESERVED();
2387 break;
2388
2389 }
2390 break;
2391
2392 #undef gen_dcache_hit_test
2393 #undef gen_dcache_hit_test4
2394 #undef gen_dcache_hit_test8
2395
2396 #define gen_icache_hit_test(w, shift) do { \
2397 if (gen_window_check1(dc, RRI##w##_S)) { \
2398 TCGv_i32 addr = tcg_temp_new_i32(); \
2399 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2400 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2401 RRI##w##_IMM##w << shift); \
2402 gen_helper_itlb_hit_test(cpu_env, addr); \
2403 tcg_temp_free(addr); \
2404 }\
2405 } while (0)
2406
2407 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2408 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2409
2410 case 12: /*IPFc*/
2411 HAS_OPTION(XTENSA_OPTION_ICACHE);
2412 gen_window_check1(dc, RRI8_S);
2413 break;
2414
2415 case 13: /*ICEc*/
2416 switch (OP1) {
2417 case 0: /*IPFLl*/
2418 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2419 if (gen_check_privilege(dc)) {
2420 gen_icache_hit_test4();
2421 }
2422 break;
2423
2424 case 2: /*IHUl*/
2425 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2426 if (gen_check_privilege(dc)) {
2427 gen_icache_hit_test4();
2428 }
2429 break;
2430
2431 case 3: /*IIUl*/
2432 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2433 if (gen_check_privilege(dc)) {
2434 gen_window_check1(dc, RRI4_S);
2435 }
2436 break;
2437
2438 default: /*reserved*/
2439 RESERVED();
2440 break;
2441 }
2442 break;
2443
2444 case 14: /*IHIc*/
2445 HAS_OPTION(XTENSA_OPTION_ICACHE);
2446 gen_icache_hit_test8();
2447 break;
2448
2449 case 15: /*IIIc*/
2450 HAS_OPTION(XTENSA_OPTION_ICACHE);
2451 if (gen_check_privilege(dc)) {
2452 gen_window_check1(dc, RRI8_S);
2453 }
2454 break;
2455
2456 default: /*reserved*/
2457 RESERVED();
2458 break;
2459 }
2460 break;
2461
2462 #undef gen_icache_hit_test
2463 #undef gen_icache_hit_test4
2464 #undef gen_icache_hit_test8
2465
2466 case 9: /*L16SI*/
2467 gen_load_store(ld16s, 1);
2468 break;
2469 #undef gen_load_store
2470
2471 case 10: /*MOVI*/
2472 if (gen_window_check1(dc, RRI8_T)) {
2473 tcg_gen_movi_i32(cpu_R[RRI8_T],
2474 RRI8_IMM8 | (RRI8_S << 8) |
2475 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2476 }
2477 break;
2478
2479 #define gen_load_store_no_hw_align(type) do { \
2480 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2481 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2482 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2483 gen_load_store_alignment(dc, 2, addr, true); \
2484 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2485 tcg_temp_free(addr); \
2486 } \
2487 } while (0)
2488
2489 case 11: /*L32AIy*/
2490 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2491 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2492 break;
2493
2494 case 12: /*ADDI*/
2495 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2496 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2497 }
2498 break;
2499
2500 case 13: /*ADDMI*/
2501 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2502 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2503 RRI8_IMM8_SE << 8);
2504 }
2505 break;
2506
2507 case 14: /*S32C1Iy*/
2508 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2509 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2510 TCGLabel *label = gen_new_label();
2511 TCGv_i32 tmp = tcg_temp_local_new_i32();
2512 TCGv_i32 addr = tcg_temp_local_new_i32();
2513 TCGv_i32 tpc;
2514
2515 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2516 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2517 gen_load_store_alignment(dc, 2, addr, true);
2518
2519 gen_advance_ccount(dc);
2520 tpc = tcg_const_i32(dc->pc);
2521 gen_helper_check_atomctl(cpu_env, tpc, addr);
2522 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2523 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2524 cpu_SR[SCOMPARE1], label);
2525
2526 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2527
2528 gen_set_label(label);
2529 tcg_temp_free(tpc);
2530 tcg_temp_free(addr);
2531 tcg_temp_free(tmp);
2532 }
2533 break;
2534
2535 case 15: /*S32RIy*/
2536 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2537 gen_load_store_no_hw_align(st32); /*TODO release?*/
2538 break;
2539 #undef gen_load_store_no_hw_align
2540
2541 default: /*reserved*/
2542 RESERVED();
2543 break;
2544 }
2545 break;
2546
2547 case 3: /*LSCIp*/
2548 switch (RRI8_R) {
2549 case 0: /*LSIf*/
2550 case 4: /*SSIf*/
2551 case 8: /*LSIUf*/
2552 case 12: /*SSIUf*/
2553 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2554 if (gen_window_check1(dc, RRI8_S) &&
2555 gen_check_cpenable(dc, 0)) {
2556 TCGv_i32 addr = tcg_temp_new_i32();
2557 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2558 gen_load_store_alignment(dc, 2, addr, false);
2559 if (RRI8_R & 0x4) {
2560 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2561 } else {
2562 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2563 }
2564 if (RRI8_R & 0x8) {
2565 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2566 }
2567 tcg_temp_free(addr);
2568 }
2569 break;
2570
2571 default: /*reserved*/
2572 RESERVED();
2573 break;
2574 }
2575 break;
2576
2577 case 4: /*MAC16d*/
2578 HAS_OPTION(XTENSA_OPTION_MAC16);
2579 {
2580 enum {
2581 MAC16_UMUL = 0x0,
2582 MAC16_MUL = 0x4,
2583 MAC16_MULA = 0x8,
2584 MAC16_MULS = 0xc,
2585 MAC16_NONE = 0xf,
2586 } op = OP1 & 0xc;
2587 bool is_m1_sr = (OP2 & 0x3) == 2;
2588 bool is_m2_sr = (OP2 & 0xc) == 0;
2589 uint32_t ld_offset = 0;
2590
2591 if (OP2 > 9) {
2592 RESERVED();
2593 }
2594
2595 switch (OP2 & 2) {
2596 case 0: /*MACI?/MACC?*/
2597 is_m1_sr = true;
2598 ld_offset = (OP2 & 1) ? -4 : 4;
2599
2600 if (OP2 >= 8) { /*MACI/MACC*/
2601 if (OP1 == 0) { /*LDINC/LDDEC*/
2602 op = MAC16_NONE;
2603 } else {
2604 RESERVED();
2605 }
2606 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2607 RESERVED();
2608 }
2609 break;
2610
2611 case 2: /*MACD?/MACA?*/
2612 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2613 RESERVED();
2614 }
2615 break;
2616 }
2617
2618 if (op != MAC16_NONE) {
2619 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2620 break;
2621 }
2622 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2623 break;
2624 }
2625 }
2626
2627 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2628 break;
2629 }
2630
2631 {
2632 TCGv_i32 vaddr = tcg_temp_new_i32();
2633 TCGv_i32 mem32 = tcg_temp_new_i32();
2634
2635 if (ld_offset) {
2636 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2637 gen_load_store_alignment(dc, 2, vaddr, false);
2638 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2639 }
2640 if (op != MAC16_NONE) {
2641 TCGv_i32 m1 = gen_mac16_m(
2642 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2643 OP1 & 1, op == MAC16_UMUL);
2644 TCGv_i32 m2 = gen_mac16_m(
2645 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2646 OP1 & 2, op == MAC16_UMUL);
2647
2648 if (op == MAC16_MUL || op == MAC16_UMUL) {
2649 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2650 if (op == MAC16_UMUL) {
2651 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2652 } else {
2653 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2654 }
2655 } else {
2656 TCGv_i32 lo = tcg_temp_new_i32();
2657 TCGv_i32 hi = tcg_temp_new_i32();
2658
2659 tcg_gen_mul_i32(lo, m1, m2);
2660 tcg_gen_sari_i32(hi, lo, 31);
2661 if (op == MAC16_MULA) {
2662 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2663 cpu_SR[ACCLO], cpu_SR[ACCHI],
2664 lo, hi);
2665 } else {
2666 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2667 cpu_SR[ACCLO], cpu_SR[ACCHI],
2668 lo, hi);
2669 }
2670 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2671
2672 tcg_temp_free_i32(lo);
2673 tcg_temp_free_i32(hi);
2674 }
2675 tcg_temp_free(m1);
2676 tcg_temp_free(m2);
2677 }
2678 if (ld_offset) {
2679 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2680 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2681 }
2682 tcg_temp_free(vaddr);
2683 tcg_temp_free(mem32);
2684 }
2685 }
2686 break;
2687
2688 case 5: /*CALLN*/
2689 switch (CALL_N) {
2690 case 0: /*CALL0*/
2691 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2692 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2693 break;
2694
2695 case 1: /*CALL4w*/
2696 case 2: /*CALL8w*/
2697 case 3: /*CALL12w*/
2698 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2699 if (gen_window_check1(dc, CALL_N << 2)) {
2700 gen_callwi(dc, CALL_N,
2701 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2702 }
2703 break;
2704 }
2705 break;
2706
2707 case 6: /*SI*/
2708 switch (CALL_N) {
2709 case 0: /*J*/
2710 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2711 break;
2712
2713 case 1: /*BZ*/
2714 if (gen_window_check1(dc, BRI12_S)) {
2715 static const TCGCond cond[] = {
2716 TCG_COND_EQ, /*BEQZ*/
2717 TCG_COND_NE, /*BNEZ*/
2718 TCG_COND_LT, /*BLTZ*/
2719 TCG_COND_GE, /*BGEZ*/
2720 };
2721
2722 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2723 4 + BRI12_IMM12_SE);
2724 }
2725 break;
2726
2727 case 2: /*BI0*/
2728 if (gen_window_check1(dc, BRI8_S)) {
2729 static const TCGCond cond[] = {
2730 TCG_COND_EQ, /*BEQI*/
2731 TCG_COND_NE, /*BNEI*/
2732 TCG_COND_LT, /*BLTI*/
2733 TCG_COND_GE, /*BGEI*/
2734 };
2735
2736 gen_brcondi(dc, cond[BRI8_M & 3],
2737 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2738 }
2739 break;
2740
2741 case 3: /*BI1*/
2742 switch (BRI8_M) {
2743 case 0: /*ENTRYw*/
2744 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2745 {
2746 TCGv_i32 pc = tcg_const_i32(dc->pc);
2747 TCGv_i32 s = tcg_const_i32(BRI12_S);
2748 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2749 gen_advance_ccount(dc);
2750 gen_helper_entry(cpu_env, pc, s, imm);
2751 tcg_temp_free(imm);
2752 tcg_temp_free(s);
2753 tcg_temp_free(pc);
2754 /* This can change tb->flags, so exit tb */
2755 gen_jumpi_check_loop_end(dc, -1);
2756 }
2757 break;
2758
2759 case 1: /*B1*/
2760 switch (BRI8_R) {
2761 case 0: /*BFp*/
2762 case 1: /*BTp*/
2763 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2764 {
2765 TCGv_i32 tmp = tcg_temp_new_i32();
2766 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2767 gen_brcondi(dc,
2768 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2769 tmp, 0, 4 + RRI8_IMM8_SE);
2770 tcg_temp_free(tmp);
2771 }
2772 break;
2773
2774 case 8: /*LOOP*/
2775 case 9: /*LOOPNEZ*/
2776 case 10: /*LOOPGTZ*/
2777 HAS_OPTION(XTENSA_OPTION_LOOP);
2778 if (gen_window_check1(dc, RRI8_S)) {
2779 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2780 TCGv_i32 tmp = tcg_const_i32(lend);
2781
2782 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2783 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2784 gen_helper_wsr_lend(cpu_env, tmp);
2785 tcg_temp_free(tmp);
2786
2787 if (BRI8_R > 8) {
2788 TCGLabel *label = gen_new_label();
2789 tcg_gen_brcondi_i32(
2790 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2791 cpu_R[RRI8_S], 0, label);
2792 gen_jumpi(dc, lend, 1);
2793 gen_set_label(label);
2794 }
2795
2796 gen_jumpi(dc, dc->next_pc, 0);
2797 }
2798 break;
2799
2800 default: /*reserved*/
2801 RESERVED();
2802 break;
2803
2804 }
2805 break;
2806
2807 case 2: /*BLTUI*/
2808 case 3: /*BGEUI*/
2809 if (gen_window_check1(dc, BRI8_S)) {
2810 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2811 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2812 4 + BRI8_IMM8_SE);
2813 }
2814 break;
2815 }
2816 break;
2817
2818 }
2819 break;
2820
2821 case 7: /*B*/
2822 {
2823 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2824
2825 switch (RRI8_R & 7) {
2826 case 0: /*BNONE*/ /*BANY*/
2827 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2828 TCGv_i32 tmp = tcg_temp_new_i32();
2829 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2830 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2831 tcg_temp_free(tmp);
2832 }
2833 break;
2834
2835 case 1: /*BEQ*/ /*BNE*/
2836 case 2: /*BLT*/ /*BGE*/
2837 case 3: /*BLTU*/ /*BGEU*/
2838 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2839 static const TCGCond cond[] = {
2840 [1] = TCG_COND_EQ,
2841 [2] = TCG_COND_LT,
2842 [3] = TCG_COND_LTU,
2843 [9] = TCG_COND_NE,
2844 [10] = TCG_COND_GE,
2845 [11] = TCG_COND_GEU,
2846 };
2847 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2848 4 + RRI8_IMM8_SE);
2849 }
2850 break;
2851
2852 case 4: /*BALL*/ /*BNALL*/
2853 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2854 TCGv_i32 tmp = tcg_temp_new_i32();
2855 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2856 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2857 4 + RRI8_IMM8_SE);
2858 tcg_temp_free(tmp);
2859 }
2860 break;
2861
2862 case 5: /*BBC*/ /*BBS*/
2863 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2864 #ifdef TARGET_WORDS_BIGENDIAN
2865 TCGv_i32 bit = tcg_const_i32(0x80000000);
2866 #else
2867 TCGv_i32 bit = tcg_const_i32(0x00000001);
2868 #endif
2869 TCGv_i32 tmp = tcg_temp_new_i32();
2870 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2871 #ifdef TARGET_WORDS_BIGENDIAN
2872 tcg_gen_shr_i32(bit, bit, tmp);
2873 #else
2874 tcg_gen_shl_i32(bit, bit, tmp);
2875 #endif
2876 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2877 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2878 tcg_temp_free(tmp);
2879 tcg_temp_free(bit);
2880 }
2881 break;
2882
2883 case 6: /*BBCI*/ /*BBSI*/
2884 case 7:
2885 if (gen_window_check1(dc, RRI8_S)) {
2886 TCGv_i32 tmp = tcg_temp_new_i32();
2887 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2888 #ifdef TARGET_WORDS_BIGENDIAN
2889 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2890 #else
2891 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2892 #endif
2893 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2894 tcg_temp_free(tmp);
2895 }
2896 break;
2897
2898 }
2899 }
2900 break;
2901
2902 #define gen_narrow_load_store(type) do { \
2903 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2904 TCGv_i32 addr = tcg_temp_new_i32(); \
2905 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2906 gen_load_store_alignment(dc, 2, addr, false); \
2907 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2908 tcg_temp_free(addr); \
2909 } \
2910 } while (0)
2911
2912 case 8: /*L32I.Nn*/
2913 gen_narrow_load_store(ld32u);
2914 break;
2915
2916 case 9: /*S32I.Nn*/
2917 gen_narrow_load_store(st32);
2918 break;
2919 #undef gen_narrow_load_store
2920
2921 case 10: /*ADD.Nn*/
2922 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2923 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2924 }
2925 break;
2926
2927 case 11: /*ADDI.Nn*/
2928 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2929 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2930 RRRN_T ? RRRN_T : -1);
2931 }
2932 break;
2933
2934 case 12: /*ST2n*/
2935 if (!gen_window_check1(dc, RRRN_S)) {
2936 break;
2937 }
2938 if (RRRN_T < 8) { /*MOVI.Nn*/
2939 tcg_gen_movi_i32(cpu_R[RRRN_S],
2940 RRRN_R | (RRRN_T << 4) |
2941 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2942 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2943 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2944
2945 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2946 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2947 }
2948 break;
2949
2950 case 13: /*ST3n*/
2951 switch (RRRN_R) {
2952 case 0: /*MOV.Nn*/
2953 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2954 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2955 }
2956 break;
2957
2958 case 15: /*S3*/
2959 switch (RRRN_T) {
2960 case 0: /*RET.Nn*/
2961 gen_jump(dc, cpu_R[0]);
2962 break;
2963
2964 case 1: /*RETW.Nn*/
2965 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2966 {
2967 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2968 gen_advance_ccount(dc);
2969 gen_helper_retw(tmp, cpu_env, tmp);
2970 gen_jump(dc, tmp);
2971 tcg_temp_free(tmp);
2972 }
2973 break;
2974
2975 case 2: /*BREAK.Nn*/
2976 HAS_OPTION(XTENSA_OPTION_DEBUG);
2977 if (dc->debug) {
2978 gen_debug_exception(dc, DEBUGCAUSE_BN);
2979 }
2980 break;
2981
2982 case 3: /*NOP.Nn*/
2983 break;
2984
2985 case 6: /*ILL.Nn*/
2986 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2987 break;
2988
2989 default: /*reserved*/
2990 RESERVED();
2991 break;
2992 }
2993 break;
2994
2995 default: /*reserved*/
2996 RESERVED();
2997 break;
2998 }
2999 break;
3000
3001 default: /*reserved*/
3002 RESERVED();
3003 break;
3004 }
3005
3006 if (dc->is_jmp == DISAS_NEXT) {
3007 gen_check_loop_end(dc, 0);
3008 }
3009 dc->pc = dc->next_pc;
3010
3011 return;
3012
3013 invalid_opcode:
3014 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
3015 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
3016 #undef HAS_OPTION
3017 }
3018
3019 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3020 {
3021 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3022 return xtensa_op0_insn_len(OP0);
3023 }
3024
3025 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
3026 {
3027 unsigned i;
3028
3029 for (i = 0; i < dc->config->nibreak; ++i) {
3030 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3031 env->sregs[IBREAKA + i] == dc->pc) {
3032 gen_debug_exception(dc, DEBUGCAUSE_IB);
3033 break;
3034 }
3035 }
3036 }
3037
3038 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3039 {
3040 XtensaCPU *cpu = xtensa_env_get_cpu(env);
3041 CPUState *cs = CPU(cpu);
3042 DisasContext dc;
3043 int insn_count = 0;
3044 int max_insns = tb->cflags & CF_COUNT_MASK;
3045 uint32_t pc_start = tb->pc;
3046 uint32_t next_page_start =
3047 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3048
3049 if (max_insns == 0) {
3050 max_insns = CF_COUNT_MASK;
3051 }
3052 if (max_insns > TCG_MAX_INSNS) {
3053 max_insns = TCG_MAX_INSNS;
3054 }
3055
3056 dc.config = env->config;
3057 dc.singlestep_enabled = cs->singlestep_enabled;
3058 dc.tb = tb;
3059 dc.pc = pc_start;
3060 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3061 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3062 dc.lbeg = env->sregs[LBEG];
3063 dc.lend = env->sregs[LEND];
3064 dc.is_jmp = DISAS_NEXT;
3065 dc.ccount_delta = 0;
3066 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3067 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3068 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3069 XTENSA_TBFLAG_CPENABLE_SHIFT;
3070 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3071 XTENSA_TBFLAG_WINDOW_SHIFT);
3072
3073 init_litbase(&dc);
3074 init_sar_tracker(&dc);
3075 if (dc.icount) {
3076 dc.next_icount = tcg_temp_local_new_i32();
3077 }
3078
3079 gen_tb_start(tb);
3080
3081 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3082 tcg_gen_movi_i32(cpu_pc, dc.pc);
3083 gen_exception(&dc, EXCP_DEBUG);
3084 }
3085
3086 do {
3087 tcg_gen_insn_start(dc.pc);
3088 ++insn_count;
3089
3090 ++dc.ccount_delta;
3091
3092 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3093 tcg_gen_movi_i32(cpu_pc, dc.pc);
3094 gen_exception(&dc, EXCP_DEBUG);
3095 dc.is_jmp = DISAS_UPDATE;
3096 /* The address covered by the breakpoint must be included in
3097 [tb->pc, tb->pc + tb->size) in order to for it to be
3098 properly cleared -- thus we increment the PC here so that
3099 the logic setting tb->size below does the right thing. */
3100 dc.pc += 2;
3101 break;
3102 }
3103
3104 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
3105 gen_io_start();
3106 }
3107
3108 if (dc.icount) {
3109 TCGLabel *label = gen_new_label();
3110
3111 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3112 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3113 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3114 if (dc.debug) {
3115 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3116 }
3117 gen_set_label(label);
3118 }
3119
3120 if (dc.debug) {
3121 gen_ibreak_check(env, &dc);
3122 }
3123
3124 disas_xtensa_insn(env, &dc);
3125 if (dc.icount) {
3126 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3127 }
3128 if (cs->singlestep_enabled) {
3129 tcg_gen_movi_i32(cpu_pc, dc.pc);
3130 gen_exception(&dc, EXCP_DEBUG);
3131 break;
3132 }
3133 } while (dc.is_jmp == DISAS_NEXT &&
3134 insn_count < max_insns &&
3135 dc.pc < next_page_start &&
3136 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3137 !tcg_op_buf_full());
3138
3139 reset_litbase(&dc);
3140 reset_sar_tracker(&dc);
3141 if (dc.icount) {
3142 tcg_temp_free(dc.next_icount);
3143 }
3144
3145 if (tb->cflags & CF_LAST_IO) {
3146 gen_io_end();
3147 }
3148
3149 if (dc.is_jmp == DISAS_NEXT) {
3150 gen_jumpi(&dc, dc.pc, 0);
3151 }
3152 gen_tb_end(tb, insn_count);
3153
3154 #ifdef DEBUG_DISAS
3155 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3156 qemu_log("----------------\n");
3157 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3158 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
3159 qemu_log("\n");
3160 }
3161 #endif
3162 tb->size = dc.pc - pc_start;
3163 tb->icount = insn_count;
3164 }
3165
3166 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3167 fprintf_function cpu_fprintf, int flags)
3168 {
3169 XtensaCPU *cpu = XTENSA_CPU(cs);
3170 CPUXtensaState *env = &cpu->env;
3171 int i, j;
3172
3173 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3174
3175 for (i = j = 0; i < 256; ++i) {
3176 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3177 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3178 (j++ % 4) == 3 ? '\n' : ' ');
3179 }
3180 }
3181
3182 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3183
3184 for (i = j = 0; i < 256; ++i) {
3185 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3186 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3187 (j++ % 4) == 3 ? '\n' : ' ');
3188 }
3189 }
3190
3191 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3192
3193 for (i = 0; i < 16; ++i) {
3194 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3195 (i % 4) == 3 ? '\n' : ' ');
3196 }
3197
3198 cpu_fprintf(f, "\n");
3199
3200 for (i = 0; i < env->config->nareg; ++i) {
3201 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3202 (i % 4) == 3 ? '\n' : ' ');
3203 }
3204
3205 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3206 cpu_fprintf(f, "\n");
3207
3208 for (i = 0; i < 16; ++i) {
3209 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3210 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3211 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3212 (i % 2) == 1 ? '\n' : ' ');
3213 }
3214 }
3215 }
3216
3217 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3218 target_ulong *data)
3219 {
3220 env->pc = data[0];
3221 }
AR7 emulation for QEMU