2 * Marvell MV88W8618 / Freecom MusicPal emulation.
4 * Copyright (c) 2008 Jan Kiszka
6 * This code is licensed under the GNU GPL v2.
8 * Contributions after 2012-01-13 are licensed under the terms of the
9 * GNU GPL, version 2 or (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
15 #include "hw/sysbus.h"
16 #include "hw/arm/boot.h"
18 #include "sysemu/sysemu.h"
19 #include "hw/boards.h"
20 #include "hw/char/serial.h"
21 #include "qemu/timer.h"
22 #include "hw/ptimer.h"
23 #include "hw/block/flash.h"
24 #include "ui/console.h"
25 #include "hw/i2c/i2c.h"
26 #include "hw/audio/wm8750.h"
27 #include "sysemu/block-backend.h"
28 #include "exec/address-spaces.h"
29 #include "ui/pixel_ops.h"
31 #define MP_MISC_BASE 0x80002000
32 #define MP_MISC_SIZE 0x00001000
34 #define MP_ETH_BASE 0x80008000
35 #define MP_ETH_SIZE 0x00001000
37 #define MP_WLAN_BASE 0x8000C000
38 #define MP_WLAN_SIZE 0x00000800
40 #define MP_UART1_BASE 0x8000C840
41 #define MP_UART2_BASE 0x8000C940
43 #define MP_GPIO_BASE 0x8000D000
44 #define MP_GPIO_SIZE 0x00001000
46 #define MP_FLASHCFG_BASE 0x90006000
47 #define MP_FLASHCFG_SIZE 0x00001000
49 #define MP_AUDIO_BASE 0x90007000
51 #define MP_PIC_BASE 0x90008000
52 #define MP_PIC_SIZE 0x00001000
54 #define MP_PIT_BASE 0x90009000
55 #define MP_PIT_SIZE 0x00001000
57 #define MP_LCD_BASE 0x9000c000
58 #define MP_LCD_SIZE 0x00001000
60 #define MP_SRAM_BASE 0xC0000000
61 #define MP_SRAM_SIZE 0x00020000
63 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
64 #define MP_FLASH_SIZE_MAX 32*1024*1024
66 #define MP_TIMER1_IRQ 4
67 #define MP_TIMER2_IRQ 5
68 #define MP_TIMER3_IRQ 6
69 #define MP_TIMER4_IRQ 7
72 #define MP_UART1_IRQ 11
73 #define MP_UART2_IRQ 11
74 #define MP_GPIO_IRQ 12
76 #define MP_AUDIO_IRQ 30
78 /* Wolfson 8750 I2C address */
79 #define MP_WM_ADDR 0x1A
81 /* Ethernet register offsets */
82 #define MP_ETH_SMIR 0x010
83 #define MP_ETH_PCXR 0x408
84 #define MP_ETH_SDCMR 0x448
85 #define MP_ETH_ICR 0x450
86 #define MP_ETH_IMR 0x458
87 #define MP_ETH_FRDP0 0x480
88 #define MP_ETH_FRDP1 0x484
89 #define MP_ETH_FRDP2 0x488
90 #define MP_ETH_FRDP3 0x48C
91 #define MP_ETH_CRDP0 0x4A0
92 #define MP_ETH_CRDP1 0x4A4
93 #define MP_ETH_CRDP2 0x4A8
94 #define MP_ETH_CRDP3 0x4AC
95 #define MP_ETH_CTDP0 0x4E0
96 #define MP_ETH_CTDP1 0x4E4
99 #define MP_ETH_SMIR_DATA 0x0000FFFF
100 #define MP_ETH_SMIR_ADDR 0x03FF0000
101 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
102 #define MP_ETH_SMIR_RDVALID (1 << 27)
105 #define MP_ETH_PHY1_BMSR 0x00210000
106 #define MP_ETH_PHY1_PHYSID1 0x00410000
107 #define MP_ETH_PHY1_PHYSID2 0x00610000
109 #define MP_PHY_BMSR_LINK 0x0004
110 #define MP_PHY_BMSR_AUTONEG 0x0008
112 #define MP_PHY_88E3015 0x01410E20
114 /* TX descriptor status */
115 #define MP_ETH_TX_OWN (1U << 31)
117 /* RX descriptor status */
118 #define MP_ETH_RX_OWN (1U << 31)
120 /* Interrupt cause/mask bits */
121 #define MP_ETH_IRQ_RX_BIT 0
122 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
123 #define MP_ETH_IRQ_TXHI_BIT 2
124 #define MP_ETH_IRQ_TXLO_BIT 3
126 /* Port config bits */
127 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
129 /* SDMA command bits */
130 #define MP_ETH_CMD_TXHI (1 << 23)
131 #define MP_ETH_CMD_TXLO (1 << 22)
133 typedef struct mv88w8618_tx_desc
{
141 typedef struct mv88w8618_rx_desc
{
144 uint16_t buffer_size
;
149 #define TYPE_MV88W8618_ETH "mv88w8618_eth"
150 #define MV88W8618_ETH(obj) \
151 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
153 typedef struct mv88w8618_eth_state
{
155 SysBusDevice parent_obj
;
164 uint32_t vlan_header
;
165 uint32_t tx_queue
[2];
166 uint32_t rx_queue
[4];
167 uint32_t frx_queue
[4];
171 } mv88w8618_eth_state
;
173 static void eth_rx_desc_put(uint32_t addr
, mv88w8618_rx_desc
*desc
)
175 cpu_to_le32s(&desc
->cmdstat
);
176 cpu_to_le16s(&desc
->bytes
);
177 cpu_to_le16s(&desc
->buffer_size
);
178 cpu_to_le32s(&desc
->buffer
);
179 cpu_to_le32s(&desc
->next
);
180 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
183 static void eth_rx_desc_get(uint32_t addr
, mv88w8618_rx_desc
*desc
)
185 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
186 le32_to_cpus(&desc
->cmdstat
);
187 le16_to_cpus(&desc
->bytes
);
188 le16_to_cpus(&desc
->buffer_size
);
189 le32_to_cpus(&desc
->buffer
);
190 le32_to_cpus(&desc
->next
);
193 static ssize_t
eth_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
195 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
197 mv88w8618_rx_desc desc
;
200 for (i
= 0; i
< 4; i
++) {
201 desc_addr
= s
->cur_rx
[i
];
206 eth_rx_desc_get(desc_addr
, &desc
);
207 if ((desc
.cmdstat
& MP_ETH_RX_OWN
) && desc
.buffer_size
>= size
) {
208 cpu_physical_memory_write(desc
.buffer
+ s
->vlan_header
,
210 desc
.bytes
= size
+ s
->vlan_header
;
211 desc
.cmdstat
&= ~MP_ETH_RX_OWN
;
212 s
->cur_rx
[i
] = desc
.next
;
214 s
->icr
|= MP_ETH_IRQ_RX
;
215 if (s
->icr
& s
->imr
) {
216 qemu_irq_raise(s
->irq
);
218 eth_rx_desc_put(desc_addr
, &desc
);
221 desc_addr
= desc
.next
;
222 } while (desc_addr
!= s
->rx_queue
[i
]);
227 static void eth_tx_desc_put(uint32_t addr
, mv88w8618_tx_desc
*desc
)
229 cpu_to_le32s(&desc
->cmdstat
);
230 cpu_to_le16s(&desc
->res
);
231 cpu_to_le16s(&desc
->bytes
);
232 cpu_to_le32s(&desc
->buffer
);
233 cpu_to_le32s(&desc
->next
);
234 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
237 static void eth_tx_desc_get(uint32_t addr
, mv88w8618_tx_desc
*desc
)
239 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
240 le32_to_cpus(&desc
->cmdstat
);
241 le16_to_cpus(&desc
->res
);
242 le16_to_cpus(&desc
->bytes
);
243 le32_to_cpus(&desc
->buffer
);
244 le32_to_cpus(&desc
->next
);
247 static void eth_send(mv88w8618_eth_state
*s
, int queue_index
)
249 uint32_t desc_addr
= s
->tx_queue
[queue_index
];
250 mv88w8618_tx_desc desc
;
256 eth_tx_desc_get(desc_addr
, &desc
);
257 next_desc
= desc
.next
;
258 if (desc
.cmdstat
& MP_ETH_TX_OWN
) {
261 cpu_physical_memory_read(desc
.buffer
, buf
, len
);
262 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, len
);
264 desc
.cmdstat
&= ~MP_ETH_TX_OWN
;
265 s
->icr
|= 1 << (MP_ETH_IRQ_TXLO_BIT
- queue_index
);
266 eth_tx_desc_put(desc_addr
, &desc
);
268 desc_addr
= next_desc
;
269 } while (desc_addr
!= s
->tx_queue
[queue_index
]);
272 static uint64_t mv88w8618_eth_read(void *opaque
, hwaddr offset
,
275 mv88w8618_eth_state
*s
= opaque
;
279 if (s
->smir
& MP_ETH_SMIR_OPCODE
) {
280 switch (s
->smir
& MP_ETH_SMIR_ADDR
) {
281 case MP_ETH_PHY1_BMSR
:
282 return MP_PHY_BMSR_LINK
| MP_PHY_BMSR_AUTONEG
|
284 case MP_ETH_PHY1_PHYSID1
:
285 return (MP_PHY_88E3015
>> 16) | MP_ETH_SMIR_RDVALID
;
286 case MP_ETH_PHY1_PHYSID2
:
287 return (MP_PHY_88E3015
& 0xFFFF) | MP_ETH_SMIR_RDVALID
;
289 return MP_ETH_SMIR_RDVALID
;
300 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
301 return s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4];
303 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
304 return s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4];
306 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
307 return s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4];
314 static void mv88w8618_eth_write(void *opaque
, hwaddr offset
,
315 uint64_t value
, unsigned size
)
317 mv88w8618_eth_state
*s
= opaque
;
325 s
->vlan_header
= ((value
>> MP_ETH_PCXR_2BSM_BIT
) & 1) * 2;
329 if (value
& MP_ETH_CMD_TXHI
) {
332 if (value
& MP_ETH_CMD_TXLO
) {
335 if (value
& (MP_ETH_CMD_TXHI
| MP_ETH_CMD_TXLO
) && s
->icr
& s
->imr
) {
336 qemu_irq_raise(s
->irq
);
346 if (s
->icr
& s
->imr
) {
347 qemu_irq_raise(s
->irq
);
351 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
352 s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4] = value
;
355 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
356 s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4] =
357 s
->cur_rx
[(offset
- MP_ETH_CRDP0
)/4] = value
;
360 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
361 s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4] = value
;
366 static const MemoryRegionOps mv88w8618_eth_ops
= {
367 .read
= mv88w8618_eth_read
,
368 .write
= mv88w8618_eth_write
,
369 .endianness
= DEVICE_NATIVE_ENDIAN
,
372 static void eth_cleanup(NetClientState
*nc
)
374 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
379 static NetClientInfo net_mv88w8618_info
= {
380 .type
= NET_CLIENT_DRIVER_NIC
,
381 .size
= sizeof(NICState
),
382 .receive
= eth_receive
,
383 .cleanup
= eth_cleanup
,
386 static void mv88w8618_eth_init(Object
*obj
)
388 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
389 DeviceState
*dev
= DEVICE(sbd
);
390 mv88w8618_eth_state
*s
= MV88W8618_ETH(dev
);
392 sysbus_init_irq(sbd
, &s
->irq
);
393 memory_region_init_io(&s
->iomem
, obj
, &mv88w8618_eth_ops
, s
,
394 "mv88w8618-eth", MP_ETH_SIZE
);
395 sysbus_init_mmio(sbd
, &s
->iomem
);
398 static void mv88w8618_eth_realize(DeviceState
*dev
, Error
**errp
)
400 mv88w8618_eth_state
*s
= MV88W8618_ETH(dev
);
402 s
->nic
= qemu_new_nic(&net_mv88w8618_info
, &s
->conf
,
403 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
406 static const VMStateDescription mv88w8618_eth_vmsd
= {
407 .name
= "mv88w8618_eth",
409 .minimum_version_id
= 1,
410 .fields
= (VMStateField
[]) {
411 VMSTATE_UINT32(smir
, mv88w8618_eth_state
),
412 VMSTATE_UINT32(icr
, mv88w8618_eth_state
),
413 VMSTATE_UINT32(imr
, mv88w8618_eth_state
),
414 VMSTATE_UINT32(vlan_header
, mv88w8618_eth_state
),
415 VMSTATE_UINT32_ARRAY(tx_queue
, mv88w8618_eth_state
, 2),
416 VMSTATE_UINT32_ARRAY(rx_queue
, mv88w8618_eth_state
, 4),
417 VMSTATE_UINT32_ARRAY(frx_queue
, mv88w8618_eth_state
, 4),
418 VMSTATE_UINT32_ARRAY(cur_rx
, mv88w8618_eth_state
, 4),
419 VMSTATE_END_OF_LIST()
423 static Property mv88w8618_eth_properties
[] = {
424 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state
, conf
),
425 DEFINE_PROP_END_OF_LIST(),
428 static void mv88w8618_eth_class_init(ObjectClass
*klass
, void *data
)
430 DeviceClass
*dc
= DEVICE_CLASS(klass
);
432 dc
->vmsd
= &mv88w8618_eth_vmsd
;
433 dc
->props
= mv88w8618_eth_properties
;
434 dc
->realize
= mv88w8618_eth_realize
;
437 static const TypeInfo mv88w8618_eth_info
= {
438 .name
= TYPE_MV88W8618_ETH
,
439 .parent
= TYPE_SYS_BUS_DEVICE
,
440 .instance_size
= sizeof(mv88w8618_eth_state
),
441 .instance_init
= mv88w8618_eth_init
,
442 .class_init
= mv88w8618_eth_class_init
,
445 /* LCD register offsets */
446 #define MP_LCD_IRQCTRL 0x180
447 #define MP_LCD_IRQSTAT 0x184
448 #define MP_LCD_SPICTRL 0x1ac
449 #define MP_LCD_INST 0x1bc
450 #define MP_LCD_DATA 0x1c0
453 #define MP_LCD_SPI_DATA 0x00100011
454 #define MP_LCD_SPI_CMD 0x00104011
455 #define MP_LCD_SPI_INVALID 0x00000000
458 #define MP_LCD_INST_SETPAGE0 0xB0
460 #define MP_LCD_INST_SETPAGE7 0xB7
462 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
464 #define TYPE_MUSICPAL_LCD "musicpal_lcd"
465 #define MUSICPAL_LCD(obj) \
466 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
468 typedef struct musicpal_lcd_state
{
470 SysBusDevice parent_obj
;
480 uint8_t video_ram
[128*64/8];
481 } musicpal_lcd_state
;
483 static uint8_t scale_lcd_color(musicpal_lcd_state
*s
, uint8_t col
)
485 switch (s
->brightness
) {
491 return (col
* s
->brightness
) / 7;
495 #define SET_LCD_PIXEL(depth, type) \
496 static inline void glue(set_lcd_pixel, depth) \
497 (musicpal_lcd_state *s, int x, int y, type col) \
500 DisplaySurface *surface = qemu_console_surface(s->con); \
501 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
503 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
504 for (dx = 0; dx < 3; dx++, pixel++) \
507 SET_LCD_PIXEL(8, uint8_t)
508 SET_LCD_PIXEL(16, uint16_t)
509 SET_LCD_PIXEL(32, uint32_t)
511 static void lcd_refresh(void *opaque
)
513 musicpal_lcd_state
*s
= opaque
;
514 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
517 switch (surface_bits_per_pixel(surface
)) {
520 #define LCD_REFRESH(depth, func) \
522 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
523 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
524 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
525 for (x = 0; x < 128; x++) { \
526 for (y = 0; y < 64; y++) { \
527 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
528 glue(set_lcd_pixel, depth)(s, x, y, col); \
530 glue(set_lcd_pixel, depth)(s, x, y, 0); \
535 LCD_REFRESH(8, rgb_to_pixel8
)
536 LCD_REFRESH(16, rgb_to_pixel16
)
537 LCD_REFRESH(32, (is_surface_bgr(surface
) ?
538 rgb_to_pixel32bgr
: rgb_to_pixel32
))
540 hw_error("unsupported colour depth %i\n",
541 surface_bits_per_pixel(surface
));
544 dpy_gfx_update(s
->con
, 0, 0, 128*3, 64*3);
547 static void lcd_invalidate(void *opaque
)
551 static void musicpal_lcd_gpio_brightness_in(void *opaque
, int irq
, int level
)
553 musicpal_lcd_state
*s
= opaque
;
554 s
->brightness
&= ~(1 << irq
);
555 s
->brightness
|= level
<< irq
;
558 static uint64_t musicpal_lcd_read(void *opaque
, hwaddr offset
,
561 musicpal_lcd_state
*s
= opaque
;
572 static void musicpal_lcd_write(void *opaque
, hwaddr offset
,
573 uint64_t value
, unsigned size
)
575 musicpal_lcd_state
*s
= opaque
;
583 if (value
== MP_LCD_SPI_DATA
|| value
== MP_LCD_SPI_CMD
) {
586 s
->mode
= MP_LCD_SPI_INVALID
;
591 if (value
>= MP_LCD_INST_SETPAGE0
&& value
<= MP_LCD_INST_SETPAGE7
) {
592 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
598 if (s
->mode
== MP_LCD_SPI_CMD
) {
599 if (value
>= MP_LCD_INST_SETPAGE0
&&
600 value
<= MP_LCD_INST_SETPAGE7
) {
601 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
604 } else if (s
->mode
== MP_LCD_SPI_DATA
) {
605 s
->video_ram
[s
->page
*128 + s
->page_off
] = value
;
606 s
->page_off
= (s
->page_off
+ 1) & 127;
612 static const MemoryRegionOps musicpal_lcd_ops
= {
613 .read
= musicpal_lcd_read
,
614 .write
= musicpal_lcd_write
,
615 .endianness
= DEVICE_NATIVE_ENDIAN
,
618 static const GraphicHwOps musicpal_gfx_ops
= {
619 .invalidate
= lcd_invalidate
,
620 .gfx_update
= lcd_refresh
,
623 static void musicpal_lcd_realize(DeviceState
*dev
, Error
**errp
)
625 musicpal_lcd_state
*s
= MUSICPAL_LCD(dev
);
626 s
->con
= graphic_console_init(dev
, 0, &musicpal_gfx_ops
, s
);
627 qemu_console_resize(s
->con
, 128 * 3, 64 * 3);
630 static void musicpal_lcd_init(Object
*obj
)
632 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
633 DeviceState
*dev
= DEVICE(sbd
);
634 musicpal_lcd_state
*s
= MUSICPAL_LCD(dev
);
638 memory_region_init_io(&s
->iomem
, obj
, &musicpal_lcd_ops
, s
,
639 "musicpal-lcd", MP_LCD_SIZE
);
640 sysbus_init_mmio(sbd
, &s
->iomem
);
642 qdev_init_gpio_in(dev
, musicpal_lcd_gpio_brightness_in
, 3);
645 static const VMStateDescription musicpal_lcd_vmsd
= {
646 .name
= "musicpal_lcd",
648 .minimum_version_id
= 1,
649 .fields
= (VMStateField
[]) {
650 VMSTATE_UINT32(brightness
, musicpal_lcd_state
),
651 VMSTATE_UINT32(mode
, musicpal_lcd_state
),
652 VMSTATE_UINT32(irqctrl
, musicpal_lcd_state
),
653 VMSTATE_UINT32(page
, musicpal_lcd_state
),
654 VMSTATE_UINT32(page_off
, musicpal_lcd_state
),
655 VMSTATE_BUFFER(video_ram
, musicpal_lcd_state
),
656 VMSTATE_END_OF_LIST()
660 static void musicpal_lcd_class_init(ObjectClass
*klass
, void *data
)
662 DeviceClass
*dc
= DEVICE_CLASS(klass
);
664 dc
->vmsd
= &musicpal_lcd_vmsd
;
665 dc
->realize
= musicpal_lcd_realize
;
668 static const TypeInfo musicpal_lcd_info
= {
669 .name
= TYPE_MUSICPAL_LCD
,
670 .parent
= TYPE_SYS_BUS_DEVICE
,
671 .instance_size
= sizeof(musicpal_lcd_state
),
672 .instance_init
= musicpal_lcd_init
,
673 .class_init
= musicpal_lcd_class_init
,
676 /* PIC register offsets */
677 #define MP_PIC_STATUS 0x00
678 #define MP_PIC_ENABLE_SET 0x08
679 #define MP_PIC_ENABLE_CLR 0x0C
681 #define TYPE_MV88W8618_PIC "mv88w8618_pic"
682 #define MV88W8618_PIC(obj) \
683 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
685 typedef struct mv88w8618_pic_state
{
687 SysBusDevice parent_obj
;
694 } mv88w8618_pic_state
;
696 static void mv88w8618_pic_update(mv88w8618_pic_state
*s
)
698 qemu_set_irq(s
->parent_irq
, (s
->level
& s
->enabled
));
701 static void mv88w8618_pic_set_irq(void *opaque
, int irq
, int level
)
703 mv88w8618_pic_state
*s
= opaque
;
706 s
->level
|= 1 << irq
;
708 s
->level
&= ~(1 << irq
);
710 mv88w8618_pic_update(s
);
713 static uint64_t mv88w8618_pic_read(void *opaque
, hwaddr offset
,
716 mv88w8618_pic_state
*s
= opaque
;
720 return s
->level
& s
->enabled
;
727 static void mv88w8618_pic_write(void *opaque
, hwaddr offset
,
728 uint64_t value
, unsigned size
)
730 mv88w8618_pic_state
*s
= opaque
;
733 case MP_PIC_ENABLE_SET
:
737 case MP_PIC_ENABLE_CLR
:
738 s
->enabled
&= ~value
;
742 mv88w8618_pic_update(s
);
745 static void mv88w8618_pic_reset(DeviceState
*d
)
747 mv88w8618_pic_state
*s
= MV88W8618_PIC(d
);
753 static const MemoryRegionOps mv88w8618_pic_ops
= {
754 .read
= mv88w8618_pic_read
,
755 .write
= mv88w8618_pic_write
,
756 .endianness
= DEVICE_NATIVE_ENDIAN
,
759 static void mv88w8618_pic_init(Object
*obj
)
761 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
762 mv88w8618_pic_state
*s
= MV88W8618_PIC(dev
);
764 qdev_init_gpio_in(DEVICE(dev
), mv88w8618_pic_set_irq
, 32);
765 sysbus_init_irq(dev
, &s
->parent_irq
);
766 memory_region_init_io(&s
->iomem
, obj
, &mv88w8618_pic_ops
, s
,
767 "musicpal-pic", MP_PIC_SIZE
);
768 sysbus_init_mmio(dev
, &s
->iomem
);
771 static const VMStateDescription mv88w8618_pic_vmsd
= {
772 .name
= "mv88w8618_pic",
774 .minimum_version_id
= 1,
775 .fields
= (VMStateField
[]) {
776 VMSTATE_UINT32(level
, mv88w8618_pic_state
),
777 VMSTATE_UINT32(enabled
, mv88w8618_pic_state
),
778 VMSTATE_END_OF_LIST()
782 static void mv88w8618_pic_class_init(ObjectClass
*klass
, void *data
)
784 DeviceClass
*dc
= DEVICE_CLASS(klass
);
786 dc
->reset
= mv88w8618_pic_reset
;
787 dc
->vmsd
= &mv88w8618_pic_vmsd
;
790 static const TypeInfo mv88w8618_pic_info
= {
791 .name
= TYPE_MV88W8618_PIC
,
792 .parent
= TYPE_SYS_BUS_DEVICE
,
793 .instance_size
= sizeof(mv88w8618_pic_state
),
794 .instance_init
= mv88w8618_pic_init
,
795 .class_init
= mv88w8618_pic_class_init
,
798 /* PIT register offsets */
799 #define MP_PIT_TIMER1_LENGTH 0x00
801 #define MP_PIT_TIMER4_LENGTH 0x0C
802 #define MP_PIT_CONTROL 0x10
803 #define MP_PIT_TIMER1_VALUE 0x14
805 #define MP_PIT_TIMER4_VALUE 0x20
806 #define MP_BOARD_RESET 0x34
808 /* Magic board reset value (probably some watchdog behind it) */
809 #define MP_BOARD_RESET_MAGIC 0x10000
811 typedef struct mv88w8618_timer_state
{
812 ptimer_state
*ptimer
;
816 } mv88w8618_timer_state
;
818 #define TYPE_MV88W8618_PIT "mv88w8618_pit"
819 #define MV88W8618_PIT(obj) \
820 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
822 typedef struct mv88w8618_pit_state
{
824 SysBusDevice parent_obj
;
828 mv88w8618_timer_state timer
[4];
829 } mv88w8618_pit_state
;
831 static void mv88w8618_timer_tick(void *opaque
)
833 mv88w8618_timer_state
*s
= opaque
;
835 qemu_irq_raise(s
->irq
);
838 static void mv88w8618_timer_init(SysBusDevice
*dev
, mv88w8618_timer_state
*s
,
843 sysbus_init_irq(dev
, &s
->irq
);
846 bh
= qemu_bh_new(mv88w8618_timer_tick
, s
);
847 s
->ptimer
= ptimer_init(bh
, PTIMER_POLICY_DEFAULT
);
850 static uint64_t mv88w8618_pit_read(void *opaque
, hwaddr offset
,
853 mv88w8618_pit_state
*s
= opaque
;
854 mv88w8618_timer_state
*t
;
857 case MP_PIT_TIMER1_VALUE
... MP_PIT_TIMER4_VALUE
:
858 t
= &s
->timer
[(offset
-MP_PIT_TIMER1_VALUE
) >> 2];
859 return ptimer_get_count(t
->ptimer
);
866 static void mv88w8618_pit_write(void *opaque
, hwaddr offset
,
867 uint64_t value
, unsigned size
)
869 mv88w8618_pit_state
*s
= opaque
;
870 mv88w8618_timer_state
*t
;
874 case MP_PIT_TIMER1_LENGTH
... MP_PIT_TIMER4_LENGTH
:
875 t
= &s
->timer
[offset
>> 2];
878 ptimer_set_limit(t
->ptimer
, t
->limit
, 1);
880 ptimer_stop(t
->ptimer
);
885 for (i
= 0; i
< 4; i
++) {
887 if (value
& 0xf && t
->limit
> 0) {
888 ptimer_set_limit(t
->ptimer
, t
->limit
, 0);
889 ptimer_set_freq(t
->ptimer
, t
->freq
);
890 ptimer_run(t
->ptimer
, 0);
892 ptimer_stop(t
->ptimer
);
899 if (value
== MP_BOARD_RESET_MAGIC
) {
900 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
906 static void mv88w8618_pit_reset(DeviceState
*d
)
908 mv88w8618_pit_state
*s
= MV88W8618_PIT(d
);
911 for (i
= 0; i
< 4; i
++) {
912 ptimer_stop(s
->timer
[i
].ptimer
);
913 s
->timer
[i
].limit
= 0;
917 static const MemoryRegionOps mv88w8618_pit_ops
= {
918 .read
= mv88w8618_pit_read
,
919 .write
= mv88w8618_pit_write
,
920 .endianness
= DEVICE_NATIVE_ENDIAN
,
923 static void mv88w8618_pit_init(Object
*obj
)
925 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
926 mv88w8618_pit_state
*s
= MV88W8618_PIT(dev
);
929 /* Letting them all run at 1 MHz is likely just a pragmatic
931 for (i
= 0; i
< 4; i
++) {
932 mv88w8618_timer_init(dev
, &s
->timer
[i
], 1000000);
935 memory_region_init_io(&s
->iomem
, obj
, &mv88w8618_pit_ops
, s
,
936 "musicpal-pit", MP_PIT_SIZE
);
937 sysbus_init_mmio(dev
, &s
->iomem
);
940 static const VMStateDescription mv88w8618_timer_vmsd
= {
943 .minimum_version_id
= 1,
944 .fields
= (VMStateField
[]) {
945 VMSTATE_PTIMER(ptimer
, mv88w8618_timer_state
),
946 VMSTATE_UINT32(limit
, mv88w8618_timer_state
),
947 VMSTATE_END_OF_LIST()
951 static const VMStateDescription mv88w8618_pit_vmsd
= {
952 .name
= "mv88w8618_pit",
954 .minimum_version_id
= 1,
955 .fields
= (VMStateField
[]) {
956 VMSTATE_STRUCT_ARRAY(timer
, mv88w8618_pit_state
, 4, 1,
957 mv88w8618_timer_vmsd
, mv88w8618_timer_state
),
958 VMSTATE_END_OF_LIST()
962 static void mv88w8618_pit_class_init(ObjectClass
*klass
, void *data
)
964 DeviceClass
*dc
= DEVICE_CLASS(klass
);
966 dc
->reset
= mv88w8618_pit_reset
;
967 dc
->vmsd
= &mv88w8618_pit_vmsd
;
970 static const TypeInfo mv88w8618_pit_info
= {
971 .name
= TYPE_MV88W8618_PIT
,
972 .parent
= TYPE_SYS_BUS_DEVICE
,
973 .instance_size
= sizeof(mv88w8618_pit_state
),
974 .instance_init
= mv88w8618_pit_init
,
975 .class_init
= mv88w8618_pit_class_init
,
978 /* Flash config register offsets */
979 #define MP_FLASHCFG_CFGR0 0x04
981 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
982 #define MV88W8618_FLASHCFG(obj) \
983 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
985 typedef struct mv88w8618_flashcfg_state
{
987 SysBusDevice parent_obj
;
992 } mv88w8618_flashcfg_state
;
994 static uint64_t mv88w8618_flashcfg_read(void *opaque
,
998 mv88w8618_flashcfg_state
*s
= opaque
;
1001 case MP_FLASHCFG_CFGR0
:
1009 static void mv88w8618_flashcfg_write(void *opaque
, hwaddr offset
,
1010 uint64_t value
, unsigned size
)
1012 mv88w8618_flashcfg_state
*s
= opaque
;
1015 case MP_FLASHCFG_CFGR0
:
1021 static const MemoryRegionOps mv88w8618_flashcfg_ops
= {
1022 .read
= mv88w8618_flashcfg_read
,
1023 .write
= mv88w8618_flashcfg_write
,
1024 .endianness
= DEVICE_NATIVE_ENDIAN
,
1027 static void mv88w8618_flashcfg_init(Object
*obj
)
1029 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1030 mv88w8618_flashcfg_state
*s
= MV88W8618_FLASHCFG(dev
);
1032 s
->cfgr0
= 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1033 memory_region_init_io(&s
->iomem
, obj
, &mv88w8618_flashcfg_ops
, s
,
1034 "musicpal-flashcfg", MP_FLASHCFG_SIZE
);
1035 sysbus_init_mmio(dev
, &s
->iomem
);
1038 static const VMStateDescription mv88w8618_flashcfg_vmsd
= {
1039 .name
= "mv88w8618_flashcfg",
1041 .minimum_version_id
= 1,
1042 .fields
= (VMStateField
[]) {
1043 VMSTATE_UINT32(cfgr0
, mv88w8618_flashcfg_state
),
1044 VMSTATE_END_OF_LIST()
1048 static void mv88w8618_flashcfg_class_init(ObjectClass
*klass
, void *data
)
1050 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1052 dc
->vmsd
= &mv88w8618_flashcfg_vmsd
;
1055 static const TypeInfo mv88w8618_flashcfg_info
= {
1056 .name
= TYPE_MV88W8618_FLASHCFG
,
1057 .parent
= TYPE_SYS_BUS_DEVICE
,
1058 .instance_size
= sizeof(mv88w8618_flashcfg_state
),
1059 .instance_init
= mv88w8618_flashcfg_init
,
1060 .class_init
= mv88w8618_flashcfg_class_init
,
1063 /* Misc register offsets */
1064 #define MP_MISC_BOARD_REVISION 0x18
1066 #define MP_BOARD_REVISION 0x31
1069 SysBusDevice parent_obj
;
1071 } MusicPalMiscState
;
1073 #define TYPE_MUSICPAL_MISC "musicpal-misc"
1074 #define MUSICPAL_MISC(obj) \
1075 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC)
1077 static uint64_t musicpal_misc_read(void *opaque
, hwaddr offset
,
1081 case MP_MISC_BOARD_REVISION
:
1082 return MP_BOARD_REVISION
;
1089 static void musicpal_misc_write(void *opaque
, hwaddr offset
,
1090 uint64_t value
, unsigned size
)
1094 static const MemoryRegionOps musicpal_misc_ops
= {
1095 .read
= musicpal_misc_read
,
1096 .write
= musicpal_misc_write
,
1097 .endianness
= DEVICE_NATIVE_ENDIAN
,
1100 static void musicpal_misc_init(Object
*obj
)
1102 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
1103 MusicPalMiscState
*s
= MUSICPAL_MISC(obj
);
1105 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_misc_ops
, NULL
,
1106 "musicpal-misc", MP_MISC_SIZE
);
1107 sysbus_init_mmio(sd
, &s
->iomem
);
1110 static const TypeInfo musicpal_misc_info
= {
1111 .name
= TYPE_MUSICPAL_MISC
,
1112 .parent
= TYPE_SYS_BUS_DEVICE
,
1113 .instance_init
= musicpal_misc_init
,
1114 .instance_size
= sizeof(MusicPalMiscState
),
1117 /* WLAN register offsets */
1118 #define MP_WLAN_MAGIC1 0x11c
1119 #define MP_WLAN_MAGIC2 0x124
1121 static uint64_t mv88w8618_wlan_read(void *opaque
, hwaddr offset
,
1125 /* Workaround to allow loading the binary-only wlandrv.ko crap
1126 * from the original Freecom firmware. */
1127 case MP_WLAN_MAGIC1
:
1129 case MP_WLAN_MAGIC2
:
1137 static void mv88w8618_wlan_write(void *opaque
, hwaddr offset
,
1138 uint64_t value
, unsigned size
)
1142 static const MemoryRegionOps mv88w8618_wlan_ops
= {
1143 .read
= mv88w8618_wlan_read
,
1144 .write
=mv88w8618_wlan_write
,
1145 .endianness
= DEVICE_NATIVE_ENDIAN
,
1148 static void mv88w8618_wlan_realize(DeviceState
*dev
, Error
**errp
)
1150 MemoryRegion
*iomem
= g_new(MemoryRegion
, 1);
1152 memory_region_init_io(iomem
, OBJECT(dev
), &mv88w8618_wlan_ops
, NULL
,
1153 "musicpal-wlan", MP_WLAN_SIZE
);
1154 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), iomem
);
1157 /* GPIO register offsets */
1158 #define MP_GPIO_OE_LO 0x008
1159 #define MP_GPIO_OUT_LO 0x00c
1160 #define MP_GPIO_IN_LO 0x010
1161 #define MP_GPIO_IER_LO 0x014
1162 #define MP_GPIO_IMR_LO 0x018
1163 #define MP_GPIO_ISR_LO 0x020
1164 #define MP_GPIO_OE_HI 0x508
1165 #define MP_GPIO_OUT_HI 0x50c
1166 #define MP_GPIO_IN_HI 0x510
1167 #define MP_GPIO_IER_HI 0x514
1168 #define MP_GPIO_IMR_HI 0x518
1169 #define MP_GPIO_ISR_HI 0x520
1171 /* GPIO bits & masks */
1172 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1173 #define MP_GPIO_I2C_DATA_BIT 29
1174 #define MP_GPIO_I2C_CLOCK_BIT 30
1176 /* LCD brightness bits in GPIO_OE_HI */
1177 #define MP_OE_LCD_BRIGHTNESS 0x0007
1179 #define TYPE_MUSICPAL_GPIO "musicpal_gpio"
1180 #define MUSICPAL_GPIO(obj) \
1181 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
1183 typedef struct musicpal_gpio_state
{
1185 SysBusDevice parent_obj
;
1189 uint32_t lcd_brightness
;
1196 qemu_irq out
[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1197 } musicpal_gpio_state
;
1199 static void musicpal_gpio_brightness_update(musicpal_gpio_state
*s
) {
1201 uint32_t brightness
;
1203 /* compute brightness ratio */
1204 switch (s
->lcd_brightness
) {
1238 /* set lcd brightness GPIOs */
1239 for (i
= 0; i
<= 2; i
++) {
1240 qemu_set_irq(s
->out
[i
], (brightness
>> i
) & 1);
1244 static void musicpal_gpio_pin_event(void *opaque
, int pin
, int level
)
1246 musicpal_gpio_state
*s
= opaque
;
1247 uint32_t mask
= 1 << pin
;
1248 uint32_t delta
= level
<< pin
;
1249 uint32_t old
= s
->in_state
& mask
;
1251 s
->in_state
&= ~mask
;
1252 s
->in_state
|= delta
;
1254 if ((old
^ delta
) &&
1255 ((level
&& (s
->imr
& mask
)) || (!level
&& (s
->ier
& mask
)))) {
1257 qemu_irq_raise(s
->irq
);
1261 static uint64_t musicpal_gpio_read(void *opaque
, hwaddr offset
,
1264 musicpal_gpio_state
*s
= opaque
;
1267 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1268 return s
->lcd_brightness
& MP_OE_LCD_BRIGHTNESS
;
1270 case MP_GPIO_OUT_LO
:
1271 return s
->out_state
& 0xFFFF;
1272 case MP_GPIO_OUT_HI
:
1273 return s
->out_state
>> 16;
1276 return s
->in_state
& 0xFFFF;
1278 return s
->in_state
>> 16;
1280 case MP_GPIO_IER_LO
:
1281 return s
->ier
& 0xFFFF;
1282 case MP_GPIO_IER_HI
:
1283 return s
->ier
>> 16;
1285 case MP_GPIO_IMR_LO
:
1286 return s
->imr
& 0xFFFF;
1287 case MP_GPIO_IMR_HI
:
1288 return s
->imr
>> 16;
1290 case MP_GPIO_ISR_LO
:
1291 return s
->isr
& 0xFFFF;
1292 case MP_GPIO_ISR_HI
:
1293 return s
->isr
>> 16;
1300 static void musicpal_gpio_write(void *opaque
, hwaddr offset
,
1301 uint64_t value
, unsigned size
)
1303 musicpal_gpio_state
*s
= opaque
;
1305 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1306 s
->lcd_brightness
= (s
->lcd_brightness
& MP_GPIO_LCD_BRIGHTNESS
) |
1307 (value
& MP_OE_LCD_BRIGHTNESS
);
1308 musicpal_gpio_brightness_update(s
);
1311 case MP_GPIO_OUT_LO
:
1312 s
->out_state
= (s
->out_state
& 0xFFFF0000) | (value
& 0xFFFF);
1314 case MP_GPIO_OUT_HI
:
1315 s
->out_state
= (s
->out_state
& 0xFFFF) | (value
<< 16);
1316 s
->lcd_brightness
= (s
->lcd_brightness
& 0xFFFF) |
1317 (s
->out_state
& MP_GPIO_LCD_BRIGHTNESS
);
1318 musicpal_gpio_brightness_update(s
);
1319 qemu_set_irq(s
->out
[3], (s
->out_state
>> MP_GPIO_I2C_DATA_BIT
) & 1);
1320 qemu_set_irq(s
->out
[4], (s
->out_state
>> MP_GPIO_I2C_CLOCK_BIT
) & 1);
1323 case MP_GPIO_IER_LO
:
1324 s
->ier
= (s
->ier
& 0xFFFF0000) | (value
& 0xFFFF);
1326 case MP_GPIO_IER_HI
:
1327 s
->ier
= (s
->ier
& 0xFFFF) | (value
<< 16);
1330 case MP_GPIO_IMR_LO
:
1331 s
->imr
= (s
->imr
& 0xFFFF0000) | (value
& 0xFFFF);
1333 case MP_GPIO_IMR_HI
:
1334 s
->imr
= (s
->imr
& 0xFFFF) | (value
<< 16);
1339 static const MemoryRegionOps musicpal_gpio_ops
= {
1340 .read
= musicpal_gpio_read
,
1341 .write
= musicpal_gpio_write
,
1342 .endianness
= DEVICE_NATIVE_ENDIAN
,
1345 static void musicpal_gpio_reset(DeviceState
*d
)
1347 musicpal_gpio_state
*s
= MUSICPAL_GPIO(d
);
1349 s
->lcd_brightness
= 0;
1351 s
->in_state
= 0xffffffff;
1357 static void musicpal_gpio_init(Object
*obj
)
1359 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1360 DeviceState
*dev
= DEVICE(sbd
);
1361 musicpal_gpio_state
*s
= MUSICPAL_GPIO(dev
);
1363 sysbus_init_irq(sbd
, &s
->irq
);
1365 memory_region_init_io(&s
->iomem
, obj
, &musicpal_gpio_ops
, s
,
1366 "musicpal-gpio", MP_GPIO_SIZE
);
1367 sysbus_init_mmio(sbd
, &s
->iomem
);
1369 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1371 qdev_init_gpio_in(dev
, musicpal_gpio_pin_event
, 32);
1374 static const VMStateDescription musicpal_gpio_vmsd
= {
1375 .name
= "musicpal_gpio",
1377 .minimum_version_id
= 1,
1378 .fields
= (VMStateField
[]) {
1379 VMSTATE_UINT32(lcd_brightness
, musicpal_gpio_state
),
1380 VMSTATE_UINT32(out_state
, musicpal_gpio_state
),
1381 VMSTATE_UINT32(in_state
, musicpal_gpio_state
),
1382 VMSTATE_UINT32(ier
, musicpal_gpio_state
),
1383 VMSTATE_UINT32(imr
, musicpal_gpio_state
),
1384 VMSTATE_UINT32(isr
, musicpal_gpio_state
),
1385 VMSTATE_END_OF_LIST()
1389 static void musicpal_gpio_class_init(ObjectClass
*klass
, void *data
)
1391 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1393 dc
->reset
= musicpal_gpio_reset
;
1394 dc
->vmsd
= &musicpal_gpio_vmsd
;
1397 static const TypeInfo musicpal_gpio_info
= {
1398 .name
= TYPE_MUSICPAL_GPIO
,
1399 .parent
= TYPE_SYS_BUS_DEVICE
,
1400 .instance_size
= sizeof(musicpal_gpio_state
),
1401 .instance_init
= musicpal_gpio_init
,
1402 .class_init
= musicpal_gpio_class_init
,
1405 /* Keyboard codes & masks */
1406 #define KEY_RELEASED 0x80
1407 #define KEY_CODE 0x7f
1409 #define KEYCODE_TAB 0x0f
1410 #define KEYCODE_ENTER 0x1c
1411 #define KEYCODE_F 0x21
1412 #define KEYCODE_M 0x32
1414 #define KEYCODE_EXTENDED 0xe0
1415 #define KEYCODE_UP 0x48
1416 #define KEYCODE_DOWN 0x50
1417 #define KEYCODE_LEFT 0x4b
1418 #define KEYCODE_RIGHT 0x4d
1420 #define MP_KEY_WHEEL_VOL (1 << 0)
1421 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1422 #define MP_KEY_WHEEL_NAV (1 << 2)
1423 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1424 #define MP_KEY_BTN_FAVORITS (1 << 4)
1425 #define MP_KEY_BTN_MENU (1 << 5)
1426 #define MP_KEY_BTN_VOLUME (1 << 6)
1427 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1429 #define TYPE_MUSICPAL_KEY "musicpal_key"
1430 #define MUSICPAL_KEY(obj) \
1431 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
1433 typedef struct musicpal_key_state
{
1435 SysBusDevice parent_obj
;
1439 uint32_t kbd_extended
;
1440 uint32_t pressed_keys
;
1442 } musicpal_key_state
;
1444 static void musicpal_key_event(void *opaque
, int keycode
)
1446 musicpal_key_state
*s
= opaque
;
1450 if (keycode
== KEYCODE_EXTENDED
) {
1451 s
->kbd_extended
= 1;
1455 if (s
->kbd_extended
) {
1456 switch (keycode
& KEY_CODE
) {
1458 event
= MP_KEY_WHEEL_NAV
| MP_KEY_WHEEL_NAV_INV
;
1462 event
= MP_KEY_WHEEL_NAV
;
1466 event
= MP_KEY_WHEEL_VOL
| MP_KEY_WHEEL_VOL_INV
;
1470 event
= MP_KEY_WHEEL_VOL
;
1474 switch (keycode
& KEY_CODE
) {
1476 event
= MP_KEY_BTN_FAVORITS
;
1480 event
= MP_KEY_BTN_VOLUME
;
1484 event
= MP_KEY_BTN_NAVIGATION
;
1488 event
= MP_KEY_BTN_MENU
;
1491 /* Do not repeat already pressed buttons */
1492 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1498 /* Raise GPIO pin first if repeating a key */
1499 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1500 for (i
= 0; i
<= 7; i
++) {
1501 if (event
& (1 << i
)) {
1502 qemu_set_irq(s
->out
[i
], 1);
1506 for (i
= 0; i
<= 7; i
++) {
1507 if (event
& (1 << i
)) {
1508 qemu_set_irq(s
->out
[i
], !!(keycode
& KEY_RELEASED
));
1511 if (keycode
& KEY_RELEASED
) {
1512 s
->pressed_keys
&= ~event
;
1514 s
->pressed_keys
|= event
;
1518 s
->kbd_extended
= 0;
1521 static void musicpal_key_init(Object
*obj
)
1523 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1524 DeviceState
*dev
= DEVICE(sbd
);
1525 musicpal_key_state
*s
= MUSICPAL_KEY(dev
);
1527 memory_region_init(&s
->iomem
, obj
, "dummy", 0);
1528 sysbus_init_mmio(sbd
, &s
->iomem
);
1530 s
->kbd_extended
= 0;
1531 s
->pressed_keys
= 0;
1533 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1535 qemu_add_kbd_event_handler(musicpal_key_event
, s
);
1538 static const VMStateDescription musicpal_key_vmsd
= {
1539 .name
= "musicpal_key",
1541 .minimum_version_id
= 1,
1542 .fields
= (VMStateField
[]) {
1543 VMSTATE_UINT32(kbd_extended
, musicpal_key_state
),
1544 VMSTATE_UINT32(pressed_keys
, musicpal_key_state
),
1545 VMSTATE_END_OF_LIST()
1549 static void musicpal_key_class_init(ObjectClass
*klass
, void *data
)
1551 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1553 dc
->vmsd
= &musicpal_key_vmsd
;
1556 static const TypeInfo musicpal_key_info
= {
1557 .name
= TYPE_MUSICPAL_KEY
,
1558 .parent
= TYPE_SYS_BUS_DEVICE
,
1559 .instance_size
= sizeof(musicpal_key_state
),
1560 .instance_init
= musicpal_key_init
,
1561 .class_init
= musicpal_key_class_init
,
1564 static struct arm_boot_info musicpal_binfo
= {
1565 .loader_start
= 0x0,
1569 static void musicpal_init(MachineState
*machine
)
1571 const char *kernel_filename
= machine
->kernel_filename
;
1572 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1573 const char *initrd_filename
= machine
->initrd_filename
;
1577 DeviceState
*i2c_dev
;
1578 DeviceState
*lcd_dev
;
1579 DeviceState
*key_dev
;
1580 DeviceState
*wm8750_dev
;
1584 unsigned long flash_size
;
1586 MemoryRegion
*address_space_mem
= get_system_memory();
1587 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1588 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1590 cpu
= ARM_CPU(cpu_create(machine
->cpu_type
));
1592 /* For now we use a fixed - the original - RAM size */
1593 memory_region_allocate_system_memory(ram
, NULL
, "musicpal.ram",
1594 MP_RAM_DEFAULT_SIZE
);
1595 memory_region_add_subregion(address_space_mem
, 0, ram
);
1597 memory_region_init_ram(sram
, NULL
, "musicpal.sram", MP_SRAM_SIZE
,
1599 memory_region_add_subregion(address_space_mem
, MP_SRAM_BASE
, sram
);
1601 dev
= sysbus_create_simple(TYPE_MV88W8618_PIC
, MP_PIC_BASE
,
1602 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
1603 for (i
= 0; i
< 32; i
++) {
1604 pic
[i
] = qdev_get_gpio_in(dev
, i
);
1606 sysbus_create_varargs(TYPE_MV88W8618_PIT
, MP_PIT_BASE
, pic
[MP_TIMER1_IRQ
],
1607 pic
[MP_TIMER2_IRQ
], pic
[MP_TIMER3_IRQ
],
1608 pic
[MP_TIMER4_IRQ
], NULL
);
1611 serial_mm_init(address_space_mem
, MP_UART1_BASE
, 2, pic
[MP_UART1_IRQ
],
1612 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN
);
1615 serial_mm_init(address_space_mem
, MP_UART2_BASE
, 2, pic
[MP_UART2_IRQ
],
1616 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN
);
1619 /* Register flash */
1620 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1622 BlockBackend
*blk
= blk_by_legacy_dinfo(dinfo
);
1624 flash_size
= blk_getlength(blk
);
1625 if (flash_size
!= 8*1024*1024 && flash_size
!= 16*1024*1024 &&
1626 flash_size
!= 32*1024*1024) {
1627 error_report("Invalid flash image size");
1632 * The original U-Boot accesses the flash at 0xFE000000 instead of
1633 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1634 * image is smaller than 32 MB.
1636 #ifdef TARGET_WORDS_BIGENDIAN
1637 pflash_cfi02_register(0x100000000ULL
- MP_FLASH_SIZE_MAX
,
1638 "musicpal.flash", flash_size
,
1640 MP_FLASH_SIZE_MAX
/ flash_size
,
1641 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1644 pflash_cfi02_register(0x100000000ULL
- MP_FLASH_SIZE_MAX
,
1645 "musicpal.flash", flash_size
,
1647 MP_FLASH_SIZE_MAX
/ flash_size
,
1648 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1653 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG
, MP_FLASHCFG_BASE
, NULL
);
1655 qemu_check_nic_model(&nd_table
[0], "mv88w8618");
1656 dev
= qdev_create(NULL
, TYPE_MV88W8618_ETH
);
1657 qdev_set_nic_properties(dev
, &nd_table
[0]);
1658 qdev_init_nofail(dev
);
1659 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, MP_ETH_BASE
);
1660 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[MP_ETH_IRQ
]);
1662 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE
, NULL
);
1664 sysbus_create_simple(TYPE_MUSICPAL_MISC
, MP_MISC_BASE
, NULL
);
1666 dev
= sysbus_create_simple(TYPE_MUSICPAL_GPIO
, MP_GPIO_BASE
,
1668 i2c_dev
= sysbus_create_simple("gpio_i2c", -1, NULL
);
1669 i2c
= (I2CBus
*)qdev_get_child_bus(i2c_dev
, "i2c");
1671 lcd_dev
= sysbus_create_simple(TYPE_MUSICPAL_LCD
, MP_LCD_BASE
, NULL
);
1672 key_dev
= sysbus_create_simple(TYPE_MUSICPAL_KEY
, -1, NULL
);
1675 qdev_connect_gpio_out(i2c_dev
, 0,
1676 qdev_get_gpio_in(dev
, MP_GPIO_I2C_DATA_BIT
));
1678 qdev_connect_gpio_out(dev
, 3, qdev_get_gpio_in(i2c_dev
, 0));
1680 qdev_connect_gpio_out(dev
, 4, qdev_get_gpio_in(i2c_dev
, 1));
1682 for (i
= 0; i
< 3; i
++) {
1683 qdev_connect_gpio_out(dev
, i
, qdev_get_gpio_in(lcd_dev
, i
));
1685 for (i
= 0; i
< 4; i
++) {
1686 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 8));
1688 for (i
= 4; i
< 8; i
++) {
1689 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 15));
1692 wm8750_dev
= i2c_create_slave(i2c
, TYPE_WM8750
, MP_WM_ADDR
);
1693 dev
= qdev_create(NULL
, TYPE_MV88W8618_AUDIO
);
1694 s
= SYS_BUS_DEVICE(dev
);
1695 object_property_set_link(OBJECT(dev
), OBJECT(wm8750_dev
),
1697 qdev_init_nofail(dev
);
1698 sysbus_mmio_map(s
, 0, MP_AUDIO_BASE
);
1699 sysbus_connect_irq(s
, 0, pic
[MP_AUDIO_IRQ
]);
1701 musicpal_binfo
.ram_size
= MP_RAM_DEFAULT_SIZE
;
1702 musicpal_binfo
.kernel_filename
= kernel_filename
;
1703 musicpal_binfo
.kernel_cmdline
= kernel_cmdline
;
1704 musicpal_binfo
.initrd_filename
= initrd_filename
;
1705 arm_load_kernel(cpu
, &musicpal_binfo
);
1708 static void musicpal_machine_init(MachineClass
*mc
)
1710 mc
->desc
= "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
1711 mc
->init
= musicpal_init
;
1712 mc
->ignore_memory_transaction_failures
= true;
1713 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
1716 DEFINE_MACHINE("musicpal", musicpal_machine_init
)
1718 static void mv88w8618_wlan_class_init(ObjectClass
*klass
, void *data
)
1720 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1722 dc
->realize
= mv88w8618_wlan_realize
;
1725 static const TypeInfo mv88w8618_wlan_info
= {
1726 .name
= "mv88w8618_wlan",
1727 .parent
= TYPE_SYS_BUS_DEVICE
,
1728 .instance_size
= sizeof(SysBusDevice
),
1729 .class_init
= mv88w8618_wlan_class_init
,
1732 static void musicpal_register_types(void)
1734 type_register_static(&mv88w8618_pic_info
);
1735 type_register_static(&mv88w8618_pit_info
);
1736 type_register_static(&mv88w8618_flashcfg_info
);
1737 type_register_static(&mv88w8618_eth_info
);
1738 type_register_static(&mv88w8618_wlan_info
);
1739 type_register_static(&musicpal_lcd_info
);
1740 type_register_static(&musicpal_gpio_info
);
1741 type_register_static(&musicpal_key_info
);
1742 type_register_static(&musicpal_misc_info
);
1745 type_init(musicpal_register_types
)