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[qemu/ar7.git] / hw / display / vga.c
blob53cc0cd6e19be56ba8f718276e0e5fe35ab04330
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "hw/hw.h"
27 #include "hw/display/vga.h"
28 #include "hw/pci/pci.h"
29 #include "vga_int.h"
30 #include "vga_regs.h"
31 #include "ui/pixel_ops.h"
32 #include "qemu/timer.h"
33 #include "hw/xen/xen.h"
34 #include "trace.h"
35
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
38
39 /* 16 state changes per vertical frame @60 Hz */
40 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
41
42 /*
43 * Video Graphics Array (VGA)
44 *
45 * Chipset docs for original IBM VGA:
46 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
47 *
48 * FreeVGA site:
49 * http://www.osdever.net/FreeVGA/home.htm
50 *
51 * Standard VGA features and Bochs VBE extensions are implemented.
52 */
53
54 /* force some bits to zero */
55 const uint8_t sr_mask[8] = {
56 0x03,
57 0x3d,
58 0x0f,
59 0x3f,
60 0x0e,
61 0x00,
62 0x00,
63 0xff,
64 };
65
66 const uint8_t gr_mask[16] = {
67 0x0f, /* 0x00 */
68 0x0f, /* 0x01 */
69 0x0f, /* 0x02 */
70 0x1f, /* 0x03 */
71 0x03, /* 0x04 */
72 0x7b, /* 0x05 */
73 0x0f, /* 0x06 */
74 0x0f, /* 0x07 */
75 0xff, /* 0x08 */
76 0x00, /* 0x09 */
77 0x00, /* 0x0a */
78 0x00, /* 0x0b */
79 0x00, /* 0x0c */
80 0x00, /* 0x0d */
81 0x00, /* 0x0e */
82 0x00, /* 0x0f */
83 };
84
85 #define cbswap_32(__x) \
86 ((uint32_t)( \
87 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
88 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
89 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
90 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
91
92 #ifdef HOST_WORDS_BIGENDIAN
93 #define PAT(x) cbswap_32(x)
94 #else
95 #define PAT(x) (x)
96 #endif
97
98 #ifdef HOST_WORDS_BIGENDIAN
99 #define BIG 1
100 #else
101 #define BIG 0
102 #endif
103
104 #ifdef HOST_WORDS_BIGENDIAN
105 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
106 #else
107 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
108 #endif
109
110 static const uint32_t mask16[16] = {
111 PAT(0x00000000),
112 PAT(0x000000ff),
113 PAT(0x0000ff00),
114 PAT(0x0000ffff),
115 PAT(0x00ff0000),
116 PAT(0x00ff00ff),
117 PAT(0x00ffff00),
118 PAT(0x00ffffff),
119 PAT(0xff000000),
120 PAT(0xff0000ff),
121 PAT(0xff00ff00),
122 PAT(0xff00ffff),
123 PAT(0xffff0000),
124 PAT(0xffff00ff),
125 PAT(0xffffff00),
126 PAT(0xffffffff),
127 };
128
129 #undef PAT
130
131 #ifdef HOST_WORDS_BIGENDIAN
132 #define PAT(x) (x)
133 #else
134 #define PAT(x) cbswap_32(x)
135 #endif
136
137 static uint32_t expand4[256];
138 static uint16_t expand2[256];
139 static uint8_t expand4to8[16];
140
141 static void vbe_update_vgaregs(VGACommonState *s);
142
143 static inline bool vbe_enabled(VGACommonState *s)
144 {
145 return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED;
146 }
147
148 static inline uint8_t sr(VGACommonState *s, int idx)
149 {
150 return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx];
151 }
152
153 static void vga_update_memory_access(VGACommonState *s)
154 {
155 hwaddr base, offset, size;
156
157 if (s->legacy_address_space == NULL) {
158 return;
159 }
160
161 if (s->has_chain4_alias) {
162 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
163 object_unparent(OBJECT(&s->chain4_alias));
164 s->has_chain4_alias = false;
165 s->plane_updated = 0xf;
166 }
167 if ((sr(s, VGA_SEQ_PLANE_WRITE) & VGA_SR02_ALL_PLANES) ==
168 VGA_SR02_ALL_PLANES && sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
169 offset = 0;
170 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
171 case 0:
172 base = 0xa0000;
173 size = 0x20000;
174 break;
175 case 1:
176 base = 0xa0000;
177 size = 0x10000;
178 offset = s->bank_offset;
179 break;
180 case 2:
181 base = 0xb0000;
182 size = 0x8000;
183 break;
184 case 3:
185 default:
186 base = 0xb8000;
187 size = 0x8000;
188 break;
189 }
190 assert(offset + size <= s->vram_size);
191 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
192 "vga.chain4", &s->vram, offset, size);
193 memory_region_add_subregion_overlap(s->legacy_address_space, base,
194 &s->chain4_alias, 2);
195 s->has_chain4_alias = true;
196 }
197 }
198
199 static void vga_dumb_update_retrace_info(VGACommonState *s)
200 {
201 (void) s;
202 }
203
204 static void vga_precise_update_retrace_info(VGACommonState *s)
205 {
206 int htotal_chars;
207 int hretr_start_char;
208 int hretr_skew_chars;
209 int hretr_end_char;
210
211 int vtotal_lines;
212 int vretr_start_line;
213 int vretr_end_line;
214
215 int dots;
216 #if 0
217 int div2, sldiv2;
218 #endif
219 int clocking_mode;
220 int clock_sel;
221 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
222 int64_t chars_per_sec;
223 struct vga_precise_retrace *r = &s->retrace_info.precise;
224
225 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
226 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
227 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
228 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
229
230 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
231 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
232 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
233 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
234 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
235 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
236 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
237
238 clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1;
239 clock_sel = (s->msr >> 2) & 3;
240 dots = (s->msr & 1) ? 8 : 9;
241
242 chars_per_sec = clk_hz[clock_sel] / dots;
243
244 htotal_chars <<= clocking_mode;
245
246 r->total_chars = vtotal_lines * htotal_chars;
247 if (r->freq) {
248 r->ticks_per_char = NANOSECONDS_PER_SECOND / (r->total_chars * r->freq);
249 } else {
250 r->ticks_per_char = NANOSECONDS_PER_SECOND / chars_per_sec;
251 }
252
253 r->vstart = vretr_start_line;
254 r->vend = r->vstart + vretr_end_line + 1;
255
256 r->hstart = hretr_start_char + hretr_skew_chars;
257 r->hend = r->hstart + hretr_end_char + 1;
258 r->htotal = htotal_chars;
259
260 #if 0
261 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
262 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
263 fprintf(stderr,
264 "hz=%f\n"
265 "htotal = %d\n"
266 "hretr_start = %d\n"
267 "hretr_skew = %d\n"
268 "hretr_end = %d\n"
269 "vtotal = %d\n"
270 "vretr_start = %d\n"
271 "vretr_end = %d\n"
272 "div2 = %d sldiv2 = %d\n"
273 "clocking_mode = %d\n"
274 "clock_sel = %d %d\n"
275 "dots = %d\n"
276 "ticks/char = %" PRId64 "\n"
277 "\n",
278 (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),
279 htotal_chars,
280 hretr_start_char,
281 hretr_skew_chars,
282 hretr_end_char,
283 vtotal_lines,
284 vretr_start_line,
285 vretr_end_line,
286 div2, sldiv2,
287 clocking_mode,
288 clock_sel,
289 clk_hz[clock_sel],
290 dots,
291 r->ticks_per_char
292 );
293 #endif
294 }
295
296 static uint8_t vga_precise_retrace(VGACommonState *s)
297 {
298 struct vga_precise_retrace *r = &s->retrace_info.precise;
299 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
300
301 if (r->total_chars) {
302 int cur_line, cur_line_char, cur_char;
303 int64_t cur_tick;
304
305 cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
306
307 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
308 cur_line = cur_char / r->htotal;
309
310 if (cur_line >= r->vstart && cur_line <= r->vend) {
311 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
312 } else {
313 cur_line_char = cur_char % r->htotal;
314 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
315 val |= ST01_DISP_ENABLE;
316 }
317 }
318
319 return val;
320 } else {
321 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
322 }
323 }
324
325 static uint8_t vga_dumb_retrace(VGACommonState *s)
326 {
327 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
328 }
329
330 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
331 {
332 if (s->msr & VGA_MIS_COLOR) {
333 /* Color */
334 return (addr >= 0x3b0 && addr <= 0x3bf);
335 } else {
336 /* Monochrome */
337 return (addr >= 0x3d0 && addr <= 0x3df);
338 }
339 }
340
341 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
342 {
343 VGACommonState *s = opaque;
344 int val, index;
345
346 if (vga_ioport_invalid(s, addr)) {
347 val = 0xff;
348 } else {
349 switch(addr) {
350 case VGA_ATT_W:
351 if (s->ar_flip_flop == 0) {
352 val = s->ar_index;
353 } else {
354 val = 0;
355 }
356 break;
357 case VGA_ATT_R:
358 index = s->ar_index & 0x1f;
359 if (index < VGA_ATT_C) {
360 val = s->ar[index];
361 } else {
362 val = 0;
363 }
364 break;
365 case VGA_MIS_W:
366 val = s->st00;
367 break;
368 case VGA_SEQ_I:
369 val = s->sr_index;
370 break;
371 case VGA_SEQ_D:
372 val = s->sr[s->sr_index];
373 #ifdef DEBUG_VGA_REG
374 fprintf(stderr, "vga: read SR%x = 0x%02x\n", s->sr_index, val);
375 #endif
376 break;
377 case VGA_PEL_IR:
378 val = s->dac_state;
379 break;
380 case VGA_PEL_IW:
381 val = s->dac_write_index;
382 break;
383 case VGA_PEL_D:
384 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
385 if (++s->dac_sub_index == 3) {
386 s->dac_sub_index = 0;
387 s->dac_read_index++;
388 }
389 break;
390 case VGA_FTC_R:
391 val = s->fcr;
392 break;
393 case VGA_MIS_R:
394 val = s->msr;
395 break;
396 case VGA_GFX_I:
397 val = s->gr_index;
398 break;
399 case VGA_GFX_D:
400 val = s->gr[s->gr_index];
401 #ifdef DEBUG_VGA_REG
402 fprintf(stderr, "vga: read GR%x = 0x%02x\n", s->gr_index, val);
403 #endif
404 break;
405 case VGA_CRT_IM:
406 case VGA_CRT_IC:
407 val = s->cr_index;
408 break;
409 case VGA_CRT_DM:
410 case VGA_CRT_DC:
411 val = s->cr[s->cr_index];
412 #ifdef DEBUG_VGA_REG
413 fprintf(stderr, "vga: read CR%x = 0x%02x\n", s->cr_index, val);
414 #endif
415 break;
416 case VGA_IS1_RM:
417 case VGA_IS1_RC:
418 /* just toggle to fool polling */
419 val = s->st01 = s->retrace(s);
420 s->ar_flip_flop = 0;
421 break;
422 default:
423 val = 0x00;
424 break;
425 }
426 }
427 trace_vga_std_read_io(addr, val);
428 return val;
429 }
430
431 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
432 {
433 VGACommonState *s = opaque;
434 int index;
435
436 /* check port range access depending on color/monochrome mode */
437 if (vga_ioport_invalid(s, addr)) {
438 return;
439 }
440 trace_vga_std_write_io(addr, val);
441
442 switch(addr) {
443 case VGA_ATT_W:
444 if (s->ar_flip_flop == 0) {
445 val &= 0x3f;
446 s->ar_index = val;
447 } else {
448 index = s->ar_index & 0x1f;
449 switch(index) {
450 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
451 s->ar[index] = val & 0x3f;
452 break;
453 case VGA_ATC_MODE:
454 s->ar[index] = val & ~0x10;
455 break;
456 case VGA_ATC_OVERSCAN:
457 s->ar[index] = val;
458 break;
459 case VGA_ATC_PLANE_ENABLE:
460 s->ar[index] = val & ~0xc0;
461 break;
462 case VGA_ATC_PEL:
463 s->ar[index] = val & ~0xf0;
464 break;
465 case VGA_ATC_COLOR_PAGE:
466 s->ar[index] = val & ~0xf0;
467 break;
468 default:
469 break;
470 }
471 }
472 s->ar_flip_flop ^= 1;
473 break;
474 case VGA_MIS_W:
475 s->msr = val & ~0x10;
476 s->update_retrace_info(s);
477 break;
478 case VGA_SEQ_I:
479 s->sr_index = val & 7;
480 break;
481 case VGA_SEQ_D:
482 #ifdef DEBUG_VGA_REG
483 fprintf(stderr, "vga: write SR%x = 0x%02x\n", s->sr_index, val);
484 #endif
485 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
486 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
487 s->update_retrace_info(s);
488 }
489 vga_update_memory_access(s);
490 break;
491 case VGA_PEL_IR:
492 s->dac_read_index = val;
493 s->dac_sub_index = 0;
494 s->dac_state = 3;
495 break;
496 case VGA_PEL_IW:
497 s->dac_write_index = val;
498 s->dac_sub_index = 0;
499 s->dac_state = 0;
500 break;
501 case VGA_PEL_D:
502 s->dac_cache[s->dac_sub_index] = val;
503 if (++s->dac_sub_index == 3) {
504 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
505 s->dac_sub_index = 0;
506 s->dac_write_index++;
507 }
508 break;
509 case VGA_GFX_I:
510 s->gr_index = val & 0x0f;
511 break;
512 case VGA_GFX_D:
513 #ifdef DEBUG_VGA_REG
514 fprintf(stderr, "vga: write GR%x = 0x%02x\n", s->gr_index, val);
515 #endif
516 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
517 vbe_update_vgaregs(s);
518 vga_update_memory_access(s);
519 break;
520 case VGA_CRT_IM:
521 case VGA_CRT_IC:
522 s->cr_index = val;
523 break;
524 case VGA_CRT_DM:
525 case VGA_CRT_DC:
526 #ifdef DEBUG_VGA_REG
527 fprintf(stderr, "vga: write CR%x = 0x%02x\n", s->cr_index, val);
528 #endif
529 /* handle CR0-7 protection */
530 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
531 s->cr_index <= VGA_CRTC_OVERFLOW) {
532 /* can always write bit 4 of CR7 */
533 if (s->cr_index == VGA_CRTC_OVERFLOW) {
534 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
535 (val & 0x10);
536 vbe_update_vgaregs(s);
537 }
538 return;
539 }
540 s->cr[s->cr_index] = val;
541 vbe_update_vgaregs(s);
542
543 switch(s->cr_index) {
544 case VGA_CRTC_H_TOTAL:
545 case VGA_CRTC_H_SYNC_START:
546 case VGA_CRTC_H_SYNC_END:
547 case VGA_CRTC_V_TOTAL:
548 case VGA_CRTC_OVERFLOW:
549 case VGA_CRTC_V_SYNC_END:
550 case VGA_CRTC_MODE:
551 s->update_retrace_info(s);
552 break;
553 }
554 break;
555 case VGA_IS1_RM:
556 case VGA_IS1_RC:
557 s->fcr = val & 0x10;
558 break;
559 }
560 }
561
562 /*
563 * Sanity check vbe register writes.
564 *
565 * As we don't have a way to signal errors to the guest in the bochs
566 * dispi interface we'll go adjust the registers to the closest valid
567 * value.
568 */
569 static void vbe_fixup_regs(VGACommonState *s)
570 {
571 uint16_t *r = s->vbe_regs;
572 uint32_t bits, linelength, maxy, offset;
573
574 if (!vbe_enabled(s)) {
575 /* vbe is turned off -- nothing to do */
576 return;
577 }
578
579 /* check depth */
580 switch (r[VBE_DISPI_INDEX_BPP]) {
581 case 4:
582 case 8:
583 case 16:
584 case 24:
585 case 32:
586 bits = r[VBE_DISPI_INDEX_BPP];
587 break;
588 case 15:
589 bits = 16;
590 break;
591 default:
592 bits = r[VBE_DISPI_INDEX_BPP] = 8;
593 break;
594 }
595
596 /* check width */
597 r[VBE_DISPI_INDEX_XRES] &= ~7u;
598 if (r[VBE_DISPI_INDEX_XRES] == 0) {
599 r[VBE_DISPI_INDEX_XRES] = 8;
600 }
601 if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
602 r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
603 }
604 r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
605 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
606 r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
607 }
608 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
609 r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
610 }
611
612 /* check height */
613 linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
614 maxy = s->vbe_size / linelength;
615 if (r[VBE_DISPI_INDEX_YRES] == 0) {
616 r[VBE_DISPI_INDEX_YRES] = 1;
617 }
618 if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
619 r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
620 }
621 if (r[VBE_DISPI_INDEX_YRES] > maxy) {
622 r[VBE_DISPI_INDEX_YRES] = maxy;
623 }
624
625 /* check offset */
626 if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
627 r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
628 }
629 if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
630 r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
631 }
632 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
633 offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
634 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
635 r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
636 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
637 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
638 r[VBE_DISPI_INDEX_X_OFFSET] = 0;
639 offset = 0;
640 }
641 }
642
643 /* update vga state */
644 r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
645 s->vbe_line_offset = linelength;
646 s->vbe_start_addr = offset / 4;
647 }
648
649 /* we initialize the VGA graphic mode */
650 static void vbe_update_vgaregs(VGACommonState *s)
651 {
652 int h, shift_control;
653
654 if (!vbe_enabled(s)) {
655 /* vbe is turned off -- nothing to do */
656 return;
657 }
658
659 /* graphic mode + memory map 1 */
660 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
661 VGA_GR06_GRAPHICS_MODE;
662 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
663 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
664 /* width */
665 s->cr[VGA_CRTC_H_DISP] =
666 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
667 /* height (only meaningful if < 1024) */
668 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
669 s->cr[VGA_CRTC_V_DISP_END] = h;
670 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
671 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
672 /* line compare to 1023 */
673 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
674 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
675 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
676
677 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
678 shift_control = 0;
679 s->sr_vbe[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
680 } else {
681 shift_control = 2;
682 /* set chain 4 mode */
683 s->sr_vbe[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
684 /* activate all planes */
685 s->sr_vbe[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
686 }
687 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
688 (shift_control << 5);
689 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
690 }
691
692 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
693 {
694 VGACommonState *s = opaque;
695 return s->vbe_index;
696 }
697
698 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
699 {
700 VGACommonState *s = opaque;
701 uint32_t val;
702
703 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
704 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
705 switch(s->vbe_index) {
706 /* XXX: do not hardcode ? */
707 case VBE_DISPI_INDEX_XRES:
708 val = VBE_DISPI_MAX_XRES;
709 break;
710 case VBE_DISPI_INDEX_YRES:
711 val = VBE_DISPI_MAX_YRES;
712 break;
713 case VBE_DISPI_INDEX_BPP:
714 val = VBE_DISPI_MAX_BPP;
715 break;
716 default:
717 val = s->vbe_regs[s->vbe_index];
718 break;
719 }
720 } else {
721 val = s->vbe_regs[s->vbe_index];
722 }
723 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
724 val = s->vbe_size / (64 * 1024);
725 } else {
726 val = 0;
727 }
728 trace_vga_vbe_read(s->vbe_index, val);
729 return val;
730 }
731
732 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
733 {
734 VGACommonState *s = opaque;
735 s->vbe_index = val;
736 }
737
738 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
739 {
740 VGACommonState *s = opaque;
741
742 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
743 trace_vga_vbe_write(s->vbe_index, val);
744 switch(s->vbe_index) {
745 case VBE_DISPI_INDEX_ID:
746 if (val == VBE_DISPI_ID0 ||
747 val == VBE_DISPI_ID1 ||
748 val == VBE_DISPI_ID2 ||
749 val == VBE_DISPI_ID3 ||
750 val == VBE_DISPI_ID4) {
751 s->vbe_regs[s->vbe_index] = val;
752 }
753 break;
754 case VBE_DISPI_INDEX_XRES:
755 case VBE_DISPI_INDEX_YRES:
756 case VBE_DISPI_INDEX_BPP:
757 case VBE_DISPI_INDEX_VIRT_WIDTH:
758 case VBE_DISPI_INDEX_X_OFFSET:
759 case VBE_DISPI_INDEX_Y_OFFSET:
760 s->vbe_regs[s->vbe_index] = val;
761 vbe_fixup_regs(s);
762 vbe_update_vgaregs(s);
763 break;
764 case VBE_DISPI_INDEX_BANK:
765 val &= s->vbe_bank_mask;
766 s->vbe_regs[s->vbe_index] = val;
767 s->bank_offset = (val << 16);
768 vga_update_memory_access(s);
769 break;
770 case VBE_DISPI_INDEX_ENABLE:
771 if ((val & VBE_DISPI_ENABLED) &&
772 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
773
774 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
775 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
776 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
777 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
778 vbe_fixup_regs(s);
779 vbe_update_vgaregs(s);
780
781 /* clear the screen */
782 if (!(val & VBE_DISPI_NOCLEARMEM)) {
783 memset(s->vram_ptr, 0,
784 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
785 }
786 } else {
787 s->bank_offset = 0;
788 }
789 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
790 s->vbe_regs[s->vbe_index] = val;
791 vga_update_memory_access(s);
792 break;
793 default:
794 break;
795 }
796 }
797 }
798
799 /* called for accesses between 0xa0000 and 0xc0000 */
800 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
801 {
802 int memory_map_mode, plane;
803 uint32_t ret;
804
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
807 addr &= 0x1ffff;
808 switch(memory_map_mode) {
809 case 0:
810 break;
811 case 1:
812 if (addr >= 0x10000)
813 return 0xff;
814 addr += s->bank_offset;
815 break;
816 case 2:
817 addr -= 0x10000;
818 if (addr >= 0x8000)
819 return 0xff;
820 break;
821 default:
822 case 3:
823 addr -= 0x18000;
824 if (addr >= 0x8000)
825 return 0xff;
826 break;
827 }
828
829 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
830 /* chain 4 mode : simplest access */
831 assert(addr < s->vram_size);
832 ret = s->vram_ptr[addr];
833 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
834 /* odd/even mode (aka text mode mapping) */
835 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
836 addr = ((addr & ~1) << 1) | plane;
837 if (addr >= s->vram_size) {
838 return 0xff;
839 }
840 ret = s->vram_ptr[addr];
841 } else {
842 /* standard VGA latched access */
843 if (addr * sizeof(uint32_t) >= s->vram_size) {
844 return 0xff;
845 }
846 s->latch = ((uint32_t *)s->vram_ptr)[addr];
847
848 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
849 /* read mode 0 */
850 plane = s->gr[VGA_GFX_PLANE_READ];
851 ret = GET_PLANE(s->latch, plane);
852 } else {
853 /* read mode 1 */
854 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
855 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
856 ret |= ret >> 16;
857 ret |= ret >> 8;
858 ret = (~ret) & 0xff;
859 }
860 }
861 return ret;
862 }
863
864 /* called for accesses between 0xa0000 and 0xc0000 */
865 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
866 {
867 int memory_map_mode, plane, write_mode, b, func_select, mask;
868 uint32_t write_mask, bit_mask, set_mask;
869
870 #ifdef DEBUG_VGA_MEM
871 fprintf(stderr, "vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
872 #endif
873 /* convert to VGA memory offset */
874 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
875 addr &= 0x1ffff;
876 switch(memory_map_mode) {
877 case 0:
878 break;
879 case 1:
880 if (addr >= 0x10000)
881 return;
882 addr += s->bank_offset;
883 break;
884 case 2:
885 addr -= 0x10000;
886 if (addr >= 0x8000)
887 return;
888 break;
889 default:
890 case 3:
891 addr -= 0x18000;
892 if (addr >= 0x8000)
893 return;
894 break;
895 }
896
897 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
898 /* chain 4 mode : simplest access */
899 plane = addr & 3;
900 mask = (1 << plane);
901 if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
902 assert(addr < s->vram_size);
903 s->vram_ptr[addr] = val;
904 #ifdef DEBUG_VGA_MEM
905 fprintf(stderr, "vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
906 #endif
907 s->plane_updated |= mask; /* only used to detect font change */
908 memory_region_set_dirty(&s->vram, addr, 1);
909 }
910 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
911 /* odd/even mode (aka text mode mapping) */
912 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
913 mask = (1 << plane);
914 if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
915 addr = ((addr & ~1) << 1) | plane;
916 if (addr >= s->vram_size) {
917 return;
918 }
919 s->vram_ptr[addr] = val;
920 #ifdef DEBUG_VGA_MEM
921 fprintf(stderr, "vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
922 #endif
923 s->plane_updated |= mask; /* only used to detect font change */
924 memory_region_set_dirty(&s->vram, addr, 1);
925 }
926 } else {
927 /* standard VGA latched access */
928 write_mode = s->gr[VGA_GFX_MODE] & 3;
929 switch(write_mode) {
930 default:
931 case 0:
932 /* rotate */
933 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
934 val = ((val >> b) | (val << (8 - b))) & 0xff;
935 val |= val << 8;
936 val |= val << 16;
937
938 /* apply set/reset mask */
939 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
940 val = (val & ~set_mask) |
941 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
942 bit_mask = s->gr[VGA_GFX_BIT_MASK];
943 break;
944 case 1:
945 val = s->latch;
946 goto do_write;
947 case 2:
948 val = mask16[val & 0x0f];
949 bit_mask = s->gr[VGA_GFX_BIT_MASK];
950 break;
951 case 3:
952 /* rotate */
953 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
954 val = (val >> b) | (val << (8 - b));
955
956 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
957 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
958 break;
959 }
960
961 /* apply logical operation */
962 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
963 switch(func_select) {
964 case 0:
965 default:
966 /* nothing to do */
967 break;
968 case 1:
969 /* and */
970 val &= s->latch;
971 break;
972 case 2:
973 /* or */
974 val |= s->latch;
975 break;
976 case 3:
977 /* xor */
978 val ^= s->latch;
979 break;
980 }
981
982 /* apply bit mask */
983 bit_mask |= bit_mask << 8;
984 bit_mask |= bit_mask << 16;
985 val = (val & bit_mask) | (s->latch & ~bit_mask);
986
987 do_write:
988 /* mask data according to sr[2] */
989 mask = sr(s, VGA_SEQ_PLANE_WRITE);
990 s->plane_updated |= mask; /* only used to detect font change */
991 write_mask = mask16[mask];
992 if (addr * sizeof(uint32_t) >= s->vram_size) {
993 return;
994 }
995 ((uint32_t *)s->vram_ptr)[addr] =
996 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
997 (val & write_mask);
998 #ifdef DEBUG_VGA_MEM
999 fprintf(stderr,
1000 "vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
1001 addr * 4, write_mask, val);
1002 #endif
1003 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
1004 }
1005 }
1006
1007 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1008 uint32_t srcaddr, int width);
1009
1010 #include "vga-helpers.h"
1011
1012 /* return true if the palette was modified */
1013 static int update_palette16(VGACommonState *s)
1014 {
1015 int full_update, i;
1016 uint32_t v, col, *palette;
1017
1018 full_update = 0;
1019 palette = s->last_palette;
1020 for(i = 0; i < 16; i++) {
1021 v = s->ar[i];
1022 if (s->ar[VGA_ATC_MODE] & 0x80) {
1023 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1024 } else {
1025 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1026 }
1027 v = v * 3;
1028 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1029 c6_to_8(s->palette[v + 1]),
1030 c6_to_8(s->palette[v + 2]));
1031 if (col != palette[i]) {
1032 full_update = 1;
1033 palette[i] = col;
1034 }
1035 }
1036 return full_update;
1037 }
1038
1039 /* return true if the palette was modified */
1040 static int update_palette256(VGACommonState *s)
1041 {
1042 int full_update, i;
1043 uint32_t v, col, *palette;
1044
1045 full_update = 0;
1046 palette = s->last_palette;
1047 v = 0;
1048 for(i = 0; i < 256; i++) {
1049 if (s->dac_8bit) {
1050 col = rgb_to_pixel32(s->palette[v],
1051 s->palette[v + 1],
1052 s->palette[v + 2]);
1053 } else {
1054 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1055 c6_to_8(s->palette[v + 1]),
1056 c6_to_8(s->palette[v + 2]));
1057 }
1058 if (col != palette[i]) {
1059 full_update = 1;
1060 palette[i] = col;
1061 }
1062 v += 3;
1063 }
1064 return full_update;
1065 }
1066
1067 static void vga_get_offsets(VGACommonState *s,
1068 uint32_t *pline_offset,
1069 uint32_t *pstart_addr,
1070 uint32_t *pline_compare)
1071 {
1072 uint32_t start_addr, line_offset, line_compare;
1073
1074 if (vbe_enabled(s)) {
1075 line_offset = s->vbe_line_offset;
1076 start_addr = s->vbe_start_addr;
1077 line_compare = 65535;
1078 } else {
1079 /* compute line_offset in bytes */
1080 line_offset = s->cr[VGA_CRTC_OFFSET];
1081 line_offset <<= 3;
1082
1083 /* starting address */
1084 start_addr = s->cr[VGA_CRTC_START_LO] |
1085 (s->cr[VGA_CRTC_START_HI] << 8);
1086
1087 /* line compare */
1088 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1089 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1090 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1091 }
1092 *pline_offset = line_offset;
1093 *pstart_addr = start_addr;
1094 *pline_compare = line_compare;
1095 }
1096
1097 /* update start_addr and line_offset. Return TRUE if modified */
1098 static int update_basic_params(VGACommonState *s)
1099 {
1100 int full_update;
1101 uint32_t start_addr, line_offset, line_compare;
1102
1103 full_update = 0;
1104
1105 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1106
1107 if (line_offset != s->line_offset ||
1108 start_addr != s->start_addr ||
1109 line_compare != s->line_compare) {
1110 s->line_offset = line_offset;
1111 s->start_addr = start_addr;
1112 s->line_compare = line_compare;
1113 full_update = 1;
1114 }
1115 return full_update;
1116 }
1117
1118
1119 static const uint8_t cursor_glyph[32 * 4] = {
1120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 };
1137
1138 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1139 int *pcwidth, int *pcheight)
1140 {
1141 int width, cwidth, height, cheight;
1142
1143 /* total width & height */
1144 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1145 cwidth = 8;
1146 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
1147 cwidth = 9;
1148 }
1149 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
1150 cwidth = 16; /* NOTE: no 18 pixel wide */
1151 }
1152 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1153 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1154 /* ugly hack for CGA 160x100x16 - explain me the logic */
1155 height = 100;
1156 } else {
1157 height = s->cr[VGA_CRTC_V_DISP_END] |
1158 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1159 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1160 height = (height + 1) / cheight;
1161 }
1162
1163 *pwidth = width;
1164 *pheight = height;
1165 *pcwidth = cwidth;
1166 *pcheight = cheight;
1167 }
1168
1169 /*
1170 * Text mode update
1171 * Missing:
1172 * - double scan
1173 * - double width
1174 * - underline
1175 * - flashing
1176 */
1177 static void vga_draw_text(VGACommonState *s, int full_update)
1178 {
1179 DisplaySurface *surface = qemu_console_surface(s->con);
1180 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1181 int cx_min, cx_max, linesize, x_incr, line, line1;
1182 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1183 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1184 const uint8_t *font_ptr, *font_base[2];
1185 int dup9, line_offset;
1186 uint32_t *palette;
1187 uint32_t *ch_attr_ptr;
1188 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1189
1190 /* compute font data address (in plane 2) */
1191 v = sr(s, VGA_SEQ_CHARACTER_MAP);
1192 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1193 if (offset != s->font_offsets[0]) {
1194 s->font_offsets[0] = offset;
1195 full_update = 1;
1196 }
1197 font_base[0] = s->vram_ptr + offset;
1198
1199 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1200 font_base[1] = s->vram_ptr + offset;
1201 if (offset != s->font_offsets[1]) {
1202 s->font_offsets[1] = offset;
1203 full_update = 1;
1204 }
1205 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
1206 /* if the plane 2 was modified since the last display, it
1207 indicates the font may have been modified */
1208 s->plane_updated = 0;
1209 full_update = 1;
1210 }
1211 full_update |= update_basic_params(s);
1212
1213 line_offset = s->line_offset;
1214
1215 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1216 if ((height * width) <= 1) {
1217 /* better than nothing: exit if transient size is too small */
1218 return;
1219 }
1220 if ((height * width) > CH_ATTR_SIZE) {
1221 /* better than nothing: exit if transient size is too big */
1222 return;
1223 }
1224
1225 if (width != s->last_width || height != s->last_height ||
1226 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1227 s->last_scr_width = width * cw;
1228 s->last_scr_height = height * cheight;
1229 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1230 surface = qemu_console_surface(s->con);
1231 dpy_text_resize(s->con, width, height);
1232 s->last_depth = 0;
1233 s->last_width = width;
1234 s->last_height = height;
1235 s->last_ch = cheight;
1236 s->last_cw = cw;
1237 full_update = 1;
1238 }
1239 full_update |= update_palette16(s);
1240 palette = s->last_palette;
1241 x_incr = cw * surface_bytes_per_pixel(surface);
1242
1243 if (full_update) {
1244 s->full_update_text = 1;
1245 }
1246 if (s->full_update_gfx) {
1247 s->full_update_gfx = 0;
1248 full_update |= 1;
1249 }
1250
1251 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1252 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1253 if (cursor_offset != s->cursor_offset ||
1254 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1255 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1256 /* if the cursor position changed, we update the old and new
1257 chars */
1258 if (s->cursor_offset < CH_ATTR_SIZE)
1259 s->last_ch_attr[s->cursor_offset] = -1;
1260 if (cursor_offset < CH_ATTR_SIZE)
1261 s->last_ch_attr[cursor_offset] = -1;
1262 s->cursor_offset = cursor_offset;
1263 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1264 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1265 }
1266 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1267 if (now >= s->cursor_blink_time) {
1268 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1269 s->cursor_visible_phase = !s->cursor_visible_phase;
1270 }
1271
1272 dest = surface_data(surface);
1273 linesize = surface_stride(surface);
1274 ch_attr_ptr = s->last_ch_attr;
1275 line = 0;
1276 offset = s->start_addr * 4;
1277 for(cy = 0; cy < height; cy++) {
1278 d1 = dest;
1279 src = s->vram_ptr + offset;
1280 cx_min = width;
1281 cx_max = -1;
1282 for(cx = 0; cx < width; cx++) {
1283 if (src + sizeof(uint16_t) > s->vram_ptr + s->vram_size) {
1284 break;
1285 }
1286 ch_attr = *(uint16_t *)src;
1287 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1288 if (cx < cx_min)
1289 cx_min = cx;
1290 if (cx > cx_max)
1291 cx_max = cx;
1292 *ch_attr_ptr = ch_attr;
1293 #ifdef HOST_WORDS_BIGENDIAN
1294 ch = ch_attr >> 8;
1295 cattr = ch_attr & 0xff;
1296 #else
1297 ch = ch_attr & 0xff;
1298 cattr = ch_attr >> 8;
1299 #endif
1300 font_ptr = font_base[(cattr >> 3) & 1];
1301 font_ptr += 32 * 4 * ch;
1302 bgcol = palette[cattr >> 4];
1303 fgcol = palette[cattr & 0x0f];
1304 if (cw == 16) {
1305 vga_draw_glyph16(d1, linesize,
1306 font_ptr, cheight, fgcol, bgcol);
1307 } else if (cw != 9) {
1308 vga_draw_glyph8(d1, linesize,
1309 font_ptr, cheight, fgcol, bgcol);
1310 } else {
1311 dup9 = 0;
1312 if (ch >= 0xb0 && ch <= 0xdf &&
1313 (s->ar[VGA_ATC_MODE] & 0x04)) {
1314 dup9 = 1;
1315 }
1316 vga_draw_glyph9(d1, linesize,
1317 font_ptr, cheight, fgcol, bgcol, dup9);
1318 }
1319 if (src == cursor_ptr &&
1320 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1321 s->cursor_visible_phase) {
1322 int line_start, line_last, h;
1323 /* draw the cursor */
1324 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1325 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1326 /* XXX: check that */
1327 if (line_last > cheight - 1)
1328 line_last = cheight - 1;
1329 if (line_last >= line_start && line_start < cheight) {
1330 h = line_last - line_start + 1;
1331 d = d1 + linesize * line_start;
1332 if (cw == 16) {
1333 vga_draw_glyph16(d, linesize,
1334 cursor_glyph, h, fgcol, bgcol);
1335 } else if (cw != 9) {
1336 vga_draw_glyph8(d, linesize,
1337 cursor_glyph, h, fgcol, bgcol);
1338 } else {
1339 vga_draw_glyph9(d, linesize,
1340 cursor_glyph, h, fgcol, bgcol, 1);
1341 }
1342 }
1343 }
1344 }
1345 d1 += x_incr;
1346 src += 4;
1347 ch_attr_ptr++;
1348 }
1349 if (cx_max != -1) {
1350 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1351 (cx_max - cx_min + 1) * cw, cheight);
1352 }
1353 dest += linesize * cheight;
1354 line1 = line + cheight;
1355 offset += line_offset;
1356 if (line < s->line_compare && line1 >= s->line_compare) {
1357 offset = 0;
1358 }
1359 line = line1;
1360 }
1361 }
1362
1363 enum {
1364 VGA_DRAW_LINE2,
1365 VGA_DRAW_LINE2D2,
1366 VGA_DRAW_LINE4,
1367 VGA_DRAW_LINE4D2,
1368 VGA_DRAW_LINE8D2,
1369 VGA_DRAW_LINE8,
1370 VGA_DRAW_LINE15_LE,
1371 VGA_DRAW_LINE16_LE,
1372 VGA_DRAW_LINE24_LE,
1373 VGA_DRAW_LINE32_LE,
1374 VGA_DRAW_LINE15_BE,
1375 VGA_DRAW_LINE16_BE,
1376 VGA_DRAW_LINE24_BE,
1377 VGA_DRAW_LINE32_BE,
1378 VGA_DRAW_LINE_NB,
1379 };
1380
1381 static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
1382 vga_draw_line2,
1383 vga_draw_line2d2,
1384 vga_draw_line4,
1385 vga_draw_line4d2,
1386 vga_draw_line8d2,
1387 vga_draw_line8,
1388 vga_draw_line15_le,
1389 vga_draw_line16_le,
1390 vga_draw_line24_le,
1391 vga_draw_line32_le,
1392 vga_draw_line15_be,
1393 vga_draw_line16_be,
1394 vga_draw_line24_be,
1395 vga_draw_line32_be,
1396 };
1397
1398 static int vga_get_bpp(VGACommonState *s)
1399 {
1400 int ret;
1401
1402 if (vbe_enabled(s)) {
1403 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1404 } else {
1405 ret = 0;
1406 }
1407 return ret;
1408 }
1409
1410 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1411 {
1412 int width, height;
1413
1414 if (vbe_enabled(s)) {
1415 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1416 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1417 } else {
1418 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1419 height = s->cr[VGA_CRTC_V_DISP_END] |
1420 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1421 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1422 height = (height + 1);
1423 }
1424 *pwidth = width;
1425 *pheight = height;
1426 }
1427
1428 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1429 {
1430 int y;
1431 if (y1 >= VGA_MAX_HEIGHT)
1432 return;
1433 if (y2 >= VGA_MAX_HEIGHT)
1434 y2 = VGA_MAX_HEIGHT;
1435 for(y = y1; y < y2; y++) {
1436 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1437 }
1438 }
1439
1440 static bool vga_scanline_invalidated(VGACommonState *s, int y)
1441 {
1442 if (y >= VGA_MAX_HEIGHT) {
1443 return false;
1444 }
1445 return s->invalidated_y_table[y >> 5] & (1 << (y & 0x1f));
1446 }
1447
1448 void vga_dirty_log_start(VGACommonState *s)
1449 {
1450 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1451 }
1452
1453 void vga_dirty_log_stop(VGACommonState *s)
1454 {
1455 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1456 }
1457
1458 /*
1459 * graphic modes
1460 */
1461 static void vga_draw_graphic(VGACommonState *s, int full_update)
1462 {
1463 DisplaySurface *surface = qemu_console_surface(s->con);
1464 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1465 int width, height, shift_control, bwidth, bits;
1466 ram_addr_t page0, page1, region_start, region_end;
1467 DirtyBitmapSnapshot *snap = NULL;
1468 int disp_width, multi_scan, multi_run;
1469 uint8_t *d;
1470 uint32_t v, addr1, addr;
1471 vga_draw_line_func *vga_draw_line = NULL;
1472 bool share_surface, force_shadow = false;
1473 pixman_format_code_t format;
1474 #ifdef HOST_WORDS_BIGENDIAN
1475 bool byteswap = !s->big_endian_fb;
1476 #else
1477 bool byteswap = s->big_endian_fb;
1478 #endif
1479
1480 full_update |= update_basic_params(s);
1481
1482 s->get_resolution(s, &width, &height);
1483 disp_width = width;
1484
1485 region_start = (s->start_addr * 4);
1486 region_end = region_start + (ram_addr_t)s->line_offset * height;
1487 region_end += width * s->get_bpp(s) / 8; /* scanline length */
1488 region_end -= s->line_offset;
1489 if (region_end > s->vbe_size) {
1490 /* wraps around (can happen with cirrus vbe modes) */
1491 region_start = 0;
1492 region_end = s->vbe_size;
1493 force_shadow = true;
1494 }
1495
1496 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1497 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1498 if (shift_control != 1) {
1499 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1500 - 1;
1501 } else {
1502 /* in CGA modes, multi_scan is ignored */
1503 /* XXX: is it correct ? */
1504 multi_scan = double_scan;
1505 }
1506 multi_run = multi_scan;
1507 if (shift_control != s->shift_control ||
1508 double_scan != s->double_scan) {
1509 full_update = 1;
1510 s->shift_control = shift_control;
1511 s->double_scan = double_scan;
1512 }
1513
1514 if (shift_control == 0) {
1515 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1516 disp_width <<= 1;
1517 }
1518 } else if (shift_control == 1) {
1519 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1520 disp_width <<= 1;
1521 }
1522 }
1523
1524 depth = s->get_bpp(s);
1525
1526 /*
1527 * Check whether we can share the surface with the backend
1528 * or whether we need a shadow surface. We share native
1529 * endian surfaces for 15bpp and above and byteswapped
1530 * surfaces for 24bpp and above.
1531 */
1532 format = qemu_default_pixman_format(depth, !byteswap);
1533 if (format) {
1534 share_surface = dpy_gfx_check_format(s->con, format)
1535 && !s->force_shadow && !force_shadow;
1536 } else {
1537 share_surface = false;
1538 }
1539 if (s->line_offset != s->last_line_offset ||
1540 disp_width != s->last_width ||
1541 height != s->last_height ||
1542 s->last_depth != depth ||
1543 s->last_byteswap != byteswap ||
1544 share_surface != is_buffer_shared(surface)) {
1545 if (share_surface) {
1546 surface = qemu_create_displaysurface_from(disp_width,
1547 height, format, s->line_offset,
1548 s->vram_ptr + (s->start_addr * 4));
1549 dpy_gfx_replace_surface(s->con, surface);
1550 } else {
1551 qemu_console_resize(s->con, disp_width, height);
1552 surface = qemu_console_surface(s->con);
1553 }
1554 s->last_scr_width = disp_width;
1555 s->last_scr_height = height;
1556 s->last_width = disp_width;
1557 s->last_height = height;
1558 s->last_line_offset = s->line_offset;
1559 s->last_depth = depth;
1560 s->last_byteswap = byteswap;
1561 full_update = 1;
1562 } else if (is_buffer_shared(surface) &&
1563 (full_update || surface_data(surface) != s->vram_ptr
1564 + (s->start_addr * 4))) {
1565 pixman_format_code_t format =
1566 qemu_default_pixman_format(depth, !byteswap);
1567 surface = qemu_create_displaysurface_from(disp_width,
1568 height, format, s->line_offset,
1569 s->vram_ptr + (s->start_addr * 4));
1570 dpy_gfx_replace_surface(s->con, surface);
1571 }
1572
1573 if (shift_control == 0) {
1574 full_update |= update_palette16(s);
1575 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1576 v = VGA_DRAW_LINE4D2;
1577 } else {
1578 v = VGA_DRAW_LINE4;
1579 }
1580 bits = 4;
1581 } else if (shift_control == 1) {
1582 full_update |= update_palette16(s);
1583 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
1584 v = VGA_DRAW_LINE2D2;
1585 } else {
1586 v = VGA_DRAW_LINE2;
1587 }
1588 bits = 4;
1589 } else {
1590 switch(s->get_bpp(s)) {
1591 default:
1592 case 0:
1593 full_update |= update_palette256(s);
1594 v = VGA_DRAW_LINE8D2;
1595 bits = 4;
1596 break;
1597 case 8:
1598 full_update |= update_palette256(s);
1599 v = VGA_DRAW_LINE8;
1600 bits = 8;
1601 break;
1602 case 15:
1603 v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
1604 bits = 16;
1605 break;
1606 case 16:
1607 v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
1608 bits = 16;
1609 break;
1610 case 24:
1611 v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
1612 bits = 24;
1613 break;
1614 case 32:
1615 v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
1616 bits = 32;
1617 break;
1618 }
1619 }
1620 vga_draw_line = vga_draw_line_table[v];
1621
1622 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1623 s->cursor_invalidate(s);
1624 }
1625
1626 #if 0
1627 fprintf(stderr,
1628 "w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x "
1629 "linecmp=%d sr[0x01]=0x%02x\n",
1630 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1631 s->line_compare, sr(s, VGA_SEQ_CLOCK_MODE));
1632 #endif
1633 addr1 = (s->start_addr * 4);
1634 bwidth = DIV_ROUND_UP(width * bits, 8);
1635 y_start = -1;
1636 d = surface_data(surface);
1637 linesize = surface_stride(surface);
1638 y1 = 0;
1639
1640 if (!full_update) {
1641 if (s->line_compare < height) {
1642 /* split screen mode */
1643 region_start = 0;
1644 }
1645 snap = memory_region_snapshot_and_clear_dirty(&s->vram, region_start,
1646 region_end - region_start,
1647 DIRTY_MEMORY_VGA);
1648 }
1649
1650 for(y = 0; y < height; y++) {
1651 addr = addr1;
1652 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1653 int shift;
1654 /* CGA compatibility handling */
1655 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1656 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1657 }
1658 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1659 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1660 }
1661 update = full_update;
1662 page0 = addr & s->vbe_size_mask;
1663 page1 = (addr + bwidth - 1) & s->vbe_size_mask;
1664 if (full_update) {
1665 update = 1;
1666 } else if (page1 < page0) {
1667 /* scanline wraps from end of video memory to the start */
1668 assert(force_shadow);
1669 update = memory_region_snapshot_get_dirty(&s->vram, snap,
1670 page0, s->vbe_size - page0);
1671 update |= memory_region_snapshot_get_dirty(&s->vram, snap,
1672 0, page1);
1673 } else {
1674 update = memory_region_snapshot_get_dirty(&s->vram, snap,
1675 page0, page1 - page0);
1676 }
1677 /* explicit invalidation for the hardware cursor (cirrus only) */
1678 update |= vga_scanline_invalidated(s, y);
1679 if (update) {
1680 if (y_start < 0)
1681 y_start = y;
1682 if (!(is_buffer_shared(surface))) {
1683 vga_draw_line(s, d, addr, width);
1684 if (s->cursor_draw_line)
1685 s->cursor_draw_line(s, d, y);
1686 }
1687 } else {
1688 if (y_start >= 0) {
1689 /* flush to display */
1690 dpy_gfx_update(s->con, 0, y_start,
1691 disp_width, y - y_start);
1692 y_start = -1;
1693 }
1694 }
1695 if (!multi_run) {
1696 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1697 if ((y1 & mask) == mask)
1698 addr1 += s->line_offset;
1699 y1++;
1700 multi_run = multi_scan;
1701 } else {
1702 multi_run--;
1703 }
1704 /* line compare acts on the displayed lines */
1705 if (y == s->line_compare)
1706 addr1 = 0;
1707 d += linesize;
1708 }
1709 if (y_start >= 0) {
1710 /* flush to display */
1711 dpy_gfx_update(s->con, 0, y_start,
1712 disp_width, y - y_start);
1713 }
1714 g_free(snap);
1715 memset(s->invalidated_y_table, 0, sizeof(s->invalidated_y_table));
1716 }
1717
1718 static void vga_draw_blank(VGACommonState *s, int full_update)
1719 {
1720 DisplaySurface *surface = qemu_console_surface(s->con);
1721 int i, w;
1722 uint8_t *d;
1723
1724 if (!full_update)
1725 return;
1726 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1727 return;
1728
1729 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1730 d = surface_data(surface);
1731 for(i = 0; i < s->last_scr_height; i++) {
1732 memset(d, 0, w);
1733 d += surface_stride(surface);
1734 }
1735 dpy_gfx_update(s->con, 0, 0,
1736 s->last_scr_width, s->last_scr_height);
1737 }
1738
1739 #define GMODE_TEXT 0
1740 #define GMODE_GRAPH 1
1741 #define GMODE_BLANK 2
1742
1743 static void vga_update_display(void *opaque)
1744 {
1745 VGACommonState *s = opaque;
1746 DisplaySurface *surface = qemu_console_surface(s->con);
1747 int full_update, graphic_mode;
1748
1749 qemu_flush_coalesced_mmio_buffer();
1750
1751 if (surface_bits_per_pixel(surface) == 0) {
1752 /* nothing to do */
1753 } else {
1754 full_update = 0;
1755 if (!(s->ar_index & 0x20)) {
1756 graphic_mode = GMODE_BLANK;
1757 } else {
1758 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1759 }
1760 if (graphic_mode != s->graphic_mode) {
1761 s->graphic_mode = graphic_mode;
1762 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1763 full_update = 1;
1764 }
1765 switch(graphic_mode) {
1766 case GMODE_TEXT:
1767 vga_draw_text(s, full_update);
1768 break;
1769 case GMODE_GRAPH:
1770 vga_draw_graphic(s, full_update);
1771 break;
1772 case GMODE_BLANK:
1773 default:
1774 vga_draw_blank(s, full_update);
1775 break;
1776 }
1777 }
1778 }
1779
1780 /* force a full display refresh */
1781 static void vga_invalidate_display(void *opaque)
1782 {
1783 VGACommonState *s = opaque;
1784
1785 s->last_width = -1;
1786 s->last_height = -1;
1787 }
1788
1789 void vga_common_reset(VGACommonState *s)
1790 {
1791 s->sr_index = 0;
1792 memset(s->sr, '\0', sizeof(s->sr));
1793 memset(s->sr_vbe, '\0', sizeof(s->sr_vbe));
1794 s->gr_index = 0;
1795 memset(s->gr, '\0', sizeof(s->gr));
1796 s->ar_index = 0;
1797 memset(s->ar, '\0', sizeof(s->ar));
1798 s->ar_flip_flop = 0;
1799 s->cr_index = 0;
1800 memset(s->cr, '\0', sizeof(s->cr));
1801 s->msr = 0;
1802 s->fcr = 0;
1803 s->st00 = 0;
1804 s->st01 = 0;
1805 s->dac_state = 0;
1806 s->dac_sub_index = 0;
1807 s->dac_read_index = 0;
1808 s->dac_write_index = 0;
1809 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1810 s->dac_8bit = 0;
1811 memset(s->palette, '\0', sizeof(s->palette));
1812 s->bank_offset = 0;
1813 s->vbe_index = 0;
1814 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1815 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1816 s->vbe_start_addr = 0;
1817 s->vbe_line_offset = 0;
1818 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1819 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1820 s->graphic_mode = -1; /* force full update */
1821 s->shift_control = 0;
1822 s->double_scan = 0;
1823 s->line_offset = 0;
1824 s->line_compare = 0;
1825 s->start_addr = 0;
1826 s->plane_updated = 0;
1827 s->last_cw = 0;
1828 s->last_ch = 0;
1829 s->last_width = 0;
1830 s->last_height = 0;
1831 s->last_scr_width = 0;
1832 s->last_scr_height = 0;
1833 s->cursor_start = 0;
1834 s->cursor_end = 0;
1835 s->cursor_offset = 0;
1836 s->big_endian_fb = s->default_endian_fb;
1837 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1838 memset(s->last_palette, '\0', sizeof(s->last_palette));
1839 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1840 switch (vga_retrace_method) {
1841 case VGA_RETRACE_DUMB:
1842 break;
1843 case VGA_RETRACE_PRECISE:
1844 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1845 break;
1846 }
1847 vga_update_memory_access(s);
1848 }
1849
1850 static void vga_reset(void *opaque)
1851 {
1852 VGACommonState *s = opaque;
1853 vga_common_reset(s);
1854 }
1855
1856 #define TEXTMODE_X(x) ((x) % width)
1857 #define TEXTMODE_Y(x) ((x) / width)
1858 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1859 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1860 /* relay text rendering to the display driver
1861 * instead of doing a full vga_update_display() */
1862 static void vga_update_text(void *opaque, console_ch_t *chardata)
1863 {
1864 VGACommonState *s = opaque;
1865 int graphic_mode, i, cursor_offset, cursor_visible;
1866 int cw, cheight, width, height, size, c_min, c_max;
1867 uint32_t *src;
1868 console_ch_t *dst, val;
1869 char msg_buffer[80];
1870 int full_update = 0;
1871
1872 qemu_flush_coalesced_mmio_buffer();
1873
1874 if (!(s->ar_index & 0x20)) {
1875 graphic_mode = GMODE_BLANK;
1876 } else {
1877 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1878 }
1879 if (graphic_mode != s->graphic_mode) {
1880 s->graphic_mode = graphic_mode;
1881 full_update = 1;
1882 }
1883 if (s->last_width == -1) {
1884 s->last_width = 0;
1885 full_update = 1;
1886 }
1887
1888 switch (graphic_mode) {
1889 case GMODE_TEXT:
1890 /* TODO: update palette */
1891 full_update |= update_basic_params(s);
1892
1893 /* total width & height */
1894 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1895 cw = 8;
1896 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
1897 cw = 9;
1898 }
1899 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
1900 cw = 16; /* NOTE: no 18 pixel wide */
1901 }
1902 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1903 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1904 /* ugly hack for CGA 160x100x16 - explain me the logic */
1905 height = 100;
1906 } else {
1907 height = s->cr[VGA_CRTC_V_DISP_END] |
1908 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1909 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1910 height = (height + 1) / cheight;
1911 }
1912
1913 size = (height * width);
1914 if (size > CH_ATTR_SIZE) {
1915 if (!full_update)
1916 return;
1917
1918 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1919 width, height);
1920 break;
1921 }
1922
1923 if (width != s->last_width || height != s->last_height ||
1924 cw != s->last_cw || cheight != s->last_ch) {
1925 s->last_scr_width = width * cw;
1926 s->last_scr_height = height * cheight;
1927 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1928 dpy_text_resize(s->con, width, height);
1929 s->last_depth = 0;
1930 s->last_width = width;
1931 s->last_height = height;
1932 s->last_ch = cheight;
1933 s->last_cw = cw;
1934 full_update = 1;
1935 }
1936
1937 if (full_update) {
1938 s->full_update_gfx = 1;
1939 }
1940 if (s->full_update_text) {
1941 s->full_update_text = 0;
1942 full_update |= 1;
1943 }
1944
1945 /* Update "hardware" cursor */
1946 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1947 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1948 if (cursor_offset != s->cursor_offset ||
1949 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1950 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
1951 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
1952 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1953 dpy_text_cursor(s->con,
1954 TEXTMODE_X(cursor_offset),
1955 TEXTMODE_Y(cursor_offset));
1956 else
1957 dpy_text_cursor(s->con, -1, -1);
1958 s->cursor_offset = cursor_offset;
1959 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1960 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1961 }
1962
1963 src = (uint32_t *) s->vram_ptr + s->start_addr;
1964 dst = chardata;
1965
1966 if (full_update) {
1967 for (i = 0; i < size; src ++, dst ++, i ++)
1968 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
1969
1970 dpy_text_update(s->con, 0, 0, width, height);
1971 } else {
1972 c_max = 0;
1973
1974 for (i = 0; i < size; src ++, dst ++, i ++) {
1975 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1976 if (*dst != val) {
1977 *dst = val;
1978 c_max = i;
1979 break;
1980 }
1981 }
1982 c_min = i;
1983 for (; i < size; src ++, dst ++, i ++) {
1984 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1985 if (*dst != val) {
1986 *dst = val;
1987 c_max = i;
1988 }
1989 }
1990
1991 if (c_min <= c_max) {
1992 i = TEXTMODE_Y(c_min);
1993 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1994 }
1995 }
1996
1997 return;
1998 case GMODE_GRAPH:
1999 if (!full_update)
2000 return;
2001
2002 s->get_resolution(s, &width, &height);
2003 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2004 width, height);
2005 break;
2006 case GMODE_BLANK:
2007 default:
2008 if (!full_update)
2009 return;
2010
2011 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2012 break;
2013 }
2014
2015 /* Display a message */
2016 s->last_width = 60;
2017 s->last_height = height = 3;
2018 dpy_text_cursor(s->con, -1, -1);
2019 dpy_text_resize(s->con, s->last_width, height);
2020
2021 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2022 console_write_ch(dst ++, ' ');
2023
2024 size = strlen(msg_buffer);
2025 width = (s->last_width - size) / 2;
2026 dst = chardata + s->last_width + width;
2027 for (i = 0; i < size; i ++)
2028 console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE,
2029 QEMU_COLOR_BLACK, 1));
2030
2031 dpy_text_update(s->con, 0, 0, s->last_width, height);
2032 }
2033
2034 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
2035 unsigned size)
2036 {
2037 VGACommonState *s = opaque;
2038
2039 return vga_mem_readb(s, addr);
2040 }
2041
2042 static void vga_mem_write(void *opaque, hwaddr addr,
2043 uint64_t data, unsigned size)
2044 {
2045 VGACommonState *s = opaque;
2046
2047 vga_mem_writeb(s, addr, data);
2048 }
2049
2050 const MemoryRegionOps vga_mem_ops = {
2051 .read = vga_mem_read,
2052 .write = vga_mem_write,
2053 .endianness = DEVICE_LITTLE_ENDIAN,
2054 .impl = {
2055 .min_access_size = 1,
2056 .max_access_size = 1,
2057 },
2058 };
2059
2060 static int vga_common_post_load(void *opaque, int version_id)
2061 {
2062 VGACommonState *s = opaque;
2063
2064 /* force refresh */
2065 s->graphic_mode = -1;
2066 vbe_update_vgaregs(s);
2067 vga_update_memory_access(s);
2068 return 0;
2069 }
2070
2071 static bool vga_endian_state_needed(void *opaque)
2072 {
2073 VGACommonState *s = opaque;
2074
2075 /*
2076 * Only send the endian state if it's different from the
2077 * default one, thus ensuring backward compatibility for
2078 * migration of the common case
2079 */
2080 return s->default_endian_fb != s->big_endian_fb;
2081 }
2082
2083 static const VMStateDescription vmstate_vga_endian = {
2084 .name = "vga.endian",
2085 .version_id = 1,
2086 .minimum_version_id = 1,
2087 .needed = vga_endian_state_needed,
2088 .fields = (VMStateField[]) {
2089 VMSTATE_BOOL(big_endian_fb, VGACommonState),
2090 VMSTATE_END_OF_LIST()
2091 }
2092 };
2093
2094 const VMStateDescription vmstate_vga_common = {
2095 .name = "vga",
2096 .version_id = 2,
2097 .minimum_version_id = 2,
2098 .post_load = vga_common_post_load,
2099 .fields = (VMStateField[]) {
2100 VMSTATE_UINT32(latch, VGACommonState),
2101 VMSTATE_UINT8(sr_index, VGACommonState),
2102 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2103 VMSTATE_UINT8(gr_index, VGACommonState),
2104 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2105 VMSTATE_UINT8(ar_index, VGACommonState),
2106 VMSTATE_BUFFER(ar, VGACommonState),
2107 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2108 VMSTATE_UINT8(cr_index, VGACommonState),
2109 VMSTATE_BUFFER(cr, VGACommonState),
2110 VMSTATE_UINT8(msr, VGACommonState),
2111 VMSTATE_UINT8(fcr, VGACommonState),
2112 VMSTATE_UINT8(st00, VGACommonState),
2113 VMSTATE_UINT8(st01, VGACommonState),
2114
2115 VMSTATE_UINT8(dac_state, VGACommonState),
2116 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2117 VMSTATE_UINT8(dac_read_index, VGACommonState),
2118 VMSTATE_UINT8(dac_write_index, VGACommonState),
2119 VMSTATE_BUFFER(dac_cache, VGACommonState),
2120 VMSTATE_BUFFER(palette, VGACommonState),
2121
2122 VMSTATE_INT32(bank_offset, VGACommonState),
2123 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState, NULL),
2124 VMSTATE_UINT16(vbe_index, VGACommonState),
2125 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2126 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2127 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2128 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2129 VMSTATE_END_OF_LIST()
2130 },
2131 .subsections = (const VMStateDescription*[]) {
2132 &vmstate_vga_endian,
2133 NULL
2134 }
2135 };
2136
2137 static const GraphicHwOps vga_ops = {
2138 .invalidate = vga_invalidate_display,
2139 .gfx_update = vga_update_display,
2140 .text_update = vga_update_text,
2141 };
2142
2143 static inline uint32_t uint_clamp(uint32_t val, uint32_t vmin, uint32_t vmax)
2144 {
2145 if (val < vmin) {
2146 return vmin;
2147 }
2148 if (val > vmax) {
2149 return vmax;
2150 }
2151 return val;
2152 }
2153
2154 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
2155 {
2156 int i, j, v, b;
2157
2158 for(i = 0;i < 256; i++) {
2159 v = 0;
2160 for(j = 0; j < 8; j++) {
2161 v |= ((i >> j) & 1) << (j * 4);
2162 }
2163 expand4[i] = v;
2164
2165 v = 0;
2166 for(j = 0; j < 4; j++) {
2167 v |= ((i >> (2 * j)) & 3) << (j * 4);
2168 }
2169 expand2[i] = v;
2170 }
2171 for(i = 0; i < 16; i++) {
2172 v = 0;
2173 for(j = 0; j < 4; j++) {
2174 b = ((i >> j) & 1);
2175 v |= b << (2 * j);
2176 v |= b << (2 * j + 1);
2177 }
2178 expand4to8[i] = v;
2179 }
2180
2181 s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
2182 s->vram_size_mb = pow2ceil(s->vram_size_mb);
2183 s->vram_size = s->vram_size_mb << 20;
2184
2185 if (!s->vbe_size) {
2186 s->vbe_size = s->vram_size;
2187 }
2188 s->vbe_size_mask = s->vbe_size - 1;
2189
2190 s->is_vbe_vmstate = 1;
2191 memory_region_init_ram_nomigrate(&s->vram, obj, "vga.vram", s->vram_size,
2192 &error_fatal);
2193 vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
2194 xen_register_framebuffer(&s->vram);
2195 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2196 s->get_bpp = vga_get_bpp;
2197 s->get_offsets = vga_get_offsets;
2198 s->get_resolution = vga_get_resolution;
2199 s->hw_ops = &vga_ops;
2200 switch (vga_retrace_method) {
2201 case VGA_RETRACE_DUMB:
2202 s->retrace = vga_dumb_retrace;
2203 s->update_retrace_info = vga_dumb_update_retrace_info;
2204 break;
2205
2206 case VGA_RETRACE_PRECISE:
2207 s->retrace = vga_precise_retrace;
2208 s->update_retrace_info = vga_precise_update_retrace_info;
2209 break;
2210 }
2211
2212 /*
2213 * Set default fb endian based on target, could probably be turned
2214 * into a device attribute set by the machine/platform to remove
2215 * all target endian dependencies from this file.
2216 */
2217 #ifdef TARGET_WORDS_BIGENDIAN
2218 s->default_endian_fb = true;
2219 #else
2220 s->default_endian_fb = false;
2221 #endif
2222 vga_dirty_log_start(s);
2223 }
2224
2225 static const MemoryRegionPortio vga_portio_list[] = {
2226 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2227 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2228 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2229 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2230 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2231 PORTIO_END_OF_LIST(),
2232 };
2233
2234 static const MemoryRegionPortio vbe_portio_list[] = {
2235 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2236 # ifdef TARGET_I386
2237 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2238 # endif
2239 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2240 PORTIO_END_OF_LIST(),
2241 };
2242
2243 /* Used by both ISA and PCI */
2244 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
2245 const MemoryRegionPortio **vga_ports,
2246 const MemoryRegionPortio **vbe_ports)
2247 {
2248 MemoryRegion *vga_mem;
2249
2250 *vga_ports = vga_portio_list;
2251 *vbe_ports = vbe_portio_list;
2252
2253 vga_mem = g_malloc(sizeof(*vga_mem));
2254 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
2255 "vga-lowmem", 0x20000);
2256 memory_region_set_flush_coalesced(vga_mem);
2257
2258 return vga_mem;
2259 }
2260
2261 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
2262 MemoryRegion *address_space_io, bool init_vga_ports)
2263 {
2264 MemoryRegion *vga_io_memory;
2265 const MemoryRegionPortio *vga_ports, *vbe_ports;
2266
2267 qemu_register_reset(vga_reset, s);
2268
2269 s->bank_offset = 0;
2270
2271 s->legacy_address_space = address_space;
2272
2273 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
2274 memory_region_add_subregion_overlap(address_space,
2275 0x000a0000,
2276 vga_io_memory,
2277 1);
2278 memory_region_set_coalescing(vga_io_memory);
2279 if (init_vga_ports) {
2280 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
2281 portio_list_set_flush_coalesced(&s->vga_port_list);
2282 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
2283 }
2284 if (vbe_ports) {
2285 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
2286 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
2287 }
2288 }
2289
2290 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
2291 {
2292 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2293 * so use an alias to avoid double-mapping the same region.
2294 */
2295 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
2296 &s->vram, 0, memory_region_size(&s->vram));
2297 /* XXX: use optimized standard vga accesses */
2298 memory_region_add_subregion(system_memory,
2299 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2300 &s->vram_vbe);
2301 s->vbe_mapped = 1;
2302 }
AR7 emulation for QEMU