hw/display/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * see docs/specs/standard-vga.txt for virtual hardware specs.
   5  *
   6  * Copyright (c) 2003 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "vga_int.h"
  30 #include "ui/pixel_ops.h"
  31 #include "qemu/timer.h"
  32 #include "hw/loader.h"
  33
  34 #define PCI_VGA_IOPORT_OFFSET 0x400
  35 #define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
  36 #define PCI_VGA_BOCHS_OFFSET  0x500
  37 #define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
  38 #define PCI_VGA_QEXT_OFFSET   0x600
  39 #define PCI_VGA_QEXT_SIZE     (2 * 4)
  40 #define PCI_VGA_MMIO_SIZE     0x1000
  41
  42 #define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
  43 #define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
  44 #define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
  45 #define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe
  46
  47 enum vga_pci_flags {
  48     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  49     PCI_VGA_FLAG_ENABLE_QEXT = 2,
  50 };
  51
  52 typedef struct PCIVGAState {
  53     PCIDevice dev;
  54     VGACommonState vga;
  55     uint32_t flags;
  56     MemoryRegion mmio;
  57     MemoryRegion mrs[3];
  58 } PCIVGAState;
  59
  60 #define TYPE_PCI_VGA "pci-vga"
  61 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
  62
  63 static const VMStateDescription vmstate_vga_pci = {
  64     .name = "vga",
  65     .version_id = 2,
  66     .minimum_version_id = 2,
  67     .fields = (VMStateField[]) {
  68         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  69         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  70         VMSTATE_END_OF_LIST()
  71     }
  72 };
  73
  74 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
  75                                     unsigned size)
  76 {
  77     VGACommonState *s = ptr;
  78     uint64_t ret = 0;
  79
  80     switch (size) {
  81     case 1:
  82         ret = vga_ioport_read(s, addr + 0x3c0);
  83         break;
  84     case 2:
  85         ret  = vga_ioport_read(s, addr + 0x3c0);
  86         ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
  87         break;
  88     }
  89     return ret;
  90 }
  91
  92 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
  93                                  uint64_t val, unsigned size)
  94 {
  95     VGACommonState *s = ptr;
  96
  97     switch (size) {
  98     case 1:
  99         vga_ioport_write(s, addr + 0x3c0, val);
 100         break;
 101     case 2:
 102         /*
 103          * Update bytes in little endian order.  Allows to update
 104          * indexed registers with a single word write because the
 105          * index byte is updated first.
 106          */
 107         vga_ioport_write(s, addr + 0x3c0, val & 0xff);
 108         vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
 109         break;
 110     }
 111 }
 112
 113 static const MemoryRegionOps pci_vga_ioport_ops = {
 114     .read = pci_vga_ioport_read,
 115     .write = pci_vga_ioport_write,
 116     .valid.min_access_size = 1,
 117     .valid.max_access_size = 4,
 118     .impl.min_access_size = 1,
 119     .impl.max_access_size = 2,
 120     .endianness = DEVICE_LITTLE_ENDIAN,
 121 };
 122
 123 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
 124                                    unsigned size)
 125 {
 126     VGACommonState *s = ptr;
 127     int index = addr >> 1;
 128
 129     vbe_ioport_write_index(s, 0, index);
 130     return vbe_ioport_read_data(s, 0);
 131 }
 132
 133 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
 134                                 uint64_t val, unsigned size)
 135 {
 136     VGACommonState *s = ptr;
 137     int index = addr >> 1;
 138
 139     vbe_ioport_write_index(s, 0, index);
 140     vbe_ioport_write_data(s, 0, val);
 141 }
 142
 143 static const MemoryRegionOps pci_vga_bochs_ops = {
 144     .read = pci_vga_bochs_read,
 145     .write = pci_vga_bochs_write,
 146     .valid.min_access_size = 1,
 147     .valid.max_access_size = 4,
 148     .impl.min_access_size = 2,
 149     .impl.max_access_size = 2,
 150     .endianness = DEVICE_LITTLE_ENDIAN,
 151 };
 152
 153 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
 154 {
 155     VGACommonState *s = ptr;
 156
 157     switch (addr) {
 158     case PCI_VGA_QEXT_REG_SIZE:
 159         return PCI_VGA_QEXT_SIZE;
 160     case PCI_VGA_QEXT_REG_BYTEORDER:
 161         return s->big_endian_fb ?
 162             PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
 163     default:
 164         return 0;
 165     }
 166 }
 167
 168 static void pci_vga_qext_write(void *ptr, hwaddr addr,
 169                                uint64_t val, unsigned size)
 170 {
 171     VGACommonState *s = ptr;
 172
 173     switch (addr) {
 174     case PCI_VGA_QEXT_REG_BYTEORDER:
 175         if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
 176             s->big_endian_fb = true;
 177         }
 178         if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
 179             s->big_endian_fb = false;
 180         }
 181         break;
 182     }
 183 }
 184
 185 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
 186 {
 187     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 188
 189     return d->vga.big_endian_fb;
 190 }
 191
 192 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 193 {
 194     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 195
 196     d->vga.big_endian_fb = value;
 197 }
 198
 199 static const MemoryRegionOps pci_vga_qext_ops = {
 200     .read = pci_vga_qext_read,
 201     .write = pci_vga_qext_write,
 202     .valid.min_access_size = 4,
 203     .valid.max_access_size = 4,
 204     .endianness = DEVICE_LITTLE_ENDIAN,
 205 };
 206
 207 void pci_std_vga_mmio_region_init(VGACommonState *s,
 208                                   MemoryRegion *parent,
 209                                   MemoryRegion *subs,
 210                                   bool qext)
 211 {
 212     memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,
 213                           "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 214     memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
 215                                 &subs[0]);
 216
 217     memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,
 218                           "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 219     memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
 220                                 &subs[1]);
 221
 222     if (qext) {
 223         memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,
 224                               "qemu extended regs", PCI_VGA_QEXT_SIZE);
 225         memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
 226                                     &subs[2]);
 227     }
 228 }
 229
 230 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
 231 {
 232     PCIVGAState *d = PCI_VGA(dev);
 233     VGACommonState *s = &d->vga;
 234     bool qext = false;
 235
 236     /* vga + console init */
 237     vga_common_init(s, OBJECT(dev), true);
 238     vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
 239              true);
 240
 241     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 242
 243     /* XXX: VGA_RAM_SIZE must be a power of two */
 244     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 245
 246     /* mmio bar for vga register access */
 247     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 248         memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
 249
 250         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 251             qext = true;
 252             pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 253         }
 254         pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
 255
 256         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 257     }
 258
 259     if (!dev->rom_bar) {
 260         /* compatibility with pc-0.13 and older */
 261         vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
 262     }
 263 }
 264
 265 static void pci_std_vga_init(Object *obj)
 266 {
 267     /* Expose framebuffer byteorder via QOM */
 268     object_property_add_bool(obj, "big-endian-framebuffer",
 269                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 270 }
 271
 272 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
 273 {
 274     PCIVGAState *d = PCI_VGA(dev);
 275     VGACommonState *s = &d->vga;
 276     bool qext = false;
 277
 278     /* vga + console init */
 279     vga_common_init(s, OBJECT(dev), false);
 280     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 281
 282     /* mmio bar */
 283     memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
 284
 285     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 286         qext = true;
 287         pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 288     }
 289     pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
 290
 291     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 292     pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 293 }
 294
 295 static void pci_secondary_vga_exit(PCIDevice *dev)
 296 {
 297     PCIVGAState *d = PCI_VGA(dev);
 298     VGACommonState *s = &d->vga;
 299
 300     graphic_console_close(s->con);
 301 }
 302
 303 static void pci_secondary_vga_init(Object *obj)
 304 {
 305     /* Expose framebuffer byteorder via QOM */
 306     object_property_add_bool(obj, "big-endian-framebuffer",
 307                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 308 }
 309
 310 static void pci_secondary_vga_reset(DeviceState *dev)
 311 {
 312     PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
 313     vga_common_reset(&d->vga);
 314 }
 315
 316 static Property vga_pci_properties[] = {
 317     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 318     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 319     DEFINE_PROP_BIT("qemu-extended-regs",
 320                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 321     DEFINE_PROP_END_OF_LIST(),
 322 };
 323
 324 static Property secondary_pci_properties[] = {
 325     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 326     DEFINE_PROP_BIT("qemu-extended-regs",
 327                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 328     DEFINE_PROP_END_OF_LIST(),
 329 };
 330
 331 static void vga_pci_class_init(ObjectClass *klass, void *data)
 332 {
 333     DeviceClass *dc = DEVICE_CLASS(klass);
 334     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 335
 336     k->vendor_id = PCI_VENDOR_ID_QEMU;
 337     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 338     dc->vmsd = &vmstate_vga_pci;
 339     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 340 }
 341
 342 static const TypeInfo vga_pci_type_info = {
 343     .name = TYPE_PCI_VGA,
 344     .parent = TYPE_PCI_DEVICE,
 345     .instance_size = sizeof(PCIVGAState),
 346     .abstract = true,
 347     .class_init = vga_pci_class_init,
 348     .interfaces = (InterfaceInfo[]) {
 349         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 350         { },
 351     },
 352 };
 353
 354 static void vga_class_init(ObjectClass *klass, void *data)
 355 {
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 358
 359     k->realize = pci_std_vga_realize;
 360     k->romfile = "vgabios-stdvga.bin";
 361     k->class_id = PCI_CLASS_DISPLAY_VGA;
 362     dc->props = vga_pci_properties;
 363     dc->hotpluggable = false;
 364 }
 365
 366 static void secondary_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 370
 371     k->realize = pci_secondary_vga_realize;
 372     k->exit = pci_secondary_vga_exit;
 373     k->class_id = PCI_CLASS_DISPLAY_OTHER;
 374     dc->props = secondary_pci_properties;
 375     dc->reset = pci_secondary_vga_reset;
 376 }
 377
 378 static const TypeInfo vga_info = {
 379     .name          = "VGA",
 380     .parent        = TYPE_PCI_VGA,
 381     .instance_init = pci_std_vga_init,
 382     .class_init    = vga_class_init,
 383 };
 384
 385 static const TypeInfo secondary_info = {
 386     .name          = "secondary-vga",
 387     .parent        = TYPE_PCI_VGA,
 388     .instance_init = pci_secondary_vga_init,
 389     .class_init    = secondary_class_init,
 390 };
 391
 392 static void vga_register_types(void)
 393 {
 394     type_register_static(&vga_pci_type_info);
 395     type_register_static(&vga_info);
 396     type_register_static(&secondary_info);
 397 }
 398
 399 type_init(vga_register_types)