2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #if !defined(__XICS_H__)
30 #include "hw/sysbus.h"
32 #define TYPE_XICS_COMMON "xics-common"
33 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
35 #define TYPE_XICS "xics"
36 #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
38 #define TYPE_KVM_XICS "xics-kvm"
39 #define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS)
41 #define XICS_COMMON_CLASS(klass) \
42 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
43 #define XICS_CLASS(klass) \
44 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS)
45 #define XICS_COMMON_GET_CLASS(obj) \
46 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
47 #define XICS_GET_CLASS(obj) \
48 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS)
52 #define XICS_IRQ_BASE (XICS_BUID << 12)
55 * We currently only support one BUID which is our interrupt base
56 * (the kernel implementation supports more but we don't exploit
59 typedef struct XICSStateClass XICSStateClass
;
60 typedef struct XICSState XICSState
;
61 typedef struct ICPStateClass ICPStateClass
;
62 typedef struct ICPState ICPState
;
63 typedef struct ICSStateClass ICSStateClass
;
64 typedef struct ICSState ICSState
;
65 typedef struct ICSIRQState ICSIRQState
;
67 struct XICSStateClass
{
68 DeviceClass parent_class
;
70 void (*cpu_setup
)(XICSState
*icp
, PowerPCCPU
*cpu
);
71 void (*set_nr_irqs
)(XICSState
*icp
, uint32_t nr_irqs
, Error
**errp
);
72 void (*set_nr_servers
)(XICSState
*icp
, uint32_t nr_servers
, Error
**errp
);
77 SysBusDevice parent_obj
;
85 #define TYPE_ICP "icp"
86 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
88 #define TYPE_KVM_ICP "icp-kvm"
89 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
91 #define ICP_CLASS(klass) \
92 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
93 #define ICP_GET_CLASS(obj) \
94 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
96 struct ICPStateClass
{
97 DeviceClass parent_class
;
99 void (*pre_save
)(ICPState
*s
);
100 int (*post_load
)(ICPState
*s
, int version_id
);
105 DeviceState parent_obj
;
109 uint8_t pending_priority
;
112 bool cap_irq_xics_enabled
;
115 #define TYPE_ICS "ics"
116 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
118 #define TYPE_KVM_ICS "icskvm"
119 #define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS)
121 #define ICS_CLASS(klass) \
122 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
123 #define ICS_GET_CLASS(obj) \
124 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
126 struct ICSStateClass
{
127 DeviceClass parent_class
;
129 void (*pre_save
)(ICSState
*s
);
130 int (*post_load
)(ICSState
*s
, int version_id
);
135 DeviceState parent_obj
;
147 uint8_t saved_priority
;
148 #define XICS_STATUS_ASSERTED 0x1
149 #define XICS_STATUS_SENT 0x2
150 #define XICS_STATUS_REJECTED 0x4
151 #define XICS_STATUS_MASKED_PENDING 0x8
153 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
154 #define XICS_FLAGS_IRQ_LSI 0x1
155 #define XICS_FLAGS_IRQ_MSI 0x2
156 #define XICS_FLAGS_IRQ_MASK 0x3
160 #define XICS_IRQS 1024
162 qemu_irq
xics_get_qirq(XICSState
*icp
, int irq
);
163 void xics_set_irq_type(XICSState
*icp
, int irq
, bool lsi
);
164 int xics_alloc(XICSState
*icp
, int src
, int irq_hint
, bool lsi
);
165 int xics_alloc_block(XICSState
*icp
, int src
, int num
, bool lsi
, bool align
);
166 void xics_free(XICSState
*icp
, int irq
, int num
);
168 void xics_cpu_setup(XICSState
*icp
, PowerPCCPU
*cpu
);
170 #endif /* __XICS_H__ */