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target/m68k: introduce is_singlestepping() function
[qemu/ar7.git] / target / m68k / translate.c
blobc774f2e8f0fcb02e0c17f1a0e557cace7edb5fed
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "qemu/log.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "trace-tcg.h"
35 #include "exec/log.h"
36 #include "fpu/softfloat.h"
37
38
39 //#define DEBUG_DISPATCH 1
40
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
43 #include "qregs.def"
44 #undef DEFO32
45 #undef DEFO64
46
47 static TCGv_i32 cpu_halted;
48 static TCGv_i32 cpu_exception_index;
49
50 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
51 static TCGv cpu_dregs[8];
52 static TCGv cpu_aregs[8];
53 static TCGv_i64 cpu_macc[4];
54
55 #define REG(insn, pos) (((insn) >> (pos)) & 7)
56 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
57 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP get_areg(s, 7)
60
61 static TCGv NULL_QREG;
62 #define IS_NULL_QREG(t) (t == NULL_QREG)
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy;
65
66 #include "exec/gen-icount.h"
67
68 void m68k_tcg_init(void)
69 {
70 char *p;
71 int i;
72
73 #define DEFO32(name, offset) \
74 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
76 #define DEFO64(name, offset) \
77 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
78 offsetof(CPUM68KState, offset), #name);
79 #include "qregs.def"
80 #undef DEFO32
81 #undef DEFO64
82
83 cpu_halted = tcg_global_mem_new_i32(cpu_env,
84 -offsetof(M68kCPU, env) +
85 offsetof(CPUState, halted), "HALTED");
86 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
87 -offsetof(M68kCPU, env) +
88 offsetof(CPUState, exception_index),
89 "EXCEPTION");
90
91 p = cpu_reg_names;
92 for (i = 0; i < 8; i++) {
93 sprintf(p, "D%d", i);
94 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
95 offsetof(CPUM68KState, dregs[i]), p);
96 p += 3;
97 sprintf(p, "A%d", i);
98 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
99 offsetof(CPUM68KState, aregs[i]), p);
100 p += 3;
101 }
102 for (i = 0; i < 4; i++) {
103 sprintf(p, "ACC%d", i);
104 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
105 offsetof(CPUM68KState, macc[i]), p);
106 p += 5;
107 }
108
109 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
110 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
111 }
112
113 /* internal defines */
114 typedef struct DisasContext {
115 DisasContextBase base;
116 CPUM68KState *env;
117 target_ulong pc;
118 CCOp cc_op; /* Current CC operation */
119 int cc_op_synced;
120 TCGv_i64 mactmp;
121 int done_mac;
122 int writeback_mask;
123 TCGv writeback[8];
124 #define MAX_TO_RELEASE 8
125 int release_count;
126 TCGv release[MAX_TO_RELEASE];
127 } DisasContext;
128
129 static void init_release_array(DisasContext *s)
130 {
131 #ifdef CONFIG_DEBUG_TCG
132 memset(s->release, 0, sizeof(s->release));
133 #endif
134 s->release_count = 0;
135 }
136
137 static void do_release(DisasContext *s)
138 {
139 int i;
140 for (i = 0; i < s->release_count; i++) {
141 tcg_temp_free(s->release[i]);
142 }
143 init_release_array(s);
144 }
145
146 static TCGv mark_to_release(DisasContext *s, TCGv tmp)
147 {
148 g_assert(s->release_count < MAX_TO_RELEASE);
149 return s->release[s->release_count++] = tmp;
150 }
151
152 static TCGv get_areg(DisasContext *s, unsigned regno)
153 {
154 if (s->writeback_mask & (1 << regno)) {
155 return s->writeback[regno];
156 } else {
157 return cpu_aregs[regno];
158 }
159 }
160
161 static void delay_set_areg(DisasContext *s, unsigned regno,
162 TCGv val, bool give_temp)
163 {
164 if (s->writeback_mask & (1 << regno)) {
165 if (give_temp) {
166 tcg_temp_free(s->writeback[regno]);
167 s->writeback[regno] = val;
168 } else {
169 tcg_gen_mov_i32(s->writeback[regno], val);
170 }
171 } else {
172 s->writeback_mask |= 1 << regno;
173 if (give_temp) {
174 s->writeback[regno] = val;
175 } else {
176 TCGv tmp = tcg_temp_new();
177 s->writeback[regno] = tmp;
178 tcg_gen_mov_i32(tmp, val);
179 }
180 }
181 }
182
183 static void do_writebacks(DisasContext *s)
184 {
185 unsigned mask = s->writeback_mask;
186 if (mask) {
187 s->writeback_mask = 0;
188 do {
189 unsigned regno = ctz32(mask);
190 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
191 tcg_temp_free(s->writeback[regno]);
192 mask &= mask - 1;
193 } while (mask);
194 }
195 }
196
197 static bool is_singlestepping(DisasContext *s)
198 {
199 /*
200 * Return true if we are singlestepping either because of QEMU gdbstub
201 * singlestep. This does not include the command line '-singlestep' mode
202 * which is rather misnamed as it only means "one instruction per TB" and
203 * doesn't affect the code we generate.
204 */
205 return s->base.singlestep_enabled;
206 }
207
208 /* is_jmp field values */
209 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
210 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
211
212 #if defined(CONFIG_USER_ONLY)
213 #define IS_USER(s) 1
214 #else
215 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
216 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
217 MMU_KERNEL_IDX : MMU_USER_IDX)
218 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
219 MMU_KERNEL_IDX : MMU_USER_IDX)
220 #endif
221
222 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
223
224 #ifdef DEBUG_DISPATCH
225 #define DISAS_INSN(name) \
226 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
227 uint16_t insn); \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
229 uint16_t insn) \
230 { \
231 qemu_log("Dispatch " #name "\n"); \
232 real_disas_##name(env, s, insn); \
233 } \
234 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
235 uint16_t insn)
236 #else
237 #define DISAS_INSN(name) \
238 static void disas_##name(CPUM68KState *env, DisasContext *s, \
239 uint16_t insn)
240 #endif
241
242 static const uint8_t cc_op_live[CC_OP_NB] = {
243 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
244 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
245 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
246 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
247 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
248 [CC_OP_LOGIC] = CCF_X | CCF_N
249 };
250
251 static void set_cc_op(DisasContext *s, CCOp op)
252 {
253 CCOp old_op = s->cc_op;
254 int dead;
255
256 if (old_op == op) {
257 return;
258 }
259 s->cc_op = op;
260 s->cc_op_synced = 0;
261
262 /*
263 * Discard CC computation that will no longer be used.
264 * Note that X and N are never dead.
265 */
266 dead = cc_op_live[old_op] & ~cc_op_live[op];
267 if (dead & CCF_C) {
268 tcg_gen_discard_i32(QREG_CC_C);
269 }
270 if (dead & CCF_Z) {
271 tcg_gen_discard_i32(QREG_CC_Z);
272 }
273 if (dead & CCF_V) {
274 tcg_gen_discard_i32(QREG_CC_V);
275 }
276 }
277
278 /* Update the CPU env CC_OP state. */
279 static void update_cc_op(DisasContext *s)
280 {
281 if (!s->cc_op_synced) {
282 s->cc_op_synced = 1;
283 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
284 }
285 }
286
287 /* Generate a jump to an immediate address. */
288 static void gen_jmp_im(DisasContext *s, uint32_t dest)
289 {
290 update_cc_op(s);
291 tcg_gen_movi_i32(QREG_PC, dest);
292 s->base.is_jmp = DISAS_JUMP;
293 }
294
295 /* Generate a jump to the address in qreg DEST. */
296 static void gen_jmp(DisasContext *s, TCGv dest)
297 {
298 update_cc_op(s);
299 tcg_gen_mov_i32(QREG_PC, dest);
300 s->base.is_jmp = DISAS_JUMP;
301 }
302
303 static void gen_raise_exception(int nr)
304 {
305 TCGv_i32 tmp;
306
307 tmp = tcg_const_i32(nr);
308 gen_helper_raise_exception(cpu_env, tmp);
309 tcg_temp_free_i32(tmp);
310 }
311
312 static void gen_exception(DisasContext *s, uint32_t dest, int nr)
313 {
314 update_cc_op(s);
315 tcg_gen_movi_i32(QREG_PC, dest);
316
317 gen_raise_exception(nr);
318
319 s->base.is_jmp = DISAS_NORETURN;
320 }
321
322 static inline void gen_addr_fault(DisasContext *s)
323 {
324 gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
325 }
326
327 /*
328 * Generate a load from the specified address. Narrow values are
329 * sign extended to full register width.
330 */
331 static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
332 int sign, int index)
333 {
334 TCGv tmp;
335 tmp = tcg_temp_new_i32();
336 switch(opsize) {
337 case OS_BYTE:
338 if (sign)
339 tcg_gen_qemu_ld8s(tmp, addr, index);
340 else
341 tcg_gen_qemu_ld8u(tmp, addr, index);
342 break;
343 case OS_WORD:
344 if (sign)
345 tcg_gen_qemu_ld16s(tmp, addr, index);
346 else
347 tcg_gen_qemu_ld16u(tmp, addr, index);
348 break;
349 case OS_LONG:
350 tcg_gen_qemu_ld32u(tmp, addr, index);
351 break;
352 default:
353 g_assert_not_reached();
354 }
355 return tmp;
356 }
357
358 /* Generate a store. */
359 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
360 int index)
361 {
362 switch(opsize) {
363 case OS_BYTE:
364 tcg_gen_qemu_st8(val, addr, index);
365 break;
366 case OS_WORD:
367 tcg_gen_qemu_st16(val, addr, index);
368 break;
369 case OS_LONG:
370 tcg_gen_qemu_st32(val, addr, index);
371 break;
372 default:
373 g_assert_not_reached();
374 }
375 }
376
377 typedef enum {
378 EA_STORE,
379 EA_LOADU,
380 EA_LOADS
381 } ea_what;
382
383 /*
384 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
385 * otherwise generate a store.
386 */
387 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
388 ea_what what, int index)
389 {
390 if (what == EA_STORE) {
391 gen_store(s, opsize, addr, val, index);
392 return store_dummy;
393 } else {
394 return mark_to_release(s, gen_load(s, opsize, addr,
395 what == EA_LOADS, index));
396 }
397 }
398
399 /* Read a 16-bit immediate constant */
400 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
401 {
402 uint16_t im;
403 im = translator_lduw(env, s->pc);
404 s->pc += 2;
405 return im;
406 }
407
408 /* Read an 8-bit immediate constant */
409 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
410 {
411 return read_im16(env, s);
412 }
413
414 /* Read a 32-bit immediate constant. */
415 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
416 {
417 uint32_t im;
418 im = read_im16(env, s) << 16;
419 im |= 0xffff & read_im16(env, s);
420 return im;
421 }
422
423 /* Read a 64-bit immediate constant. */
424 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
425 {
426 uint64_t im;
427 im = (uint64_t)read_im32(env, s) << 32;
428 im |= (uint64_t)read_im32(env, s);
429 return im;
430 }
431
432 /* Calculate and address index. */
433 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
434 {
435 TCGv add;
436 int scale;
437
438 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
439 if ((ext & 0x800) == 0) {
440 tcg_gen_ext16s_i32(tmp, add);
441 add = tmp;
442 }
443 scale = (ext >> 9) & 3;
444 if (scale != 0) {
445 tcg_gen_shli_i32(tmp, add, scale);
446 add = tmp;
447 }
448 return add;
449 }
450
451 /*
452 * Handle a base + index + displacement effective address.
453 * A NULL_QREG base means pc-relative.
454 */
455 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
456 {
457 uint32_t offset;
458 uint16_t ext;
459 TCGv add;
460 TCGv tmp;
461 uint32_t bd, od;
462
463 offset = s->pc;
464 ext = read_im16(env, s);
465
466 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
467 return NULL_QREG;
468
469 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
470 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
471 ext &= ~(3 << 9);
472 }
473
474 if (ext & 0x100) {
475 /* full extension word format */
476 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
477 return NULL_QREG;
478
479 if ((ext & 0x30) > 0x10) {
480 /* base displacement */
481 if ((ext & 0x30) == 0x20) {
482 bd = (int16_t)read_im16(env, s);
483 } else {
484 bd = read_im32(env, s);
485 }
486 } else {
487 bd = 0;
488 }
489 tmp = mark_to_release(s, tcg_temp_new());
490 if ((ext & 0x44) == 0) {
491 /* pre-index */
492 add = gen_addr_index(s, ext, tmp);
493 } else {
494 add = NULL_QREG;
495 }
496 if ((ext & 0x80) == 0) {
497 /* base not suppressed */
498 if (IS_NULL_QREG(base)) {
499 base = mark_to_release(s, tcg_const_i32(offset + bd));
500 bd = 0;
501 }
502 if (!IS_NULL_QREG(add)) {
503 tcg_gen_add_i32(tmp, add, base);
504 add = tmp;
505 } else {
506 add = base;
507 }
508 }
509 if (!IS_NULL_QREG(add)) {
510 if (bd != 0) {
511 tcg_gen_addi_i32(tmp, add, bd);
512 add = tmp;
513 }
514 } else {
515 add = mark_to_release(s, tcg_const_i32(bd));
516 }
517 if ((ext & 3) != 0) {
518 /* memory indirect */
519 base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
520 if ((ext & 0x44) == 4) {
521 add = gen_addr_index(s, ext, tmp);
522 tcg_gen_add_i32(tmp, add, base);
523 add = tmp;
524 } else {
525 add = base;
526 }
527 if ((ext & 3) > 1) {
528 /* outer displacement */
529 if ((ext & 3) == 2) {
530 od = (int16_t)read_im16(env, s);
531 } else {
532 od = read_im32(env, s);
533 }
534 } else {
535 od = 0;
536 }
537 if (od != 0) {
538 tcg_gen_addi_i32(tmp, add, od);
539 add = tmp;
540 }
541 }
542 } else {
543 /* brief extension word format */
544 tmp = mark_to_release(s, tcg_temp_new());
545 add = gen_addr_index(s, ext, tmp);
546 if (!IS_NULL_QREG(base)) {
547 tcg_gen_add_i32(tmp, add, base);
548 if ((int8_t)ext)
549 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
550 } else {
551 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
552 }
553 add = tmp;
554 }
555 return add;
556 }
557
558 /* Sign or zero extend a value. */
559
560 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
561 {
562 switch (opsize) {
563 case OS_BYTE:
564 if (sign) {
565 tcg_gen_ext8s_i32(res, val);
566 } else {
567 tcg_gen_ext8u_i32(res, val);
568 }
569 break;
570 case OS_WORD:
571 if (sign) {
572 tcg_gen_ext16s_i32(res, val);
573 } else {
574 tcg_gen_ext16u_i32(res, val);
575 }
576 break;
577 case OS_LONG:
578 tcg_gen_mov_i32(res, val);
579 break;
580 default:
581 g_assert_not_reached();
582 }
583 }
584
585 /* Evaluate all the CC flags. */
586
587 static void gen_flush_flags(DisasContext *s)
588 {
589 TCGv t0, t1;
590
591 switch (s->cc_op) {
592 case CC_OP_FLAGS:
593 return;
594
595 case CC_OP_ADDB:
596 case CC_OP_ADDW:
597 case CC_OP_ADDL:
598 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
599 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
600 /* Compute signed overflow for addition. */
601 t0 = tcg_temp_new();
602 t1 = tcg_temp_new();
603 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
604 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
605 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
606 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
607 tcg_temp_free(t0);
608 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
609 tcg_temp_free(t1);
610 break;
611
612 case CC_OP_SUBB:
613 case CC_OP_SUBW:
614 case CC_OP_SUBL:
615 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
616 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
617 /* Compute signed overflow for subtraction. */
618 t0 = tcg_temp_new();
619 t1 = tcg_temp_new();
620 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
621 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
622 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
623 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
624 tcg_temp_free(t0);
625 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
626 tcg_temp_free(t1);
627 break;
628
629 case CC_OP_CMPB:
630 case CC_OP_CMPW:
631 case CC_OP_CMPL:
632 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
633 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
634 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
635 /* Compute signed overflow for subtraction. */
636 t0 = tcg_temp_new();
637 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
638 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
639 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
640 tcg_temp_free(t0);
641 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
642 break;
643
644 case CC_OP_LOGIC:
645 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
646 tcg_gen_movi_i32(QREG_CC_C, 0);
647 tcg_gen_movi_i32(QREG_CC_V, 0);
648 break;
649
650 case CC_OP_DYNAMIC:
651 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
652 s->cc_op_synced = 1;
653 break;
654
655 default:
656 t0 = tcg_const_i32(s->cc_op);
657 gen_helper_flush_flags(cpu_env, t0);
658 tcg_temp_free(t0);
659 s->cc_op_synced = 1;
660 break;
661 }
662
663 /* Note that flush_flags also assigned to env->cc_op. */
664 s->cc_op = CC_OP_FLAGS;
665 }
666
667 static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
668 {
669 TCGv tmp;
670
671 if (opsize == OS_LONG) {
672 tmp = val;
673 } else {
674 tmp = mark_to_release(s, tcg_temp_new());
675 gen_ext(tmp, val, opsize, sign);
676 }
677
678 return tmp;
679 }
680
681 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
682 {
683 gen_ext(QREG_CC_N, val, opsize, 1);
684 set_cc_op(s, CC_OP_LOGIC);
685 }
686
687 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
688 {
689 tcg_gen_mov_i32(QREG_CC_N, dest);
690 tcg_gen_mov_i32(QREG_CC_V, src);
691 set_cc_op(s, CC_OP_CMPB + opsize);
692 }
693
694 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
695 {
696 gen_ext(QREG_CC_N, dest, opsize, 1);
697 tcg_gen_mov_i32(QREG_CC_V, src);
698 }
699
700 static inline int opsize_bytes(int opsize)
701 {
702 switch (opsize) {
703 case OS_BYTE: return 1;
704 case OS_WORD: return 2;
705 case OS_LONG: return 4;
706 case OS_SINGLE: return 4;
707 case OS_DOUBLE: return 8;
708 case OS_EXTENDED: return 12;
709 case OS_PACKED: return 12;
710 default:
711 g_assert_not_reached();
712 }
713 }
714
715 static inline int insn_opsize(int insn)
716 {
717 switch ((insn >> 6) & 3) {
718 case 0: return OS_BYTE;
719 case 1: return OS_WORD;
720 case 2: return OS_LONG;
721 default:
722 g_assert_not_reached();
723 }
724 }
725
726 static inline int ext_opsize(int ext, int pos)
727 {
728 switch ((ext >> pos) & 7) {
729 case 0: return OS_LONG;
730 case 1: return OS_SINGLE;
731 case 2: return OS_EXTENDED;
732 case 3: return OS_PACKED;
733 case 4: return OS_WORD;
734 case 5: return OS_DOUBLE;
735 case 6: return OS_BYTE;
736 default:
737 g_assert_not_reached();
738 }
739 }
740
741 /*
742 * Assign value to a register. If the width is less than the register width
743 * only the low part of the register is set.
744 */
745 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
746 {
747 TCGv tmp;
748 switch (opsize) {
749 case OS_BYTE:
750 tcg_gen_andi_i32(reg, reg, 0xffffff00);
751 tmp = tcg_temp_new();
752 tcg_gen_ext8u_i32(tmp, val);
753 tcg_gen_or_i32(reg, reg, tmp);
754 tcg_temp_free(tmp);
755 break;
756 case OS_WORD:
757 tcg_gen_andi_i32(reg, reg, 0xffff0000);
758 tmp = tcg_temp_new();
759 tcg_gen_ext16u_i32(tmp, val);
760 tcg_gen_or_i32(reg, reg, tmp);
761 tcg_temp_free(tmp);
762 break;
763 case OS_LONG:
764 case OS_SINGLE:
765 tcg_gen_mov_i32(reg, val);
766 break;
767 default:
768 g_assert_not_reached();
769 }
770 }
771
772 /*
773 * Generate code for an "effective address". Does not adjust the base
774 * register for autoincrement addressing modes.
775 */
776 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
777 int mode, int reg0, int opsize)
778 {
779 TCGv reg;
780 TCGv tmp;
781 uint16_t ext;
782 uint32_t offset;
783
784 switch (mode) {
785 case 0: /* Data register direct. */
786 case 1: /* Address register direct. */
787 return NULL_QREG;
788 case 3: /* Indirect postincrement. */
789 if (opsize == OS_UNSIZED) {
790 return NULL_QREG;
791 }
792 /* fallthru */
793 case 2: /* Indirect register */
794 return get_areg(s, reg0);
795 case 4: /* Indirect predecrememnt. */
796 if (opsize == OS_UNSIZED) {
797 return NULL_QREG;
798 }
799 reg = get_areg(s, reg0);
800 tmp = mark_to_release(s, tcg_temp_new());
801 if (reg0 == 7 && opsize == OS_BYTE &&
802 m68k_feature(s->env, M68K_FEATURE_M68000)) {
803 tcg_gen_subi_i32(tmp, reg, 2);
804 } else {
805 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
806 }
807 return tmp;
808 case 5: /* Indirect displacement. */
809 reg = get_areg(s, reg0);
810 tmp = mark_to_release(s, tcg_temp_new());
811 ext = read_im16(env, s);
812 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
813 return tmp;
814 case 6: /* Indirect index + displacement. */
815 reg = get_areg(s, reg0);
816 return gen_lea_indexed(env, s, reg);
817 case 7: /* Other */
818 switch (reg0) {
819 case 0: /* Absolute short. */
820 offset = (int16_t)read_im16(env, s);
821 return mark_to_release(s, tcg_const_i32(offset));
822 case 1: /* Absolute long. */
823 offset = read_im32(env, s);
824 return mark_to_release(s, tcg_const_i32(offset));
825 case 2: /* pc displacement */
826 offset = s->pc;
827 offset += (int16_t)read_im16(env, s);
828 return mark_to_release(s, tcg_const_i32(offset));
829 case 3: /* pc index+displacement. */
830 return gen_lea_indexed(env, s, NULL_QREG);
831 case 4: /* Immediate. */
832 default:
833 return NULL_QREG;
834 }
835 }
836 /* Should never happen. */
837 return NULL_QREG;
838 }
839
840 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
841 int opsize)
842 {
843 int mode = extract32(insn, 3, 3);
844 int reg0 = REG(insn, 0);
845 return gen_lea_mode(env, s, mode, reg0, opsize);
846 }
847
848 /*
849 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
850 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
851 * ADDRP is non-null for readwrite operands.
852 */
853 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
854 int opsize, TCGv val, TCGv *addrp, ea_what what,
855 int index)
856 {
857 TCGv reg, tmp, result;
858 int32_t offset;
859
860 switch (mode) {
861 case 0: /* Data register direct. */
862 reg = cpu_dregs[reg0];
863 if (what == EA_STORE) {
864 gen_partset_reg(opsize, reg, val);
865 return store_dummy;
866 } else {
867 return gen_extend(s, reg, opsize, what == EA_LOADS);
868 }
869 case 1: /* Address register direct. */
870 reg = get_areg(s, reg0);
871 if (what == EA_STORE) {
872 tcg_gen_mov_i32(reg, val);
873 return store_dummy;
874 } else {
875 return gen_extend(s, reg, opsize, what == EA_LOADS);
876 }
877 case 2: /* Indirect register */
878 reg = get_areg(s, reg0);
879 return gen_ldst(s, opsize, reg, val, what, index);
880 case 3: /* Indirect postincrement. */
881 reg = get_areg(s, reg0);
882 result = gen_ldst(s, opsize, reg, val, what, index);
883 if (what == EA_STORE || !addrp) {
884 TCGv tmp = tcg_temp_new();
885 if (reg0 == 7 && opsize == OS_BYTE &&
886 m68k_feature(s->env, M68K_FEATURE_M68000)) {
887 tcg_gen_addi_i32(tmp, reg, 2);
888 } else {
889 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
890 }
891 delay_set_areg(s, reg0, tmp, true);
892 }
893 return result;
894 case 4: /* Indirect predecrememnt. */
895 if (addrp && what == EA_STORE) {
896 tmp = *addrp;
897 } else {
898 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
899 if (IS_NULL_QREG(tmp)) {
900 return tmp;
901 }
902 if (addrp) {
903 *addrp = tmp;
904 }
905 }
906 result = gen_ldst(s, opsize, tmp, val, what, index);
907 if (what == EA_STORE || !addrp) {
908 delay_set_areg(s, reg0, tmp, false);
909 }
910 return result;
911 case 5: /* Indirect displacement. */
912 case 6: /* Indirect index + displacement. */
913 do_indirect:
914 if (addrp && what == EA_STORE) {
915 tmp = *addrp;
916 } else {
917 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
918 if (IS_NULL_QREG(tmp)) {
919 return tmp;
920 }
921 if (addrp) {
922 *addrp = tmp;
923 }
924 }
925 return gen_ldst(s, opsize, tmp, val, what, index);
926 case 7: /* Other */
927 switch (reg0) {
928 case 0: /* Absolute short. */
929 case 1: /* Absolute long. */
930 case 2: /* pc displacement */
931 case 3: /* pc index+displacement. */
932 goto do_indirect;
933 case 4: /* Immediate. */
934 /* Sign extend values for consistency. */
935 switch (opsize) {
936 case OS_BYTE:
937 if (what == EA_LOADS) {
938 offset = (int8_t)read_im8(env, s);
939 } else {
940 offset = read_im8(env, s);
941 }
942 break;
943 case OS_WORD:
944 if (what == EA_LOADS) {
945 offset = (int16_t)read_im16(env, s);
946 } else {
947 offset = read_im16(env, s);
948 }
949 break;
950 case OS_LONG:
951 offset = read_im32(env, s);
952 break;
953 default:
954 g_assert_not_reached();
955 }
956 return mark_to_release(s, tcg_const_i32(offset));
957 default:
958 return NULL_QREG;
959 }
960 }
961 /* Should never happen. */
962 return NULL_QREG;
963 }
964
965 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
966 int opsize, TCGv val, TCGv *addrp, ea_what what, int index)
967 {
968 int mode = extract32(insn, 3, 3);
969 int reg0 = REG(insn, 0);
970 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index);
971 }
972
973 static TCGv_ptr gen_fp_ptr(int freg)
974 {
975 TCGv_ptr fp = tcg_temp_new_ptr();
976 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
977 return fp;
978 }
979
980 static TCGv_ptr gen_fp_result_ptr(void)
981 {
982 TCGv_ptr fp = tcg_temp_new_ptr();
983 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
984 return fp;
985 }
986
987 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
988 {
989 TCGv t32;
990 TCGv_i64 t64;
991
992 t32 = tcg_temp_new();
993 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
994 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
995 tcg_temp_free(t32);
996
997 t64 = tcg_temp_new_i64();
998 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
999 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
1000 tcg_temp_free_i64(t64);
1001 }
1002
1003 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1004 int index)
1005 {
1006 TCGv tmp;
1007 TCGv_i64 t64;
1008
1009 t64 = tcg_temp_new_i64();
1010 tmp = tcg_temp_new();
1011 switch (opsize) {
1012 case OS_BYTE:
1013 tcg_gen_qemu_ld8s(tmp, addr, index);
1014 gen_helper_exts32(cpu_env, fp, tmp);
1015 break;
1016 case OS_WORD:
1017 tcg_gen_qemu_ld16s(tmp, addr, index);
1018 gen_helper_exts32(cpu_env, fp, tmp);
1019 break;
1020 case OS_LONG:
1021 tcg_gen_qemu_ld32u(tmp, addr, index);
1022 gen_helper_exts32(cpu_env, fp, tmp);
1023 break;
1024 case OS_SINGLE:
1025 tcg_gen_qemu_ld32u(tmp, addr, index);
1026 gen_helper_extf32(cpu_env, fp, tmp);
1027 break;
1028 case OS_DOUBLE:
1029 tcg_gen_qemu_ld64(t64, addr, index);
1030 gen_helper_extf64(cpu_env, fp, t64);
1031 break;
1032 case OS_EXTENDED:
1033 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1034 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1035 break;
1036 }
1037 tcg_gen_qemu_ld32u(tmp, addr, index);
1038 tcg_gen_shri_i32(tmp, tmp, 16);
1039 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1040 tcg_gen_addi_i32(tmp, addr, 4);
1041 tcg_gen_qemu_ld64(t64, tmp, index);
1042 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1043 break;
1044 case OS_PACKED:
1045 /*
1046 * unimplemented data type on 68040/ColdFire
1047 * FIXME if needed for another FPU
1048 */
1049 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1050 break;
1051 default:
1052 g_assert_not_reached();
1053 }
1054 tcg_temp_free(tmp);
1055 tcg_temp_free_i64(t64);
1056 }
1057
1058 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1059 int index)
1060 {
1061 TCGv tmp;
1062 TCGv_i64 t64;
1063
1064 t64 = tcg_temp_new_i64();
1065 tmp = tcg_temp_new();
1066 switch (opsize) {
1067 case OS_BYTE:
1068 gen_helper_reds32(tmp, cpu_env, fp);
1069 tcg_gen_qemu_st8(tmp, addr, index);
1070 break;
1071 case OS_WORD:
1072 gen_helper_reds32(tmp, cpu_env, fp);
1073 tcg_gen_qemu_st16(tmp, addr, index);
1074 break;
1075 case OS_LONG:
1076 gen_helper_reds32(tmp, cpu_env, fp);
1077 tcg_gen_qemu_st32(tmp, addr, index);
1078 break;
1079 case OS_SINGLE:
1080 gen_helper_redf32(tmp, cpu_env, fp);
1081 tcg_gen_qemu_st32(tmp, addr, index);
1082 break;
1083 case OS_DOUBLE:
1084 gen_helper_redf64(t64, cpu_env, fp);
1085 tcg_gen_qemu_st64(t64, addr, index);
1086 break;
1087 case OS_EXTENDED:
1088 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1089 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1090 break;
1091 }
1092 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1093 tcg_gen_shli_i32(tmp, tmp, 16);
1094 tcg_gen_qemu_st32(tmp, addr, index);
1095 tcg_gen_addi_i32(tmp, addr, 4);
1096 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1097 tcg_gen_qemu_st64(t64, tmp, index);
1098 break;
1099 case OS_PACKED:
1100 /*
1101 * unimplemented data type on 68040/ColdFire
1102 * FIXME if needed for another FPU
1103 */
1104 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1105 break;
1106 default:
1107 g_assert_not_reached();
1108 }
1109 tcg_temp_free(tmp);
1110 tcg_temp_free_i64(t64);
1111 }
1112
1113 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1114 TCGv_ptr fp, ea_what what, int index)
1115 {
1116 if (what == EA_STORE) {
1117 gen_store_fp(s, opsize, addr, fp, index);
1118 } else {
1119 gen_load_fp(s, opsize, addr, fp, index);
1120 }
1121 }
1122
1123 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1124 int reg0, int opsize, TCGv_ptr fp, ea_what what,
1125 int index)
1126 {
1127 TCGv reg, addr, tmp;
1128 TCGv_i64 t64;
1129
1130 switch (mode) {
1131 case 0: /* Data register direct. */
1132 reg = cpu_dregs[reg0];
1133 if (what == EA_STORE) {
1134 switch (opsize) {
1135 case OS_BYTE:
1136 case OS_WORD:
1137 case OS_LONG:
1138 gen_helper_reds32(reg, cpu_env, fp);
1139 break;
1140 case OS_SINGLE:
1141 gen_helper_redf32(reg, cpu_env, fp);
1142 break;
1143 default:
1144 g_assert_not_reached();
1145 }
1146 } else {
1147 tmp = tcg_temp_new();
1148 switch (opsize) {
1149 case OS_BYTE:
1150 tcg_gen_ext8s_i32(tmp, reg);
1151 gen_helper_exts32(cpu_env, fp, tmp);
1152 break;
1153 case OS_WORD:
1154 tcg_gen_ext16s_i32(tmp, reg);
1155 gen_helper_exts32(cpu_env, fp, tmp);
1156 break;
1157 case OS_LONG:
1158 gen_helper_exts32(cpu_env, fp, reg);
1159 break;
1160 case OS_SINGLE:
1161 gen_helper_extf32(cpu_env, fp, reg);
1162 break;
1163 default:
1164 g_assert_not_reached();
1165 }
1166 tcg_temp_free(tmp);
1167 }
1168 return 0;
1169 case 1: /* Address register direct. */
1170 return -1;
1171 case 2: /* Indirect register */
1172 addr = get_areg(s, reg0);
1173 gen_ldst_fp(s, opsize, addr, fp, what, index);
1174 return 0;
1175 case 3: /* Indirect postincrement. */
1176 addr = cpu_aregs[reg0];
1177 gen_ldst_fp(s, opsize, addr, fp, what, index);
1178 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1179 return 0;
1180 case 4: /* Indirect predecrememnt. */
1181 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1182 if (IS_NULL_QREG(addr)) {
1183 return -1;
1184 }
1185 gen_ldst_fp(s, opsize, addr, fp, what, index);
1186 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1187 return 0;
1188 case 5: /* Indirect displacement. */
1189 case 6: /* Indirect index + displacement. */
1190 do_indirect:
1191 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1192 if (IS_NULL_QREG(addr)) {
1193 return -1;
1194 }
1195 gen_ldst_fp(s, opsize, addr, fp, what, index);
1196 return 0;
1197 case 7: /* Other */
1198 switch (reg0) {
1199 case 0: /* Absolute short. */
1200 case 1: /* Absolute long. */
1201 case 2: /* pc displacement */
1202 case 3: /* pc index+displacement. */
1203 goto do_indirect;
1204 case 4: /* Immediate. */
1205 if (what == EA_STORE) {
1206 return -1;
1207 }
1208 switch (opsize) {
1209 case OS_BYTE:
1210 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1211 gen_helper_exts32(cpu_env, fp, tmp);
1212 tcg_temp_free(tmp);
1213 break;
1214 case OS_WORD:
1215 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1216 gen_helper_exts32(cpu_env, fp, tmp);
1217 tcg_temp_free(tmp);
1218 break;
1219 case OS_LONG:
1220 tmp = tcg_const_i32(read_im32(env, s));
1221 gen_helper_exts32(cpu_env, fp, tmp);
1222 tcg_temp_free(tmp);
1223 break;
1224 case OS_SINGLE:
1225 tmp = tcg_const_i32(read_im32(env, s));
1226 gen_helper_extf32(cpu_env, fp, tmp);
1227 tcg_temp_free(tmp);
1228 break;
1229 case OS_DOUBLE:
1230 t64 = tcg_const_i64(read_im64(env, s));
1231 gen_helper_extf64(cpu_env, fp, t64);
1232 tcg_temp_free_i64(t64);
1233 break;
1234 case OS_EXTENDED:
1235 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1236 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1237 break;
1238 }
1239 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1240 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1241 tcg_temp_free(tmp);
1242 t64 = tcg_const_i64(read_im64(env, s));
1243 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1244 tcg_temp_free_i64(t64);
1245 break;
1246 case OS_PACKED:
1247 /*
1248 * unimplemented data type on 68040/ColdFire
1249 * FIXME if needed for another FPU
1250 */
1251 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1252 break;
1253 default:
1254 g_assert_not_reached();
1255 }
1256 return 0;
1257 default:
1258 return -1;
1259 }
1260 }
1261 return -1;
1262 }
1263
1264 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1265 int opsize, TCGv_ptr fp, ea_what what, int index)
1266 {
1267 int mode = extract32(insn, 3, 3);
1268 int reg0 = REG(insn, 0);
1269 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index);
1270 }
1271
1272 typedef struct {
1273 TCGCond tcond;
1274 bool g1;
1275 bool g2;
1276 TCGv v1;
1277 TCGv v2;
1278 } DisasCompare;
1279
1280 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1281 {
1282 TCGv tmp, tmp2;
1283 TCGCond tcond;
1284 CCOp op = s->cc_op;
1285
1286 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1287 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1288 c->g1 = c->g2 = 1;
1289 c->v1 = QREG_CC_N;
1290 c->v2 = QREG_CC_V;
1291 switch (cond) {
1292 case 2: /* HI */
1293 case 3: /* LS */
1294 tcond = TCG_COND_LEU;
1295 goto done;
1296 case 4: /* CC */
1297 case 5: /* CS */
1298 tcond = TCG_COND_LTU;
1299 goto done;
1300 case 6: /* NE */
1301 case 7: /* EQ */
1302 tcond = TCG_COND_EQ;
1303 goto done;
1304 case 10: /* PL */
1305 case 11: /* MI */
1306 c->g1 = c->g2 = 0;
1307 c->v2 = tcg_const_i32(0);
1308 c->v1 = tmp = tcg_temp_new();
1309 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1310 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1311 /* fallthru */
1312 case 12: /* GE */
1313 case 13: /* LT */
1314 tcond = TCG_COND_LT;
1315 goto done;
1316 case 14: /* GT */
1317 case 15: /* LE */
1318 tcond = TCG_COND_LE;
1319 goto done;
1320 }
1321 }
1322
1323 c->g1 = 1;
1324 c->g2 = 0;
1325 c->v2 = tcg_const_i32(0);
1326
1327 switch (cond) {
1328 case 0: /* T */
1329 case 1: /* F */
1330 c->v1 = c->v2;
1331 tcond = TCG_COND_NEVER;
1332 goto done;
1333 case 14: /* GT (!(Z || (N ^ V))) */
1334 case 15: /* LE (Z || (N ^ V)) */
1335 /*
1336 * Logic operations clear V, which simplifies LE to (Z || N),
1337 * and since Z and N are co-located, this becomes a normal
1338 * comparison vs N.
1339 */
1340 if (op == CC_OP_LOGIC) {
1341 c->v1 = QREG_CC_N;
1342 tcond = TCG_COND_LE;
1343 goto done;
1344 }
1345 break;
1346 case 12: /* GE (!(N ^ V)) */
1347 case 13: /* LT (N ^ V) */
1348 /* Logic operations clear V, which simplifies this to N. */
1349 if (op != CC_OP_LOGIC) {
1350 break;
1351 }
1352 /* fallthru */
1353 case 10: /* PL (!N) */
1354 case 11: /* MI (N) */
1355 /* Several cases represent N normally. */
1356 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1357 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1358 op == CC_OP_LOGIC) {
1359 c->v1 = QREG_CC_N;
1360 tcond = TCG_COND_LT;
1361 goto done;
1362 }
1363 break;
1364 case 6: /* NE (!Z) */
1365 case 7: /* EQ (Z) */
1366 /* Some cases fold Z into N. */
1367 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1368 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1369 op == CC_OP_LOGIC) {
1370 tcond = TCG_COND_EQ;
1371 c->v1 = QREG_CC_N;
1372 goto done;
1373 }
1374 break;
1375 case 4: /* CC (!C) */
1376 case 5: /* CS (C) */
1377 /* Some cases fold C into X. */
1378 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1379 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1380 tcond = TCG_COND_NE;
1381 c->v1 = QREG_CC_X;
1382 goto done;
1383 }
1384 /* fallthru */
1385 case 8: /* VC (!V) */
1386 case 9: /* VS (V) */
1387 /* Logic operations clear V and C. */
1388 if (op == CC_OP_LOGIC) {
1389 tcond = TCG_COND_NEVER;
1390 c->v1 = c->v2;
1391 goto done;
1392 }
1393 break;
1394 }
1395
1396 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1397 gen_flush_flags(s);
1398
1399 switch (cond) {
1400 case 0: /* T */
1401 case 1: /* F */
1402 default:
1403 /* Invalid, or handled above. */
1404 abort();
1405 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1406 case 3: /* LS (C || Z) */
1407 c->v1 = tmp = tcg_temp_new();
1408 c->g1 = 0;
1409 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1410 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1411 tcond = TCG_COND_NE;
1412 break;
1413 case 4: /* CC (!C) */
1414 case 5: /* CS (C) */
1415 c->v1 = QREG_CC_C;
1416 tcond = TCG_COND_NE;
1417 break;
1418 case 6: /* NE (!Z) */
1419 case 7: /* EQ (Z) */
1420 c->v1 = QREG_CC_Z;
1421 tcond = TCG_COND_EQ;
1422 break;
1423 case 8: /* VC (!V) */
1424 case 9: /* VS (V) */
1425 c->v1 = QREG_CC_V;
1426 tcond = TCG_COND_LT;
1427 break;
1428 case 10: /* PL (!N) */
1429 case 11: /* MI (N) */
1430 c->v1 = QREG_CC_N;
1431 tcond = TCG_COND_LT;
1432 break;
1433 case 12: /* GE (!(N ^ V)) */
1434 case 13: /* LT (N ^ V) */
1435 c->v1 = tmp = tcg_temp_new();
1436 c->g1 = 0;
1437 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1438 tcond = TCG_COND_LT;
1439 break;
1440 case 14: /* GT (!(Z || (N ^ V))) */
1441 case 15: /* LE (Z || (N ^ V)) */
1442 c->v1 = tmp = tcg_temp_new();
1443 c->g1 = 0;
1444 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1445 tcg_gen_neg_i32(tmp, tmp);
1446 tmp2 = tcg_temp_new();
1447 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1448 tcg_gen_or_i32(tmp, tmp, tmp2);
1449 tcg_temp_free(tmp2);
1450 tcond = TCG_COND_LT;
1451 break;
1452 }
1453
1454 done:
1455 if ((cond & 1) == 0) {
1456 tcond = tcg_invert_cond(tcond);
1457 }
1458 c->tcond = tcond;
1459 }
1460
1461 static void free_cond(DisasCompare *c)
1462 {
1463 if (!c->g1) {
1464 tcg_temp_free(c->v1);
1465 }
1466 if (!c->g2) {
1467 tcg_temp_free(c->v2);
1468 }
1469 }
1470
1471 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1472 {
1473 DisasCompare c;
1474
1475 gen_cc_cond(&c, s, cond);
1476 update_cc_op(s);
1477 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1478 free_cond(&c);
1479 }
1480
1481 /* Force a TB lookup after an instruction that changes the CPU state. */
1482 static void gen_exit_tb(DisasContext *s)
1483 {
1484 update_cc_op(s);
1485 tcg_gen_movi_i32(QREG_PC, s->pc);
1486 s->base.is_jmp = DISAS_EXIT;
1487 }
1488
1489 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1490 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1491 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1492 if (IS_NULL_QREG(result)) { \
1493 gen_addr_fault(s); \
1494 return; \
1495 } \
1496 } while (0)
1497
1498 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1499 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1500 EA_STORE, IS_USER(s)); \
1501 if (IS_NULL_QREG(ea_result)) { \
1502 gen_addr_fault(s); \
1503 return; \
1504 } \
1505 } while (0)
1506
1507 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1508 {
1509 #ifndef CONFIG_USER_ONLY
1510 return (s->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
1511 || (s->base.pc_next & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1512 #else
1513 return true;
1514 #endif
1515 }
1516
1517 /* Generate a jump to an immediate address. */
1518 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1519 {
1520 if (unlikely(is_singlestepping(s))) {
1521 gen_exception(s, dest, EXCP_DEBUG);
1522 } else if (use_goto_tb(s, dest)) {
1523 tcg_gen_goto_tb(n);
1524 tcg_gen_movi_i32(QREG_PC, dest);
1525 tcg_gen_exit_tb(s->base.tb, n);
1526 } else {
1527 gen_jmp_im(s, dest);
1528 tcg_gen_exit_tb(NULL, 0);
1529 }
1530 s->base.is_jmp = DISAS_NORETURN;
1531 }
1532
1533 DISAS_INSN(scc)
1534 {
1535 DisasCompare c;
1536 int cond;
1537 TCGv tmp;
1538
1539 cond = (insn >> 8) & 0xf;
1540 gen_cc_cond(&c, s, cond);
1541
1542 tmp = tcg_temp_new();
1543 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1544 free_cond(&c);
1545
1546 tcg_gen_neg_i32(tmp, tmp);
1547 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1548 tcg_temp_free(tmp);
1549 }
1550
1551 DISAS_INSN(dbcc)
1552 {
1553 TCGLabel *l1;
1554 TCGv reg;
1555 TCGv tmp;
1556 int16_t offset;
1557 uint32_t base;
1558
1559 reg = DREG(insn, 0);
1560 base = s->pc;
1561 offset = (int16_t)read_im16(env, s);
1562 l1 = gen_new_label();
1563 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1564
1565 tmp = tcg_temp_new();
1566 tcg_gen_ext16s_i32(tmp, reg);
1567 tcg_gen_addi_i32(tmp, tmp, -1);
1568 gen_partset_reg(OS_WORD, reg, tmp);
1569 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1570 gen_jmp_tb(s, 1, base + offset);
1571 gen_set_label(l1);
1572 gen_jmp_tb(s, 0, s->pc);
1573 }
1574
1575 DISAS_INSN(undef_mac)
1576 {
1577 gen_exception(s, s->base.pc_next, EXCP_LINEA);
1578 }
1579
1580 DISAS_INSN(undef_fpu)
1581 {
1582 gen_exception(s, s->base.pc_next, EXCP_LINEF);
1583 }
1584
1585 DISAS_INSN(undef)
1586 {
1587 /*
1588 * ??? This is both instructions that are as yet unimplemented
1589 * for the 680x0 series, as well as those that are implemented
1590 * but actually illegal for CPU32 or pre-68020.
1591 */
1592 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
1593 insn, s->base.pc_next);
1594 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1595 }
1596
1597 DISAS_INSN(mulw)
1598 {
1599 TCGv reg;
1600 TCGv tmp;
1601 TCGv src;
1602 int sign;
1603
1604 sign = (insn & 0x100) != 0;
1605 reg = DREG(insn, 9);
1606 tmp = tcg_temp_new();
1607 if (sign)
1608 tcg_gen_ext16s_i32(tmp, reg);
1609 else
1610 tcg_gen_ext16u_i32(tmp, reg);
1611 SRC_EA(env, src, OS_WORD, sign, NULL);
1612 tcg_gen_mul_i32(tmp, tmp, src);
1613 tcg_gen_mov_i32(reg, tmp);
1614 gen_logic_cc(s, tmp, OS_LONG);
1615 tcg_temp_free(tmp);
1616 }
1617
1618 DISAS_INSN(divw)
1619 {
1620 int sign;
1621 TCGv src;
1622 TCGv destr;
1623
1624 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1625
1626 sign = (insn & 0x100) != 0;
1627
1628 /* dest.l / src.w */
1629
1630 SRC_EA(env, src, OS_WORD, sign, NULL);
1631 destr = tcg_const_i32(REG(insn, 9));
1632 if (sign) {
1633 gen_helper_divsw(cpu_env, destr, src);
1634 } else {
1635 gen_helper_divuw(cpu_env, destr, src);
1636 }
1637 tcg_temp_free(destr);
1638
1639 set_cc_op(s, CC_OP_FLAGS);
1640 }
1641
1642 DISAS_INSN(divl)
1643 {
1644 TCGv num, reg, den;
1645 int sign;
1646 uint16_t ext;
1647
1648 ext = read_im16(env, s);
1649
1650 sign = (ext & 0x0800) != 0;
1651
1652 if (ext & 0x400) {
1653 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1654 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1655 return;
1656 }
1657
1658 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1659
1660 SRC_EA(env, den, OS_LONG, 0, NULL);
1661 num = tcg_const_i32(REG(ext, 12));
1662 reg = tcg_const_i32(REG(ext, 0));
1663 if (sign) {
1664 gen_helper_divsll(cpu_env, num, reg, den);
1665 } else {
1666 gen_helper_divull(cpu_env, num, reg, den);
1667 }
1668 tcg_temp_free(reg);
1669 tcg_temp_free(num);
1670 set_cc_op(s, CC_OP_FLAGS);
1671 return;
1672 }
1673
1674 /* divX.l <EA>, Dq 32/32 -> 32q */
1675 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1676
1677 SRC_EA(env, den, OS_LONG, 0, NULL);
1678 num = tcg_const_i32(REG(ext, 12));
1679 reg = tcg_const_i32(REG(ext, 0));
1680 if (sign) {
1681 gen_helper_divsl(cpu_env, num, reg, den);
1682 } else {
1683 gen_helper_divul(cpu_env, num, reg, den);
1684 }
1685 tcg_temp_free(reg);
1686 tcg_temp_free(num);
1687
1688 set_cc_op(s, CC_OP_FLAGS);
1689 }
1690
1691 static void bcd_add(TCGv dest, TCGv src)
1692 {
1693 TCGv t0, t1;
1694
1695 /*
1696 * dest10 = dest10 + src10 + X
1697 *
1698 * t1 = src
1699 * t2 = t1 + 0x066
1700 * t3 = t2 + dest + X
1701 * t4 = t2 ^ dest
1702 * t5 = t3 ^ t4
1703 * t6 = ~t5 & 0x110
1704 * t7 = (t6 >> 2) | (t6 >> 3)
1705 * return t3 - t7
1706 */
1707
1708 /*
1709 * t1 = (src + 0x066) + dest + X
1710 * = result with some possible exceeding 0x6
1711 */
1712
1713 t0 = tcg_const_i32(0x066);
1714 tcg_gen_add_i32(t0, t0, src);
1715
1716 t1 = tcg_temp_new();
1717 tcg_gen_add_i32(t1, t0, dest);
1718 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1719
1720 /* we will remove exceeding 0x6 where there is no carry */
1721
1722 /*
1723 * t0 = (src + 0x0066) ^ dest
1724 * = t1 without carries
1725 */
1726
1727 tcg_gen_xor_i32(t0, t0, dest);
1728
1729 /*
1730 * extract the carries
1731 * t0 = t0 ^ t1
1732 * = only the carries
1733 */
1734
1735 tcg_gen_xor_i32(t0, t0, t1);
1736
1737 /*
1738 * generate 0x1 where there is no carry
1739 * and for each 0x10, generate a 0x6
1740 */
1741
1742 tcg_gen_shri_i32(t0, t0, 3);
1743 tcg_gen_not_i32(t0, t0);
1744 tcg_gen_andi_i32(t0, t0, 0x22);
1745 tcg_gen_add_i32(dest, t0, t0);
1746 tcg_gen_add_i32(dest, dest, t0);
1747 tcg_temp_free(t0);
1748
1749 /*
1750 * remove the exceeding 0x6
1751 * for digits that have not generated a carry
1752 */
1753
1754 tcg_gen_sub_i32(dest, t1, dest);
1755 tcg_temp_free(t1);
1756 }
1757
1758 static void bcd_sub(TCGv dest, TCGv src)
1759 {
1760 TCGv t0, t1, t2;
1761
1762 /*
1763 * dest10 = dest10 - src10 - X
1764 * = bcd_add(dest + 1 - X, 0x199 - src)
1765 */
1766
1767 /* t0 = 0x066 + (0x199 - src) */
1768
1769 t0 = tcg_temp_new();
1770 tcg_gen_subfi_i32(t0, 0x1ff, src);
1771
1772 /* t1 = t0 + dest + 1 - X*/
1773
1774 t1 = tcg_temp_new();
1775 tcg_gen_add_i32(t1, t0, dest);
1776 tcg_gen_addi_i32(t1, t1, 1);
1777 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1778
1779 /* t2 = t0 ^ dest */
1780
1781 t2 = tcg_temp_new();
1782 tcg_gen_xor_i32(t2, t0, dest);
1783
1784 /* t0 = t1 ^ t2 */
1785
1786 tcg_gen_xor_i32(t0, t1, t2);
1787
1788 /*
1789 * t2 = ~t0 & 0x110
1790 * t0 = (t2 >> 2) | (t2 >> 3)
1791 *
1792 * to fit on 8bit operands, changed in:
1793 *
1794 * t2 = ~(t0 >> 3) & 0x22
1795 * t0 = t2 + t2
1796 * t0 = t0 + t2
1797 */
1798
1799 tcg_gen_shri_i32(t2, t0, 3);
1800 tcg_gen_not_i32(t2, t2);
1801 tcg_gen_andi_i32(t2, t2, 0x22);
1802 tcg_gen_add_i32(t0, t2, t2);
1803 tcg_gen_add_i32(t0, t0, t2);
1804 tcg_temp_free(t2);
1805
1806 /* return t1 - t0 */
1807
1808 tcg_gen_sub_i32(dest, t1, t0);
1809 tcg_temp_free(t0);
1810 tcg_temp_free(t1);
1811 }
1812
1813 static void bcd_flags(TCGv val)
1814 {
1815 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1816 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1817
1818 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1819
1820 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1821 }
1822
1823 DISAS_INSN(abcd_reg)
1824 {
1825 TCGv src;
1826 TCGv dest;
1827
1828 gen_flush_flags(s); /* !Z is sticky */
1829
1830 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1831 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1832 bcd_add(dest, src);
1833 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1834
1835 bcd_flags(dest);
1836 }
1837
1838 DISAS_INSN(abcd_mem)
1839 {
1840 TCGv src, dest, addr;
1841
1842 gen_flush_flags(s); /* !Z is sticky */
1843
1844 /* Indirect pre-decrement load (mode 4) */
1845
1846 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1847 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1848 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1849 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1850
1851 bcd_add(dest, src);
1852
1853 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1854 EA_STORE, IS_USER(s));
1855
1856 bcd_flags(dest);
1857 }
1858
1859 DISAS_INSN(sbcd_reg)
1860 {
1861 TCGv src, dest;
1862
1863 gen_flush_flags(s); /* !Z is sticky */
1864
1865 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1866 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1867
1868 bcd_sub(dest, src);
1869
1870 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1871
1872 bcd_flags(dest);
1873 }
1874
1875 DISAS_INSN(sbcd_mem)
1876 {
1877 TCGv src, dest, addr;
1878
1879 gen_flush_flags(s); /* !Z is sticky */
1880
1881 /* Indirect pre-decrement load (mode 4) */
1882
1883 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1884 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1885 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1886 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1887
1888 bcd_sub(dest, src);
1889
1890 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1891 EA_STORE, IS_USER(s));
1892
1893 bcd_flags(dest);
1894 }
1895
1896 DISAS_INSN(nbcd)
1897 {
1898 TCGv src, dest;
1899 TCGv addr;
1900
1901 gen_flush_flags(s); /* !Z is sticky */
1902
1903 SRC_EA(env, src, OS_BYTE, 0, &addr);
1904
1905 dest = tcg_const_i32(0);
1906 bcd_sub(dest, src);
1907
1908 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1909
1910 bcd_flags(dest);
1911
1912 tcg_temp_free(dest);
1913 }
1914
1915 DISAS_INSN(addsub)
1916 {
1917 TCGv reg;
1918 TCGv dest;
1919 TCGv src;
1920 TCGv tmp;
1921 TCGv addr;
1922 int add;
1923 int opsize;
1924
1925 add = (insn & 0x4000) != 0;
1926 opsize = insn_opsize(insn);
1927 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1928 dest = tcg_temp_new();
1929 if (insn & 0x100) {
1930 SRC_EA(env, tmp, opsize, 1, &addr);
1931 src = reg;
1932 } else {
1933 tmp = reg;
1934 SRC_EA(env, src, opsize, 1, NULL);
1935 }
1936 if (add) {
1937 tcg_gen_add_i32(dest, tmp, src);
1938 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1939 set_cc_op(s, CC_OP_ADDB + opsize);
1940 } else {
1941 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1942 tcg_gen_sub_i32(dest, tmp, src);
1943 set_cc_op(s, CC_OP_SUBB + opsize);
1944 }
1945 gen_update_cc_add(dest, src, opsize);
1946 if (insn & 0x100) {
1947 DEST_EA(env, insn, opsize, dest, &addr);
1948 } else {
1949 gen_partset_reg(opsize, DREG(insn, 9), dest);
1950 }
1951 tcg_temp_free(dest);
1952 }
1953
1954 /* Reverse the order of the bits in REG. */
1955 DISAS_INSN(bitrev)
1956 {
1957 TCGv reg;
1958 reg = DREG(insn, 0);
1959 gen_helper_bitrev(reg, reg);
1960 }
1961
1962 DISAS_INSN(bitop_reg)
1963 {
1964 int opsize;
1965 int op;
1966 TCGv src1;
1967 TCGv src2;
1968 TCGv tmp;
1969 TCGv addr;
1970 TCGv dest;
1971
1972 if ((insn & 0x38) != 0)
1973 opsize = OS_BYTE;
1974 else
1975 opsize = OS_LONG;
1976 op = (insn >> 6) & 3;
1977 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1978
1979 gen_flush_flags(s);
1980 src2 = tcg_temp_new();
1981 if (opsize == OS_BYTE)
1982 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1983 else
1984 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1985
1986 tmp = tcg_const_i32(1);
1987 tcg_gen_shl_i32(tmp, tmp, src2);
1988 tcg_temp_free(src2);
1989
1990 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1991
1992 dest = tcg_temp_new();
1993 switch (op) {
1994 case 1: /* bchg */
1995 tcg_gen_xor_i32(dest, src1, tmp);
1996 break;
1997 case 2: /* bclr */
1998 tcg_gen_andc_i32(dest, src1, tmp);
1999 break;
2000 case 3: /* bset */
2001 tcg_gen_or_i32(dest, src1, tmp);
2002 break;
2003 default: /* btst */
2004 break;
2005 }
2006 tcg_temp_free(tmp);
2007 if (op) {
2008 DEST_EA(env, insn, opsize, dest, &addr);
2009 }
2010 tcg_temp_free(dest);
2011 }
2012
2013 DISAS_INSN(sats)
2014 {
2015 TCGv reg;
2016 reg = DREG(insn, 0);
2017 gen_flush_flags(s);
2018 gen_helper_sats(reg, reg, QREG_CC_V);
2019 gen_logic_cc(s, reg, OS_LONG);
2020 }
2021
2022 static void gen_push(DisasContext *s, TCGv val)
2023 {
2024 TCGv tmp;
2025
2026 tmp = tcg_temp_new();
2027 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2028 gen_store(s, OS_LONG, tmp, val, IS_USER(s));
2029 tcg_gen_mov_i32(QREG_SP, tmp);
2030 tcg_temp_free(tmp);
2031 }
2032
2033 static TCGv mreg(int reg)
2034 {
2035 if (reg < 8) {
2036 /* Dx */
2037 return cpu_dregs[reg];
2038 }
2039 /* Ax */
2040 return cpu_aregs[reg & 7];
2041 }
2042
2043 DISAS_INSN(movem)
2044 {
2045 TCGv addr, incr, tmp, r[16];
2046 int is_load = (insn & 0x0400) != 0;
2047 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
2048 uint16_t mask = read_im16(env, s);
2049 int mode = extract32(insn, 3, 3);
2050 int reg0 = REG(insn, 0);
2051 int i;
2052
2053 tmp = cpu_aregs[reg0];
2054
2055 switch (mode) {
2056 case 0: /* data register direct */
2057 case 1: /* addr register direct */
2058 do_addr_fault:
2059 gen_addr_fault(s);
2060 return;
2061
2062 case 2: /* indirect */
2063 break;
2064
2065 case 3: /* indirect post-increment */
2066 if (!is_load) {
2067 /* post-increment is not allowed */
2068 goto do_addr_fault;
2069 }
2070 break;
2071
2072 case 4: /* indirect pre-decrement */
2073 if (is_load) {
2074 /* pre-decrement is not allowed */
2075 goto do_addr_fault;
2076 }
2077 /*
2078 * We want a bare copy of the address reg, without any pre-decrement
2079 * adjustment, as gen_lea would provide.
2080 */
2081 break;
2082
2083 default:
2084 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2085 if (IS_NULL_QREG(tmp)) {
2086 goto do_addr_fault;
2087 }
2088 break;
2089 }
2090
2091 addr = tcg_temp_new();
2092 tcg_gen_mov_i32(addr, tmp);
2093 incr = tcg_const_i32(opsize_bytes(opsize));
2094
2095 if (is_load) {
2096 /* memory to register */
2097 for (i = 0; i < 16; i++) {
2098 if (mask & (1 << i)) {
2099 r[i] = gen_load(s, opsize, addr, 1, IS_USER(s));
2100 tcg_gen_add_i32(addr, addr, incr);
2101 }
2102 }
2103 for (i = 0; i < 16; i++) {
2104 if (mask & (1 << i)) {
2105 tcg_gen_mov_i32(mreg(i), r[i]);
2106 tcg_temp_free(r[i]);
2107 }
2108 }
2109 if (mode == 3) {
2110 /* post-increment: movem (An)+,X */
2111 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2112 }
2113 } else {
2114 /* register to memory */
2115 if (mode == 4) {
2116 /* pre-decrement: movem X,-(An) */
2117 for (i = 15; i >= 0; i--) {
2118 if ((mask << i) & 0x8000) {
2119 tcg_gen_sub_i32(addr, addr, incr);
2120 if (reg0 + 8 == i &&
2121 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2122 /*
2123 * M68020+: if the addressing register is the
2124 * register moved to memory, the value written
2125 * is the initial value decremented by the size of
2126 * the operation, regardless of how many actual
2127 * stores have been performed until this point.
2128 * M68000/M68010: the value is the initial value.
2129 */
2130 tmp = tcg_temp_new();
2131 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2132 gen_store(s, opsize, addr, tmp, IS_USER(s));
2133 tcg_temp_free(tmp);
2134 } else {
2135 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2136 }
2137 }
2138 }
2139 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2140 } else {
2141 for (i = 0; i < 16; i++) {
2142 if (mask & (1 << i)) {
2143 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2144 tcg_gen_add_i32(addr, addr, incr);
2145 }
2146 }
2147 }
2148 }
2149
2150 tcg_temp_free(incr);
2151 tcg_temp_free(addr);
2152 }
2153
2154 DISAS_INSN(movep)
2155 {
2156 uint8_t i;
2157 int16_t displ;
2158 TCGv reg;
2159 TCGv addr;
2160 TCGv abuf;
2161 TCGv dbuf;
2162
2163 displ = read_im16(env, s);
2164
2165 addr = AREG(insn, 0);
2166 reg = DREG(insn, 9);
2167
2168 abuf = tcg_temp_new();
2169 tcg_gen_addi_i32(abuf, addr, displ);
2170 dbuf = tcg_temp_new();
2171
2172 if (insn & 0x40) {
2173 i = 4;
2174 } else {
2175 i = 2;
2176 }
2177
2178 if (insn & 0x80) {
2179 for ( ; i > 0 ; i--) {
2180 tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
2181 tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
2182 if (i > 1) {
2183 tcg_gen_addi_i32(abuf, abuf, 2);
2184 }
2185 }
2186 } else {
2187 for ( ; i > 0 ; i--) {
2188 tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
2189 tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
2190 if (i > 1) {
2191 tcg_gen_addi_i32(abuf, abuf, 2);
2192 }
2193 }
2194 }
2195 tcg_temp_free(abuf);
2196 tcg_temp_free(dbuf);
2197 }
2198
2199 DISAS_INSN(bitop_im)
2200 {
2201 int opsize;
2202 int op;
2203 TCGv src1;
2204 uint32_t mask;
2205 int bitnum;
2206 TCGv tmp;
2207 TCGv addr;
2208
2209 if ((insn & 0x38) != 0)
2210 opsize = OS_BYTE;
2211 else
2212 opsize = OS_LONG;
2213 op = (insn >> 6) & 3;
2214
2215 bitnum = read_im16(env, s);
2216 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2217 if (bitnum & 0xfe00) {
2218 disas_undef(env, s, insn);
2219 return;
2220 }
2221 } else {
2222 if (bitnum & 0xff00) {
2223 disas_undef(env, s, insn);
2224 return;
2225 }
2226 }
2227
2228 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2229
2230 gen_flush_flags(s);
2231 if (opsize == OS_BYTE)
2232 bitnum &= 7;
2233 else
2234 bitnum &= 31;
2235 mask = 1 << bitnum;
2236
2237 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2238
2239 if (op) {
2240 tmp = tcg_temp_new();
2241 switch (op) {
2242 case 1: /* bchg */
2243 tcg_gen_xori_i32(tmp, src1, mask);
2244 break;
2245 case 2: /* bclr */
2246 tcg_gen_andi_i32(tmp, src1, ~mask);
2247 break;
2248 case 3: /* bset */
2249 tcg_gen_ori_i32(tmp, src1, mask);
2250 break;
2251 default: /* btst */
2252 break;
2253 }
2254 DEST_EA(env, insn, opsize, tmp, &addr);
2255 tcg_temp_free(tmp);
2256 }
2257 }
2258
2259 static TCGv gen_get_ccr(DisasContext *s)
2260 {
2261 TCGv dest;
2262
2263 update_cc_op(s);
2264 dest = tcg_temp_new();
2265 gen_helper_get_ccr(dest, cpu_env);
2266 return dest;
2267 }
2268
2269 static TCGv gen_get_sr(DisasContext *s)
2270 {
2271 TCGv ccr;
2272 TCGv sr;
2273
2274 ccr = gen_get_ccr(s);
2275 sr = tcg_temp_new();
2276 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2277 tcg_gen_or_i32(sr, sr, ccr);
2278 tcg_temp_free(ccr);
2279 return sr;
2280 }
2281
2282 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2283 {
2284 if (ccr_only) {
2285 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2286 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2287 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2288 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2289 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2290 } else {
2291 TCGv sr = tcg_const_i32(val);
2292 gen_helper_set_sr(cpu_env, sr);
2293 tcg_temp_free(sr);
2294 }
2295 set_cc_op(s, CC_OP_FLAGS);
2296 }
2297
2298 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
2299 {
2300 if (ccr_only) {
2301 gen_helper_set_ccr(cpu_env, val);
2302 } else {
2303 gen_helper_set_sr(cpu_env, val);
2304 }
2305 set_cc_op(s, CC_OP_FLAGS);
2306 }
2307
2308 static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2309 bool ccr_only)
2310 {
2311 if ((insn & 0x3f) == 0x3c) {
2312 uint16_t val;
2313 val = read_im16(env, s);
2314 gen_set_sr_im(s, val, ccr_only);
2315 } else {
2316 TCGv src;
2317 SRC_EA(env, src, OS_WORD, 0, NULL);
2318 gen_set_sr(s, src, ccr_only);
2319 }
2320 }
2321
2322 DISAS_INSN(arith_im)
2323 {
2324 int op;
2325 TCGv im;
2326 TCGv src1;
2327 TCGv dest;
2328 TCGv addr;
2329 int opsize;
2330 bool with_SR = ((insn & 0x3f) == 0x3c);
2331
2332 op = (insn >> 9) & 7;
2333 opsize = insn_opsize(insn);
2334 switch (opsize) {
2335 case OS_BYTE:
2336 im = tcg_const_i32((int8_t)read_im8(env, s));
2337 break;
2338 case OS_WORD:
2339 im = tcg_const_i32((int16_t)read_im16(env, s));
2340 break;
2341 case OS_LONG:
2342 im = tcg_const_i32(read_im32(env, s));
2343 break;
2344 default:
2345 g_assert_not_reached();
2346 }
2347
2348 if (with_SR) {
2349 /* SR/CCR can only be used with andi/eori/ori */
2350 if (op == 2 || op == 3 || op == 6) {
2351 disas_undef(env, s, insn);
2352 return;
2353 }
2354 switch (opsize) {
2355 case OS_BYTE:
2356 src1 = gen_get_ccr(s);
2357 break;
2358 case OS_WORD:
2359 if (IS_USER(s)) {
2360 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2361 return;
2362 }
2363 src1 = gen_get_sr(s);
2364 break;
2365 default:
2366 /* OS_LONG; others already g_assert_not_reached. */
2367 disas_undef(env, s, insn);
2368 return;
2369 }
2370 } else {
2371 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2372 }
2373 dest = tcg_temp_new();
2374 switch (op) {
2375 case 0: /* ori */
2376 tcg_gen_or_i32(dest, src1, im);
2377 if (with_SR) {
2378 gen_set_sr(s, dest, opsize == OS_BYTE);
2379 } else {
2380 DEST_EA(env, insn, opsize, dest, &addr);
2381 gen_logic_cc(s, dest, opsize);
2382 }
2383 break;
2384 case 1: /* andi */
2385 tcg_gen_and_i32(dest, src1, im);
2386 if (with_SR) {
2387 gen_set_sr(s, dest, opsize == OS_BYTE);
2388 } else {
2389 DEST_EA(env, insn, opsize, dest, &addr);
2390 gen_logic_cc(s, dest, opsize);
2391 }
2392 break;
2393 case 2: /* subi */
2394 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2395 tcg_gen_sub_i32(dest, src1, im);
2396 gen_update_cc_add(dest, im, opsize);
2397 set_cc_op(s, CC_OP_SUBB + opsize);
2398 DEST_EA(env, insn, opsize, dest, &addr);
2399 break;
2400 case 3: /* addi */
2401 tcg_gen_add_i32(dest, src1, im);
2402 gen_update_cc_add(dest, im, opsize);
2403 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2404 set_cc_op(s, CC_OP_ADDB + opsize);
2405 DEST_EA(env, insn, opsize, dest, &addr);
2406 break;
2407 case 5: /* eori */
2408 tcg_gen_xor_i32(dest, src1, im);
2409 if (with_SR) {
2410 gen_set_sr(s, dest, opsize == OS_BYTE);
2411 } else {
2412 DEST_EA(env, insn, opsize, dest, &addr);
2413 gen_logic_cc(s, dest, opsize);
2414 }
2415 break;
2416 case 6: /* cmpi */
2417 gen_update_cc_cmp(s, src1, im, opsize);
2418 break;
2419 default:
2420 abort();
2421 }
2422 tcg_temp_free(im);
2423 tcg_temp_free(dest);
2424 }
2425
2426 DISAS_INSN(cas)
2427 {
2428 int opsize;
2429 TCGv addr;
2430 uint16_t ext;
2431 TCGv load;
2432 TCGv cmp;
2433 MemOp opc;
2434
2435 switch ((insn >> 9) & 3) {
2436 case 1:
2437 opsize = OS_BYTE;
2438 opc = MO_SB;
2439 break;
2440 case 2:
2441 opsize = OS_WORD;
2442 opc = MO_TESW;
2443 break;
2444 case 3:
2445 opsize = OS_LONG;
2446 opc = MO_TESL;
2447 break;
2448 default:
2449 g_assert_not_reached();
2450 }
2451
2452 ext = read_im16(env, s);
2453
2454 /* cas Dc,Du,<EA> */
2455
2456 addr = gen_lea(env, s, insn, opsize);
2457 if (IS_NULL_QREG(addr)) {
2458 gen_addr_fault(s);
2459 return;
2460 }
2461
2462 cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2463
2464 /*
2465 * if <EA> == Dc then
2466 * <EA> = Du
2467 * Dc = <EA> (because <EA> == Dc)
2468 * else
2469 * Dc = <EA>
2470 */
2471
2472 load = tcg_temp_new();
2473 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2474 IS_USER(s), opc);
2475 /* update flags before setting cmp to load */
2476 gen_update_cc_cmp(s, load, cmp, opsize);
2477 gen_partset_reg(opsize, DREG(ext, 0), load);
2478
2479 tcg_temp_free(load);
2480
2481 switch (extract32(insn, 3, 3)) {
2482 case 3: /* Indirect postincrement. */
2483 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2484 break;
2485 case 4: /* Indirect predecrememnt. */
2486 tcg_gen_mov_i32(AREG(insn, 0), addr);
2487 break;
2488 }
2489 }
2490
2491 DISAS_INSN(cas2w)
2492 {
2493 uint16_t ext1, ext2;
2494 TCGv addr1, addr2;
2495 TCGv regs;
2496
2497 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2498
2499 ext1 = read_im16(env, s);
2500
2501 if (ext1 & 0x8000) {
2502 /* Address Register */
2503 addr1 = AREG(ext1, 12);
2504 } else {
2505 /* Data Register */
2506 addr1 = DREG(ext1, 12);
2507 }
2508
2509 ext2 = read_im16(env, s);
2510 if (ext2 & 0x8000) {
2511 /* Address Register */
2512 addr2 = AREG(ext2, 12);
2513 } else {
2514 /* Data Register */
2515 addr2 = DREG(ext2, 12);
2516 }
2517
2518 /*
2519 * if (R1) == Dc1 && (R2) == Dc2 then
2520 * (R1) = Du1
2521 * (R2) = Du2
2522 * else
2523 * Dc1 = (R1)
2524 * Dc2 = (R2)
2525 */
2526
2527 regs = tcg_const_i32(REG(ext2, 6) |
2528 (REG(ext1, 6) << 3) |
2529 (REG(ext2, 0) << 6) |
2530 (REG(ext1, 0) << 9));
2531 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2532 gen_helper_exit_atomic(cpu_env);
2533 } else {
2534 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2535 }
2536 tcg_temp_free(regs);
2537
2538 /* Note that cas2w also assigned to env->cc_op. */
2539 s->cc_op = CC_OP_CMPW;
2540 s->cc_op_synced = 1;
2541 }
2542
2543 DISAS_INSN(cas2l)
2544 {
2545 uint16_t ext1, ext2;
2546 TCGv addr1, addr2, regs;
2547
2548 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2549
2550 ext1 = read_im16(env, s);
2551
2552 if (ext1 & 0x8000) {
2553 /* Address Register */
2554 addr1 = AREG(ext1, 12);
2555 } else {
2556 /* Data Register */
2557 addr1 = DREG(ext1, 12);
2558 }
2559
2560 ext2 = read_im16(env, s);
2561 if (ext2 & 0x8000) {
2562 /* Address Register */
2563 addr2 = AREG(ext2, 12);
2564 } else {
2565 /* Data Register */
2566 addr2 = DREG(ext2, 12);
2567 }
2568
2569 /*
2570 * if (R1) == Dc1 && (R2) == Dc2 then
2571 * (R1) = Du1
2572 * (R2) = Du2
2573 * else
2574 * Dc1 = (R1)
2575 * Dc2 = (R2)
2576 */
2577
2578 regs = tcg_const_i32(REG(ext2, 6) |
2579 (REG(ext1, 6) << 3) |
2580 (REG(ext2, 0) << 6) |
2581 (REG(ext1, 0) << 9));
2582 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2583 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2584 } else {
2585 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2586 }
2587 tcg_temp_free(regs);
2588
2589 /* Note that cas2l also assigned to env->cc_op. */
2590 s->cc_op = CC_OP_CMPL;
2591 s->cc_op_synced = 1;
2592 }
2593
2594 DISAS_INSN(byterev)
2595 {
2596 TCGv reg;
2597
2598 reg = DREG(insn, 0);
2599 tcg_gen_bswap32_i32(reg, reg);
2600 }
2601
2602 DISAS_INSN(move)
2603 {
2604 TCGv src;
2605 TCGv dest;
2606 int op;
2607 int opsize;
2608
2609 switch (insn >> 12) {
2610 case 1: /* move.b */
2611 opsize = OS_BYTE;
2612 break;
2613 case 2: /* move.l */
2614 opsize = OS_LONG;
2615 break;
2616 case 3: /* move.w */
2617 opsize = OS_WORD;
2618 break;
2619 default:
2620 abort();
2621 }
2622 SRC_EA(env, src, opsize, 1, NULL);
2623 op = (insn >> 6) & 7;
2624 if (op == 1) {
2625 /* movea */
2626 /* The value will already have been sign extended. */
2627 dest = AREG(insn, 9);
2628 tcg_gen_mov_i32(dest, src);
2629 } else {
2630 /* normal move */
2631 uint16_t dest_ea;
2632 dest_ea = ((insn >> 9) & 7) | (op << 3);
2633 DEST_EA(env, dest_ea, opsize, src, NULL);
2634 /* This will be correct because loads sign extend. */
2635 gen_logic_cc(s, src, opsize);
2636 }
2637 }
2638
2639 DISAS_INSN(negx)
2640 {
2641 TCGv z;
2642 TCGv src;
2643 TCGv addr;
2644 int opsize;
2645
2646 opsize = insn_opsize(insn);
2647 SRC_EA(env, src, opsize, 1, &addr);
2648
2649 gen_flush_flags(s); /* compute old Z */
2650
2651 /*
2652 * Perform subtract with borrow.
2653 * (X, N) = -(src + X);
2654 */
2655
2656 z = tcg_const_i32(0);
2657 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2658 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2659 tcg_temp_free(z);
2660 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2661
2662 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2663
2664 /*
2665 * Compute signed-overflow for negation. The normal formula for
2666 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2667 * this simplifies to res & src.
2668 */
2669
2670 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2671
2672 /* Copy the rest of the results into place. */
2673 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2674 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2675
2676 set_cc_op(s, CC_OP_FLAGS);
2677
2678 /* result is in QREG_CC_N */
2679
2680 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2681 }
2682
2683 DISAS_INSN(lea)
2684 {
2685 TCGv reg;
2686 TCGv tmp;
2687
2688 reg = AREG(insn, 9);
2689 tmp = gen_lea(env, s, insn, OS_LONG);
2690 if (IS_NULL_QREG(tmp)) {
2691 gen_addr_fault(s);
2692 return;
2693 }
2694 tcg_gen_mov_i32(reg, tmp);
2695 }
2696
2697 DISAS_INSN(clr)
2698 {
2699 int opsize;
2700 TCGv zero;
2701
2702 zero = tcg_const_i32(0);
2703
2704 opsize = insn_opsize(insn);
2705 DEST_EA(env, insn, opsize, zero, NULL);
2706 gen_logic_cc(s, zero, opsize);
2707 tcg_temp_free(zero);
2708 }
2709
2710 DISAS_INSN(move_from_ccr)
2711 {
2712 TCGv ccr;
2713
2714 ccr = gen_get_ccr(s);
2715 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2716 }
2717
2718 DISAS_INSN(neg)
2719 {
2720 TCGv src1;
2721 TCGv dest;
2722 TCGv addr;
2723 int opsize;
2724
2725 opsize = insn_opsize(insn);
2726 SRC_EA(env, src1, opsize, 1, &addr);
2727 dest = tcg_temp_new();
2728 tcg_gen_neg_i32(dest, src1);
2729 set_cc_op(s, CC_OP_SUBB + opsize);
2730 gen_update_cc_add(dest, src1, opsize);
2731 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2732 DEST_EA(env, insn, opsize, dest, &addr);
2733 tcg_temp_free(dest);
2734 }
2735
2736 DISAS_INSN(move_to_ccr)
2737 {
2738 gen_move_to_sr(env, s, insn, true);
2739 }
2740
2741 DISAS_INSN(not)
2742 {
2743 TCGv src1;
2744 TCGv dest;
2745 TCGv addr;
2746 int opsize;
2747
2748 opsize = insn_opsize(insn);
2749 SRC_EA(env, src1, opsize, 1, &addr);
2750 dest = tcg_temp_new();
2751 tcg_gen_not_i32(dest, src1);
2752 DEST_EA(env, insn, opsize, dest, &addr);
2753 gen_logic_cc(s, dest, opsize);
2754 }
2755
2756 DISAS_INSN(swap)
2757 {
2758 TCGv src1;
2759 TCGv src2;
2760 TCGv reg;
2761
2762 src1 = tcg_temp_new();
2763 src2 = tcg_temp_new();
2764 reg = DREG(insn, 0);
2765 tcg_gen_shli_i32(src1, reg, 16);
2766 tcg_gen_shri_i32(src2, reg, 16);
2767 tcg_gen_or_i32(reg, src1, src2);
2768 tcg_temp_free(src2);
2769 tcg_temp_free(src1);
2770 gen_logic_cc(s, reg, OS_LONG);
2771 }
2772
2773 DISAS_INSN(bkpt)
2774 {
2775 gen_exception(s, s->base.pc_next, EXCP_DEBUG);
2776 }
2777
2778 DISAS_INSN(pea)
2779 {
2780 TCGv tmp;
2781
2782 tmp = gen_lea(env, s, insn, OS_LONG);
2783 if (IS_NULL_QREG(tmp)) {
2784 gen_addr_fault(s);
2785 return;
2786 }
2787 gen_push(s, tmp);
2788 }
2789
2790 DISAS_INSN(ext)
2791 {
2792 int op;
2793 TCGv reg;
2794 TCGv tmp;
2795
2796 reg = DREG(insn, 0);
2797 op = (insn >> 6) & 7;
2798 tmp = tcg_temp_new();
2799 if (op == 3)
2800 tcg_gen_ext16s_i32(tmp, reg);
2801 else
2802 tcg_gen_ext8s_i32(tmp, reg);
2803 if (op == 2)
2804 gen_partset_reg(OS_WORD, reg, tmp);
2805 else
2806 tcg_gen_mov_i32(reg, tmp);
2807 gen_logic_cc(s, tmp, OS_LONG);
2808 tcg_temp_free(tmp);
2809 }
2810
2811 DISAS_INSN(tst)
2812 {
2813 int opsize;
2814 TCGv tmp;
2815
2816 opsize = insn_opsize(insn);
2817 SRC_EA(env, tmp, opsize, 1, NULL);
2818 gen_logic_cc(s, tmp, opsize);
2819 }
2820
2821 DISAS_INSN(pulse)
2822 {
2823 /* Implemented as a NOP. */
2824 }
2825
2826 DISAS_INSN(illegal)
2827 {
2828 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2829 }
2830
2831 /* ??? This should be atomic. */
2832 DISAS_INSN(tas)
2833 {
2834 TCGv dest;
2835 TCGv src1;
2836 TCGv addr;
2837
2838 dest = tcg_temp_new();
2839 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2840 gen_logic_cc(s, src1, OS_BYTE);
2841 tcg_gen_ori_i32(dest, src1, 0x80);
2842 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2843 tcg_temp_free(dest);
2844 }
2845
2846 DISAS_INSN(mull)
2847 {
2848 uint16_t ext;
2849 TCGv src1;
2850 int sign;
2851
2852 ext = read_im16(env, s);
2853
2854 sign = ext & 0x800;
2855
2856 if (ext & 0x400) {
2857 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2858 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2859 return;
2860 }
2861
2862 SRC_EA(env, src1, OS_LONG, 0, NULL);
2863
2864 if (sign) {
2865 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2866 } else {
2867 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2868 }
2869 /* if Dl == Dh, 68040 returns low word */
2870 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2871 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2872 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2873
2874 tcg_gen_movi_i32(QREG_CC_V, 0);
2875 tcg_gen_movi_i32(QREG_CC_C, 0);
2876
2877 set_cc_op(s, CC_OP_FLAGS);
2878 return;
2879 }
2880 SRC_EA(env, src1, OS_LONG, 0, NULL);
2881 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2882 tcg_gen_movi_i32(QREG_CC_C, 0);
2883 if (sign) {
2884 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2885 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2886 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2887 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2888 } else {
2889 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2890 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2891 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2892 }
2893 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2894 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2895
2896 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2897
2898 set_cc_op(s, CC_OP_FLAGS);
2899 } else {
2900 /*
2901 * The upper 32 bits of the product are discarded, so
2902 * muls.l and mulu.l are functionally equivalent.
2903 */
2904 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2905 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2906 }
2907 }
2908
2909 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2910 {
2911 TCGv reg;
2912 TCGv tmp;
2913
2914 reg = AREG(insn, 0);
2915 tmp = tcg_temp_new();
2916 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2917 gen_store(s, OS_LONG, tmp, reg, IS_USER(s));
2918 if ((insn & 7) != 7) {
2919 tcg_gen_mov_i32(reg, tmp);
2920 }
2921 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2922 tcg_temp_free(tmp);
2923 }
2924
2925 DISAS_INSN(link)
2926 {
2927 int16_t offset;
2928
2929 offset = read_im16(env, s);
2930 gen_link(s, insn, offset);
2931 }
2932
2933 DISAS_INSN(linkl)
2934 {
2935 int32_t offset;
2936
2937 offset = read_im32(env, s);
2938 gen_link(s, insn, offset);
2939 }
2940
2941 DISAS_INSN(unlk)
2942 {
2943 TCGv src;
2944 TCGv reg;
2945 TCGv tmp;
2946
2947 src = tcg_temp_new();
2948 reg = AREG(insn, 0);
2949 tcg_gen_mov_i32(src, reg);
2950 tmp = gen_load(s, OS_LONG, src, 0, IS_USER(s));
2951 tcg_gen_mov_i32(reg, tmp);
2952 tcg_gen_addi_i32(QREG_SP, src, 4);
2953 tcg_temp_free(src);
2954 tcg_temp_free(tmp);
2955 }
2956
2957 #if defined(CONFIG_SOFTMMU)
2958 DISAS_INSN(reset)
2959 {
2960 if (IS_USER(s)) {
2961 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2962 return;
2963 }
2964
2965 gen_helper_reset(cpu_env);
2966 }
2967 #endif
2968
2969 DISAS_INSN(nop)
2970 {
2971 }
2972
2973 DISAS_INSN(rtd)
2974 {
2975 TCGv tmp;
2976 int16_t offset = read_im16(env, s);
2977
2978 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2979 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2980 gen_jmp(s, tmp);
2981 }
2982
2983 DISAS_INSN(rtr)
2984 {
2985 TCGv tmp;
2986 TCGv ccr;
2987 TCGv sp;
2988
2989 sp = tcg_temp_new();
2990 ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
2991 tcg_gen_addi_i32(sp, QREG_SP, 2);
2992 tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
2993 tcg_gen_addi_i32(QREG_SP, sp, 4);
2994 tcg_temp_free(sp);
2995
2996 gen_set_sr(s, ccr, true);
2997 tcg_temp_free(ccr);
2998
2999 gen_jmp(s, tmp);
3000 }
3001
3002 DISAS_INSN(rts)
3003 {
3004 TCGv tmp;
3005
3006 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
3007 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
3008 gen_jmp(s, tmp);
3009 }
3010
3011 DISAS_INSN(jump)
3012 {
3013 TCGv tmp;
3014
3015 /*
3016 * Load the target address first to ensure correct exception
3017 * behavior.
3018 */
3019 tmp = gen_lea(env, s, insn, OS_LONG);
3020 if (IS_NULL_QREG(tmp)) {
3021 gen_addr_fault(s);
3022 return;
3023 }
3024 if ((insn & 0x40) == 0) {
3025 /* jsr */
3026 gen_push(s, tcg_const_i32(s->pc));
3027 }
3028 gen_jmp(s, tmp);
3029 }
3030
3031 DISAS_INSN(addsubq)
3032 {
3033 TCGv src;
3034 TCGv dest;
3035 TCGv val;
3036 int imm;
3037 TCGv addr;
3038 int opsize;
3039
3040 if ((insn & 070) == 010) {
3041 /* Operation on address register is always long. */
3042 opsize = OS_LONG;
3043 } else {
3044 opsize = insn_opsize(insn);
3045 }
3046 SRC_EA(env, src, opsize, 1, &addr);
3047 imm = (insn >> 9) & 7;
3048 if (imm == 0) {
3049 imm = 8;
3050 }
3051 val = tcg_const_i32(imm);
3052 dest = tcg_temp_new();
3053 tcg_gen_mov_i32(dest, src);
3054 if ((insn & 0x38) == 0x08) {
3055 /*
3056 * Don't update condition codes if the destination is an
3057 * address register.
3058 */
3059 if (insn & 0x0100) {
3060 tcg_gen_sub_i32(dest, dest, val);
3061 } else {
3062 tcg_gen_add_i32(dest, dest, val);
3063 }
3064 } else {
3065 if (insn & 0x0100) {
3066 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3067 tcg_gen_sub_i32(dest, dest, val);
3068 set_cc_op(s, CC_OP_SUBB + opsize);
3069 } else {
3070 tcg_gen_add_i32(dest, dest, val);
3071 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3072 set_cc_op(s, CC_OP_ADDB + opsize);
3073 }
3074 gen_update_cc_add(dest, val, opsize);
3075 }
3076 tcg_temp_free(val);
3077 DEST_EA(env, insn, opsize, dest, &addr);
3078 tcg_temp_free(dest);
3079 }
3080
3081 DISAS_INSN(tpf)
3082 {
3083 switch (insn & 7) {
3084 case 2: /* One extension word. */
3085 s->pc += 2;
3086 break;
3087 case 3: /* Two extension words. */
3088 s->pc += 4;
3089 break;
3090 case 4: /* No extension words. */
3091 break;
3092 default:
3093 disas_undef(env, s, insn);
3094 }
3095 }
3096
3097 DISAS_INSN(branch)
3098 {
3099 int32_t offset;
3100 uint32_t base;
3101 int op;
3102
3103 base = s->pc;
3104 op = (insn >> 8) & 0xf;
3105 offset = (int8_t)insn;
3106 if (offset == 0) {
3107 offset = (int16_t)read_im16(env, s);
3108 } else if (offset == -1) {
3109 offset = read_im32(env, s);
3110 }
3111 if (op == 1) {
3112 /* bsr */
3113 gen_push(s, tcg_const_i32(s->pc));
3114 }
3115 if (op > 1) {
3116 /* Bcc */
3117 TCGLabel *l1 = gen_new_label();
3118 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
3119 gen_jmp_tb(s, 1, base + offset);
3120 gen_set_label(l1);
3121 gen_jmp_tb(s, 0, s->pc);
3122 } else {
3123 /* Unconditional branch. */
3124 update_cc_op(s);
3125 gen_jmp_tb(s, 0, base + offset);
3126 }
3127 }
3128
3129 DISAS_INSN(moveq)
3130 {
3131 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
3132 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
3133 }
3134
3135 DISAS_INSN(mvzs)
3136 {
3137 int opsize;
3138 TCGv src;
3139 TCGv reg;
3140
3141 if (insn & 0x40)
3142 opsize = OS_WORD;
3143 else
3144 opsize = OS_BYTE;
3145 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
3146 reg = DREG(insn, 9);
3147 tcg_gen_mov_i32(reg, src);
3148 gen_logic_cc(s, src, opsize);
3149 }
3150
3151 DISAS_INSN(or)
3152 {
3153 TCGv reg;
3154 TCGv dest;
3155 TCGv src;
3156 TCGv addr;
3157 int opsize;
3158
3159 opsize = insn_opsize(insn);
3160 reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3161 dest = tcg_temp_new();
3162 if (insn & 0x100) {
3163 SRC_EA(env, src, opsize, 0, &addr);
3164 tcg_gen_or_i32(dest, src, reg);
3165 DEST_EA(env, insn, opsize, dest, &addr);
3166 } else {
3167 SRC_EA(env, src, opsize, 0, NULL);
3168 tcg_gen_or_i32(dest, src, reg);
3169 gen_partset_reg(opsize, DREG(insn, 9), dest);
3170 }
3171 gen_logic_cc(s, dest, opsize);
3172 tcg_temp_free(dest);
3173 }
3174
3175 DISAS_INSN(suba)
3176 {
3177 TCGv src;
3178 TCGv reg;
3179
3180 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3181 reg = AREG(insn, 9);
3182 tcg_gen_sub_i32(reg, reg, src);
3183 }
3184
3185 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3186 {
3187 TCGv tmp;
3188
3189 gen_flush_flags(s); /* compute old Z */
3190
3191 /*
3192 * Perform subtract with borrow.
3193 * (X, N) = dest - (src + X);
3194 */
3195
3196 tmp = tcg_const_i32(0);
3197 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
3198 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
3199 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3200 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
3201
3202 /* Compute signed-overflow for subtract. */
3203
3204 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
3205 tcg_gen_xor_i32(tmp, dest, src);
3206 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
3207 tcg_temp_free(tmp);
3208
3209 /* Copy the rest of the results into place. */
3210 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3211 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3212
3213 set_cc_op(s, CC_OP_FLAGS);
3214
3215 /* result is in QREG_CC_N */
3216 }
3217
3218 DISAS_INSN(subx_reg)
3219 {
3220 TCGv dest;
3221 TCGv src;
3222 int opsize;
3223
3224 opsize = insn_opsize(insn);
3225
3226 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3227 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3228
3229 gen_subx(s, src, dest, opsize);
3230
3231 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3232 }
3233
3234 DISAS_INSN(subx_mem)
3235 {
3236 TCGv src;
3237 TCGv addr_src;
3238 TCGv dest;
3239 TCGv addr_dest;
3240 int opsize;
3241
3242 opsize = insn_opsize(insn);
3243
3244 addr_src = AREG(insn, 0);
3245 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3246 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3247
3248 addr_dest = AREG(insn, 9);
3249 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3250 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3251
3252 gen_subx(s, src, dest, opsize);
3253
3254 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3255
3256 tcg_temp_free(dest);
3257 tcg_temp_free(src);
3258 }
3259
3260 DISAS_INSN(mov3q)
3261 {
3262 TCGv src;
3263 int val;
3264
3265 val = (insn >> 9) & 7;
3266 if (val == 0)
3267 val = -1;
3268 src = tcg_const_i32(val);
3269 gen_logic_cc(s, src, OS_LONG);
3270 DEST_EA(env, insn, OS_LONG, src, NULL);
3271 tcg_temp_free(src);
3272 }
3273
3274 DISAS_INSN(cmp)
3275 {
3276 TCGv src;
3277 TCGv reg;
3278 int opsize;
3279
3280 opsize = insn_opsize(insn);
3281 SRC_EA(env, src, opsize, 1, NULL);
3282 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3283 gen_update_cc_cmp(s, reg, src, opsize);
3284 }
3285
3286 DISAS_INSN(cmpa)
3287 {
3288 int opsize;
3289 TCGv src;
3290 TCGv reg;
3291
3292 if (insn & 0x100) {
3293 opsize = OS_LONG;
3294 } else {
3295 opsize = OS_WORD;
3296 }
3297 SRC_EA(env, src, opsize, 1, NULL);
3298 reg = AREG(insn, 9);
3299 gen_update_cc_cmp(s, reg, src, OS_LONG);
3300 }
3301
3302 DISAS_INSN(cmpm)
3303 {
3304 int opsize = insn_opsize(insn);
3305 TCGv src, dst;
3306
3307 /* Post-increment load (mode 3) from Ay. */
3308 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3309 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3310 /* Post-increment load (mode 3) from Ax. */
3311 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3312 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3313
3314 gen_update_cc_cmp(s, dst, src, opsize);
3315 }
3316
3317 DISAS_INSN(eor)
3318 {
3319 TCGv src;
3320 TCGv dest;
3321 TCGv addr;
3322 int opsize;
3323
3324 opsize = insn_opsize(insn);
3325
3326 SRC_EA(env, src, opsize, 0, &addr);
3327 dest = tcg_temp_new();
3328 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3329 gen_logic_cc(s, dest, opsize);
3330 DEST_EA(env, insn, opsize, dest, &addr);
3331 tcg_temp_free(dest);
3332 }
3333
3334 static void do_exg(TCGv reg1, TCGv reg2)
3335 {
3336 TCGv temp = tcg_temp_new();
3337 tcg_gen_mov_i32(temp, reg1);
3338 tcg_gen_mov_i32(reg1, reg2);
3339 tcg_gen_mov_i32(reg2, temp);
3340 tcg_temp_free(temp);
3341 }
3342
3343 DISAS_INSN(exg_dd)
3344 {
3345 /* exchange Dx and Dy */
3346 do_exg(DREG(insn, 9), DREG(insn, 0));
3347 }
3348
3349 DISAS_INSN(exg_aa)
3350 {
3351 /* exchange Ax and Ay */
3352 do_exg(AREG(insn, 9), AREG(insn, 0));
3353 }
3354
3355 DISAS_INSN(exg_da)
3356 {
3357 /* exchange Dx and Ay */
3358 do_exg(DREG(insn, 9), AREG(insn, 0));
3359 }
3360
3361 DISAS_INSN(and)
3362 {
3363 TCGv src;
3364 TCGv reg;
3365 TCGv dest;
3366 TCGv addr;
3367 int opsize;
3368
3369 dest = tcg_temp_new();
3370
3371 opsize = insn_opsize(insn);
3372 reg = DREG(insn, 9);
3373 if (insn & 0x100) {
3374 SRC_EA(env, src, opsize, 0, &addr);
3375 tcg_gen_and_i32(dest, src, reg);
3376 DEST_EA(env, insn, opsize, dest, &addr);
3377 } else {
3378 SRC_EA(env, src, opsize, 0, NULL);
3379 tcg_gen_and_i32(dest, src, reg);
3380 gen_partset_reg(opsize, reg, dest);
3381 }
3382 gen_logic_cc(s, dest, opsize);
3383 tcg_temp_free(dest);
3384 }
3385
3386 DISAS_INSN(adda)
3387 {
3388 TCGv src;
3389 TCGv reg;
3390
3391 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3392 reg = AREG(insn, 9);
3393 tcg_gen_add_i32(reg, reg, src);
3394 }
3395
3396 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3397 {
3398 TCGv tmp;
3399
3400 gen_flush_flags(s); /* compute old Z */
3401
3402 /*
3403 * Perform addition with carry.
3404 * (X, N) = src + dest + X;
3405 */
3406
3407 tmp = tcg_const_i32(0);
3408 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3409 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3410 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3411
3412 /* Compute signed-overflow for addition. */
3413
3414 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3415 tcg_gen_xor_i32(tmp, dest, src);
3416 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3417 tcg_temp_free(tmp);
3418
3419 /* Copy the rest of the results into place. */
3420 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3421 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3422
3423 set_cc_op(s, CC_OP_FLAGS);
3424
3425 /* result is in QREG_CC_N */
3426 }
3427
3428 DISAS_INSN(addx_reg)
3429 {
3430 TCGv dest;
3431 TCGv src;
3432 int opsize;
3433
3434 opsize = insn_opsize(insn);
3435
3436 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3437 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3438
3439 gen_addx(s, src, dest, opsize);
3440
3441 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3442 }
3443
3444 DISAS_INSN(addx_mem)
3445 {
3446 TCGv src;
3447 TCGv addr_src;
3448 TCGv dest;
3449 TCGv addr_dest;
3450 int opsize;
3451
3452 opsize = insn_opsize(insn);
3453
3454 addr_src = AREG(insn, 0);
3455 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3456 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3457
3458 addr_dest = AREG(insn, 9);
3459 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3460 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3461
3462 gen_addx(s, src, dest, opsize);
3463
3464 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3465
3466 tcg_temp_free(dest);
3467 tcg_temp_free(src);
3468 }
3469
3470 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3471 {
3472 int count = (insn >> 9) & 7;
3473 int logical = insn & 8;
3474 int left = insn & 0x100;
3475 int bits = opsize_bytes(opsize) * 8;
3476 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3477
3478 if (count == 0) {
3479 count = 8;
3480 }
3481
3482 tcg_gen_movi_i32(QREG_CC_V, 0);
3483 if (left) {
3484 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3485 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3486
3487 /*
3488 * Note that ColdFire always clears V (done above),
3489 * while M68000 sets if the most significant bit is changed at
3490 * any time during the shift operation.
3491 */
3492 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3493 /* if shift count >= bits, V is (reg != 0) */
3494 if (count >= bits) {
3495 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3496 } else {
3497 TCGv t0 = tcg_temp_new();
3498 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3499 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3500 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3501 tcg_temp_free(t0);
3502 }
3503 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3504 }
3505 } else {
3506 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3507 if (logical) {
3508 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3509 } else {
3510 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3511 }
3512 }
3513
3514 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3515 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3516 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3517 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3518
3519 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3520 set_cc_op(s, CC_OP_FLAGS);
3521 }
3522
3523 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3524 {
3525 int logical = insn & 8;
3526 int left = insn & 0x100;
3527 int bits = opsize_bytes(opsize) * 8;
3528 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3529 TCGv s32;
3530 TCGv_i64 t64, s64;
3531
3532 t64 = tcg_temp_new_i64();
3533 s64 = tcg_temp_new_i64();
3534 s32 = tcg_temp_new();
3535
3536 /*
3537 * Note that m68k truncates the shift count modulo 64, not 32.
3538 * In addition, a 64-bit shift makes it easy to find "the last
3539 * bit shifted out", for the carry flag.
3540 */
3541 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3542 tcg_gen_extu_i32_i64(s64, s32);
3543 tcg_gen_extu_i32_i64(t64, reg);
3544
3545 /* Optimistically set V=0. Also used as a zero source below. */
3546 tcg_gen_movi_i32(QREG_CC_V, 0);
3547 if (left) {
3548 tcg_gen_shl_i64(t64, t64, s64);
3549
3550 if (opsize == OS_LONG) {
3551 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3552 /* Note that C=0 if shift count is 0, and we get that for free. */
3553 } else {
3554 TCGv zero = tcg_const_i32(0);
3555 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3556 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3557 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3558 s32, zero, zero, QREG_CC_C);
3559 tcg_temp_free(zero);
3560 }
3561 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3562
3563 /* X = C, but only if the shift count was non-zero. */
3564 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3565 QREG_CC_C, QREG_CC_X);
3566
3567 /*
3568 * M68000 sets V if the most significant bit is changed at
3569 * any time during the shift operation. Do this via creating
3570 * an extension of the sign bit, comparing, and discarding
3571 * the bits below the sign bit. I.e.
3572 * int64_t s = (intN_t)reg;
3573 * int64_t t = (int64_t)(intN_t)reg << count;
3574 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3575 */
3576 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3577 TCGv_i64 tt = tcg_const_i64(32);
3578 /* if shift is greater than 32, use 32 */
3579 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3580 tcg_temp_free_i64(tt);
3581 /* Sign extend the input to 64 bits; re-do the shift. */
3582 tcg_gen_ext_i32_i64(t64, reg);
3583 tcg_gen_shl_i64(s64, t64, s64);
3584 /* Clear all bits that are unchanged. */
3585 tcg_gen_xor_i64(t64, t64, s64);
3586 /* Ignore the bits below the sign bit. */
3587 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3588 /* If any bits remain set, we have overflow. */
3589 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3590 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3591 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3592 }
3593 } else {
3594 tcg_gen_shli_i64(t64, t64, 32);
3595 if (logical) {
3596 tcg_gen_shr_i64(t64, t64, s64);
3597 } else {
3598 tcg_gen_sar_i64(t64, t64, s64);
3599 }
3600 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3601
3602 /* Note that C=0 if shift count is 0, and we get that for free. */
3603 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3604
3605 /* X = C, but only if the shift count was non-zero. */
3606 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3607 QREG_CC_C, QREG_CC_X);
3608 }
3609 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3610 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3611
3612 tcg_temp_free(s32);
3613 tcg_temp_free_i64(s64);
3614 tcg_temp_free_i64(t64);
3615
3616 /* Write back the result. */
3617 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3618 set_cc_op(s, CC_OP_FLAGS);
3619 }
3620
3621 DISAS_INSN(shift8_im)
3622 {
3623 shift_im(s, insn, OS_BYTE);
3624 }
3625
3626 DISAS_INSN(shift16_im)
3627 {
3628 shift_im(s, insn, OS_WORD);
3629 }
3630
3631 DISAS_INSN(shift_im)
3632 {
3633 shift_im(s, insn, OS_LONG);
3634 }
3635
3636 DISAS_INSN(shift8_reg)
3637 {
3638 shift_reg(s, insn, OS_BYTE);
3639 }
3640
3641 DISAS_INSN(shift16_reg)
3642 {
3643 shift_reg(s, insn, OS_WORD);
3644 }
3645
3646 DISAS_INSN(shift_reg)
3647 {
3648 shift_reg(s, insn, OS_LONG);
3649 }
3650
3651 DISAS_INSN(shift_mem)
3652 {
3653 int logical = insn & 8;
3654 int left = insn & 0x100;
3655 TCGv src;
3656 TCGv addr;
3657
3658 SRC_EA(env, src, OS_WORD, !logical, &addr);
3659 tcg_gen_movi_i32(QREG_CC_V, 0);
3660 if (left) {
3661 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3662 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3663
3664 /*
3665 * Note that ColdFire always clears V,
3666 * while M68000 sets if the most significant bit is changed at
3667 * any time during the shift operation
3668 */
3669 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3670 src = gen_extend(s, src, OS_WORD, 1);
3671 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3672 }
3673 } else {
3674 tcg_gen_mov_i32(QREG_CC_C, src);
3675 if (logical) {
3676 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3677 } else {
3678 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3679 }
3680 }
3681
3682 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3683 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3684 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3685 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3686
3687 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3688 set_cc_op(s, CC_OP_FLAGS);
3689 }
3690
3691 static void rotate(TCGv reg, TCGv shift, int left, int size)
3692 {
3693 switch (size) {
3694 case 8:
3695 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3696 tcg_gen_ext8u_i32(reg, reg);
3697 tcg_gen_muli_i32(reg, reg, 0x01010101);
3698 goto do_long;
3699 case 16:
3700 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3701 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3702 goto do_long;
3703 do_long:
3704 default:
3705 if (left) {
3706 tcg_gen_rotl_i32(reg, reg, shift);
3707 } else {
3708 tcg_gen_rotr_i32(reg, reg, shift);
3709 }
3710 }
3711
3712 /* compute flags */
3713
3714 switch (size) {
3715 case 8:
3716 tcg_gen_ext8s_i32(reg, reg);
3717 break;
3718 case 16:
3719 tcg_gen_ext16s_i32(reg, reg);
3720 break;
3721 default:
3722 break;
3723 }
3724
3725 /* QREG_CC_X is not affected */
3726
3727 tcg_gen_mov_i32(QREG_CC_N, reg);
3728 tcg_gen_mov_i32(QREG_CC_Z, reg);
3729
3730 if (left) {
3731 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3732 } else {
3733 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3734 }
3735
3736 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3737 }
3738
3739 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3740 {
3741 switch (size) {
3742 case 8:
3743 tcg_gen_ext8s_i32(reg, reg);
3744 break;
3745 case 16:
3746 tcg_gen_ext16s_i32(reg, reg);
3747 break;
3748 default:
3749 break;
3750 }
3751 tcg_gen_mov_i32(QREG_CC_N, reg);
3752 tcg_gen_mov_i32(QREG_CC_Z, reg);
3753 tcg_gen_mov_i32(QREG_CC_X, X);
3754 tcg_gen_mov_i32(QREG_CC_C, X);
3755 tcg_gen_movi_i32(QREG_CC_V, 0);
3756 }
3757
3758 /* Result of rotate_x() is valid if 0 <= shift <= size */
3759 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3760 {
3761 TCGv X, shl, shr, shx, sz, zero;
3762
3763 sz = tcg_const_i32(size);
3764
3765 shr = tcg_temp_new();
3766 shl = tcg_temp_new();
3767 shx = tcg_temp_new();
3768 if (left) {
3769 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3770 tcg_gen_movi_i32(shr, size + 1);
3771 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3772 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3773 /* shx = shx < 0 ? size : shx; */
3774 zero = tcg_const_i32(0);
3775 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3776 tcg_temp_free(zero);
3777 } else {
3778 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3779 tcg_gen_movi_i32(shl, size + 1);
3780 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3781 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3782 }
3783 tcg_temp_free_i32(sz);
3784
3785 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3786
3787 tcg_gen_shl_i32(shl, reg, shl);
3788 tcg_gen_shr_i32(shr, reg, shr);
3789 tcg_gen_or_i32(reg, shl, shr);
3790 tcg_temp_free(shl);
3791 tcg_temp_free(shr);
3792 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3793 tcg_gen_or_i32(reg, reg, shx);
3794 tcg_temp_free(shx);
3795
3796 /* X = (reg >> size) & 1 */
3797
3798 X = tcg_temp_new();
3799 tcg_gen_extract_i32(X, reg, size, 1);
3800
3801 return X;
3802 }
3803
3804 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3805 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3806 {
3807 TCGv_i64 t0, shift64;
3808 TCGv X, lo, hi, zero;
3809
3810 shift64 = tcg_temp_new_i64();
3811 tcg_gen_extu_i32_i64(shift64, shift);
3812
3813 t0 = tcg_temp_new_i64();
3814
3815 X = tcg_temp_new();
3816 lo = tcg_temp_new();
3817 hi = tcg_temp_new();
3818
3819 if (left) {
3820 /* create [reg:X:..] */
3821
3822 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3823 tcg_gen_concat_i32_i64(t0, lo, reg);
3824
3825 /* rotate */
3826
3827 tcg_gen_rotl_i64(t0, t0, shift64);
3828 tcg_temp_free_i64(shift64);
3829
3830 /* result is [reg:..:reg:X] */
3831
3832 tcg_gen_extr_i64_i32(lo, hi, t0);
3833 tcg_gen_andi_i32(X, lo, 1);
3834
3835 tcg_gen_shri_i32(lo, lo, 1);
3836 } else {
3837 /* create [..:X:reg] */
3838
3839 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3840
3841 tcg_gen_rotr_i64(t0, t0, shift64);
3842 tcg_temp_free_i64(shift64);
3843
3844 /* result is value: [X:reg:..:reg] */
3845
3846 tcg_gen_extr_i64_i32(lo, hi, t0);
3847
3848 /* extract X */
3849
3850 tcg_gen_shri_i32(X, hi, 31);
3851
3852 /* extract result */
3853
3854 tcg_gen_shli_i32(hi, hi, 1);
3855 }
3856 tcg_temp_free_i64(t0);
3857 tcg_gen_or_i32(lo, lo, hi);
3858 tcg_temp_free(hi);
3859
3860 /* if shift == 0, register and X are not affected */
3861
3862 zero = tcg_const_i32(0);
3863 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3864 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3865 tcg_temp_free(zero);
3866 tcg_temp_free(lo);
3867
3868 return X;
3869 }
3870
3871 DISAS_INSN(rotate_im)
3872 {
3873 TCGv shift;
3874 int tmp;
3875 int left = (insn & 0x100);
3876
3877 tmp = (insn >> 9) & 7;
3878 if (tmp == 0) {
3879 tmp = 8;
3880 }
3881
3882 shift = tcg_const_i32(tmp);
3883 if (insn & 8) {
3884 rotate(DREG(insn, 0), shift, left, 32);
3885 } else {
3886 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3887 rotate_x_flags(DREG(insn, 0), X, 32);
3888 tcg_temp_free(X);
3889 }
3890 tcg_temp_free(shift);
3891
3892 set_cc_op(s, CC_OP_FLAGS);
3893 }
3894
3895 DISAS_INSN(rotate8_im)
3896 {
3897 int left = (insn & 0x100);
3898 TCGv reg;
3899 TCGv shift;
3900 int tmp;
3901
3902 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3903
3904 tmp = (insn >> 9) & 7;
3905 if (tmp == 0) {
3906 tmp = 8;
3907 }
3908
3909 shift = tcg_const_i32(tmp);
3910 if (insn & 8) {
3911 rotate(reg, shift, left, 8);
3912 } else {
3913 TCGv X = rotate_x(reg, shift, left, 8);
3914 rotate_x_flags(reg, X, 8);
3915 tcg_temp_free(X);
3916 }
3917 tcg_temp_free(shift);
3918 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3919 set_cc_op(s, CC_OP_FLAGS);
3920 }
3921
3922 DISAS_INSN(rotate16_im)
3923 {
3924 int left = (insn & 0x100);
3925 TCGv reg;
3926 TCGv shift;
3927 int tmp;
3928
3929 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3930 tmp = (insn >> 9) & 7;
3931 if (tmp == 0) {
3932 tmp = 8;
3933 }
3934
3935 shift = tcg_const_i32(tmp);
3936 if (insn & 8) {
3937 rotate(reg, shift, left, 16);
3938 } else {
3939 TCGv X = rotate_x(reg, shift, left, 16);
3940 rotate_x_flags(reg, X, 16);
3941 tcg_temp_free(X);
3942 }
3943 tcg_temp_free(shift);
3944 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3945 set_cc_op(s, CC_OP_FLAGS);
3946 }
3947
3948 DISAS_INSN(rotate_reg)
3949 {
3950 TCGv reg;
3951 TCGv src;
3952 TCGv t0, t1;
3953 int left = (insn & 0x100);
3954
3955 reg = DREG(insn, 0);
3956 src = DREG(insn, 9);
3957 /* shift in [0..63] */
3958 t0 = tcg_temp_new();
3959 tcg_gen_andi_i32(t0, src, 63);
3960 t1 = tcg_temp_new_i32();
3961 if (insn & 8) {
3962 tcg_gen_andi_i32(t1, src, 31);
3963 rotate(reg, t1, left, 32);
3964 /* if shift == 0, clear C */
3965 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3966 t0, QREG_CC_V /* 0 */,
3967 QREG_CC_V /* 0 */, QREG_CC_C);
3968 } else {
3969 TCGv X;
3970 /* modulo 33 */
3971 tcg_gen_movi_i32(t1, 33);
3972 tcg_gen_remu_i32(t1, t0, t1);
3973 X = rotate32_x(DREG(insn, 0), t1, left);
3974 rotate_x_flags(DREG(insn, 0), X, 32);
3975 tcg_temp_free(X);
3976 }
3977 tcg_temp_free(t1);
3978 tcg_temp_free(t0);
3979 set_cc_op(s, CC_OP_FLAGS);
3980 }
3981
3982 DISAS_INSN(rotate8_reg)
3983 {
3984 TCGv reg;
3985 TCGv src;
3986 TCGv t0, t1;
3987 int left = (insn & 0x100);
3988
3989 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3990 src = DREG(insn, 9);
3991 /* shift in [0..63] */
3992 t0 = tcg_temp_new_i32();
3993 tcg_gen_andi_i32(t0, src, 63);
3994 t1 = tcg_temp_new_i32();
3995 if (insn & 8) {
3996 tcg_gen_andi_i32(t1, src, 7);
3997 rotate(reg, t1, left, 8);
3998 /* if shift == 0, clear C */
3999 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4000 t0, QREG_CC_V /* 0 */,
4001 QREG_CC_V /* 0 */, QREG_CC_C);
4002 } else {
4003 TCGv X;
4004 /* modulo 9 */
4005 tcg_gen_movi_i32(t1, 9);
4006 tcg_gen_remu_i32(t1, t0, t1);
4007 X = rotate_x(reg, t1, left, 8);
4008 rotate_x_flags(reg, X, 8);
4009 tcg_temp_free(X);
4010 }
4011 tcg_temp_free(t1);
4012 tcg_temp_free(t0);
4013 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
4014 set_cc_op(s, CC_OP_FLAGS);
4015 }
4016
4017 DISAS_INSN(rotate16_reg)
4018 {
4019 TCGv reg;
4020 TCGv src;
4021 TCGv t0, t1;
4022 int left = (insn & 0x100);
4023
4024 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
4025 src = DREG(insn, 9);
4026 /* shift in [0..63] */
4027 t0 = tcg_temp_new_i32();
4028 tcg_gen_andi_i32(t0, src, 63);
4029 t1 = tcg_temp_new_i32();
4030 if (insn & 8) {
4031 tcg_gen_andi_i32(t1, src, 15);
4032 rotate(reg, t1, left, 16);
4033 /* if shift == 0, clear C */
4034 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4035 t0, QREG_CC_V /* 0 */,
4036 QREG_CC_V /* 0 */, QREG_CC_C);
4037 } else {
4038 TCGv X;
4039 /* modulo 17 */
4040 tcg_gen_movi_i32(t1, 17);
4041 tcg_gen_remu_i32(t1, t0, t1);
4042 X = rotate_x(reg, t1, left, 16);
4043 rotate_x_flags(reg, X, 16);
4044 tcg_temp_free(X);
4045 }
4046 tcg_temp_free(t1);
4047 tcg_temp_free(t0);
4048 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
4049 set_cc_op(s, CC_OP_FLAGS);
4050 }
4051
4052 DISAS_INSN(rotate_mem)
4053 {
4054 TCGv src;
4055 TCGv addr;
4056 TCGv shift;
4057 int left = (insn & 0x100);
4058
4059 SRC_EA(env, src, OS_WORD, 0, &addr);
4060
4061 shift = tcg_const_i32(1);
4062 if (insn & 0x0200) {
4063 rotate(src, shift, left, 16);
4064 } else {
4065 TCGv X = rotate_x(src, shift, left, 16);
4066 rotate_x_flags(src, X, 16);
4067 tcg_temp_free(X);
4068 }
4069 tcg_temp_free(shift);
4070 DEST_EA(env, insn, OS_WORD, src, &addr);
4071 set_cc_op(s, CC_OP_FLAGS);
4072 }
4073
4074 DISAS_INSN(bfext_reg)
4075 {
4076 int ext = read_im16(env, s);
4077 int is_sign = insn & 0x200;
4078 TCGv src = DREG(insn, 0);
4079 TCGv dst = DREG(ext, 12);
4080 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4081 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4082 int pos = 32 - ofs - len; /* little bit-endian */
4083 TCGv tmp = tcg_temp_new();
4084 TCGv shift;
4085
4086 /*
4087 * In general, we're going to rotate the field so that it's at the
4088 * top of the word and then right-shift by the complement of the
4089 * width to extend the field.
4090 */
4091 if (ext & 0x20) {
4092 /* Variable width. */
4093 if (ext & 0x800) {
4094 /* Variable offset. */
4095 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4096 tcg_gen_rotl_i32(tmp, src, tmp);
4097 } else {
4098 tcg_gen_rotli_i32(tmp, src, ofs);
4099 }
4100
4101 shift = tcg_temp_new();
4102 tcg_gen_neg_i32(shift, DREG(ext, 0));
4103 tcg_gen_andi_i32(shift, shift, 31);
4104 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
4105 if (is_sign) {
4106 tcg_gen_mov_i32(dst, QREG_CC_N);
4107 } else {
4108 tcg_gen_shr_i32(dst, tmp, shift);
4109 }
4110 tcg_temp_free(shift);
4111 } else {
4112 /* Immediate width. */
4113 if (ext & 0x800) {
4114 /* Variable offset */
4115 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4116 tcg_gen_rotl_i32(tmp, src, tmp);
4117 src = tmp;
4118 pos = 32 - len;
4119 } else {
4120 /*
4121 * Immediate offset. If the field doesn't wrap around the
4122 * end of the word, rely on (s)extract completely.
4123 */
4124 if (pos < 0) {
4125 tcg_gen_rotli_i32(tmp, src, ofs);
4126 src = tmp;
4127 pos = 32 - len;
4128 }
4129 }
4130
4131 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
4132 if (is_sign) {
4133 tcg_gen_mov_i32(dst, QREG_CC_N);
4134 } else {
4135 tcg_gen_extract_i32(dst, src, pos, len);
4136 }
4137 }
4138
4139 tcg_temp_free(tmp);
4140 set_cc_op(s, CC_OP_LOGIC);
4141 }
4142
4143 DISAS_INSN(bfext_mem)
4144 {
4145 int ext = read_im16(env, s);
4146 int is_sign = insn & 0x200;
4147 TCGv dest = DREG(ext, 12);
4148 TCGv addr, len, ofs;
4149
4150 addr = gen_lea(env, s, insn, OS_UNSIZED);
4151 if (IS_NULL_QREG(addr)) {
4152 gen_addr_fault(s);
4153 return;
4154 }
4155
4156 if (ext & 0x20) {
4157 len = DREG(ext, 0);
4158 } else {
4159 len = tcg_const_i32(extract32(ext, 0, 5));
4160 }
4161 if (ext & 0x800) {
4162 ofs = DREG(ext, 6);
4163 } else {
4164 ofs = tcg_const_i32(extract32(ext, 6, 5));
4165 }
4166
4167 if (is_sign) {
4168 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
4169 tcg_gen_mov_i32(QREG_CC_N, dest);
4170 } else {
4171 TCGv_i64 tmp = tcg_temp_new_i64();
4172 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
4173 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
4174 tcg_temp_free_i64(tmp);
4175 }
4176 set_cc_op(s, CC_OP_LOGIC);
4177
4178 if (!(ext & 0x20)) {
4179 tcg_temp_free(len);
4180 }
4181 if (!(ext & 0x800)) {
4182 tcg_temp_free(ofs);
4183 }
4184 }
4185
4186 DISAS_INSN(bfop_reg)
4187 {
4188 int ext = read_im16(env, s);
4189 TCGv src = DREG(insn, 0);
4190 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4191 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4192 TCGv mask, tofs, tlen;
4193
4194 tofs = NULL;
4195 tlen = NULL;
4196 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
4197 tofs = tcg_temp_new();
4198 tlen = tcg_temp_new();
4199 }
4200
4201 if ((ext & 0x820) == 0) {
4202 /* Immediate width and offset. */
4203 uint32_t maski = 0x7fffffffu >> (len - 1);
4204 if (ofs + len <= 32) {
4205 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
4206 } else {
4207 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4208 }
4209 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
4210 mask = tcg_const_i32(ror32(maski, ofs));
4211 if (tofs) {
4212 tcg_gen_movi_i32(tofs, ofs);
4213 tcg_gen_movi_i32(tlen, len);
4214 }
4215 } else {
4216 TCGv tmp = tcg_temp_new();
4217 if (ext & 0x20) {
4218 /* Variable width */
4219 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
4220 tcg_gen_andi_i32(tmp, tmp, 31);
4221 mask = tcg_const_i32(0x7fffffffu);
4222 tcg_gen_shr_i32(mask, mask, tmp);
4223 if (tlen) {
4224 tcg_gen_addi_i32(tlen, tmp, 1);
4225 }
4226 } else {
4227 /* Immediate width */
4228 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
4229 if (tlen) {
4230 tcg_gen_movi_i32(tlen, len);
4231 }
4232 }
4233 if (ext & 0x800) {
4234 /* Variable offset */
4235 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4236 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
4237 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4238 tcg_gen_rotr_i32(mask, mask, tmp);
4239 if (tofs) {
4240 tcg_gen_mov_i32(tofs, tmp);
4241 }
4242 } else {
4243 /* Immediate offset (and variable width) */
4244 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4245 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4246 tcg_gen_rotri_i32(mask, mask, ofs);
4247 if (tofs) {
4248 tcg_gen_movi_i32(tofs, ofs);
4249 }
4250 }
4251 tcg_temp_free(tmp);
4252 }
4253 set_cc_op(s, CC_OP_LOGIC);
4254
4255 switch (insn & 0x0f00) {
4256 case 0x0a00: /* bfchg */
4257 tcg_gen_eqv_i32(src, src, mask);
4258 break;
4259 case 0x0c00: /* bfclr */
4260 tcg_gen_and_i32(src, src, mask);
4261 break;
4262 case 0x0d00: /* bfffo */
4263 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4264 tcg_temp_free(tlen);
4265 tcg_temp_free(tofs);
4266 break;
4267 case 0x0e00: /* bfset */
4268 tcg_gen_orc_i32(src, src, mask);
4269 break;
4270 case 0x0800: /* bftst */
4271 /* flags already set; no other work to do. */
4272 break;
4273 default:
4274 g_assert_not_reached();
4275 }
4276 tcg_temp_free(mask);
4277 }
4278
4279 DISAS_INSN(bfop_mem)
4280 {
4281 int ext = read_im16(env, s);
4282 TCGv addr, len, ofs;
4283 TCGv_i64 t64;
4284
4285 addr = gen_lea(env, s, insn, OS_UNSIZED);
4286 if (IS_NULL_QREG(addr)) {
4287 gen_addr_fault(s);
4288 return;
4289 }
4290
4291 if (ext & 0x20) {
4292 len = DREG(ext, 0);
4293 } else {
4294 len = tcg_const_i32(extract32(ext, 0, 5));
4295 }
4296 if (ext & 0x800) {
4297 ofs = DREG(ext, 6);
4298 } else {
4299 ofs = tcg_const_i32(extract32(ext, 6, 5));
4300 }
4301
4302 switch (insn & 0x0f00) {
4303 case 0x0a00: /* bfchg */
4304 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4305 break;
4306 case 0x0c00: /* bfclr */
4307 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4308 break;
4309 case 0x0d00: /* bfffo */
4310 t64 = tcg_temp_new_i64();
4311 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4312 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4313 tcg_temp_free_i64(t64);
4314 break;
4315 case 0x0e00: /* bfset */
4316 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4317 break;
4318 case 0x0800: /* bftst */
4319 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4320 break;
4321 default:
4322 g_assert_not_reached();
4323 }
4324 set_cc_op(s, CC_OP_LOGIC);
4325
4326 if (!(ext & 0x20)) {
4327 tcg_temp_free(len);
4328 }
4329 if (!(ext & 0x800)) {
4330 tcg_temp_free(ofs);
4331 }
4332 }
4333
4334 DISAS_INSN(bfins_reg)
4335 {
4336 int ext = read_im16(env, s);
4337 TCGv dst = DREG(insn, 0);
4338 TCGv src = DREG(ext, 12);
4339 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4340 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4341 int pos = 32 - ofs - len; /* little bit-endian */
4342 TCGv tmp;
4343
4344 tmp = tcg_temp_new();
4345
4346 if (ext & 0x20) {
4347 /* Variable width */
4348 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4349 tcg_gen_andi_i32(tmp, tmp, 31);
4350 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4351 } else {
4352 /* Immediate width */
4353 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4354 }
4355 set_cc_op(s, CC_OP_LOGIC);
4356
4357 /* Immediate width and offset */
4358 if ((ext & 0x820) == 0) {
4359 /* Check for suitability for deposit. */
4360 if (pos >= 0) {
4361 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4362 } else {
4363 uint32_t maski = -2U << (len - 1);
4364 uint32_t roti = (ofs + len) & 31;
4365 tcg_gen_andi_i32(tmp, src, ~maski);
4366 tcg_gen_rotri_i32(tmp, tmp, roti);
4367 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4368 tcg_gen_or_i32(dst, dst, tmp);
4369 }
4370 } else {
4371 TCGv mask = tcg_temp_new();
4372 TCGv rot = tcg_temp_new();
4373
4374 if (ext & 0x20) {
4375 /* Variable width */
4376 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4377 tcg_gen_andi_i32(rot, rot, 31);
4378 tcg_gen_movi_i32(mask, -2);
4379 tcg_gen_shl_i32(mask, mask, rot);
4380 tcg_gen_mov_i32(rot, DREG(ext, 0));
4381 tcg_gen_andc_i32(tmp, src, mask);
4382 } else {
4383 /* Immediate width (variable offset) */
4384 uint32_t maski = -2U << (len - 1);
4385 tcg_gen_andi_i32(tmp, src, ~maski);
4386 tcg_gen_movi_i32(mask, maski);
4387 tcg_gen_movi_i32(rot, len & 31);
4388 }
4389 if (ext & 0x800) {
4390 /* Variable offset */
4391 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4392 } else {
4393 /* Immediate offset (variable width) */
4394 tcg_gen_addi_i32(rot, rot, ofs);
4395 }
4396 tcg_gen_andi_i32(rot, rot, 31);
4397 tcg_gen_rotr_i32(mask, mask, rot);
4398 tcg_gen_rotr_i32(tmp, tmp, rot);
4399 tcg_gen_and_i32(dst, dst, mask);
4400 tcg_gen_or_i32(dst, dst, tmp);
4401
4402 tcg_temp_free(rot);
4403 tcg_temp_free(mask);
4404 }
4405 tcg_temp_free(tmp);
4406 }
4407
4408 DISAS_INSN(bfins_mem)
4409 {
4410 int ext = read_im16(env, s);
4411 TCGv src = DREG(ext, 12);
4412 TCGv addr, len, ofs;
4413
4414 addr = gen_lea(env, s, insn, OS_UNSIZED);
4415 if (IS_NULL_QREG(addr)) {
4416 gen_addr_fault(s);
4417 return;
4418 }
4419
4420 if (ext & 0x20) {
4421 len = DREG(ext, 0);
4422 } else {
4423 len = tcg_const_i32(extract32(ext, 0, 5));
4424 }
4425 if (ext & 0x800) {
4426 ofs = DREG(ext, 6);
4427 } else {
4428 ofs = tcg_const_i32(extract32(ext, 6, 5));
4429 }
4430
4431 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4432 set_cc_op(s, CC_OP_LOGIC);
4433
4434 if (!(ext & 0x20)) {
4435 tcg_temp_free(len);
4436 }
4437 if (!(ext & 0x800)) {
4438 tcg_temp_free(ofs);
4439 }
4440 }
4441
4442 DISAS_INSN(ff1)
4443 {
4444 TCGv reg;
4445 reg = DREG(insn, 0);
4446 gen_logic_cc(s, reg, OS_LONG);
4447 gen_helper_ff1(reg, reg);
4448 }
4449
4450 DISAS_INSN(chk)
4451 {
4452 TCGv src, reg;
4453 int opsize;
4454
4455 switch ((insn >> 7) & 3) {
4456 case 3:
4457 opsize = OS_WORD;
4458 break;
4459 case 2:
4460 if (m68k_feature(env, M68K_FEATURE_CHK2)) {
4461 opsize = OS_LONG;
4462 break;
4463 }
4464 /* fallthru */
4465 default:
4466 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4467 return;
4468 }
4469 SRC_EA(env, src, opsize, 1, NULL);
4470 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4471
4472 gen_flush_flags(s);
4473 gen_helper_chk(cpu_env, reg, src);
4474 }
4475
4476 DISAS_INSN(chk2)
4477 {
4478 uint16_t ext;
4479 TCGv addr1, addr2, bound1, bound2, reg;
4480 int opsize;
4481
4482 switch ((insn >> 9) & 3) {
4483 case 0:
4484 opsize = OS_BYTE;
4485 break;
4486 case 1:
4487 opsize = OS_WORD;
4488 break;
4489 case 2:
4490 opsize = OS_LONG;
4491 break;
4492 default:
4493 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4494 return;
4495 }
4496
4497 ext = read_im16(env, s);
4498 if ((ext & 0x0800) == 0) {
4499 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4500 return;
4501 }
4502
4503 addr1 = gen_lea(env, s, insn, OS_UNSIZED);
4504 addr2 = tcg_temp_new();
4505 tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize));
4506
4507 bound1 = gen_load(s, opsize, addr1, 1, IS_USER(s));
4508 tcg_temp_free(addr1);
4509 bound2 = gen_load(s, opsize, addr2, 1, IS_USER(s));
4510 tcg_temp_free(addr2);
4511
4512 reg = tcg_temp_new();
4513 if (ext & 0x8000) {
4514 tcg_gen_mov_i32(reg, AREG(ext, 12));
4515 } else {
4516 gen_ext(reg, DREG(ext, 12), opsize, 1);
4517 }
4518
4519 gen_flush_flags(s);
4520 gen_helper_chk2(cpu_env, reg, bound1, bound2);
4521 tcg_temp_free(reg);
4522 tcg_temp_free(bound1);
4523 tcg_temp_free(bound2);
4524 }
4525
4526 static void m68k_copy_line(TCGv dst, TCGv src, int index)
4527 {
4528 TCGv addr;
4529 TCGv_i64 t0, t1;
4530
4531 addr = tcg_temp_new();
4532
4533 t0 = tcg_temp_new_i64();
4534 t1 = tcg_temp_new_i64();
4535
4536 tcg_gen_andi_i32(addr, src, ~15);
4537 tcg_gen_qemu_ld64(t0, addr, index);
4538 tcg_gen_addi_i32(addr, addr, 8);
4539 tcg_gen_qemu_ld64(t1, addr, index);
4540
4541 tcg_gen_andi_i32(addr, dst, ~15);
4542 tcg_gen_qemu_st64(t0, addr, index);
4543 tcg_gen_addi_i32(addr, addr, 8);
4544 tcg_gen_qemu_st64(t1, addr, index);
4545
4546 tcg_temp_free_i64(t0);
4547 tcg_temp_free_i64(t1);
4548 tcg_temp_free(addr);
4549 }
4550
4551 DISAS_INSN(move16_reg)
4552 {
4553 int index = IS_USER(s);
4554 TCGv tmp;
4555 uint16_t ext;
4556
4557 ext = read_im16(env, s);
4558 if ((ext & (1 << 15)) == 0) {
4559 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4560 }
4561
4562 m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
4563
4564 /* Ax can be Ay, so save Ay before incrementing Ax */
4565 tmp = tcg_temp_new();
4566 tcg_gen_mov_i32(tmp, AREG(ext, 12));
4567 tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16);
4568 tcg_gen_addi_i32(AREG(ext, 12), tmp, 16);
4569 tcg_temp_free(tmp);
4570 }
4571
4572 DISAS_INSN(move16_mem)
4573 {
4574 int index = IS_USER(s);
4575 TCGv reg, addr;
4576
4577 reg = AREG(insn, 0);
4578 addr = tcg_const_i32(read_im32(env, s));
4579
4580 if ((insn >> 3) & 1) {
4581 /* MOVE16 (xxx).L, (Ay) */
4582 m68k_copy_line(reg, addr, index);
4583 } else {
4584 /* MOVE16 (Ay), (xxx).L */
4585 m68k_copy_line(addr, reg, index);
4586 }
4587
4588 tcg_temp_free(addr);
4589
4590 if (((insn >> 3) & 2) == 0) {
4591 /* (Ay)+ */
4592 tcg_gen_addi_i32(reg, reg, 16);
4593 }
4594 }
4595
4596 DISAS_INSN(strldsr)
4597 {
4598 uint16_t ext;
4599 uint32_t addr;
4600
4601 addr = s->pc - 2;
4602 ext = read_im16(env, s);
4603 if (ext != 0x46FC) {
4604 gen_exception(s, addr, EXCP_ILLEGAL);
4605 return;
4606 }
4607 ext = read_im16(env, s);
4608 if (IS_USER(s) || (ext & SR_S) == 0) {
4609 gen_exception(s, addr, EXCP_PRIVILEGE);
4610 return;
4611 }
4612 gen_push(s, gen_get_sr(s));
4613 gen_set_sr_im(s, ext, 0);
4614 }
4615
4616 DISAS_INSN(move_from_sr)
4617 {
4618 TCGv sr;
4619
4620 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4621 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4622 return;
4623 }
4624 sr = gen_get_sr(s);
4625 DEST_EA(env, insn, OS_WORD, sr, NULL);
4626 }
4627
4628 #if defined(CONFIG_SOFTMMU)
4629 DISAS_INSN(moves)
4630 {
4631 int opsize;
4632 uint16_t ext;
4633 TCGv reg;
4634 TCGv addr;
4635 int extend;
4636
4637 if (IS_USER(s)) {
4638 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4639 return;
4640 }
4641
4642 ext = read_im16(env, s);
4643
4644 opsize = insn_opsize(insn);
4645
4646 if (ext & 0x8000) {
4647 /* address register */
4648 reg = AREG(ext, 12);
4649 extend = 1;
4650 } else {
4651 /* data register */
4652 reg = DREG(ext, 12);
4653 extend = 0;
4654 }
4655
4656 addr = gen_lea(env, s, insn, opsize);
4657 if (IS_NULL_QREG(addr)) {
4658 gen_addr_fault(s);
4659 return;
4660 }
4661
4662 if (ext & 0x0800) {
4663 /* from reg to ea */
4664 gen_store(s, opsize, addr, reg, DFC_INDEX(s));
4665 } else {
4666 /* from ea to reg */
4667 TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s));
4668 if (extend) {
4669 gen_ext(reg, tmp, opsize, 1);
4670 } else {
4671 gen_partset_reg(opsize, reg, tmp);
4672 }
4673 tcg_temp_free(tmp);
4674 }
4675 switch (extract32(insn, 3, 3)) {
4676 case 3: /* Indirect postincrement. */
4677 tcg_gen_addi_i32(AREG(insn, 0), addr,
4678 REG(insn, 0) == 7 && opsize == OS_BYTE
4679 ? 2
4680 : opsize_bytes(opsize));
4681 break;
4682 case 4: /* Indirect predecrememnt. */
4683 tcg_gen_mov_i32(AREG(insn, 0), addr);
4684 break;
4685 }
4686 }
4687
4688 DISAS_INSN(move_to_sr)
4689 {
4690 if (IS_USER(s)) {
4691 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4692 return;
4693 }
4694 gen_move_to_sr(env, s, insn, false);
4695 gen_exit_tb(s);
4696 }
4697
4698 DISAS_INSN(move_from_usp)
4699 {
4700 if (IS_USER(s)) {
4701 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4702 return;
4703 }
4704 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4705 offsetof(CPUM68KState, sp[M68K_USP]));
4706 }
4707
4708 DISAS_INSN(move_to_usp)
4709 {
4710 if (IS_USER(s)) {
4711 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4712 return;
4713 }
4714 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4715 offsetof(CPUM68KState, sp[M68K_USP]));
4716 }
4717
4718 DISAS_INSN(halt)
4719 {
4720 if (IS_USER(s)) {
4721 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4722 return;
4723 }
4724
4725 gen_exception(s, s->pc, EXCP_HALT_INSN);
4726 }
4727
4728 DISAS_INSN(stop)
4729 {
4730 uint16_t ext;
4731
4732 if (IS_USER(s)) {
4733 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4734 return;
4735 }
4736
4737 ext = read_im16(env, s);
4738
4739 gen_set_sr_im(s, ext, 0);
4740 tcg_gen_movi_i32(cpu_halted, 1);
4741 gen_exception(s, s->pc, EXCP_HLT);
4742 }
4743
4744 DISAS_INSN(rte)
4745 {
4746 if (IS_USER(s)) {
4747 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4748 return;
4749 }
4750 gen_exception(s, s->base.pc_next, EXCP_RTE);
4751 }
4752
4753 DISAS_INSN(cf_movec)
4754 {
4755 uint16_t ext;
4756 TCGv reg;
4757
4758 if (IS_USER(s)) {
4759 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4760 return;
4761 }
4762
4763 ext = read_im16(env, s);
4764
4765 if (ext & 0x8000) {
4766 reg = AREG(ext, 12);
4767 } else {
4768 reg = DREG(ext, 12);
4769 }
4770 gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4771 gen_exit_tb(s);
4772 }
4773
4774 DISAS_INSN(m68k_movec)
4775 {
4776 uint16_t ext;
4777 TCGv reg;
4778
4779 if (IS_USER(s)) {
4780 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4781 return;
4782 }
4783
4784 ext = read_im16(env, s);
4785
4786 if (ext & 0x8000) {
4787 reg = AREG(ext, 12);
4788 } else {
4789 reg = DREG(ext, 12);
4790 }
4791 if (insn & 1) {
4792 gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4793 } else {
4794 gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
4795 }
4796 gen_exit_tb(s);
4797 }
4798
4799 DISAS_INSN(intouch)
4800 {
4801 if (IS_USER(s)) {
4802 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4803 return;
4804 }
4805 /* ICache fetch. Implement as no-op. */
4806 }
4807
4808 DISAS_INSN(cpushl)
4809 {
4810 if (IS_USER(s)) {
4811 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4812 return;
4813 }
4814 /* Cache push/invalidate. Implement as no-op. */
4815 }
4816
4817 DISAS_INSN(cpush)
4818 {
4819 if (IS_USER(s)) {
4820 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4821 return;
4822 }
4823 /* Cache push/invalidate. Implement as no-op. */
4824 }
4825
4826 DISAS_INSN(cinv)
4827 {
4828 if (IS_USER(s)) {
4829 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4830 return;
4831 }
4832 /* Invalidate cache line. Implement as no-op. */
4833 }
4834
4835 #if defined(CONFIG_SOFTMMU)
4836 DISAS_INSN(pflush)
4837 {
4838 TCGv opmode;
4839
4840 if (IS_USER(s)) {
4841 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4842 return;
4843 }
4844
4845 opmode = tcg_const_i32((insn >> 3) & 3);
4846 gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
4847 tcg_temp_free(opmode);
4848 }
4849
4850 DISAS_INSN(ptest)
4851 {
4852 TCGv is_read;
4853
4854 if (IS_USER(s)) {
4855 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4856 return;
4857 }
4858 is_read = tcg_const_i32((insn >> 5) & 1);
4859 gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
4860 tcg_temp_free(is_read);
4861 }
4862 #endif
4863
4864 DISAS_INSN(wddata)
4865 {
4866 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4867 }
4868
4869 DISAS_INSN(wdebug)
4870 {
4871 if (IS_USER(s)) {
4872 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4873 return;
4874 }
4875 /* TODO: Implement wdebug. */
4876 cpu_abort(env_cpu(env), "WDEBUG not implemented");
4877 }
4878 #endif
4879
4880 DISAS_INSN(trap)
4881 {
4882 gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf));
4883 }
4884
4885 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4886 {
4887 switch (reg) {
4888 case M68K_FPIAR:
4889 tcg_gen_movi_i32(res, 0);
4890 break;
4891 case M68K_FPSR:
4892 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4893 break;
4894 case M68K_FPCR:
4895 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4896 break;
4897 }
4898 }
4899
4900 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4901 {
4902 switch (reg) {
4903 case M68K_FPIAR:
4904 break;
4905 case M68K_FPSR:
4906 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4907 break;
4908 case M68K_FPCR:
4909 gen_helper_set_fpcr(cpu_env, val);
4910 break;
4911 }
4912 }
4913
4914 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4915 {
4916 int index = IS_USER(s);
4917 TCGv tmp;
4918
4919 tmp = tcg_temp_new();
4920 gen_load_fcr(s, tmp, reg);
4921 tcg_gen_qemu_st32(tmp, addr, index);
4922 tcg_temp_free(tmp);
4923 }
4924
4925 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4926 {
4927 int index = IS_USER(s);
4928 TCGv tmp;
4929
4930 tmp = tcg_temp_new();
4931 tcg_gen_qemu_ld32u(tmp, addr, index);
4932 gen_store_fcr(s, tmp, reg);
4933 tcg_temp_free(tmp);
4934 }
4935
4936
4937 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4938 uint32_t insn, uint32_t ext)
4939 {
4940 int mask = (ext >> 10) & 7;
4941 int is_write = (ext >> 13) & 1;
4942 int mode = extract32(insn, 3, 3);
4943 int i;
4944 TCGv addr, tmp;
4945
4946 switch (mode) {
4947 case 0: /* Dn */
4948 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4949 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4950 return;
4951 }
4952 if (is_write) {
4953 gen_load_fcr(s, DREG(insn, 0), mask);
4954 } else {
4955 gen_store_fcr(s, DREG(insn, 0), mask);
4956 }
4957 return;
4958 case 1: /* An, only with FPIAR */
4959 if (mask != M68K_FPIAR) {
4960 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4961 return;
4962 }
4963 if (is_write) {
4964 gen_load_fcr(s, AREG(insn, 0), mask);
4965 } else {
4966 gen_store_fcr(s, AREG(insn, 0), mask);
4967 }
4968 return;
4969 case 7: /* Immediate */
4970 if (REG(insn, 0) == 4) {
4971 if (is_write ||
4972 (mask != M68K_FPIAR && mask != M68K_FPSR &&
4973 mask != M68K_FPCR)) {
4974 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4975 return;
4976 }
4977 tmp = tcg_const_i32(read_im32(env, s));
4978 gen_store_fcr(s, tmp, mask);
4979 tcg_temp_free(tmp);
4980 return;
4981 }
4982 break;
4983 default:
4984 break;
4985 }
4986
4987 tmp = gen_lea(env, s, insn, OS_LONG);
4988 if (IS_NULL_QREG(tmp)) {
4989 gen_addr_fault(s);
4990 return;
4991 }
4992
4993 addr = tcg_temp_new();
4994 tcg_gen_mov_i32(addr, tmp);
4995
4996 /*
4997 * mask:
4998 *
4999 * 0b100 Floating-Point Control Register
5000 * 0b010 Floating-Point Status Register
5001 * 0b001 Floating-Point Instruction Address Register
5002 *
5003 */
5004
5005 if (is_write && mode == 4) {
5006 for (i = 2; i >= 0; i--, mask >>= 1) {
5007 if (mask & 1) {
5008 gen_qemu_store_fcr(s, addr, 1 << i);
5009 if (mask != 1) {
5010 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
5011 }
5012 }
5013 }
5014 tcg_gen_mov_i32(AREG(insn, 0), addr);
5015 } else {
5016 for (i = 0; i < 3; i++, mask >>= 1) {
5017 if (mask & 1) {
5018 if (is_write) {
5019 gen_qemu_store_fcr(s, addr, 1 << i);
5020 } else {
5021 gen_qemu_load_fcr(s, addr, 1 << i);
5022 }
5023 if (mask != 1 || mode == 3) {
5024 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
5025 }
5026 }
5027 }
5028 if (mode == 3) {
5029 tcg_gen_mov_i32(AREG(insn, 0), addr);
5030 }
5031 }
5032 tcg_temp_free_i32(addr);
5033 }
5034
5035 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
5036 uint32_t insn, uint32_t ext)
5037 {
5038 int opsize;
5039 TCGv addr, tmp;
5040 int mode = (ext >> 11) & 0x3;
5041 int is_load = ((ext & 0x2000) == 0);
5042
5043 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
5044 opsize = OS_EXTENDED;
5045 } else {
5046 opsize = OS_DOUBLE; /* FIXME */
5047 }
5048
5049 addr = gen_lea(env, s, insn, opsize);
5050 if (IS_NULL_QREG(addr)) {
5051 gen_addr_fault(s);
5052 return;
5053 }
5054
5055 tmp = tcg_temp_new();
5056 if (mode & 0x1) {
5057 /* Dynamic register list */
5058 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
5059 } else {
5060 /* Static register list */
5061 tcg_gen_movi_i32(tmp, ext & 0xff);
5062 }
5063
5064 if (!is_load && (mode & 2) == 0) {
5065 /*
5066 * predecrement addressing mode
5067 * only available to store register to memory
5068 */
5069 if (opsize == OS_EXTENDED) {
5070 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
5071 } else {
5072 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
5073 }
5074 } else {
5075 /* postincrement addressing mode */
5076 if (opsize == OS_EXTENDED) {
5077 if (is_load) {
5078 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
5079 } else {
5080 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
5081 }
5082 } else {
5083 if (is_load) {
5084 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
5085 } else {
5086 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
5087 }
5088 }
5089 }
5090 if ((insn & 070) == 030 || (insn & 070) == 040) {
5091 tcg_gen_mov_i32(AREG(insn, 0), tmp);
5092 }
5093 tcg_temp_free(tmp);
5094 }
5095
5096 /*
5097 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5098 * immediately before the next FP instruction is executed.
5099 */
5100 DISAS_INSN(fpu)
5101 {
5102 uint16_t ext;
5103 int opmode;
5104 int opsize;
5105 TCGv_ptr cpu_src, cpu_dest;
5106
5107 ext = read_im16(env, s);
5108 opmode = ext & 0x7f;
5109 switch ((ext >> 13) & 7) {
5110 case 0:
5111 break;
5112 case 1:
5113 goto undef;
5114 case 2:
5115 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
5116 /* fmovecr */
5117 TCGv rom_offset = tcg_const_i32(opmode);
5118 cpu_dest = gen_fp_ptr(REG(ext, 7));
5119 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
5120 tcg_temp_free_ptr(cpu_dest);
5121 tcg_temp_free(rom_offset);
5122 return;
5123 }
5124 break;
5125 case 3: /* fmove out */
5126 cpu_src = gen_fp_ptr(REG(ext, 7));
5127 opsize = ext_opsize(ext, 10);
5128 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5129 EA_STORE, IS_USER(s)) == -1) {
5130 gen_addr_fault(s);
5131 }
5132 gen_helper_ftst(cpu_env, cpu_src);
5133 tcg_temp_free_ptr(cpu_src);
5134 return;
5135 case 4: /* fmove to control register. */
5136 case 5: /* fmove from control register. */
5137 gen_op_fmove_fcr(env, s, insn, ext);
5138 return;
5139 case 6: /* fmovem */
5140 case 7:
5141 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
5142 goto undef;
5143 }
5144 gen_op_fmovem(env, s, insn, ext);
5145 return;
5146 }
5147 if (ext & (1 << 14)) {
5148 /* Source effective address. */
5149 opsize = ext_opsize(ext, 10);
5150 cpu_src = gen_fp_result_ptr();
5151 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5152 EA_LOADS, IS_USER(s)) == -1) {
5153 gen_addr_fault(s);
5154 return;
5155 }
5156 } else {
5157 /* Source register. */
5158 opsize = OS_EXTENDED;
5159 cpu_src = gen_fp_ptr(REG(ext, 10));
5160 }
5161 cpu_dest = gen_fp_ptr(REG(ext, 7));
5162 switch (opmode) {
5163 case 0: /* fmove */
5164 gen_fp_move(cpu_dest, cpu_src);
5165 break;
5166 case 0x40: /* fsmove */
5167 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
5168 break;
5169 case 0x44: /* fdmove */
5170 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
5171 break;
5172 case 1: /* fint */
5173 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
5174 break;
5175 case 2: /* fsinh */
5176 gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
5177 break;
5178 case 3: /* fintrz */
5179 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
5180 break;
5181 case 4: /* fsqrt */
5182 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
5183 break;
5184 case 0x41: /* fssqrt */
5185 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
5186 break;
5187 case 0x45: /* fdsqrt */
5188 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
5189 break;
5190 case 0x06: /* flognp1 */
5191 gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
5192 break;
5193 case 0x08: /* fetoxm1 */
5194 gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
5195 break;
5196 case 0x09: /* ftanh */
5197 gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
5198 break;
5199 case 0x0a: /* fatan */
5200 gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
5201 break;
5202 case 0x0c: /* fasin */
5203 gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
5204 break;
5205 case 0x0d: /* fatanh */
5206 gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
5207 break;
5208 case 0x0e: /* fsin */
5209 gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
5210 break;
5211 case 0x0f: /* ftan */
5212 gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
5213 break;
5214 case 0x10: /* fetox */
5215 gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
5216 break;
5217 case 0x11: /* ftwotox */
5218 gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
5219 break;
5220 case 0x12: /* ftentox */
5221 gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
5222 break;
5223 case 0x14: /* flogn */
5224 gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
5225 break;
5226 case 0x15: /* flog10 */
5227 gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
5228 break;
5229 case 0x16: /* flog2 */
5230 gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
5231 break;
5232 case 0x18: /* fabs */
5233 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
5234 break;
5235 case 0x58: /* fsabs */
5236 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
5237 break;
5238 case 0x5c: /* fdabs */
5239 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
5240 break;
5241 case 0x19: /* fcosh */
5242 gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
5243 break;
5244 case 0x1a: /* fneg */
5245 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
5246 break;
5247 case 0x5a: /* fsneg */
5248 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
5249 break;
5250 case 0x5e: /* fdneg */
5251 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
5252 break;
5253 case 0x1c: /* facos */
5254 gen_helper_facos(cpu_env, cpu_dest, cpu_src);
5255 break;
5256 case 0x1d: /* fcos */
5257 gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
5258 break;
5259 case 0x1e: /* fgetexp */
5260 gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
5261 break;
5262 case 0x1f: /* fgetman */
5263 gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
5264 break;
5265 case 0x20: /* fdiv */
5266 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5267 break;
5268 case 0x60: /* fsdiv */
5269 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5270 break;
5271 case 0x64: /* fddiv */
5272 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5273 break;
5274 case 0x21: /* fmod */
5275 gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
5276 break;
5277 case 0x22: /* fadd */
5278 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5279 break;
5280 case 0x62: /* fsadd */
5281 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5282 break;
5283 case 0x66: /* fdadd */
5284 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5285 break;
5286 case 0x23: /* fmul */
5287 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5288 break;
5289 case 0x63: /* fsmul */
5290 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5291 break;
5292 case 0x67: /* fdmul */
5293 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5294 break;
5295 case 0x24: /* fsgldiv */
5296 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5297 break;
5298 case 0x25: /* frem */
5299 gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
5300 break;
5301 case 0x26: /* fscale */
5302 gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
5303 break;
5304 case 0x27: /* fsglmul */
5305 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5306 break;
5307 case 0x28: /* fsub */
5308 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5309 break;
5310 case 0x68: /* fssub */
5311 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5312 break;
5313 case 0x6c: /* fdsub */
5314 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5315 break;
5316 case 0x30: case 0x31: case 0x32:
5317 case 0x33: case 0x34: case 0x35:
5318 case 0x36: case 0x37: {
5319 TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
5320 gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
5321 tcg_temp_free_ptr(cpu_dest2);
5322 }
5323 break;
5324 case 0x38: /* fcmp */
5325 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
5326 return;
5327 case 0x3a: /* ftst */
5328 gen_helper_ftst(cpu_env, cpu_src);
5329 return;
5330 default:
5331 goto undef;
5332 }
5333 tcg_temp_free_ptr(cpu_src);
5334 gen_helper_ftst(cpu_env, cpu_dest);
5335 tcg_temp_free_ptr(cpu_dest);
5336 return;
5337 undef:
5338 /* FIXME: Is this right for offset addressing modes? */
5339 s->pc -= 2;
5340 disas_undef_fpu(env, s, insn);
5341 }
5342
5343 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
5344 {
5345 TCGv fpsr;
5346
5347 c->g1 = 1;
5348 c->v2 = tcg_const_i32(0);
5349 c->g2 = 0;
5350 /* TODO: Raise BSUN exception. */
5351 fpsr = tcg_temp_new();
5352 gen_load_fcr(s, fpsr, M68K_FPSR);
5353 switch (cond) {
5354 case 0: /* False */
5355 case 16: /* Signaling False */
5356 c->v1 = c->v2;
5357 c->tcond = TCG_COND_NEVER;
5358 break;
5359 case 1: /* EQual Z */
5360 case 17: /* Signaling EQual Z */
5361 c->v1 = tcg_temp_new();
5362 c->g1 = 0;
5363 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5364 c->tcond = TCG_COND_NE;
5365 break;
5366 case 2: /* Ordered Greater Than !(A || Z || N) */
5367 case 18: /* Greater Than !(A || Z || N) */
5368 c->v1 = tcg_temp_new();
5369 c->g1 = 0;
5370 tcg_gen_andi_i32(c->v1, fpsr,
5371 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5372 c->tcond = TCG_COND_EQ;
5373 break;
5374 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5375 case 19: /* Greater than or Equal Z || !(A || N) */
5376 c->v1 = tcg_temp_new();
5377 c->g1 = 0;
5378 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5379 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5380 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
5381 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5382 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5383 c->tcond = TCG_COND_NE;
5384 break;
5385 case 4: /* Ordered Less Than !(!N || A || Z); */
5386 case 20: /* Less Than !(!N || A || Z); */
5387 c->v1 = tcg_temp_new();
5388 c->g1 = 0;
5389 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
5390 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
5391 c->tcond = TCG_COND_EQ;
5392 break;
5393 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5394 case 21: /* Less than or Equal Z || (N && !A) */
5395 c->v1 = tcg_temp_new();
5396 c->g1 = 0;
5397 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5398 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5399 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5400 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
5401 c->tcond = TCG_COND_NE;
5402 break;
5403 case 6: /* Ordered Greater or Less than !(A || Z) */
5404 case 22: /* Greater or Less than !(A || Z) */
5405 c->v1 = tcg_temp_new();
5406 c->g1 = 0;
5407 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5408 c->tcond = TCG_COND_EQ;
5409 break;
5410 case 7: /* Ordered !A */
5411 case 23: /* Greater, Less or Equal !A */
5412 c->v1 = tcg_temp_new();
5413 c->g1 = 0;
5414 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5415 c->tcond = TCG_COND_EQ;
5416 break;
5417 case 8: /* Unordered A */
5418 case 24: /* Not Greater, Less or Equal A */
5419 c->v1 = tcg_temp_new();
5420 c->g1 = 0;
5421 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5422 c->tcond = TCG_COND_NE;
5423 break;
5424 case 9: /* Unordered or Equal A || Z */
5425 case 25: /* Not Greater or Less then A || Z */
5426 c->v1 = tcg_temp_new();
5427 c->g1 = 0;
5428 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5429 c->tcond = TCG_COND_NE;
5430 break;
5431 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5432 case 26: /* Not Less or Equal A || !(N || Z)) */
5433 c->v1 = tcg_temp_new();
5434 c->g1 = 0;
5435 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5436 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5437 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
5438 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5439 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5440 c->tcond = TCG_COND_NE;
5441 break;
5442 case 11: /* Unordered or Greater or Equal A || Z || !N */
5443 case 27: /* Not Less Than A || Z || !N */
5444 c->v1 = tcg_temp_new();
5445 c->g1 = 0;
5446 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5447 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5448 c->tcond = TCG_COND_NE;
5449 break;
5450 case 12: /* Unordered or Less Than A || (N && !Z) */
5451 case 28: /* Not Greater than or Equal A || (N && !Z) */
5452 c->v1 = tcg_temp_new();
5453 c->g1 = 0;
5454 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5455 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5456 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5457 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
5458 c->tcond = TCG_COND_NE;
5459 break;
5460 case 13: /* Unordered or Less or Equal A || Z || N */
5461 case 29: /* Not Greater Than A || Z || N */
5462 c->v1 = tcg_temp_new();
5463 c->g1 = 0;
5464 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5465 c->tcond = TCG_COND_NE;
5466 break;
5467 case 14: /* Not Equal !Z */
5468 case 30: /* Signaling Not Equal !Z */
5469 c->v1 = tcg_temp_new();
5470 c->g1 = 0;
5471 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5472 c->tcond = TCG_COND_EQ;
5473 break;
5474 case 15: /* True */
5475 case 31: /* Signaling True */
5476 c->v1 = c->v2;
5477 c->tcond = TCG_COND_ALWAYS;
5478 break;
5479 }
5480 tcg_temp_free(fpsr);
5481 }
5482
5483 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
5484 {
5485 DisasCompare c;
5486
5487 gen_fcc_cond(&c, s, cond);
5488 update_cc_op(s);
5489 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
5490 free_cond(&c);
5491 }
5492
5493 DISAS_INSN(fbcc)
5494 {
5495 uint32_t offset;
5496 uint32_t base;
5497 TCGLabel *l1;
5498
5499 base = s->pc;
5500 offset = (int16_t)read_im16(env, s);
5501 if (insn & (1 << 6)) {
5502 offset = (offset << 16) | read_im16(env, s);
5503 }
5504
5505 l1 = gen_new_label();
5506 update_cc_op(s);
5507 gen_fjmpcc(s, insn & 0x3f, l1);
5508 gen_jmp_tb(s, 0, s->pc);
5509 gen_set_label(l1);
5510 gen_jmp_tb(s, 1, base + offset);
5511 }
5512
5513 DISAS_INSN(fscc)
5514 {
5515 DisasCompare c;
5516 int cond;
5517 TCGv tmp;
5518 uint16_t ext;
5519
5520 ext = read_im16(env, s);
5521 cond = ext & 0x3f;
5522 gen_fcc_cond(&c, s, cond);
5523
5524 tmp = tcg_temp_new();
5525 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
5526 free_cond(&c);
5527
5528 tcg_gen_neg_i32(tmp, tmp);
5529 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
5530 tcg_temp_free(tmp);
5531 }
5532
5533 #if defined(CONFIG_SOFTMMU)
5534 DISAS_INSN(frestore)
5535 {
5536 TCGv addr;
5537
5538 if (IS_USER(s)) {
5539 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5540 return;
5541 }
5542 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5543 SRC_EA(env, addr, OS_LONG, 0, NULL);
5544 /* FIXME: check the state frame */
5545 } else {
5546 disas_undef(env, s, insn);
5547 }
5548 }
5549
5550 DISAS_INSN(fsave)
5551 {
5552 if (IS_USER(s)) {
5553 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5554 return;
5555 }
5556
5557 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5558 /* always write IDLE */
5559 TCGv idle = tcg_const_i32(0x41000000);
5560 DEST_EA(env, insn, OS_LONG, idle, NULL);
5561 tcg_temp_free(idle);
5562 } else {
5563 disas_undef(env, s, insn);
5564 }
5565 }
5566 #endif
5567
5568 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
5569 {
5570 TCGv tmp = tcg_temp_new();
5571 if (s->env->macsr & MACSR_FI) {
5572 if (upper)
5573 tcg_gen_andi_i32(tmp, val, 0xffff0000);
5574 else
5575 tcg_gen_shli_i32(tmp, val, 16);
5576 } else if (s->env->macsr & MACSR_SU) {
5577 if (upper)
5578 tcg_gen_sari_i32(tmp, val, 16);
5579 else
5580 tcg_gen_ext16s_i32(tmp, val);
5581 } else {
5582 if (upper)
5583 tcg_gen_shri_i32(tmp, val, 16);
5584 else
5585 tcg_gen_ext16u_i32(tmp, val);
5586 }
5587 return tmp;
5588 }
5589
5590 static void gen_mac_clear_flags(void)
5591 {
5592 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
5593 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
5594 }
5595
5596 DISAS_INSN(mac)
5597 {
5598 TCGv rx;
5599 TCGv ry;
5600 uint16_t ext;
5601 int acc;
5602 TCGv tmp;
5603 TCGv addr;
5604 TCGv loadval;
5605 int dual;
5606 TCGv saved_flags;
5607
5608 if (!s->done_mac) {
5609 s->mactmp = tcg_temp_new_i64();
5610 s->done_mac = 1;
5611 }
5612
5613 ext = read_im16(env, s);
5614
5615 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
5616 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
5617 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
5618 disas_undef(env, s, insn);
5619 return;
5620 }
5621 if (insn & 0x30) {
5622 /* MAC with load. */
5623 tmp = gen_lea(env, s, insn, OS_LONG);
5624 addr = tcg_temp_new();
5625 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5626 /*
5627 * Load the value now to ensure correct exception behavior.
5628 * Perform writeback after reading the MAC inputs.
5629 */
5630 loadval = gen_load(s, OS_LONG, addr, 0, IS_USER(s));
5631
5632 acc ^= 1;
5633 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5634 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5635 } else {
5636 loadval = addr = NULL_QREG;
5637 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5638 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5639 }
5640
5641 gen_mac_clear_flags();
5642 #if 0
5643 l1 = -1;
5644 /* Disabled because conditional branches clobber temporary vars. */
5645 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5646 /* Skip the multiply if we know we will ignore it. */
5647 l1 = gen_new_label();
5648 tmp = tcg_temp_new();
5649 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5650 gen_op_jmp_nz32(tmp, l1);
5651 }
5652 #endif
5653
5654 if ((ext & 0x0800) == 0) {
5655 /* Word. */
5656 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5657 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5658 }
5659 if (s->env->macsr & MACSR_FI) {
5660 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5661 } else {
5662 if (s->env->macsr & MACSR_SU)
5663 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5664 else
5665 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5666 switch ((ext >> 9) & 3) {
5667 case 1:
5668 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5669 break;
5670 case 3:
5671 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5672 break;
5673 }
5674 }
5675
5676 if (dual) {
5677 /* Save the overflow flag from the multiply. */
5678 saved_flags = tcg_temp_new();
5679 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5680 } else {
5681 saved_flags = NULL_QREG;
5682 }
5683
5684 #if 0
5685 /* Disabled because conditional branches clobber temporary vars. */
5686 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5687 /* Skip the accumulate if the value is already saturated. */
5688 l1 = gen_new_label();
5689 tmp = tcg_temp_new();
5690 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5691 gen_op_jmp_nz32(tmp, l1);
5692 }
5693 #endif
5694
5695 if (insn & 0x100)
5696 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5697 else
5698 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5699
5700 if (s->env->macsr & MACSR_FI)
5701 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5702 else if (s->env->macsr & MACSR_SU)
5703 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5704 else
5705 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5706
5707 #if 0
5708 /* Disabled because conditional branches clobber temporary vars. */
5709 if (l1 != -1)
5710 gen_set_label(l1);
5711 #endif
5712
5713 if (dual) {
5714 /* Dual accumulate variant. */
5715 acc = (ext >> 2) & 3;
5716 /* Restore the overflow flag from the multiplier. */
5717 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5718 #if 0
5719 /* Disabled because conditional branches clobber temporary vars. */
5720 if ((s->env->macsr & MACSR_OMC) != 0) {
5721 /* Skip the accumulate if the value is already saturated. */
5722 l1 = gen_new_label();
5723 tmp = tcg_temp_new();
5724 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5725 gen_op_jmp_nz32(tmp, l1);
5726 }
5727 #endif
5728 if (ext & 2)
5729 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5730 else
5731 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5732 if (s->env->macsr & MACSR_FI)
5733 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5734 else if (s->env->macsr & MACSR_SU)
5735 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5736 else
5737 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5738 #if 0
5739 /* Disabled because conditional branches clobber temporary vars. */
5740 if (l1 != -1)
5741 gen_set_label(l1);
5742 #endif
5743 }
5744 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5745
5746 if (insn & 0x30) {
5747 TCGv rw;
5748 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5749 tcg_gen_mov_i32(rw, loadval);
5750 /*
5751 * FIXME: Should address writeback happen with the masked or
5752 * unmasked value?
5753 */
5754 switch ((insn >> 3) & 7) {
5755 case 3: /* Post-increment. */
5756 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5757 break;
5758 case 4: /* Pre-decrement. */
5759 tcg_gen_mov_i32(AREG(insn, 0), addr);
5760 }
5761 tcg_temp_free(loadval);
5762 }
5763 }
5764
5765 DISAS_INSN(from_mac)
5766 {
5767 TCGv rx;
5768 TCGv_i64 acc;
5769 int accnum;
5770
5771 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5772 accnum = (insn >> 9) & 3;
5773 acc = MACREG(accnum);
5774 if (s->env->macsr & MACSR_FI) {
5775 gen_helper_get_macf(rx, cpu_env, acc);
5776 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5777 tcg_gen_extrl_i64_i32(rx, acc);
5778 } else if (s->env->macsr & MACSR_SU) {
5779 gen_helper_get_macs(rx, acc);
5780 } else {
5781 gen_helper_get_macu(rx, acc);
5782 }
5783 if (insn & 0x40) {
5784 tcg_gen_movi_i64(acc, 0);
5785 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5786 }
5787 }
5788
5789 DISAS_INSN(move_mac)
5790 {
5791 /* FIXME: This can be done without a helper. */
5792 int src;
5793 TCGv dest;
5794 src = insn & 3;
5795 dest = tcg_const_i32((insn >> 9) & 3);
5796 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5797 gen_mac_clear_flags();
5798 gen_helper_mac_set_flags(cpu_env, dest);
5799 }
5800
5801 DISAS_INSN(from_macsr)
5802 {
5803 TCGv reg;
5804
5805 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5806 tcg_gen_mov_i32(reg, QREG_MACSR);
5807 }
5808
5809 DISAS_INSN(from_mask)
5810 {
5811 TCGv reg;
5812 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5813 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5814 }
5815
5816 DISAS_INSN(from_mext)
5817 {
5818 TCGv reg;
5819 TCGv acc;
5820 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5821 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5822 if (s->env->macsr & MACSR_FI)
5823 gen_helper_get_mac_extf(reg, cpu_env, acc);
5824 else
5825 gen_helper_get_mac_exti(reg, cpu_env, acc);
5826 }
5827
5828 DISAS_INSN(macsr_to_ccr)
5829 {
5830 TCGv tmp = tcg_temp_new();
5831 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5832 gen_helper_set_sr(cpu_env, tmp);
5833 tcg_temp_free(tmp);
5834 set_cc_op(s, CC_OP_FLAGS);
5835 }
5836
5837 DISAS_INSN(to_mac)
5838 {
5839 TCGv_i64 acc;
5840 TCGv val;
5841 int accnum;
5842 accnum = (insn >> 9) & 3;
5843 acc = MACREG(accnum);
5844 SRC_EA(env, val, OS_LONG, 0, NULL);
5845 if (s->env->macsr & MACSR_FI) {
5846 tcg_gen_ext_i32_i64(acc, val);
5847 tcg_gen_shli_i64(acc, acc, 8);
5848 } else if (s->env->macsr & MACSR_SU) {
5849 tcg_gen_ext_i32_i64(acc, val);
5850 } else {
5851 tcg_gen_extu_i32_i64(acc, val);
5852 }
5853 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5854 gen_mac_clear_flags();
5855 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5856 }
5857
5858 DISAS_INSN(to_macsr)
5859 {
5860 TCGv val;
5861 SRC_EA(env, val, OS_LONG, 0, NULL);
5862 gen_helper_set_macsr(cpu_env, val);
5863 gen_exit_tb(s);
5864 }
5865
5866 DISAS_INSN(to_mask)
5867 {
5868 TCGv val;
5869 SRC_EA(env, val, OS_LONG, 0, NULL);
5870 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5871 }
5872
5873 DISAS_INSN(to_mext)
5874 {
5875 TCGv val;
5876 TCGv acc;
5877 SRC_EA(env, val, OS_LONG, 0, NULL);
5878 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5879 if (s->env->macsr & MACSR_FI)
5880 gen_helper_set_mac_extf(cpu_env, val, acc);
5881 else if (s->env->macsr & MACSR_SU)
5882 gen_helper_set_mac_exts(cpu_env, val, acc);
5883 else
5884 gen_helper_set_mac_extu(cpu_env, val, acc);
5885 }
5886
5887 static disas_proc opcode_table[65536];
5888
5889 static void
5890 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5891 {
5892 int i;
5893 int from;
5894 int to;
5895
5896 /* Sanity check. All set bits must be included in the mask. */
5897 if (opcode & ~mask) {
5898 fprintf(stderr,
5899 "qemu internal error: bogus opcode definition %04x/%04x\n",
5900 opcode, mask);
5901 abort();
5902 }
5903 /*
5904 * This could probably be cleverer. For now just optimize the case where
5905 * the top bits are known.
5906 */
5907 /* Find the first zero bit in the mask. */
5908 i = 0x8000;
5909 while ((i & mask) != 0)
5910 i >>= 1;
5911 /* Iterate over all combinations of this and lower bits. */
5912 if (i == 0)
5913 i = 1;
5914 else
5915 i <<= 1;
5916 from = opcode & ~(i - 1);
5917 to = from + i;
5918 for (i = from; i < to; i++) {
5919 if ((i & mask) == opcode)
5920 opcode_table[i] = proc;
5921 }
5922 }
5923
5924 /*
5925 * Register m68k opcode handlers. Order is important.
5926 * Later insn override earlier ones.
5927 */
5928 void register_m68k_insns (CPUM68KState *env)
5929 {
5930 /*
5931 * Build the opcode table only once to avoid
5932 * multithreading issues.
5933 */
5934 if (opcode_table[0] != NULL) {
5935 return;
5936 }
5937
5938 /*
5939 * use BASE() for instruction available
5940 * for CF_ISA_A and M68000.
5941 */
5942 #define BASE(name, opcode, mask) \
5943 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5944 #define INSN(name, opcode, mask, feature) do { \
5945 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5946 BASE(name, opcode, mask); \
5947 } while(0)
5948 BASE(undef, 0000, 0000);
5949 INSN(arith_im, 0080, fff8, CF_ISA_A);
5950 INSN(arith_im, 0000, ff00, M68000);
5951 INSN(chk2, 00c0, f9c0, CHK2);
5952 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5953 BASE(bitop_reg, 0100, f1c0);
5954 BASE(bitop_reg, 0140, f1c0);
5955 BASE(bitop_reg, 0180, f1c0);
5956 BASE(bitop_reg, 01c0, f1c0);
5957 INSN(movep, 0108, f138, MOVEP);
5958 INSN(arith_im, 0280, fff8, CF_ISA_A);
5959 INSN(arith_im, 0200, ff00, M68000);
5960 INSN(undef, 02c0, ffc0, M68000);
5961 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5962 INSN(arith_im, 0480, fff8, CF_ISA_A);
5963 INSN(arith_im, 0400, ff00, M68000);
5964 INSN(undef, 04c0, ffc0, M68000);
5965 INSN(arith_im, 0600, ff00, M68000);
5966 INSN(undef, 06c0, ffc0, M68000);
5967 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5968 INSN(arith_im, 0680, fff8, CF_ISA_A);
5969 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5970 INSN(arith_im, 0c00, ff00, M68000);
5971 BASE(bitop_im, 0800, ffc0);
5972 BASE(bitop_im, 0840, ffc0);
5973 BASE(bitop_im, 0880, ffc0);
5974 BASE(bitop_im, 08c0, ffc0);
5975 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5976 INSN(arith_im, 0a00, ff00, M68000);
5977 #if defined(CONFIG_SOFTMMU)
5978 INSN(moves, 0e00, ff00, M68000);
5979 #endif
5980 INSN(cas, 0ac0, ffc0, CAS);
5981 INSN(cas, 0cc0, ffc0, CAS);
5982 INSN(cas, 0ec0, ffc0, CAS);
5983 INSN(cas2w, 0cfc, ffff, CAS);
5984 INSN(cas2l, 0efc, ffff, CAS);
5985 BASE(move, 1000, f000);
5986 BASE(move, 2000, f000);
5987 BASE(move, 3000, f000);
5988 INSN(chk, 4000, f040, M68000);
5989 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
5990 INSN(negx, 4080, fff8, CF_ISA_A);
5991 INSN(negx, 4000, ff00, M68000);
5992 INSN(undef, 40c0, ffc0, M68000);
5993 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
5994 INSN(move_from_sr, 40c0, ffc0, M68000);
5995 BASE(lea, 41c0, f1c0);
5996 BASE(clr, 4200, ff00);
5997 BASE(undef, 42c0, ffc0);
5998 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
5999 INSN(move_from_ccr, 42c0, ffc0, M68000);
6000 INSN(neg, 4480, fff8, CF_ISA_A);
6001 INSN(neg, 4400, ff00, M68000);
6002 INSN(undef, 44c0, ffc0, M68000);
6003 BASE(move_to_ccr, 44c0, ffc0);
6004 INSN(not, 4680, fff8, CF_ISA_A);
6005 INSN(not, 4600, ff00, M68000);
6006 #if defined(CONFIG_SOFTMMU)
6007 BASE(move_to_sr, 46c0, ffc0);
6008 #endif
6009 INSN(nbcd, 4800, ffc0, M68000);
6010 INSN(linkl, 4808, fff8, M68000);
6011 BASE(pea, 4840, ffc0);
6012 BASE(swap, 4840, fff8);
6013 INSN(bkpt, 4848, fff8, BKPT);
6014 INSN(movem, 48d0, fbf8, CF_ISA_A);
6015 INSN(movem, 48e8, fbf8, CF_ISA_A);
6016 INSN(movem, 4880, fb80, M68000);
6017 BASE(ext, 4880, fff8);
6018 BASE(ext, 48c0, fff8);
6019 BASE(ext, 49c0, fff8);
6020 BASE(tst, 4a00, ff00);
6021 INSN(tas, 4ac0, ffc0, CF_ISA_B);
6022 INSN(tas, 4ac0, ffc0, M68000);
6023 #if defined(CONFIG_SOFTMMU)
6024 INSN(halt, 4ac8, ffff, CF_ISA_A);
6025 #endif
6026 INSN(pulse, 4acc, ffff, CF_ISA_A);
6027 BASE(illegal, 4afc, ffff);
6028 INSN(mull, 4c00, ffc0, CF_ISA_A);
6029 INSN(mull, 4c00, ffc0, LONG_MULDIV);
6030 INSN(divl, 4c40, ffc0, CF_ISA_A);
6031 INSN(divl, 4c40, ffc0, LONG_MULDIV);
6032 INSN(sats, 4c80, fff8, CF_ISA_B);
6033 BASE(trap, 4e40, fff0);
6034 BASE(link, 4e50, fff8);
6035 BASE(unlk, 4e58, fff8);
6036 #if defined(CONFIG_SOFTMMU)
6037 INSN(move_to_usp, 4e60, fff8, USP);
6038 INSN(move_from_usp, 4e68, fff8, USP);
6039 INSN(reset, 4e70, ffff, M68000);
6040 BASE(stop, 4e72, ffff);
6041 BASE(rte, 4e73, ffff);
6042 INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
6043 INSN(m68k_movec, 4e7a, fffe, MOVEC);
6044 #endif
6045 BASE(nop, 4e71, ffff);
6046 INSN(rtd, 4e74, ffff, RTD);
6047 BASE(rts, 4e75, ffff);
6048 INSN(rtr, 4e77, ffff, M68000);
6049 BASE(jump, 4e80, ffc0);
6050 BASE(jump, 4ec0, ffc0);
6051 INSN(addsubq, 5000, f080, M68000);
6052 BASE(addsubq, 5080, f0c0);
6053 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
6054 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
6055 INSN(dbcc, 50c8, f0f8, M68000);
6056 INSN(tpf, 51f8, fff8, CF_ISA_A);
6057
6058 /* Branch instructions. */
6059 BASE(branch, 6000, f000);
6060 /* Disable long branch instructions, then add back the ones we want. */
6061 BASE(undef, 60ff, f0ff); /* All long branches. */
6062 INSN(branch, 60ff, f0ff, CF_ISA_B);
6063 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
6064 INSN(branch, 60ff, ffff, BRAL);
6065 INSN(branch, 60ff, f0ff, BCCL);
6066
6067 BASE(moveq, 7000, f100);
6068 INSN(mvzs, 7100, f100, CF_ISA_B);
6069 BASE(or, 8000, f000);
6070 BASE(divw, 80c0, f0c0);
6071 INSN(sbcd_reg, 8100, f1f8, M68000);
6072 INSN(sbcd_mem, 8108, f1f8, M68000);
6073 BASE(addsub, 9000, f000);
6074 INSN(undef, 90c0, f0c0, CF_ISA_A);
6075 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
6076 INSN(subx_reg, 9100, f138, M68000);
6077 INSN(subx_mem, 9108, f138, M68000);
6078 INSN(suba, 91c0, f1c0, CF_ISA_A);
6079 INSN(suba, 90c0, f0c0, M68000);
6080
6081 BASE(undef_mac, a000, f000);
6082 INSN(mac, a000, f100, CF_EMAC);
6083 INSN(from_mac, a180, f9b0, CF_EMAC);
6084 INSN(move_mac, a110, f9fc, CF_EMAC);
6085 INSN(from_macsr,a980, f9f0, CF_EMAC);
6086 INSN(from_mask, ad80, fff0, CF_EMAC);
6087 INSN(from_mext, ab80, fbf0, CF_EMAC);
6088 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
6089 INSN(to_mac, a100, f9c0, CF_EMAC);
6090 INSN(to_macsr, a900, ffc0, CF_EMAC);
6091 INSN(to_mext, ab00, fbc0, CF_EMAC);
6092 INSN(to_mask, ad00, ffc0, CF_EMAC);
6093
6094 INSN(mov3q, a140, f1c0, CF_ISA_B);
6095 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
6096 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
6097 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
6098 INSN(cmp, b080, f1c0, CF_ISA_A);
6099 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
6100 INSN(cmp, b000, f100, M68000);
6101 INSN(eor, b100, f100, M68000);
6102 INSN(cmpm, b108, f138, M68000);
6103 INSN(cmpa, b0c0, f0c0, M68000);
6104 INSN(eor, b180, f1c0, CF_ISA_A);
6105 BASE(and, c000, f000);
6106 INSN(exg_dd, c140, f1f8, M68000);
6107 INSN(exg_aa, c148, f1f8, M68000);
6108 INSN(exg_da, c188, f1f8, M68000);
6109 BASE(mulw, c0c0, f0c0);
6110 INSN(abcd_reg, c100, f1f8, M68000);
6111 INSN(abcd_mem, c108, f1f8, M68000);
6112 BASE(addsub, d000, f000);
6113 INSN(undef, d0c0, f0c0, CF_ISA_A);
6114 INSN(addx_reg, d180, f1f8, CF_ISA_A);
6115 INSN(addx_reg, d100, f138, M68000);
6116 INSN(addx_mem, d108, f138, M68000);
6117 INSN(adda, d1c0, f1c0, CF_ISA_A);
6118 INSN(adda, d0c0, f0c0, M68000);
6119 INSN(shift_im, e080, f0f0, CF_ISA_A);
6120 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
6121 INSN(shift8_im, e000, f0f0, M68000);
6122 INSN(shift16_im, e040, f0f0, M68000);
6123 INSN(shift_im, e080, f0f0, M68000);
6124 INSN(shift8_reg, e020, f0f0, M68000);
6125 INSN(shift16_reg, e060, f0f0, M68000);
6126 INSN(shift_reg, e0a0, f0f0, M68000);
6127 INSN(shift_mem, e0c0, fcc0, M68000);
6128 INSN(rotate_im, e090, f0f0, M68000);
6129 INSN(rotate8_im, e010, f0f0, M68000);
6130 INSN(rotate16_im, e050, f0f0, M68000);
6131 INSN(rotate_reg, e0b0, f0f0, M68000);
6132 INSN(rotate8_reg, e030, f0f0, M68000);
6133 INSN(rotate16_reg, e070, f0f0, M68000);
6134 INSN(rotate_mem, e4c0, fcc0, M68000);
6135 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
6136 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
6137 INSN(bfins_mem, efc0, ffc0, BITFIELD);
6138 INSN(bfins_reg, efc0, fff8, BITFIELD);
6139 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
6140 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
6141 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
6142 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
6143 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
6144 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
6145 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
6146 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
6147 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
6148 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
6149 BASE(undef_fpu, f000, f000);
6150 INSN(fpu, f200, ffc0, CF_FPU);
6151 INSN(fbcc, f280, ffc0, CF_FPU);
6152 INSN(fpu, f200, ffc0, FPU);
6153 INSN(fscc, f240, ffc0, FPU);
6154 INSN(fbcc, f280, ff80, FPU);
6155 #if defined(CONFIG_SOFTMMU)
6156 INSN(frestore, f340, ffc0, CF_FPU);
6157 INSN(fsave, f300, ffc0, CF_FPU);
6158 INSN(frestore, f340, ffc0, FPU);
6159 INSN(fsave, f300, ffc0, FPU);
6160 INSN(intouch, f340, ffc0, CF_ISA_A);
6161 INSN(cpushl, f428, ff38, CF_ISA_A);
6162 INSN(cpush, f420, ff20, M68040);
6163 INSN(cinv, f400, ff20, M68040);
6164 INSN(pflush, f500, ffe0, M68040);
6165 INSN(ptest, f548, ffd8, M68040);
6166 INSN(wddata, fb00, ff00, CF_ISA_A);
6167 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
6168 #endif
6169 INSN(move16_mem, f600, ffe0, M68040);
6170 INSN(move16_reg, f620, fff8, M68040);
6171 #undef INSN
6172 }
6173
6174 static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
6175 {
6176 DisasContext *dc = container_of(dcbase, DisasContext, base);
6177 CPUM68KState *env = cpu->env_ptr;
6178
6179 dc->env = env;
6180 dc->pc = dc->base.pc_first;
6181 dc->cc_op = CC_OP_DYNAMIC;
6182 dc->cc_op_synced = 1;
6183 dc->done_mac = 0;
6184 dc->writeback_mask = 0;
6185 init_release_array(dc);
6186 }
6187
6188 static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
6189 {
6190 }
6191
6192 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
6193 {
6194 DisasContext *dc = container_of(dcbase, DisasContext, base);
6195 tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
6196 }
6197
6198 static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
6199 const CPUBreakpoint *bp)
6200 {
6201 DisasContext *dc = container_of(dcbase, DisasContext, base);
6202
6203 gen_exception(dc, dc->base.pc_next, EXCP_DEBUG);
6204 /*
6205 * The address covered by the breakpoint must be included in
6206 * [tb->pc, tb->pc + tb->size) in order to for it to be
6207 * properly cleared -- thus we increment the PC here so that
6208 * the logic setting tb->size below does the right thing.
6209 */
6210 dc->base.pc_next += 2;
6211
6212 return true;
6213 }
6214
6215 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
6216 {
6217 DisasContext *dc = container_of(dcbase, DisasContext, base);
6218 CPUM68KState *env = cpu->env_ptr;
6219 uint16_t insn = read_im16(env, dc);
6220
6221 opcode_table[insn](env, dc, insn);
6222 do_writebacks(dc);
6223 do_release(dc);
6224
6225 dc->base.pc_next = dc->pc;
6226
6227 if (dc->base.is_jmp == DISAS_NEXT) {
6228 /*
6229 * Stop translation when the next insn might touch a new page.
6230 * This ensures that prefetch aborts at the right place.
6231 *
6232 * We cannot determine the size of the next insn without
6233 * completely decoding it. However, the maximum insn size
6234 * is 32 bytes, so end if we do not have that much remaining.
6235 * This may produce several small TBs at the end of each page,
6236 * but they will all be linked with goto_tb.
6237 *
6238 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6239 * smaller than MC68020's.
6240 */
6241 target_ulong start_page_offset
6242 = dc->pc - (dc->base.pc_first & TARGET_PAGE_MASK);
6243
6244 if (start_page_offset >= TARGET_PAGE_SIZE - 32) {
6245 dc->base.is_jmp = DISAS_TOO_MANY;
6246 }
6247 }
6248 }
6249
6250 static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
6251 {
6252 DisasContext *dc = container_of(dcbase, DisasContext, base);
6253
6254 switch (dc->base.is_jmp) {
6255 case DISAS_NORETURN:
6256 break;
6257 case DISAS_TOO_MANY:
6258 update_cc_op(dc);
6259 if (is_singlestepping(dc)) {
6260 tcg_gen_movi_i32(QREG_PC, dc->pc);
6261 gen_raise_exception(EXCP_DEBUG);
6262 } else {
6263 gen_jmp_tb(dc, 0, dc->pc);
6264 }
6265 break;
6266 case DISAS_JUMP:
6267 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6268 if (is_singlestepping(dc)) {
6269 gen_raise_exception(EXCP_DEBUG);
6270 } else {
6271 tcg_gen_lookup_and_goto_ptr();
6272 }
6273 break;
6274 case DISAS_EXIT:
6275 /*
6276 * We updated CC_OP and PC in gen_exit_tb, but also modified
6277 * other state that may require returning to the main loop.
6278 */
6279 if (is_singlestepping(dc)) {
6280 gen_raise_exception(EXCP_DEBUG);
6281 } else {
6282 tcg_gen_exit_tb(NULL, 0);
6283 }
6284 break;
6285 default:
6286 g_assert_not_reached();
6287 }
6288 }
6289
6290 static void m68k_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
6291 {
6292 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
6293 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
6294 }
6295
6296 static const TranslatorOps m68k_tr_ops = {
6297 .init_disas_context = m68k_tr_init_disas_context,
6298 .tb_start = m68k_tr_tb_start,
6299 .insn_start = m68k_tr_insn_start,
6300 .breakpoint_check = m68k_tr_breakpoint_check,
6301 .translate_insn = m68k_tr_translate_insn,
6302 .tb_stop = m68k_tr_tb_stop,
6303 .disas_log = m68k_tr_disas_log,
6304 };
6305
6306 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
6307 {
6308 DisasContext dc;
6309 translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
6310 }
6311
6312 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
6313 {
6314 floatx80 a = { .high = high, .low = low };
6315 union {
6316 float64 f64;
6317 double d;
6318 } u;
6319
6320 u.f64 = floatx80_to_float64(a, &env->fp_status);
6321 return u.d;
6322 }
6323
6324 void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
6325 {
6326 M68kCPU *cpu = M68K_CPU(cs);
6327 CPUM68KState *env = &cpu->env;
6328 int i;
6329 uint16_t sr;
6330 for (i = 0; i < 8; i++) {
6331 qemu_fprintf(f, "D%d = %08x A%d = %08x "
6332 "F%d = %04x %016"PRIx64" (%12g)\n",
6333 i, env->dregs[i], i, env->aregs[i],
6334 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
6335 floatx80_to_double(env, env->fregs[i].l.upper,
6336 env->fregs[i].l.lower));
6337 }
6338 qemu_fprintf(f, "PC = %08x ", env->pc);
6339 sr = env->sr | cpu_m68k_get_ccr(env);
6340 qemu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6341 sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,
6342 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',
6343 (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',
6344 (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',
6345 (sr & CCF_C) ? 'C' : '-');
6346 qemu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
6347 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
6348 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
6349 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
6350 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
6351 qemu_fprintf(f, "\n "
6352 "FPCR = %04x ", env->fpcr);
6353 switch (env->fpcr & FPCR_PREC_MASK) {
6354 case FPCR_PREC_X:
6355 qemu_fprintf(f, "X ");
6356 break;
6357 case FPCR_PREC_S:
6358 qemu_fprintf(f, "S ");
6359 break;
6360 case FPCR_PREC_D:
6361 qemu_fprintf(f, "D ");
6362 break;
6363 }
6364 switch (env->fpcr & FPCR_RND_MASK) {
6365 case FPCR_RND_N:
6366 qemu_fprintf(f, "RN ");
6367 break;
6368 case FPCR_RND_Z:
6369 qemu_fprintf(f, "RZ ");
6370 break;
6371 case FPCR_RND_M:
6372 qemu_fprintf(f, "RM ");
6373 break;
6374 case FPCR_RND_P:
6375 qemu_fprintf(f, "RP ");
6376 break;
6377 }
6378 qemu_fprintf(f, "\n");
6379 #ifdef CONFIG_SOFTMMU
6380 qemu_fprintf(f, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6381 env->current_sp == M68K_SSP ? "->" : " ", env->sp[M68K_SSP],
6382 env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
6383 env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
6384 qemu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
6385 qemu_fprintf(f, "SFC = %x DFC %x\n", env->sfc, env->dfc);
6386 qemu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6387 env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
6388 qemu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6389 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1],
6390 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]);
6391 qemu_fprintf(f, "MMUSR %08x, fault at %08x\n",
6392 env->mmu.mmusr, env->mmu.ar);
6393 #endif
6394 }
6395
6396 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
6397 target_ulong *data)
6398 {
6399 int cc_op = data[1];
6400 env->pc = data[0];
6401 if (cc_op != CC_OP_DYNAMIC) {
6402 env->cc_op = cc_op;
6403 }
6404 }
AR7 emulation for QEMU