hw/ppc/spapr_pci_vfio.c

   1 /*
   2  * QEMU sPAPR PCI host for VFIO
   3  *
   4  * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License,
   9  *  or (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include <linux/vfio.h>
  22 #include "hw/ppc/spapr.h"
  23 #include "hw/pci-host/spapr.h"
  24 #include "hw/pci/msix.h"
  25 #include "hw/pci/pci_device.h"
  26 #include "hw/vfio/vfio.h"
  27 #include "qemu/error-report.h"
  28
  29 bool spapr_phb_eeh_available(SpaprPhbState *sphb)
  30 {
  31     return vfio_eeh_as_ok(&sphb->iommu_as);
  32 }
  33
  34 static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb)
  35 {
  36     vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE);
  37 }
  38
  39 void spapr_phb_vfio_reset(DeviceState *qdev)
  40 {
  41     /*
  42      * The PE might be in frozen state. To reenable the EEH
  43      * functionality on it will clean the frozen state, which
  44      * ensures that the contained PCI devices will work properly
  45      * after reboot.
  46      */
  47     spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev));
  48 }
  49
  50 static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev,
  51                                       void *opaque)
  52 {
  53     bool *found = opaque;
  54
  55     if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
  56         *found = true;
  57     }
  58 }
  59
  60 int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
  61                                   unsigned int addr, int option)
  62 {
  63     uint32_t op;
  64     int ret;
  65
  66     switch (option) {
  67     case RTAS_EEH_DISABLE:
  68         op = VFIO_EEH_PE_DISABLE;
  69         break;
  70     case RTAS_EEH_ENABLE: {
  71         PCIHostState *phb;
  72         bool found = false;
  73
  74         /*
  75          * The EEH functionality is enabled per sphb level instead of
  76          * per PCI device. We have already identified this specific sphb
  77          * based on buid passed as argument to ibm,set-eeh-option rtas
  78          * call. Now we just need to check the validity of the PCI
  79          * pass-through devices (vfio-pci) under this sphb bus.
  80          * We have already validated that all the devices under this sphb
  81          * are from same iommu group (within same PE) before coming here.
  82          *
  83          * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
  84          * Rework device EEH PE determination") kernel would call
  85          * eeh-set-option for each device in the PE using the device's
  86          * config_address as the argument rather than the PE address.
  87          * Hence if we check validity of supplied config_addr whether
  88          * it matches to this PHB will cause issues with older kernel
  89          * versions v5.9 and older. If we return an error from
  90          * eeh-set-option when the argument isn't a valid PE address
  91          * then older kernels (v5.9 and older) will interpret that as
  92          * EEH not being supported.
  93          */
  94         phb = PCI_HOST_BRIDGE(sphb);
  95         pci_for_each_device(phb->bus, (addr >> 16) & 0xFF,
  96                             spapr_eeh_pci_find_device, &found);
  97
  98         if (!found) {
  99             return RTAS_OUT_PARAM_ERROR;
 100         }
 101
 102         op = VFIO_EEH_PE_ENABLE;
 103         break;
 104     }
 105     case RTAS_EEH_THAW_IO:
 106         op = VFIO_EEH_PE_UNFREEZE_IO;
 107         break;
 108     case RTAS_EEH_THAW_DMA:
 109         op = VFIO_EEH_PE_UNFREEZE_DMA;
 110         break;
 111     default:
 112         return RTAS_OUT_PARAM_ERROR;
 113     }
 114
 115     ret = vfio_eeh_as_op(&sphb->iommu_as, op);
 116     if (ret < 0) {
 117         return RTAS_OUT_HW_ERROR;
 118     }
 119
 120     return RTAS_OUT_SUCCESS;
 121 }
 122
 123 int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
 124 {
 125     int ret;
 126
 127     ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE);
 128     if (ret < 0) {
 129         return RTAS_OUT_PARAM_ERROR;
 130     }
 131
 132     *state = ret;
 133     return RTAS_OUT_SUCCESS;
 134 }
 135
 136 static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
 137                                               PCIDevice *pdev,
 138                                               void *opaque)
 139 {
 140     /* Check if the device is VFIO PCI device */
 141     if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
 142         return;
 143     }
 144
 145     /*
 146      * The MSIx table will be cleaned out by reset. We need
 147      * disable it so that it can be reenabled properly. Also,
 148      * the cached MSIx table should be cleared as it's not
 149      * reflecting the contents in hardware.
 150      */
 151     if (msix_enabled(pdev)) {
 152         uint16_t flags;
 153
 154         flags = pci_host_config_read_common(pdev,
 155                                             pdev->msix_cap + PCI_MSIX_FLAGS,
 156                                             pci_config_size(pdev), 2);
 157         flags &= ~PCI_MSIX_FLAGS_ENABLE;
 158         pci_host_config_write_common(pdev,
 159                                      pdev->msix_cap + PCI_MSIX_FLAGS,
 160                                      pci_config_size(pdev), flags, 2);
 161     }
 162
 163     msix_reset(pdev);
 164 }
 165
 166 static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
 167 {
 168        pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msix,
 169                                      NULL);
 170 }
 171
 172 static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb)
 173 {
 174        PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
 175
 176        pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
 177 }
 178
 179 int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
 180 {
 181     uint32_t op;
 182     int ret;
 183
 184     switch (option) {
 185     case RTAS_SLOT_RESET_DEACTIVATE:
 186         op = VFIO_EEH_PE_RESET_DEACTIVATE;
 187         break;
 188     case RTAS_SLOT_RESET_HOT:
 189         spapr_phb_vfio_eeh_pre_reset(sphb);
 190         op = VFIO_EEH_PE_RESET_HOT;
 191         break;
 192     case RTAS_SLOT_RESET_FUNDAMENTAL:
 193         spapr_phb_vfio_eeh_pre_reset(sphb);
 194         op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
 195         break;
 196     default:
 197         return RTAS_OUT_PARAM_ERROR;
 198     }
 199
 200     ret = vfio_eeh_as_op(&sphb->iommu_as, op);
 201     if (ret < 0) {
 202         return RTAS_OUT_HW_ERROR;
 203     }
 204
 205     return RTAS_OUT_SUCCESS;
 206 }
 207
 208 int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
 209 {
 210     int ret;
 211
 212     ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE);
 213     if (ret < 0) {
 214         return RTAS_OUT_PARAM_ERROR;
 215     }
 216
 217     return RTAS_OUT_SUCCESS;
 218 }