target/mips/cpu.h

   1 #ifndef MIPS_CPU_H
   2 #define MIPS_CPU_H
   3
   4 #include "cpu-qom.h"
   5 #include "exec/cpu-defs.h"
   6 #include "fpu/softfloat-types.h"
   7 #include "hw/clock.h"
   8 #include "mips-defs.h"
   9
  10 #define TCG_GUEST_DEFAULT_MO (0)
  11
  12 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  13
  14 /* MSA Context */
  15 #define MSA_WRLEN (128)
  16
  17 typedef union wr_t wr_t;
  18 union wr_t {
  19     int8_t  b[MSA_WRLEN / 8];
  20     int16_t h[MSA_WRLEN / 16];
  21     int32_t w[MSA_WRLEN / 32];
  22     int64_t d[MSA_WRLEN / 64];
  23 };
  24
  25 typedef union fpr_t fpr_t;
  26 union fpr_t {
  27     float64  fd;   /* ieee double precision */
  28     float32  fs[2];/* ieee single precision */
  29     uint64_t d;    /* binary double fixed-point */
  30     uint32_t w[2]; /* binary single fixed-point */
  31 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  32     wr_t     wr;   /* vector data */
  33 };
  34 /*
  35  *define FP_ENDIAN_IDX to access the same location
  36  * in the fpr_t union regardless of the host endianness
  37  */
  38 #if defined(HOST_WORDS_BIGENDIAN)
  39 #  define FP_ENDIAN_IDX 1
  40 #else
  41 #  define FP_ENDIAN_IDX 0
  42 #endif
  43
  44 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  45 struct CPUMIPSFPUContext {
  46     /* Floating point registers */
  47     fpr_t fpr[32];
  48     float_status fp_status;
  49     /* fpu implementation/revision register (fir) */
  50     uint32_t fcr0;
  51 #define FCR0_FREP 29
  52 #define FCR0_UFRP 28
  53 #define FCR0_HAS2008 23
  54 #define FCR0_F64 22
  55 #define FCR0_L 21
  56 #define FCR0_W 20
  57 #define FCR0_3D 19
  58 #define FCR0_PS 18
  59 #define FCR0_D 17
  60 #define FCR0_S 16
  61 #define FCR0_PRID 8
  62 #define FCR0_REV 0
  63     /* fcsr */
  64     uint32_t fcr31_rw_bitmask;
  65     uint32_t fcr31;
  66 #define FCR31_FS 24
  67 #define FCR31_ABS2008 19
  68 #define FCR31_NAN2008 18
  69 #define SET_FP_COND(num, env)     do { ((env).fcr31) |=                 \
  70                                        ((num) ? (1 << ((num) + 24)) :   \
  71                                                 (1 << 23));             \
  72                                      } while (0)
  73 #define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &=                 \
  74                                        ~((num) ? (1 << ((num) + 24)) :  \
  75                                                  (1 << 23));            \
  76                                      } while (0)
  77 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) |        \
  78                                  (((env).fcr31 >> 23) & 0x1))
  79 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  80 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  81 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  82 #define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | \
  83                                                ((v & 0x3f) << 12);       \
  84                                      } while (0)
  85 #define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | \
  86                                                ((v & 0x1f) << 7);        \
  87                                      } while (0)
  88 #define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | \
  89                                                ((v & 0x1f) << 2);        \
  90                                      } while (0)
  91 #define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
  92 #define FP_INEXACT        1
  93 #define FP_UNDERFLOW      2
  94 #define FP_OVERFLOW       4
  95 #define FP_DIV0           8
  96 #define FP_INVALID        16
  97 #define FP_UNIMPLEMENTED  32
  98 };
  99
 100 #define TARGET_INSN_START_EXTRA_WORDS 2
 101
 102 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 103 struct CPUMIPSMVPContext {
 104     int32_t CP0_MVPControl;
 105 #define CP0MVPCo_CPA    3
 106 #define CP0MVPCo_STLB   2
 107 #define CP0MVPCo_VPC    1
 108 #define CP0MVPCo_EVP    0
 109     int32_t CP0_MVPConf0;
 110 #define CP0MVPC0_M      31
 111 #define CP0MVPC0_TLBS   29
 112 #define CP0MVPC0_GS     28
 113 #define CP0MVPC0_PCP    27
 114 #define CP0MVPC0_PTLBE  16
 115 #define CP0MVPC0_TCA    15
 116 #define CP0MVPC0_PVPE   10
 117 #define CP0MVPC0_PTC    0
 118     int32_t CP0_MVPConf1;
 119 #define CP0MVPC1_CIM    31
 120 #define CP0MVPC1_CIF    30
 121 #define CP0MVPC1_PCX    20
 122 #define CP0MVPC1_PCP2   10
 123 #define CP0MVPC1_PCP1   0
 124 };
 125
 126 typedef struct mips_def_t mips_def_t;
 127
 128 #define MIPS_SHADOW_SET_MAX 16
 129 #define MIPS_TC_MAX 5
 130 #define MIPS_FPU_MAX 1
 131 #define MIPS_DSP_ACC 4
 132 #define MIPS_KSCRATCH_NUM 6
 133 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 134
 135
 136 /*
 137  *     Summary of CP0 registers
 138  *     ========================
 139  *
 140  *
 141  *     Register 0        Register 1        Register 2        Register 3
 142  *     ----------        ----------        ----------        ----------
 143  *
 144  * 0   Index             Random            EntryLo0          EntryLo1
 145  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
 146  * 2   MVPConf0          VPEConf0          TCBind
 147  * 3   MVPConf1          VPEConf1          TCRestart
 148  * 4   VPControl         YQMask            TCHalt
 149  * 5                     VPESchedule       TCContext
 150  * 6                     VPEScheFBack      TCSchedule
 151  * 7                     VPEOpt            TCScheFBack       TCOpt
 152  *
 153  *
 154  *     Register 4        Register 5        Register 6        Register 7
 155  *     ----------        ----------        ----------        ----------
 156  *
 157  * 0   Context           PageMask          Wired             HWREna
 158  * 1   ContextConfig     PageGrain         SRSConf0
 159  * 2   UserLocal         SegCtl0           SRSConf1
 160  * 3   XContextConfig    SegCtl1           SRSConf2
 161  * 4   DebugContextID    SegCtl2           SRSConf3
 162  * 5   MemoryMapID       PWBase            SRSConf4
 163  * 6                     PWField           PWCtl
 164  * 7                     PWSize
 165  *
 166  *
 167  *     Register 8        Register 9        Register 10       Register 11
 168  *     ----------        ----------        -----------       -----------
 169  *
 170  * 0   BadVAddr          Count             EntryHi           Compare
 171  * 1   BadInstr
 172  * 2   BadInstrP
 173  * 3   BadInstrX
 174  * 4                                       GuestCtl1         GuestCtl0Ext
 175  * 5                                       GuestCtl2
 176  * 6                     SAARI             GuestCtl3
 177  * 7                     SAAR
 178  *
 179  *
 180  *     Register 12       Register 13       Register 14       Register 15
 181  *     -----------       -----------       -----------       -----------
 182  *
 183  * 0   Status            Cause             EPC               PRId
 184  * 1   IntCtl                                                EBase
 185  * 2   SRSCtl                              NestedEPC         CDMMBase
 186  * 3   SRSMap                                                CMGCRBase
 187  * 4   View_IPL          View_RIPL                           BEVVA
 188  * 5   SRSMap2           NestedExc
 189  * 6   GuestCtl0
 190  * 7   GTOffset
 191  *
 192  *
 193  *     Register 16       Register 17       Register 18       Register 19
 194  *     -----------       -----------       -----------       -----------
 195  *
 196  * 0   Config            LLAddr            WatchLo0          WatchHi
 197  * 1   Config1           MAAR              WatchLo1          WatchHi
 198  * 2   Config2           MAARI             WatchLo2          WatchHi
 199  * 3   Config3                             WatchLo3          WatchHi
 200  * 4   Config4                             WatchLo4          WatchHi
 201  * 5   Config5                             WatchLo5          WatchHi
 202  * 6   Config6                             WatchLo6          WatchHi
 203  * 7   Config7                             WatchLo7          WatchHi
 204  *
 205  *
 206  *     Register 20       Register 21       Register 22       Register 23
 207  *     -----------       -----------       -----------       -----------
 208  *
 209  * 0   XContext                                              Debug
 210  * 1                                                         TraceControl
 211  * 2                                                         TraceControl2
 212  * 3                                                         UserTraceData1
 213  * 4                                                         TraceIBPC
 214  * 5                                                         TraceDBPC
 215  * 6                                                         Debug2
 216  * 7
 217  *
 218  *
 219  *     Register 24       Register 25       Register 26       Register 27
 220  *     -----------       -----------       -----------       -----------
 221  *
 222  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
 223  * 1                     PerfCnt
 224  * 2   TraceControl3     PerfCnt
 225  * 3   UserTraceData2    PerfCnt
 226  * 4                     PerfCnt
 227  * 5                     PerfCnt
 228  * 6                     PerfCnt
 229  * 7                     PerfCnt
 230  *
 231  *
 232  *     Register 28       Register 29       Register 30       Register 31
 233  *     -----------       -----------       -----------       -----------
 234  *
 235  * 0   DataLo            DataHi            ErrorEPC          DESAVE
 236  * 1   TagLo             TagHi
 237  * 2   DataLo1           DataHi1                             KScratch<n>
 238  * 3   TagLo1            TagHi1                              KScratch<n>
 239  * 4   DataLo2           DataHi2                             KScratch<n>
 240  * 5   TagLo2            TagHi2                              KScratch<n>
 241  * 6   DataLo3           DataHi3                             KScratch<n>
 242  * 7   TagLo3            TagHi3                              KScratch<n>
 243  *
 244  */
 245 #define CP0_REGISTER_00     0
 246 #define CP0_REGISTER_01     1
 247 #define CP0_REGISTER_02     2
 248 #define CP0_REGISTER_03     3
 249 #define CP0_REGISTER_04     4
 250 #define CP0_REGISTER_05     5
 251 #define CP0_REGISTER_06     6
 252 #define CP0_REGISTER_07     7
 253 #define CP0_REGISTER_08     8
 254 #define CP0_REGISTER_09     9
 255 #define CP0_REGISTER_10    10
 256 #define CP0_REGISTER_11    11
 257 #define CP0_REGISTER_12    12
 258 #define CP0_REGISTER_13    13
 259 #define CP0_REGISTER_14    14
 260 #define CP0_REGISTER_15    15
 261 #define CP0_REGISTER_16    16
 262 #define CP0_REGISTER_17    17
 263 #define CP0_REGISTER_18    18
 264 #define CP0_REGISTER_19    19
 265 #define CP0_REGISTER_20    20
 266 #define CP0_REGISTER_21    21
 267 #define CP0_REGISTER_22    22
 268 #define CP0_REGISTER_23    23
 269 #define CP0_REGISTER_24    24
 270 #define CP0_REGISTER_25    25
 271 #define CP0_REGISTER_26    26
 272 #define CP0_REGISTER_27    27
 273 #define CP0_REGISTER_28    28
 274 #define CP0_REGISTER_29    29
 275 #define CP0_REGISTER_30    30
 276 #define CP0_REGISTER_31    31
 277
 278
 279 /* CP0 Register 00 */
 280 #define CP0_REG00__INDEX           0
 281 #define CP0_REG00__MVPCONTROL      1
 282 #define CP0_REG00__MVPCONF0        2
 283 #define CP0_REG00__MVPCONF1        3
 284 #define CP0_REG00__VPCONTROL       4
 285 /* CP0 Register 01 */
 286 #define CP0_REG01__RANDOM          0
 287 #define CP0_REG01__VPECONTROL      1
 288 #define CP0_REG01__VPECONF0        2
 289 #define CP0_REG01__VPECONF1        3
 290 #define CP0_REG01__YQMASK          4
 291 #define CP0_REG01__VPESCHEDULE     5
 292 #define CP0_REG01__VPESCHEFBACK    6
 293 #define CP0_REG01__VPEOPT          7
 294 /* CP0 Register 02 */
 295 #define CP0_REG02__ENTRYLO0        0
 296 #define CP0_REG02__TCSTATUS        1
 297 #define CP0_REG02__TCBIND          2
 298 #define CP0_REG02__TCRESTART       3
 299 #define CP0_REG02__TCHALT          4
 300 #define CP0_REG02__TCCONTEXT       5
 301 #define CP0_REG02__TCSCHEDULE      6
 302 #define CP0_REG02__TCSCHEFBACK     7
 303 /* CP0 Register 03 */
 304 #define CP0_REG03__ENTRYLO1        0
 305 #define CP0_REG03__GLOBALNUM       1
 306 #define CP0_REG03__TCOPT           7
 307 /* CP0 Register 04 */
 308 #define CP0_REG04__CONTEXT         0
 309 #define CP0_REG04__CONTEXTCONFIG   1
 310 #define CP0_REG04__USERLOCAL       2
 311 #define CP0_REG04__XCONTEXTCONFIG  3
 312 #define CP0_REG04__DBGCONTEXTID    4
 313 #define CP0_REG04__MMID            5
 314 /* CP0 Register 05 */
 315 #define CP0_REG05__PAGEMASK        0
 316 #define CP0_REG05__PAGEGRAIN       1
 317 #define CP0_REG05__SEGCTL0         2
 318 #define CP0_REG05__SEGCTL1         3
 319 #define CP0_REG05__SEGCTL2         4
 320 #define CP0_REG05__PWBASE          5
 321 #define CP0_REG05__PWFIELD         6
 322 #define CP0_REG05__PWSIZE          7
 323 /* CP0 Register 06 */
 324 #define CP0_REG06__WIRED           0
 325 #define CP0_REG06__SRSCONF0        1
 326 #define CP0_REG06__SRSCONF1        2
 327 #define CP0_REG06__SRSCONF2        3
 328 #define CP0_REG06__SRSCONF3        4
 329 #define CP0_REG06__SRSCONF4        5
 330 #define CP0_REG06__PWCTL           6
 331 /* CP0 Register 07 */
 332 #define CP0_REG07__HWRENA          0
 333 /* CP0 Register 08 */
 334 #define CP0_REG08__BADVADDR        0
 335 #define CP0_REG08__BADINSTR        1
 336 #define CP0_REG08__BADINSTRP       2
 337 #define CP0_REG08__BADINSTRX       3
 338 /* CP0 Register 09 */
 339 #define CP0_REG09__COUNT           0
 340 #define CP0_REG09__SAARI           6
 341 #define CP0_REG09__SAAR            7
 342 /* CP0 Register 10 */
 343 #define CP0_REG10__ENTRYHI         0
 344 #define CP0_REG10__GUESTCTL1       4
 345 #define CP0_REG10__GUESTCTL2       5
 346 #define CP0_REG10__GUESTCTL3       6
 347 /* CP0 Register 11 */
 348 #define CP0_REG11__COMPARE         0
 349 #define CP0_REG11__GUESTCTL0EXT    4
 350 /* CP0 Register 12 */
 351 #define CP0_REG12__STATUS          0
 352 #define CP0_REG12__INTCTL          1
 353 #define CP0_REG12__SRSCTL          2
 354 #define CP0_REG12__SRSMAP          3
 355 #define CP0_REG12__VIEW_IPL        4
 356 #define CP0_REG12__SRSMAP2         5
 357 #define CP0_REG12__GUESTCTL0       6
 358 #define CP0_REG12__GTOFFSET        7
 359 /* CP0 Register 13 */
 360 #define CP0_REG13__CAUSE           0
 361 #define CP0_REG13__VIEW_RIPL       4
 362 #define CP0_REG13__NESTEDEXC       5
 363 /* CP0 Register 14 */
 364 #define CP0_REG14__EPC             0
 365 #define CP0_REG14__NESTEDEPC       2
 366 /* CP0 Register 15 */
 367 #define CP0_REG15__PRID            0
 368 #define CP0_REG15__EBASE           1
 369 #define CP0_REG15__CDMMBASE        2
 370 #define CP0_REG15__CMGCRBASE       3
 371 #define CP0_REG15__BEVVA           4
 372 /* CP0 Register 16 */
 373 #define CP0_REG16__CONFIG          0
 374 #define CP0_REG16__CONFIG1         1
 375 #define CP0_REG16__CONFIG2         2
 376 #define CP0_REG16__CONFIG3         3
 377 #define CP0_REG16__CONFIG4         4
 378 #define CP0_REG16__CONFIG5         5
 379 #define CP0_REG16__CONFIG6         6
 380 #define CP0_REG16__CONFIG7         7
 381 /* CP0 Register 17 */
 382 #define CP0_REG17__LLADDR          0
 383 #define CP0_REG17__MAAR            1
 384 #define CP0_REG17__MAARI           2
 385 /* CP0 Register 18 */
 386 #define CP0_REG18__WATCHLO0        0
 387 #define CP0_REG18__WATCHLO1        1
 388 #define CP0_REG18__WATCHLO2        2
 389 #define CP0_REG18__WATCHLO3        3
 390 #define CP0_REG18__WATCHLO4        4
 391 #define CP0_REG18__WATCHLO5        5
 392 #define CP0_REG18__WATCHLO6        6
 393 #define CP0_REG18__WATCHLO7        7
 394 /* CP0 Register 19 */
 395 #define CP0_REG19__WATCHHI0        0
 396 #define CP0_REG19__WATCHHI1        1
 397 #define CP0_REG19__WATCHHI2        2
 398 #define CP0_REG19__WATCHHI3        3
 399 #define CP0_REG19__WATCHHI4        4
 400 #define CP0_REG19__WATCHHI5        5
 401 #define CP0_REG19__WATCHHI6        6
 402 #define CP0_REG19__WATCHHI7        7
 403 /* CP0 Register 20 */
 404 #define CP0_REG20__XCONTEXT        0
 405 /* CP0 Register 21 */
 406 /* CP0 Register 22 */
 407 /* CP0 Register 23 */
 408 #define CP0_REG23__DEBUG           0
 409 #define CP0_REG23__TRACECONTROL    1
 410 #define CP0_REG23__TRACECONTROL2   2
 411 #define CP0_REG23__USERTRACEDATA1  3
 412 #define CP0_REG23__TRACEIBPC       4
 413 #define CP0_REG23__TRACEDBPC       5
 414 #define CP0_REG23__DEBUG2          6
 415 /* CP0 Register 24 */
 416 #define CP0_REG24__DEPC            0
 417 /* CP0 Register 25 */
 418 #define CP0_REG25__PERFCTL0        0
 419 #define CP0_REG25__PERFCNT0        1
 420 #define CP0_REG25__PERFCTL1        2
 421 #define CP0_REG25__PERFCNT1        3
 422 #define CP0_REG25__PERFCTL2        4
 423 #define CP0_REG25__PERFCNT2        5
 424 #define CP0_REG25__PERFCTL3        6
 425 #define CP0_REG25__PERFCNT3        7
 426 /* CP0 Register 26 */
 427 #define CP0_REG26__ERRCTL          0
 428 /* CP0 Register 27 */
 429 #define CP0_REG27__CACHERR         0
 430 /* CP0 Register 28 */
 431 #define CP0_REG28__TAGLO           0
 432 #define CP0_REG28__DATALO          1
 433 #define CP0_REG28__TAGLO1          2
 434 #define CP0_REG28__DATALO1         3
 435 #define CP0_REG28__TAGLO2          4
 436 #define CP0_REG28__DATALO2         5
 437 #define CP0_REG28__TAGLO3          6
 438 #define CP0_REG28__DATALO3         7
 439 /* CP0 Register 29 */
 440 #define CP0_REG29__TAGHI           0
 441 #define CP0_REG29__DATAHI          1
 442 #define CP0_REG29__TAGHI1          2
 443 #define CP0_REG29__DATAHI1         3
 444 #define CP0_REG29__TAGHI2          4
 445 #define CP0_REG29__DATAHI2         5
 446 #define CP0_REG29__TAGHI3          6
 447 #define CP0_REG29__DATAHI3         7
 448 /* CP0 Register 30 */
 449 #define CP0_REG30__ERROREPC        0
 450 /* CP0 Register 31 */
 451 #define CP0_REG31__DESAVE          0
 452 #define CP0_REG31__KSCRATCH1       2
 453 #define CP0_REG31__KSCRATCH2       3
 454 #define CP0_REG31__KSCRATCH3       4
 455 #define CP0_REG31__KSCRATCH4       5
 456 #define CP0_REG31__KSCRATCH5       6
 457 #define CP0_REG31__KSCRATCH6       7
 458
 459
 460 typedef struct TCState TCState;
 461 struct TCState {
 462     target_ulong gpr[32];
 463 #if defined(TARGET_MIPS64)
 464     /*
 465      * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
 466      * and the upper halves in gpr_hi[].
 467      */
 468     uint64_t gpr_hi[32];
 469 #endif /* TARGET_MIPS64 */
 470     target_ulong PC;
 471     target_ulong HI[MIPS_DSP_ACC];
 472     target_ulong LO[MIPS_DSP_ACC];
 473     target_ulong ACX[MIPS_DSP_ACC];
 474     target_ulong DSPControl;
 475     int32_t CP0_TCStatus;
 476 #define CP0TCSt_TCU3    31
 477 #define CP0TCSt_TCU2    30
 478 #define CP0TCSt_TCU1    29
 479 #define CP0TCSt_TCU0    28
 480 #define CP0TCSt_TMX     27
 481 #define CP0TCSt_RNST    23
 482 #define CP0TCSt_TDS     21
 483 #define CP0TCSt_DT      20
 484 #define CP0TCSt_DA      15
 485 #define CP0TCSt_A       13
 486 #define CP0TCSt_TKSU    11
 487 #define CP0TCSt_IXMT    10
 488 #define CP0TCSt_TASID   0
 489     int32_t CP0_TCBind;
 490 #define CP0TCBd_CurTC   21
 491 #define CP0TCBd_TBE     17
 492 #define CP0TCBd_CurVPE  0
 493     target_ulong CP0_TCHalt;
 494     target_ulong CP0_TCContext;
 495     target_ulong CP0_TCSchedule;
 496     target_ulong CP0_TCScheFBack;
 497     int32_t CP0_Debug_tcstatus;
 498     target_ulong CP0_UserLocal;
 499
 500     int32_t msacsr;
 501
 502 #define MSACSR_FS       24
 503 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 504 #define MSACSR_NX       18
 505 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 506 #define MSACSR_CEF      2
 507 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 508 #define MSACSR_RM       0
 509 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 510 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 511         MSACSR_FS_MASK)
 512
 513     float_status msa_fp_status;
 514
 515 #define NUMBER_OF_MXU_REGISTERS 16
 516     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 517     target_ulong mxu_cr;
 518 #define MXU_CR_LC       31
 519 #define MXU_CR_RC       30
 520 #define MXU_CR_BIAS     2
 521 #define MXU_CR_RD_EN    1
 522 #define MXU_CR_MXU_EN   0
 523
 524 };
 525
 526 struct MIPSITUState;
 527 typedef struct CPUMIPSState CPUMIPSState;
 528 struct CPUMIPSState {
 529     TCState active_tc;
 530     CPUMIPSFPUContext active_fpu;
 531
 532     uint32_t current_tc;
 533     uint32_t current_fpu;
 534
 535     uint32_t SEGBITS;
 536     uint32_t PABITS;
 537 #if defined(TARGET_MIPS64)
 538 # define PABITS_BASE 36
 539 #else
 540 # define PABITS_BASE 32
 541 #endif
 542     target_ulong SEGMask;
 543     uint64_t PAMask;
 544 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 545
 546     int32_t msair;
 547 #define MSAIR_ProcID    8
 548 #define MSAIR_Rev       0
 549
 550 /*
 551  * CP0 Register 0
 552  */
 553     int32_t CP0_Index;
 554     /* CP0_MVP* are per MVP registers. */
 555     int32_t CP0_VPControl;
 556 #define CP0VPCtl_DIS    0
 557 /*
 558  * CP0 Register 1
 559  */
 560     int32_t CP0_Random;
 561     int32_t CP0_VPEControl;
 562 #define CP0VPECo_YSI    21
 563 #define CP0VPECo_GSI    20
 564 #define CP0VPECo_EXCPT  16
 565 #define CP0VPECo_TE     15
 566 #define CP0VPECo_TargTC 0
 567     int32_t CP0_VPEConf0;
 568 #define CP0VPEC0_M      31
 569 #define CP0VPEC0_XTC    21
 570 #define CP0VPEC0_TCS    19
 571 #define CP0VPEC0_SCS    18
 572 #define CP0VPEC0_DSC    17
 573 #define CP0VPEC0_ICS    16
 574 #define CP0VPEC0_MVP    1
 575 #define CP0VPEC0_VPA    0
 576     int32_t CP0_VPEConf1;
 577 #define CP0VPEC1_NCX    20
 578 #define CP0VPEC1_NCP2   10
 579 #define CP0VPEC1_NCP1   0
 580     target_ulong CP0_YQMask;
 581     target_ulong CP0_VPESchedule;
 582     target_ulong CP0_VPEScheFBack;
 583     int32_t CP0_VPEOpt;
 584 #define CP0VPEOpt_IWX7  15
 585 #define CP0VPEOpt_IWX6  14
 586 #define CP0VPEOpt_IWX5  13
 587 #define CP0VPEOpt_IWX4  12
 588 #define CP0VPEOpt_IWX3  11
 589 #define CP0VPEOpt_IWX2  10
 590 #define CP0VPEOpt_IWX1  9
 591 #define CP0VPEOpt_IWX0  8
 592 #define CP0VPEOpt_DWX7  7
 593 #define CP0VPEOpt_DWX6  6
 594 #define CP0VPEOpt_DWX5  5
 595 #define CP0VPEOpt_DWX4  4
 596 #define CP0VPEOpt_DWX3  3
 597 #define CP0VPEOpt_DWX2  2
 598 #define CP0VPEOpt_DWX1  1
 599 #define CP0VPEOpt_DWX0  0
 600 /*
 601  * CP0 Register 2
 602  */
 603     uint64_t CP0_EntryLo0;
 604 /*
 605  * CP0 Register 3
 606  */
 607     uint64_t CP0_EntryLo1;
 608 #if defined(TARGET_MIPS64)
 609 # define CP0EnLo_RI 63
 610 # define CP0EnLo_XI 62
 611 #else
 612 # define CP0EnLo_RI 31
 613 # define CP0EnLo_XI 30
 614 #endif
 615     int32_t CP0_GlobalNumber;
 616 #define CP0GN_VPId 0
 617 /*
 618  * CP0 Register 4
 619  */
 620     target_ulong CP0_Context;
 621     int32_t CP0_MemoryMapID;
 622 /*
 623  * CP0 Register 5
 624  */
 625     int32_t CP0_PageMask;
 626 #define CP0PM_MASK 13
 627     int32_t CP0_PageGrain_rw_bitmask;
 628     int32_t CP0_PageGrain;
 629 #define CP0PG_RIE 31
 630 #define CP0PG_XIE 30
 631 #define CP0PG_ELPA 29
 632 #define CP0PG_IEC 27
 633     target_ulong CP0_SegCtl0;
 634     target_ulong CP0_SegCtl1;
 635     target_ulong CP0_SegCtl2;
 636 #define CP0SC_PA        9
 637 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
 638 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
 639 #define CP0SC_AM        4
 640 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
 641 #define CP0SC_AM_UK     0ULL
 642 #define CP0SC_AM_MK     1ULL
 643 #define CP0SC_AM_MSK    2ULL
 644 #define CP0SC_AM_MUSK   3ULL
 645 #define CP0SC_AM_MUSUK  4ULL
 646 #define CP0SC_AM_USK    5ULL
 647 #define CP0SC_AM_UUSK   7ULL
 648 #define CP0SC_EU        3
 649 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
 650 #define CP0SC_C         0
 651 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
 652 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 653                          CP0SC_PA_MASK)
 654 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 655                          CP0SC_PA_1GMASK)
 656 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
 657 #define CP0SC1_XAM      59
 658 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
 659 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
 660 #define CP0SC2_XR       56
 661 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
 662 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
 663     target_ulong CP0_PWBase;
 664     target_ulong CP0_PWField;
 665 #if defined(TARGET_MIPS64)
 666 #define CP0PF_BDI  32    /* 37..32 */
 667 #define CP0PF_GDI  24    /* 29..24 */
 668 #define CP0PF_UDI  18    /* 23..18 */
 669 #define CP0PF_MDI  12    /* 17..12 */
 670 #define CP0PF_PTI  6     /* 11..6  */
 671 #define CP0PF_PTEI 0     /*  5..0  */
 672 #else
 673 #define CP0PF_GDW  24    /* 29..24 */
 674 #define CP0PF_UDW  18    /* 23..18 */
 675 #define CP0PF_MDW  12    /* 17..12 */
 676 #define CP0PF_PTW  6     /* 11..6  */
 677 #define CP0PF_PTEW 0     /*  5..0  */
 678 #endif
 679     target_ulong CP0_PWSize;
 680 #if defined(TARGET_MIPS64)
 681 #define CP0PS_BDW  32    /* 37..32 */
 682 #endif
 683 #define CP0PS_PS   30
 684 #define CP0PS_GDW  24    /* 29..24 */
 685 #define CP0PS_UDW  18    /* 23..18 */
 686 #define CP0PS_MDW  12    /* 17..12 */
 687 #define CP0PS_PTW  6     /* 11..6  */
 688 #define CP0PS_PTEW 0     /*  5..0  */
 689 /*
 690  * CP0 Register 6
 691  */
 692     int32_t CP0_Wired;
 693     int32_t CP0_PWCtl;
 694 #define CP0PC_PWEN      31
 695 #if defined(TARGET_MIPS64)
 696 #define CP0PC_PWDIREXT  30
 697 #define CP0PC_XK        28
 698 #define CP0PC_XS        27
 699 #define CP0PC_XU        26
 700 #endif
 701 #define CP0PC_DPH       7
 702 #define CP0PC_HUGEPG    6
 703 #define CP0PC_PSN       0     /*  5..0  */
 704     int32_t CP0_SRSConf0_rw_bitmask;
 705     int32_t CP0_SRSConf0;
 706 #define CP0SRSC0_M      31
 707 #define CP0SRSC0_SRS3   20
 708 #define CP0SRSC0_SRS2   10
 709 #define CP0SRSC0_SRS1   0
 710     int32_t CP0_SRSConf1_rw_bitmask;
 711     int32_t CP0_SRSConf1;
 712 #define CP0SRSC1_M      31
 713 #define CP0SRSC1_SRS6   20
 714 #define CP0SRSC1_SRS5   10
 715 #define CP0SRSC1_SRS4   0
 716     int32_t CP0_SRSConf2_rw_bitmask;
 717     int32_t CP0_SRSConf2;
 718 #define CP0SRSC2_M      31
 719 #define CP0SRSC2_SRS9   20
 720 #define CP0SRSC2_SRS8   10
 721 #define CP0SRSC2_SRS7   0
 722     int32_t CP0_SRSConf3_rw_bitmask;
 723     int32_t CP0_SRSConf3;
 724 #define CP0SRSC3_M      31
 725 #define CP0SRSC3_SRS12  20
 726 #define CP0SRSC3_SRS11  10
 727 #define CP0SRSC3_SRS10  0
 728     int32_t CP0_SRSConf4_rw_bitmask;
 729     int32_t CP0_SRSConf4;
 730 #define CP0SRSC4_SRS15  20
 731 #define CP0SRSC4_SRS14  10
 732 #define CP0SRSC4_SRS13  0
 733 /*
 734  * CP0 Register 7
 735  */
 736     int32_t CP0_HWREna;
 737 /*
 738  * CP0 Register 8
 739  */
 740     target_ulong CP0_BadVAddr;
 741     uint32_t CP0_BadInstr;
 742     uint32_t CP0_BadInstrP;
 743     uint32_t CP0_BadInstrX;
 744 /*
 745  * CP0 Register 9
 746  */
 747     int32_t CP0_Count;
 748     uint32_t CP0_SAARI;
 749 #define CP0SAARI_TARGET 0    /*  5..0  */
 750     uint64_t CP0_SAAR[2];
 751 #define CP0SAAR_BASE    12   /* 43..12 */
 752 #define CP0SAAR_SIZE    1    /*  5..1  */
 753 #define CP0SAAR_EN      0
 754 /*
 755  * CP0 Register 10
 756  */
 757     target_ulong CP0_EntryHi;
 758 #define CP0EnHi_EHINV 10
 759     target_ulong CP0_EntryHi_ASID_mask;
 760 /*
 761  * CP0 Register 11
 762  */
 763     int32_t CP0_Compare;
 764 /*
 765  * CP0 Register 12
 766  */
 767     int32_t CP0_Status;
 768 #define CP0St_CU3   31
 769 #define CP0St_CU2   30
 770 #define CP0St_CU1   29
 771 #define CP0St_CU0   28
 772 #define CP0St_RP    27
 773 #define CP0St_FR    26
 774 #define CP0St_RE    25
 775 #define CP0St_MX    24
 776 #define CP0St_PX    23
 777 #define CP0St_BEV   22
 778 #define CP0St_TS    21
 779 #define CP0St_SR    20
 780 #define CP0St_NMI   19
 781 #define CP0St_IM    8
 782 #define CP0St_KX    7
 783 #define CP0St_SX    6
 784 #define CP0St_UX    5
 785 #define CP0St_KSU   3
 786 #define CP0St_ERL   2
 787 #define CP0St_EXL   1
 788 #define CP0St_IE    0
 789     int32_t CP0_IntCtl;
 790 #define CP0IntCtl_IPTI 29
 791 #define CP0IntCtl_IPPCI 26
 792 #define CP0IntCtl_VS 5
 793     int32_t CP0_SRSCtl;
 794 #define CP0SRSCtl_HSS 26
 795 #define CP0SRSCtl_EICSS 18
 796 #define CP0SRSCtl_ESS 12
 797 #define CP0SRSCtl_PSS 6
 798 #define CP0SRSCtl_CSS 0
 799     int32_t CP0_SRSMap;
 800 #define CP0SRSMap_SSV7 28
 801 #define CP0SRSMap_SSV6 24
 802 #define CP0SRSMap_SSV5 20
 803 #define CP0SRSMap_SSV4 16
 804 #define CP0SRSMap_SSV3 12
 805 #define CP0SRSMap_SSV2 8
 806 #define CP0SRSMap_SSV1 4
 807 #define CP0SRSMap_SSV0 0
 808 /*
 809  * CP0 Register 13
 810  */
 811     int32_t CP0_Cause;
 812 #define CP0Ca_BD   31
 813 #define CP0Ca_TI   30
 814 #define CP0Ca_CE   28
 815 #define CP0Ca_DC   27
 816 #define CP0Ca_PCI  26
 817 #define CP0Ca_IV   23
 818 #define CP0Ca_WP   22
 819 #define CP0Ca_IP    8
 820 #define CP0Ca_IP_mask 0x0000FF00
 821 #define CP0Ca_EC    2
 822 /*
 823  * CP0 Register 14
 824  */
 825     target_ulong CP0_EPC;
 826 /*
 827  * CP0 Register 15
 828  */
 829     int32_t CP0_PRid;
 830     target_ulong CP0_EBase;
 831     target_ulong CP0_EBaseWG_rw_bitmask;
 832 #define CP0EBase_WG 11
 833     target_ulong CP0_CMGCRBase;
 834 /*
 835  * CP0 Register 16 (after Release 1)
 836  */
 837     int32_t CP0_Config0;
 838 #define CP0C0_M    31
 839 #define CP0C0_K23  28    /* 30..28 */
 840 #define CP0C0_KU   25    /* 27..25 */
 841 #define CP0C0_MDU  20
 842 #define CP0C0_MM   18
 843 #define CP0C0_BM   16
 844 #define CP0C0_Impl 16    /* 24..16 */
 845 #define CP0C0_BE   15
 846 #define CP0C0_AT   13    /* 14..13 */
 847 #define CP0C0_AR   10    /* 12..10 */
 848 #define CP0C0_MT   7     /*  9..7  */
 849 #define CP0C0_VI   3
 850 #define CP0C0_K0   0     /*  2..0  */
 851 #define CP0C0_AR_LENGTH 3
 852 /*
 853  * CP0 Register 16 (before Release 1)
 854  */
 855 #define CP0C0_Impl 16    /* 24..16 */
 856 #define CP0C0_IC   9     /* 11..9 */
 857 #define CP0C0_DC   6     /*  8..6 */
 858 #define CP0C0_IB   5
 859 #define CP0C0_DB   4
 860     int32_t CP0_Config1;
 861 #define CP0C1_M    31
 862 #define CP0C1_MMU  25    /* 30..25 */
 863 #define CP0C1_IS   22    /* 24..22 */
 864 #define CP0C1_IL   19    /* 21..19 */
 865 #define CP0C1_IA   16    /* 18..16 */
 866 #define CP0C1_DS   13    /* 15..13 */
 867 #define CP0C1_DL   10    /* 12..10 */
 868 #define CP0C1_DA   7     /*  9..7  */
 869 #define CP0C1_C2   6
 870 #define CP0C1_MD   5
 871 #define CP0C1_PC   4
 872 #define CP0C1_WR   3
 873 #define CP0C1_CA   2
 874 #define CP0C1_EP   1
 875 #define CP0C1_FP   0
 876     int32_t CP0_Config2;
 877 #define CP0C2_M    31
 878 #define CP0C2_TU   28    /* 30..28 */
 879 #define CP0C2_TS   24    /* 27..24 */
 880 #define CP0C2_TL   20    /* 23..20 */
 881 #define CP0C2_TA   16    /* 19..16 */
 882 #define CP0C2_SU   12    /* 15..12 */
 883 #define CP0C2_SS   8     /* 11..8  */
 884 #define CP0C2_SL   4     /*  7..4  */
 885 #define CP0C2_SA   0     /*  3..0  */
 886     int32_t CP0_Config3;
 887 #define CP0C3_M            31
 888 #define CP0C3_BPG          30
 889 #define CP0C3_CMGCR        29
 890 #define CP0C3_MSAP         28
 891 #define CP0C3_BP           27
 892 #define CP0C3_BI           26
 893 #define CP0C3_SC           25
 894 #define CP0C3_PW           24
 895 #define CP0C3_VZ           23
 896 #define CP0C3_IPLV         21    /* 22..21 */
 897 #define CP0C3_MMAR         18    /* 20..18 */
 898 #define CP0C3_MCU          17
 899 #define CP0C3_ISA_ON_EXC   16
 900 #define CP0C3_ISA          14    /* 15..14 */
 901 #define CP0C3_ULRI         13
 902 #define CP0C3_RXI          12
 903 #define CP0C3_DSP2P        11
 904 #define CP0C3_DSPP         10
 905 #define CP0C3_CTXTC        9
 906 #define CP0C3_ITL          8
 907 #define CP0C3_LPA          7
 908 #define CP0C3_VEIC         6
 909 #define CP0C3_VInt         5
 910 #define CP0C3_SP           4
 911 #define CP0C3_CDMM         3
 912 #define CP0C3_MT           2
 913 #define CP0C3_SM           1
 914 #define CP0C3_TL           0
 915     int32_t CP0_Config4;
 916     int32_t CP0_Config4_rw_bitmask;
 917 #define CP0C4_M            31
 918 #define CP0C4_IE           29    /* 30..29 */
 919 #define CP0C4_AE           28
 920 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
 921 #define CP0C4_KScrExist    16
 922 #define CP0C4_MMUExtDef    14
 923 #define CP0C4_FTLBPageSize 8     /* 12..8  */
 924 /* bit layout if MMUExtDef=1 */
 925 #define CP0C4_MMUSizeExt   0     /*  7..0  */
 926 /* bit layout if MMUExtDef=2 */
 927 #define CP0C4_FTLBWays     4     /*  7..4  */
 928 #define CP0C4_FTLBSets     0     /*  3..0  */
 929     int32_t CP0_Config5;
 930     int32_t CP0_Config5_rw_bitmask;
 931 #define CP0C5_M            31
 932 #define CP0C5_K            30
 933 #define CP0C5_CV           29
 934 #define CP0C5_EVA          28
 935 #define CP0C5_MSAEn        27
 936 #define CP0C5_PMJ          23    /* 25..23 */
 937 #define CP0C5_WR2          22
 938 #define CP0C5_NMS          21
 939 #define CP0C5_ULS          20
 940 #define CP0C5_XPA          19
 941 #define CP0C5_CRCP         18
 942 #define CP0C5_MI           17
 943 #define CP0C5_GI           15    /* 16..15 */
 944 #define CP0C5_CA2          14
 945 #define CP0C5_XNP          13
 946 #define CP0C5_DEC          11
 947 #define CP0C5_L2C          10
 948 #define CP0C5_UFE          9
 949 #define CP0C5_FRE          8
 950 #define CP0C5_VP           7
 951 #define CP0C5_SBRI         6
 952 #define CP0C5_MVH          5
 953 #define CP0C5_LLB          4
 954 #define CP0C5_MRP          3
 955 #define CP0C5_UFR          2
 956 #define CP0C5_NFExists     0
 957     int32_t CP0_Config6;
 958     int32_t CP0_Config6_rw_bitmask;
 959 #define CP0C6_BPPASS          31
 960 #define CP0C6_KPOS            24
 961 #define CP0C6_KE              23
 962 #define CP0C6_VTLBONLY        22
 963 #define CP0C6_LASX            21
 964 #define CP0C6_SSEN            20
 965 #define CP0C6_DISDRTIME       19
 966 #define CP0C6_PIXNUEN         18
 967 #define CP0C6_SCRAND          17
 968 #define CP0C6_LLEXCEN         16
 969 #define CP0C6_DISVC           15
 970 #define CP0C6_VCLRU           14
 971 #define CP0C6_DCLRU           13
 972 #define CP0C6_PIXUEN          12
 973 #define CP0C6_DISBLKLYEN      11
 974 #define CP0C6_UMEMUALEN       10
 975 #define CP0C6_SFBEN           8
 976 #define CP0C6_FLTINT          7
 977 #define CP0C6_VLTINT          6
 978 #define CP0C6_DISBTB          5
 979 #define CP0C6_STPREFCTL       2
 980 #define CP0C6_INSTPREF        1
 981 #define CP0C6_DATAPREF        0
 982     int32_t CP0_Config7;
 983     int64_t CP0_Config7_rw_bitmask;
 984 #define CP0C7_NAPCGEN       2
 985 #define CP0C7_UNIMUEN       1
 986 #define CP0C7_VFPUCGEN      0
 987     uint64_t CP0_LLAddr;
 988     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 989     int32_t CP0_MAARI;
 990     /* XXX: Maybe make LLAddr per-TC? */
 991 /*
 992  * CP0 Register 17
 993  */
 994     target_ulong lladdr; /* LL virtual address compared against SC */
 995     target_ulong llval;
 996     uint64_t llval_wp;
 997     uint32_t llnewval_wp;
 998     uint64_t CP0_LLAddr_rw_bitmask;
 999     int CP0_LLAddr_shift;
1000 /*
1001  * CP0 Register 18
1002  */
1003     target_ulong CP0_WatchLo[8];
1004 /*
1005  * CP0 Register 19
1006  */
1007     uint64_t CP0_WatchHi[8];
1008 #define CP0WH_ASID 16
1009 /*
1010  * CP0 Register 20
1011  */
1012     target_ulong CP0_XContext;
1013     int32_t CP0_Framemask;
1014 /*
1015  * CP0 Register 23
1016  */
1017     int32_t CP0_Debug;
1018 #define CP0DB_DBD  31
1019 #define CP0DB_DM   30
1020 #define CP0DB_LSNM 28
1021 #define CP0DB_Doze 27
1022 #define CP0DB_Halt 26
1023 #define CP0DB_CNT  25
1024 #define CP0DB_IBEP 24
1025 #define CP0DB_DBEP 21
1026 #define CP0DB_IEXI 20
1027 #define CP0DB_VER  15
1028 #define CP0DB_DEC  10
1029 #define CP0DB_SSt  8
1030 #define CP0DB_DINT 5
1031 #define CP0DB_DIB  4
1032 #define CP0DB_DDBS 3
1033 #define CP0DB_DDBL 2
1034 #define CP0DB_DBp  1
1035 #define CP0DB_DSS  0
1036 /*
1037  * CP0 Register 24
1038  */
1039     target_ulong CP0_DEPC;
1040 /*
1041  * CP0 Register 25
1042  */
1043     int32_t CP0_Performance0;
1044 /*
1045  * CP0 Register 26
1046  */
1047     int32_t CP0_ErrCtl;
1048 #define CP0EC_WST 29
1049 #define CP0EC_SPR 28
1050 #define CP0EC_ITC 26
1051 /*
1052  * CP0 Register 28
1053  */
1054     uint64_t CP0_TagLo;
1055     int32_t CP0_DataLo;
1056 /*
1057  * CP0 Register 29
1058  */
1059     int32_t CP0_TagHi;
1060     int32_t CP0_DataHi;
1061 /*
1062  * CP0 Register 30
1063  */
1064     target_ulong CP0_ErrorEPC;
1065 /*
1066  * CP0 Register 31
1067  */
1068     int32_t CP0_DESAVE;
1069     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
1070
1071     /* We waste some space so we can handle shadow registers like TCs. */
1072     TCState tcs[MIPS_SHADOW_SET_MAX];
1073     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
1074     /* QEMU */
1075     int error_code;
1076 #define EXCP_TLB_NOMATCH   0x1
1077 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1078     uint32_t hflags;    /* CPU State */
1079     /* TMASK defines different execution modes */
1080 #define MIPS_HFLAG_TMASK  0x1F5807FF
1081 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
1082     /*
1083      * The KSU flags must be the lowest bits in hflags. The flag order
1084      * must be the same as defined for CP0 Status. This allows to use
1085      * the bits as the value of mmu_idx.
1086      */
1087 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
1088 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
1089 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
1090 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
1091 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
1092 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
1093 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
1094 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
1095 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
1096     /*
1097      * True if the MIPS IV COP1X instructions can be used.  This also
1098      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1099      * and RSQRT.D.
1100      */
1101 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
1102 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
1103 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
1104 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
1105 #define MIPS_HFLAG_M16_SHIFT 10
1106     /*
1107      * If translation is interrupted between the branch instruction and
1108      * the delay slot, record what type of branch it is so that we can
1109      * resume translation properly.  It might be possible to reduce
1110      * this from three bits to two.
1111      */
1112 #define MIPS_HFLAG_BMASK_BASE  0x803800
1113 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
1114 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
1115 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
1116 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
1117     /* Extra flags about the current pending branch.  */
1118 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1119 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
1120 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1121 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1122 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
1123 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
1124 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1125     /* MIPS DSP resources access. */
1126 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
1127 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
1128 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1129     /* Extra flag about HWREna register. */
1130 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1131 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1132 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
1133 #define MIPS_HFLAG_MSA   0x1000000
1134 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
1135 #define MIPS_HFLAG_ELPA  0x4000000
1136 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
1137 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
1138     target_ulong btarget;        /* Jump / branch target               */
1139     target_ulong bcond;          /* Branch condition (if needed)       */
1140
1141     int SYNCI_Step; /* Address step size for SYNCI */
1142     int CCRes; /* Cycle count resolution/divisor */
1143     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1144     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1145     uint64_t insn_flags; /* Supported instruction set */
1146     int saarp;
1147
1148     /* Fields up to this point are cleared by a CPU reset */
1149     struct {} end_reset_fields;
1150
1151     /* Fields from here on are preserved across CPU reset. */
1152     CPUMIPSMVPContext *mvp;
1153 #if !defined(CONFIG_USER_ONLY)
1154     CPUMIPSTLBContext *tlb;
1155 #endif
1156
1157     const mips_def_t *cpu_model;
1158     void *irq[8];
1159     QEMUTimer *timer; /* Internal timer */
1160     struct MIPSITUState *itu;
1161     MemoryRegion *itc_tag; /* ITC Configuration Tags */
1162     target_ulong exception_base; /* ExceptionBase input to the core */
1163     uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
1164 };
1165
1166 /**
1167  * MIPSCPU:
1168  * @env: #CPUMIPSState
1169  * @clock: this CPU input clock (may be connected
1170  *         to an output clock from another device).
1171  * @cp0_count_rate: rate at which the coprocessor 0 counter increments
1172  *
1173  * A MIPS CPU.
1174  */
1175 struct MIPSCPU {
1176     /*< private >*/
1177     CPUState parent_obj;
1178     /*< public >*/
1179
1180     Clock *clock;
1181     CPUNegativeOffsetState neg;
1182     CPUMIPSState env;
1183     /*
1184      * The Count register acts as a timer, incrementing at a constant rate,
1185      * whether or not an instruction is executed, retired, or any forward
1186      * progress is made through the pipeline. The rate at which the counter
1187      * increments is implementation dependent, and is a function of the
1188      * pipeline clock of the processor, not the issue width of the processor.
1189      */
1190     unsigned cp0_count_rate;
1191 };
1192
1193
1194 void mips_cpu_list(void);
1195
1196 #define cpu_signal_handler cpu_mips_signal_handler
1197 #define cpu_list mips_cpu_list
1198
1199 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1200 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1201
1202 /*
1203  * MMU modes definitions. We carefully match the indices with our
1204  * hflags layout.
1205  */
1206 #define MMU_USER_IDX 2
1207
1208 static inline int hflags_mmu_index(uint32_t hflags)
1209 {
1210     if (hflags & MIPS_HFLAG_ERL) {
1211         return 3; /* ERL */
1212     } else {
1213         return hflags & MIPS_HFLAG_KSU;
1214     }
1215 }
1216
1217 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
1218 {
1219     return hflags_mmu_index(env->hflags);
1220 }
1221
1222 typedef CPUMIPSState CPUArchState;
1223 typedef MIPSCPU ArchCPU;
1224
1225 #include "exec/cpu-all.h"
1226
1227 /* Exceptions */
1228 enum {
1229     EXCP_NONE          = -1,
1230     EXCP_RESET         = 0,
1231     EXCP_SRESET,
1232     EXCP_DSS,
1233     EXCP_DINT,
1234     EXCP_DDBL,
1235     EXCP_DDBS,
1236     EXCP_NMI,
1237     EXCP_MCHECK,
1238     EXCP_EXT_INTERRUPT, /* 8 */
1239     EXCP_DFWATCH,
1240     EXCP_DIB,
1241     EXCP_IWATCH,
1242     EXCP_AdEL,
1243     EXCP_AdES,
1244     EXCP_TLBF,
1245     EXCP_IBE,
1246     EXCP_DBp, /* 16 */
1247     EXCP_SYSCALL,
1248     EXCP_BREAK,
1249     EXCP_CpU,
1250     EXCP_RI,
1251     EXCP_OVERFLOW,
1252     EXCP_TRAP,
1253     EXCP_FPE,
1254     EXCP_DWATCH, /* 24 */
1255     EXCP_LTLBL,
1256     EXCP_TLBL,
1257     EXCP_TLBS,
1258     EXCP_DBE,
1259     EXCP_THREAD,
1260     EXCP_MDMX,
1261     EXCP_C2E,
1262     EXCP_CACHE, /* 32 */
1263     EXCP_DSPDIS,
1264     EXCP_MSADIS,
1265     EXCP_MSAFPE,
1266     EXCP_TLBXI,
1267     EXCP_TLBRI,
1268
1269     EXCP_LAST = EXCP_TLBRI,
1270 };
1271
1272 /*
1273  * This is an internally generated WAKE request line.
1274  * It is driven by the CPU itself. Raised when the MT
1275  * block wants to wake a VPE from an inactive state and
1276  * cleared when VPE goes from active to inactive.
1277  */
1278 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1279
1280 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1281
1282 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1283 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1284 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1285
1286 bool cpu_type_supports_cps_smp(const char *cpu_type);
1287 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
1288 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
1289
1290 /* Check presence of MSA implementation */
1291 static inline bool ase_msa_available(CPUMIPSState *env)
1292 {
1293     return env->CP0_Config3 & (1 << CP0C3_MSAP);
1294 }
1295
1296 /* Check presence of multi-threading ASE implementation */
1297 static inline bool ase_mt_available(CPUMIPSState *env)
1298 {
1299     return env->CP0_Config3 & (1 << CP0C3_MT);
1300 }
1301
1302 static inline bool cpu_type_is_64bit(const char *cpu_type)
1303 {
1304     return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
1305 }
1306
1307 void cpu_set_exception_base(int vp_index, target_ulong address);
1308
1309 /* addr.c */
1310 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
1311 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
1312
1313 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
1314 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
1315 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
1316 bool mips_um_ksegs_enabled(void);
1317 void mips_um_ksegs_enable(void);
1318
1319 /* mips_int.c */
1320 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1321
1322 /* mips_itu.c */
1323 void itc_reconfigure(struct MIPSITUState *tag);
1324
1325 /* helper.c */
1326 target_ulong exception_resume_pc(CPUMIPSState *env);
1327
1328 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1329                                         target_ulong *cs_base, uint32_t *flags)
1330 {
1331     *pc = env->active_tc.PC;
1332     *cs_base = 0;
1333     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1334                             MIPS_HFLAG_HWRENA_ULR);
1335 }
1336
1337 /**
1338  * mips_cpu_create_with_clock:
1339  * @typename: a MIPS CPU type.
1340  * @cpu_refclk: this cpu input clock (an output clock of another device)
1341  *
1342  * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
1343  * then realizes the CPU.
1344  *
1345  * Returns: A #CPUState or %NULL if an error occurred.
1346  */
1347 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
1348
1349 #endif /* MIPS_CPU_H */