target/hexagon/macros.h

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_MACROS_H
  19 #define HEXAGON_MACROS_H
  20
  21 #include "cpu.h"
  22 #include "hex_regs.h"
  23 #include "reg_fields.h"
  24
  25 #ifdef QEMU_GENERATE
  26 #define READ_REG(dest, NUM)              gen_read_reg(dest, NUM)
  27 #define READ_PREG(dest, NUM)             gen_read_preg(dest, (NUM))
  28 #else
  29 #define READ_REG(NUM)                    (env->gpr[(NUM)])
  30 #define READ_PREG(NUM)                   (env->pred[NUM])
  31
  32 #define WRITE_RREG(NUM, VAL)             log_reg_write(env, NUM, VAL, slot)
  33 #define WRITE_PREG(NUM, VAL)             log_pred_write(env, NUM, VAL)
  34 #endif
  35
  36 #define PCALIGN 4
  37 #define PCALIGN_MASK (PCALIGN - 1)
  38
  39 #define GET_FIELD(FIELD, REGIN) \
  40     fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  41                    reg_field_info[FIELD].offset)
  42
  43 #ifdef QEMU_GENERATE
  44 #define GET_USR_FIELD(FIELD, DST) \
  45     tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  46                        reg_field_info[FIELD].offset, \
  47                        reg_field_info[FIELD].width)
  48
  49 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  50 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  51 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  52
  53 #define SET_USR_FIELD_FUNC(X) \
  54     __builtin_choose_expr(TYPE_INT(X), \
  55         gen_set_usr_fieldi, \
  56         __builtin_choose_expr(TYPE_TCGV(X), \
  57             gen_set_usr_field, (void)0))
  58 #define SET_USR_FIELD(FIELD, VAL) \
  59     SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
  60 #else
  61 #define GET_USR_FIELD(FIELD) \
  62     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  63                    reg_field_info[FIELD].offset)
  64
  65 #define SET_USR_FIELD(FIELD, VAL) \
  66     fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  67                  reg_field_info[FIELD].offset, (VAL))
  68 #endif
  69
  70 #ifdef QEMU_GENERATE
  71 /*
  72  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  73  *
  74  * Slot 1 store with slot 0 load
  75  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  76  * The packet attribute :mem_noshuf inhibits the instruction reordering that
  77  * would otherwise be done by the assembler. For example:
  78  *     {
  79  *         memw(R5) = R2 // slot 1 store
  80  *         R3 = memh(R6) // slot 0 load
  81  *     }:mem_noshuf
  82  * Unlike most packetized operations, these memory operations are not executed
  83  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  84  * effectively executes first, followed by the load instruction in Slot 0. If
  85  * the addresses of the two operations are overlapping, the load will receive
  86  * the newly stored data. This feature is supported in processor versions
  87  * V65 or greater.
  88  *
  89  *
  90  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  91  * in the same packet.  When we see this, we call a helper that merges the
  92  * bytes from the store buffer with the value loaded from memory.
  93  */
  94 #define CHECK_NOSHUF \
  95     do { \
  96         if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
  97             process_store(ctx, pkt, 1); \
  98         } \
  99     } while (0)
 100
 101 #define MEM_LOAD1s(DST, VA) \
 102     do { \
 103         CHECK_NOSHUF; \
 104         tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
 105     } while (0)
 106 #define MEM_LOAD1u(DST, VA) \
 107     do { \
 108         CHECK_NOSHUF; \
 109         tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
 110     } while (0)
 111 #define MEM_LOAD2s(DST, VA) \
 112     do { \
 113         CHECK_NOSHUF; \
 114         tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
 115     } while (0)
 116 #define MEM_LOAD2u(DST, VA) \
 117     do { \
 118         CHECK_NOSHUF; \
 119         tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
 120     } while (0)
 121 #define MEM_LOAD4s(DST, VA) \
 122     do { \
 123         CHECK_NOSHUF; \
 124         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 125     } while (0)
 126 #define MEM_LOAD4u(DST, VA) \
 127     do { \
 128         CHECK_NOSHUF; \
 129         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 130     } while (0)
 131 #define MEM_LOAD8u(DST, VA) \
 132     do { \
 133         CHECK_NOSHUF; \
 134         tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
 135     } while (0)
 136 #else
 137 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 138 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
 139 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
 140 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
 141 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
 142 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
 143 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
 144 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
 145
 146 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 147 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 148 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 149 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 150 #endif
 151
 152 #define CANCEL cancel_slot(env, slot)
 153
 154 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 155
 156 #ifdef QEMU_GENERATE
 157 static inline void gen_pred_cancel(TCGv pred, int slot_num)
 158  {
 159     TCGv slot_mask = tcg_const_tl(1 << slot_num);
 160     TCGv tmp = tcg_temp_new();
 161     TCGv zero = tcg_const_tl(0);
 162     TCGv one = tcg_const_tl(1);
 163     tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask);
 164     tcg_gen_andi_tl(tmp, pred, 1);
 165     tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
 166                        slot_mask, hex_slot_cancelled);
 167     tcg_temp_free(slot_mask);
 168     tcg_temp_free(tmp);
 169     tcg_temp_free(zero);
 170     tcg_temp_free(one);
 171 }
 172 #define PRED_LOAD_CANCEL(PRED, EA) \
 173     gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
 174 #endif
 175
 176 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 177
 178 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 179
 180 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 181
 182 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
 183 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 184     REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 185 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 186     ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 187 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 188     (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 189 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 190     (((HIBIT) - (LOWBIT) + 1) ? \
 191         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 192         0LL)
 193
 194 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 195
 196 #ifdef QEMU_GENERATE
 197 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 198 #else
 199 #define fLSBOLD(VAL)  ((VAL) & 1)
 200 #endif
 201
 202 #ifdef QEMU_GENERATE
 203 #define fLSBNEW(PVAL)   tcg_gen_mov_tl(LSB, (PVAL))
 204 #define fLSBNEW0        tcg_gen_mov_tl(LSB, hex_new_pred_value[0])
 205 #define fLSBNEW1        tcg_gen_mov_tl(LSB, hex_new_pred_value[1])
 206 #else
 207 #define fLSBNEW(PVAL)   (PVAL)
 208 #define fLSBNEW0        new_pred_value(env, 0)
 209 #define fLSBNEW1        new_pred_value(env, 1)
 210 #endif
 211
 212 #ifdef QEMU_GENERATE
 213 static inline void gen_logical_not(TCGv dest, TCGv src)
 214 {
 215     TCGv one = tcg_const_tl(1);
 216     TCGv zero = tcg_const_tl(0);
 217
 218     tcg_gen_movcond_tl(TCG_COND_NE, dest, src, zero, zero, one);
 219
 220     tcg_temp_free(one);
 221     tcg_temp_free(zero);
 222 }
 223 #define fLSBOLDNOT(VAL) \
 224     do { \
 225         tcg_gen_andi_tl(LSB, (VAL), 1); \
 226         tcg_gen_xori_tl(LSB, LSB, 1); \
 227     } while (0)
 228 #define fLSBNEWNOT(PNUM) \
 229     gen_logical_not(LSB, (PNUM))
 230 #else
 231 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 232 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 233 #define fLSBNEW0NOT (!fLSBNEW0)
 234 #define fLSBNEW1NOT (!fLSBNEW1)
 235 #endif
 236
 237 #define fNEWREG(VAL) ((int32_t)(VAL))
 238
 239 #define fNEWREG_ST(VAL) (VAL)
 240
 241 #define fSATUVALN(N, VAL) \
 242     ({ \
 243         fSET_OVERFLOW(); \
 244         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 245     })
 246 #define fSATVALN(N, VAL) \
 247     ({ \
 248         fSET_OVERFLOW(); \
 249         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 250     })
 251 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 252 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 253 #define fSATN(N, VAL) \
 254     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 255 #define fADDSAT64(DST, A, B) \
 256     do { \
 257         uint64_t __a = fCAST8u(A); \
 258         uint64_t __b = fCAST8u(B); \
 259         uint64_t __sum = __a + __b; \
 260         uint64_t __xor = __a ^ __b; \
 261         const uint64_t __mask = 0x8000000000000000ULL; \
 262         if (__xor & __mask) { \
 263             DST = __sum; \
 264         } \
 265         else if ((__a ^ __sum) & __mask) { \
 266             if (__sum & __mask) { \
 267                 DST = 0x7FFFFFFFFFFFFFFFLL; \
 268                 fSET_OVERFLOW(); \
 269             } else { \
 270                 DST = 0x8000000000000000LL; \
 271                 fSET_OVERFLOW(); \
 272             } \
 273         } else { \
 274             DST = __sum; \
 275         } \
 276     } while (0)
 277 #define fSATUN(N, VAL) \
 278     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 279 #define fSATH(VAL) (fSATN(16, VAL))
 280 #define fSATUH(VAL) (fSATUN(16, VAL))
 281 #define fSATUB(VAL) (fSATUN(8, VAL))
 282 #define fSATB(VAL) (fSATN(8, VAL))
 283 #define fIMMEXT(IMM) (IMM = IMM)
 284 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 285
 286 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 287
 288 #define fREAD_LR() (READ_REG(HEX_REG_LR))
 289
 290 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
 291 #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
 292 #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
 293
 294 #define fREAD_SP() (READ_REG(HEX_REG_SP))
 295 #define fREAD_LC0 (READ_REG(HEX_REG_LC0))
 296 #define fREAD_LC1 (READ_REG(HEX_REG_LC1))
 297 #define fREAD_SA0 (READ_REG(HEX_REG_SA0))
 298 #define fREAD_SA1 (READ_REG(HEX_REG_SA1))
 299 #define fREAD_FP() (READ_REG(HEX_REG_FP))
 300 #ifdef FIXME
 301 /* Figure out how to get insn->extension_valid to helper */
 302 #define fREAD_GP() \
 303     (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
 304 #else
 305 #define fREAD_GP() READ_REG(HEX_REG_GP)
 306 #endif
 307 #define fREAD_PC() (READ_REG(HEX_REG_PC))
 308
 309 #define fREAD_NPC() (env->next_PC & (0xfffffffe))
 310
 311 #define fREAD_P0() (READ_PREG(0))
 312 #define fREAD_P3() (READ_PREG(3))
 313
 314 #define fCHECK_PCALIGN(A)
 315
 316 #define fWRITE_NPC(A) write_new_pc(env, A)
 317
 318 #define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 319 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 320 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 321 #define fCALL(A) \
 322     do { \
 323         fWRITE_LR(fREAD_NPC()); \
 324         fBRANCH(A, COF_TYPE_CALL); \
 325     } while (0)
 326 #define fCALLR(A) \
 327     do { \
 328         fWRITE_LR(fREAD_NPC()); \
 329         fBRANCH(A, COF_TYPE_CALLR); \
 330     } while (0)
 331 #define fWRITE_LOOP_REGS0(START, COUNT) \
 332     do { \
 333         WRITE_RREG(HEX_REG_LC0, COUNT);  \
 334         WRITE_RREG(HEX_REG_SA0, START); \
 335     } while (0)
 336 #define fWRITE_LOOP_REGS1(START, COUNT) \
 337     do { \
 338         WRITE_RREG(HEX_REG_LC1, COUNT);  \
 339         WRITE_RREG(HEX_REG_SA1, START);\
 340     } while (0)
 341 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
 342 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 343
 344 #define fCARRY_FROM_ADD(A, B, C) carry_from_add64(A, B, C)
 345
 346 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 347 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 348 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 349 #define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
 350 #define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
 351 #define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
 352 #define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
 353 #define fPART1(WORK) if (part1) { WORK; return; }
 354 #define fCAST4u(A) ((uint32_t)(A))
 355 #define fCAST4s(A) ((int32_t)(A))
 356 #define fCAST8u(A) ((uint64_t)(A))
 357 #define fCAST8s(A) ((int64_t)(A))
 358 #define fCAST4_4s(A) ((int32_t)(A))
 359 #define fCAST4_4u(A) ((uint32_t)(A))
 360 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 361 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 362 #define fCAST8_8s(A) ((int64_t)(A))
 363 #define fCAST8_8u(A) ((uint64_t)(A))
 364 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 365 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 366 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 367 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
 368 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
 369 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 370 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
 371 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 372 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
 373 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 374 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 375 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 376 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 377 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 378 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 379 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 380 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 381 #define fMPY16US(A, B) fMPY16SU(B, A)
 382 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 383 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 384 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 385 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 386 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 387 #define fROUND(A) (A + 0x8000)
 388 #define fCLIP(DST, SRC, U) \
 389     do { \
 390         int32_t maxv = (1 << U) - 1; \
 391         int32_t minv = -(1 << U); \
 392         DST = fMIN(maxv, fMAX(SRC, minv)); \
 393     } while (0)
 394 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 395 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 396 #define fCRNDN(A, N) (conv_round(A, N))
 397 #define fADD128(A, B) (int128_add(A, B))
 398 #define fSUB128(A, B) (int128_sub(A, B))
 399 #define fSHIFTR128(A, B) (int128_rshift(A, B))
 400 #define fSHIFTL128(A, B) (int128_lshift(A, B))
 401 #define fAND128(A, B) (int128_and(A, B))
 402 #define fCAST8S_16S(A) (int128_exts64(A))
 403 #define fCAST16S_8S(A) (int128_getlo(A))
 404
 405 #define fEA_RI(REG, IMM) \
 406     do { \
 407         EA = REG + IMM; \
 408     } while (0)
 409 #define fEA_RRs(REG, REG2, SCALE) \
 410     do { \
 411         EA = REG + (REG2 << SCALE); \
 412     } while (0)
 413 #define fEA_IRs(IMM, REG, SCALE) \
 414     do { \
 415         EA = IMM + (REG << SCALE); \
 416     } while (0)
 417
 418 #ifdef QEMU_GENERATE
 419 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 420 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 421 #define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 422 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 423 #else
 424 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 425 #define fEA_REG(REG)        do { EA = (REG); } while (0)
 426 #define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 427 #define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 428 #define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 429 #endif
 430 #define fSCALE(N, A) (((int64_t)(A)) << N)
 431 #define fSATW(A) fSATN(32, ((long long)A))
 432 #define fSAT(A) fSATN(32, (A))
 433 #define fSAT_ORIG_SHL(A, ORIG_REG) \
 434     ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 435         ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 436         : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 437                                             : fSAT(A)))
 438 #define fPASS(A) A
 439 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 440     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 441                    : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 442 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 443     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 444 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 445     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 446 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 447     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 448                    : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 449 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 450     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 451                    : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 452 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 453     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 454 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 455     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 456 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 457     (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 458                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 459                    : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 460 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 461 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 462     (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 463 #define fROTL(SRC, SHAMT, REGSTYPE) \
 464     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 465                               ((fCAST##REGSTYPE##u(SRC) >> \
 466                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 467 #define fROTR(SRC, SHAMT, REGSTYPE) \
 468     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 469                               ((fCAST##REGSTYPE##u(SRC) << \
 470                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 471 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 472     (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 473
 474 #ifdef QEMU_GENERATE
 475 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 476 #else
 477 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 478     DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 479 #endif
 480
 481 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 482
 483 #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
 484 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 485 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 486
 487 #ifdef CONFIG_USER_ONLY
 488 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 489 #else
 490 /* System mode not implemented yet */
 491 #define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 492 #endif
 493
 494 #ifdef QEMU_GENERATE
 495 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 496     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 497 #endif
 498
 499 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 500
 501 #ifdef QEMU_GENERATE
 502 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 503     gen_store_conditional##SIZE(env, ctx, PdN, PRED, EA, SRC);
 504 #endif
 505
 506 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 507 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 508
 509 #define fSETBYTE(N, DST, VAL) \
 510     do { \
 511         DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 512         (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 513     } while (0)
 514 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 515 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 516 #define fSETHALF(N, DST, VAL) \
 517     do { \
 518         DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 519         (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 520     } while (0)
 521 #define fSETHALFw fSETHALF
 522 #define fSETHALFd fSETHALF
 523
 524 #define fGETWORD(N, SRC) \
 525     ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 526 #define fGETUWORD(N, SRC) \
 527     ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 528
 529 #define fSETWORD(N, DST, VAL) \
 530     do { \
 531         DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 532               (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 533     } while (0)
 534
 535 #define fSETBIT(N, DST, VAL) \
 536     do { \
 537         DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 538     } while (0)
 539
 540 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 541 #define fSETBITS(HI, LO, DST, VAL) \
 542     do { \
 543         int j; \
 544         for (j = LO; j <= HI; j++) { \
 545             fSETBIT(j, DST, VAL); \
 546         } \
 547     } while (0)
 548 #define fCOUNTONES_4(VAL) ctpop32(VAL)
 549 #define fCOUNTONES_8(VAL) ctpop64(VAL)
 550 #define fBREV_8(VAL) revbit64(VAL)
 551 #define fBREV_4(VAL) revbit32(VAL)
 552 #define fCL1_8(VAL) clo64(VAL)
 553 #define fCL1_4(VAL) clo32(VAL)
 554 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 555 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 556 #define fHIDE(A) A
 557 #define fCONSTLL(A) A##LL
 558 #define fECHO(A) (A)
 559
 560 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 561 #define fPAUSE(IMM)
 562
 563 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 564     ((VAL) << reg_field_info[FIELD].offset)
 565 #define fGET_REG_FIELD_MASK(FIELD) \
 566     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 567 #define fREAD_REG_FIELD(REG, FIELD) \
 568     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 569                    reg_field_info[FIELD].width, \
 570                    reg_field_info[FIELD].offset)
 571 #define fGET_FIELD(VAL, FIELD)
 572 #define fSET_FIELD(VAL, FIELD, NEWVAL)
 573 #define fBARRIER()
 574 #define fSYNCH()
 575 #define fISYNC()
 576 #define fDCFETCH(REG) \
 577     do { (void)REG; } while (0) /* Nothing to do in qemu */
 578 #define fICINVA(REG) \
 579     do { (void)REG; } while (0) /* Nothing to do in qemu */
 580 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
 581 #define fDCCLEANA(REG) \
 582     do { (void)REG; } while (0) /* Nothing to do in qemu */
 583 #define fDCCLEANINVA(REG) \
 584     do { (void)REG; } while (0) /* Nothing to do in qemu */
 585
 586 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
 587
 588 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 589                                 STRBITNUM) /* Nothing */
 590
 591
 592 #endif