2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o BIOS work to boot from USB storage
28 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
34 #include "hw/sysbus.h"
35 #include "hw/qdev-dma.h"
39 /* This causes frames to occur 1000x slower */
40 //#define OHCI_TIME_WARP 1
42 #define ED_LINK_LIMIT 32
44 static int64_t usb_frame_time
;
45 static int64_t usb_bit_time
;
47 /* Host Controller Communications Area */
53 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
54 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
56 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
57 #define ED_WBACK_SIZE 4
59 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
);
61 /* Bitfields for the first word of an Endpoint Desciptor. */
62 #define OHCI_ED_FA_SHIFT 0
63 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
64 #define OHCI_ED_EN_SHIFT 7
65 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
66 #define OHCI_ED_D_SHIFT 11
67 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
68 #define OHCI_ED_S (1<<13)
69 #define OHCI_ED_K (1<<14)
70 #define OHCI_ED_F (1<<15)
71 #define OHCI_ED_MPS_SHIFT 16
72 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
74 /* Flags in the head field of an Endpoint Desciptor. */
78 /* Bitfields for the first word of a Transfer Desciptor. */
79 #define OHCI_TD_R (1<<18)
80 #define OHCI_TD_DP_SHIFT 19
81 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
82 #define OHCI_TD_DI_SHIFT 21
83 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
84 #define OHCI_TD_T0 (1<<24)
85 #define OHCI_TD_T1 (1<<25)
86 #define OHCI_TD_EC_SHIFT 26
87 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
88 #define OHCI_TD_CC_SHIFT 28
89 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
92 /* CC & DI - same as in the General Transfer Desciptor */
93 #define OHCI_TD_SF_SHIFT 0
94 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
95 #define OHCI_TD_FC_SHIFT 24
96 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
99 #define OHCI_TD_PSW_CC_SHIFT 12
100 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
101 #define OHCI_TD_PSW_SIZE_SHIFT 0
102 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
104 #define OHCI_PAGE_MASK 0xfffff000
105 #define OHCI_OFFSET_MASK 0xfff
107 #define OHCI_DPTR_MASK 0xfffffff0
109 #define OHCI_BM(val, field) \
110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
112 #define OHCI_SET_BM(val, field, newval) do { \
113 val &= ~OHCI_##field##_MASK; \
114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
117 /* endpoint descriptor */
125 /* General transfer descriptor */
133 /* Isochronous transfer descriptor */
142 #define USB_HZ 12000000
144 /* OHCI Local stuff */
145 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
146 #define OHCI_CTL_PLE (1<<2)
147 #define OHCI_CTL_IE (1<<3)
148 #define OHCI_CTL_CLE (1<<4)
149 #define OHCI_CTL_BLE (1<<5)
150 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
151 #define OHCI_USB_RESET 0x00
152 #define OHCI_USB_RESUME 0x40
153 #define OHCI_USB_OPERATIONAL 0x80
154 #define OHCI_USB_SUSPEND 0xc0
155 #define OHCI_CTL_IR (1<<8)
156 #define OHCI_CTL_RWC (1<<9)
157 #define OHCI_CTL_RWE (1<<10)
159 #define OHCI_STATUS_HCR (1<<0)
160 #define OHCI_STATUS_CLF (1<<1)
161 #define OHCI_STATUS_BLF (1<<2)
162 #define OHCI_STATUS_OCR (1<<3)
163 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
165 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
166 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
167 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
168 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
169 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
170 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
171 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
172 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
173 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
175 #define OHCI_HCCA_SIZE 0x100
176 #define OHCI_HCCA_MASK 0xffffff00
178 #define OHCI_EDPTR_MASK 0xfffffff0
180 #define OHCI_FMI_FI 0x00003fff
181 #define OHCI_FMI_FSMPS 0xffff0000
182 #define OHCI_FMI_FIT 0x80000000
184 #define OHCI_FR_RT (1U<<31)
186 #define OHCI_LS_THRESH 0x628
188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
189 #define OHCI_RHA_PSM (1<<8)
190 #define OHCI_RHA_NPS (1<<9)
191 #define OHCI_RHA_DT (1<<10)
192 #define OHCI_RHA_OCPM (1<<11)
193 #define OHCI_RHA_NOCP (1<<12)
194 #define OHCI_RHA_POTPGT_MASK 0xff000000
196 #define OHCI_RHS_LPS (1U<<0)
197 #define OHCI_RHS_OCI (1U<<1)
198 #define OHCI_RHS_DRWE (1U<<15)
199 #define OHCI_RHS_LPSC (1U<<16)
200 #define OHCI_RHS_OCIC (1U<<17)
201 #define OHCI_RHS_CRWE (1U<<31)
203 #define OHCI_PORT_CCS (1<<0)
204 #define OHCI_PORT_PES (1<<1)
205 #define OHCI_PORT_PSS (1<<2)
206 #define OHCI_PORT_POCI (1<<3)
207 #define OHCI_PORT_PRS (1<<4)
208 #define OHCI_PORT_PPS (1<<8)
209 #define OHCI_PORT_LSDA (1<<9)
210 #define OHCI_PORT_CSC (1<<16)
211 #define OHCI_PORT_PESC (1<<17)
212 #define OHCI_PORT_PSSC (1<<18)
213 #define OHCI_PORT_OCIC (1<<19)
214 #define OHCI_PORT_PRSC (1<<20)
215 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
216 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
218 #define OHCI_TD_DIR_SETUP 0x0
219 #define OHCI_TD_DIR_OUT 0x1
220 #define OHCI_TD_DIR_IN 0x2
221 #define OHCI_TD_DIR_RESERVED 0x3
223 #define OHCI_CC_NOERROR 0x0
224 #define OHCI_CC_CRC 0x1
225 #define OHCI_CC_BITSTUFFING 0x2
226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
227 #define OHCI_CC_STALL 0x4
228 #define OHCI_CC_DEVICENOTRESPONDING 0x5
229 #define OHCI_CC_PIDCHECKFAILURE 0x6
230 #define OHCI_CC_UNDEXPETEDPID 0x7
231 #define OHCI_CC_DATAOVERRUN 0x8
232 #define OHCI_CC_DATAUNDERRUN 0x9
233 #define OHCI_CC_BUFFEROVERRUN 0xc
234 #define OHCI_CC_BUFFERUNDERRUN 0xd
236 #define OHCI_HRESET_FSBIR (1 << 0)
238 static void ohci_die(OHCIState
*ohci
)
240 ohci
->ohci_die(ohci
);
243 /* Update IRQ levels */
244 static inline void ohci_intr_update(OHCIState
*ohci
)
248 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
249 (ohci
->intr_status
& ohci
->intr
))
252 qemu_set_irq(ohci
->irq
, level
);
255 /* Set an interrupt */
256 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
258 ohci
->intr_status
|= intr
;
259 ohci_intr_update(ohci
);
262 /* Attach or detach a device on a root hub port. */
263 static void ohci_attach(USBPort
*port1
)
265 OHCIState
*s
= port1
->opaque
;
266 OHCIPort
*port
= &s
->rhport
[port1
->index
];
267 uint32_t old_state
= port
->ctrl
;
269 /* set connect status */
270 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
273 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
274 port
->ctrl
|= OHCI_PORT_LSDA
;
276 port
->ctrl
&= ~OHCI_PORT_LSDA
;
279 /* notify of remote-wakeup */
280 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
281 ohci_set_interrupt(s
, OHCI_INTR_RD
);
284 trace_usb_ohci_port_attach(port1
->index
);
286 if (old_state
!= port
->ctrl
) {
287 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
291 static void ohci_detach(USBPort
*port1
)
293 OHCIState
*s
= port1
->opaque
;
294 OHCIPort
*port
= &s
->rhport
[port1
->index
];
295 uint32_t old_state
= port
->ctrl
;
297 ohci_async_cancel_device(s
, port1
->dev
);
299 /* set connect status */
300 if (port
->ctrl
& OHCI_PORT_CCS
) {
301 port
->ctrl
&= ~OHCI_PORT_CCS
;
302 port
->ctrl
|= OHCI_PORT_CSC
;
305 if (port
->ctrl
& OHCI_PORT_PES
) {
306 port
->ctrl
&= ~OHCI_PORT_PES
;
307 port
->ctrl
|= OHCI_PORT_PESC
;
309 trace_usb_ohci_port_detach(port1
->index
);
311 if (old_state
!= port
->ctrl
) {
312 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
316 static void ohci_wakeup(USBPort
*port1
)
318 OHCIState
*s
= port1
->opaque
;
319 OHCIPort
*port
= &s
->rhport
[port1
->index
];
321 if (port
->ctrl
& OHCI_PORT_PSS
) {
322 trace_usb_ohci_port_wakeup(port1
->index
);
323 port
->ctrl
|= OHCI_PORT_PSSC
;
324 port
->ctrl
&= ~OHCI_PORT_PSS
;
325 intr
= OHCI_INTR_RHSC
;
327 /* Note that the controller can be suspended even if this port is not */
328 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
329 trace_usb_ohci_remote_wakeup(s
->name
);
330 /* This is the one state transition the controller can do by itself */
331 s
->ctl
&= ~OHCI_CTL_HCFS
;
332 s
->ctl
|= OHCI_USB_RESUME
;
333 /* In suspend mode only ResumeDetected is possible, not RHSC:
334 * see the OHCI spec 5.1.2.3.
338 ohci_set_interrupt(s
, intr
);
341 static void ohci_child_detach(USBPort
*port1
, USBDevice
*child
)
343 OHCIState
*s
= port1
->opaque
;
345 ohci_async_cancel_device(s
, child
);
348 static USBDevice
*ohci_find_device(OHCIState
*ohci
, uint8_t addr
)
353 for (i
= 0; i
< ohci
->num_ports
; i
++) {
354 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0) {
357 dev
= usb_find_device(&ohci
->rhport
[i
].port
, addr
);
365 void ohci_stop_endpoints(OHCIState
*ohci
)
370 for (i
= 0; i
< ohci
->num_ports
; i
++) {
371 dev
= ohci
->rhport
[i
].port
.dev
;
372 if (dev
&& dev
->attached
) {
373 usb_device_ep_stopped(dev
, &dev
->ep_ctl
);
374 for (j
= 0; j
< USB_MAX_ENDPOINTS
; j
++) {
375 usb_device_ep_stopped(dev
, &dev
->ep_in
[j
]);
376 usb_device_ep_stopped(dev
, &dev
->ep_out
[j
]);
382 static void ohci_roothub_reset(OHCIState
*ohci
)
388 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
389 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
392 for (i
= 0; i
< ohci
->num_ports
; i
++) {
393 port
= &ohci
->rhport
[i
];
395 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
396 usb_port_reset(&port
->port
);
399 if (ohci
->async_td
) {
400 usb_cancel_packet(&ohci
->usb_packet
);
403 ohci_stop_endpoints(ohci
);
406 /* Reset the controller */
407 static void ohci_soft_reset(OHCIState
*ohci
)
409 trace_usb_ohci_reset(ohci
->name
);
412 ohci
->ctl
= (ohci
->ctl
& OHCI_CTL_IR
) | OHCI_USB_SUSPEND
;
415 ohci
->intr_status
= 0;
416 ohci
->intr
= OHCI_INTR_MIE
;
419 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
420 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
423 ohci
->done_count
= 7;
425 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
426 * I took the value linux sets ...
428 ohci
->fsmps
= 0x2778;
432 ohci
->frame_number
= 0;
434 ohci
->lst
= OHCI_LS_THRESH
;
437 void ohci_hard_reset(OHCIState
*ohci
)
439 ohci_soft_reset(ohci
);
441 ohci_roothub_reset(ohci
);
444 /* Get an array of dwords from main memory */
445 static inline int get_dwords(OHCIState
*ohci
,
446 dma_addr_t addr
, uint32_t *buf
, int num
)
450 addr
+= ohci
->localmem_base
;
452 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
453 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
456 *buf
= le32_to_cpu(*buf
);
462 /* Put an array of dwords in to main memory */
463 static inline int put_dwords(OHCIState
*ohci
,
464 dma_addr_t addr
, uint32_t *buf
, int num
)
468 addr
+= ohci
->localmem_base
;
470 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
471 uint32_t tmp
= cpu_to_le32(*buf
);
472 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
480 /* Get an array of words from main memory */
481 static inline int get_words(OHCIState
*ohci
,
482 dma_addr_t addr
, uint16_t *buf
, int num
)
486 addr
+= ohci
->localmem_base
;
488 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
489 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
492 *buf
= le16_to_cpu(*buf
);
498 /* Put an array of words in to main memory */
499 static inline int put_words(OHCIState
*ohci
,
500 dma_addr_t addr
, uint16_t *buf
, int num
)
504 addr
+= ohci
->localmem_base
;
506 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
507 uint16_t tmp
= cpu_to_le16(*buf
);
508 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
516 static inline int ohci_read_ed(OHCIState
*ohci
,
517 dma_addr_t addr
, struct ohci_ed
*ed
)
519 return get_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
522 static inline int ohci_read_td(OHCIState
*ohci
,
523 dma_addr_t addr
, struct ohci_td
*td
)
525 return get_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
528 static inline int ohci_read_iso_td(OHCIState
*ohci
,
529 dma_addr_t addr
, struct ohci_iso_td
*td
)
531 return get_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
532 get_words(ohci
, addr
+ 16, td
->offset
, 8);
535 static inline int ohci_read_hcca(OHCIState
*ohci
,
536 dma_addr_t addr
, struct ohci_hcca
*hcca
)
538 return dma_memory_read(ohci
->as
, addr
+ ohci
->localmem_base
,
539 hcca
, sizeof(*hcca
));
542 static inline int ohci_put_ed(OHCIState
*ohci
,
543 dma_addr_t addr
, struct ohci_ed
*ed
)
545 /* ed->tail is under control of the HCD.
546 * Since just ed->head is changed by HC, just write back this
549 return put_dwords(ohci
, addr
+ ED_WBACK_OFFSET
,
550 (uint32_t *)((char *)ed
+ ED_WBACK_OFFSET
),
554 static inline int ohci_put_td(OHCIState
*ohci
,
555 dma_addr_t addr
, struct ohci_td
*td
)
557 return put_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
560 static inline int ohci_put_iso_td(OHCIState
*ohci
,
561 dma_addr_t addr
, struct ohci_iso_td
*td
)
563 return put_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
564 put_words(ohci
, addr
+ 16, td
->offset
, 8);
567 static inline int ohci_put_hcca(OHCIState
*ohci
,
568 dma_addr_t addr
, struct ohci_hcca
*hcca
)
570 return dma_memory_write(ohci
->as
,
571 addr
+ ohci
->localmem_base
+ HCCA_WRITEBACK_OFFSET
,
572 (char *)hcca
+ HCCA_WRITEBACK_OFFSET
,
573 HCCA_WRITEBACK_SIZE
);
576 /* Read/Write the contents of a TD from/to main memory. */
577 static int ohci_copy_td(OHCIState
*ohci
, struct ohci_td
*td
,
578 uint8_t *buf
, int len
, DMADirection dir
)
583 n
= 0x1000 - (ptr
& 0xfff);
587 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
593 ptr
= td
->be
& ~0xfffu
;
595 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
602 /* Read/Write the contents of an ISO TD from/to main memory. */
603 static int ohci_copy_iso_td(OHCIState
*ohci
,
604 uint32_t start_addr
, uint32_t end_addr
,
605 uint8_t *buf
, int len
, DMADirection dir
)
610 n
= 0x1000 - (ptr
& 0xfff);
614 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
620 ptr
= end_addr
& ~0xfffu
;
622 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
629 static void ohci_process_lists(OHCIState
*ohci
, int completion
);
631 static void ohci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
633 OHCIState
*ohci
= container_of(packet
, OHCIState
, usb_packet
);
635 trace_usb_ohci_async_complete();
636 ohci
->async_complete
= true;
637 ohci_process_lists(ohci
, 1);
640 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
642 static int ohci_service_iso_td(OHCIState
*ohci
, struct ohci_ed
*ed
,
647 const char *str
= NULL
;
653 struct ohci_iso_td iso_td
;
655 uint16_t starting_frame
;
656 int16_t relative_frame_number
;
658 uint32_t start_offset
, next_offset
, end_offset
= 0;
659 uint32_t start_addr
, end_addr
;
661 addr
= ed
->head
& OHCI_DPTR_MASK
;
663 if (ohci_read_iso_td(ohci
, addr
, &iso_td
)) {
664 trace_usb_ohci_iso_td_read_failed(addr
);
669 starting_frame
= OHCI_BM(iso_td
.flags
, TD_SF
);
670 frame_count
= OHCI_BM(iso_td
.flags
, TD_FC
);
671 relative_frame_number
= USUB(ohci
->frame_number
, starting_frame
);
673 trace_usb_ohci_iso_td_head(
674 ed
->head
& OHCI_DPTR_MASK
, ed
->tail
& OHCI_DPTR_MASK
,
675 iso_td
.flags
, iso_td
.bp
, iso_td
.next
, iso_td
.be
,
676 ohci
->frame_number
, starting_frame
,
677 frame_count
, relative_frame_number
);
678 trace_usb_ohci_iso_td_head_offset(
679 iso_td
.offset
[0], iso_td
.offset
[1],
680 iso_td
.offset
[2], iso_td
.offset
[3],
681 iso_td
.offset
[4], iso_td
.offset
[5],
682 iso_td
.offset
[6], iso_td
.offset
[7]);
684 if (relative_frame_number
< 0) {
685 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number
);
687 } else if (relative_frame_number
> frame_count
) {
688 /* ISO TD expired - retire the TD to the Done Queue and continue with
689 the next ISO TD of the same ED */
690 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number
,
692 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
693 ed
->head
&= ~OHCI_DPTR_MASK
;
694 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
695 iso_td
.next
= ohci
->done
;
697 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
698 if (i
< ohci
->done_count
)
699 ohci
->done_count
= i
;
700 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
707 dir
= OHCI_BM(ed
->flags
, ED_D
);
713 case OHCI_TD_DIR_OUT
:
717 case OHCI_TD_DIR_SETUP
:
719 pid
= USB_TOKEN_SETUP
;
722 trace_usb_ohci_iso_td_bad_direction(dir
);
726 if (!iso_td
.bp
|| !iso_td
.be
) {
727 trace_usb_ohci_iso_td_bad_bp_be(iso_td
.bp
, iso_td
.be
);
731 start_offset
= iso_td
.offset
[relative_frame_number
];
732 next_offset
= iso_td
.offset
[relative_frame_number
+ 1];
734 if (!(OHCI_BM(start_offset
, TD_PSW_CC
) & 0xe) ||
735 ((relative_frame_number
< frame_count
) &&
736 !(OHCI_BM(next_offset
, TD_PSW_CC
) & 0xe))) {
737 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset
, next_offset
);
741 if ((relative_frame_number
< frame_count
) && (start_offset
> next_offset
)) {
742 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset
, next_offset
);
746 if ((start_offset
& 0x1000) == 0) {
747 start_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
748 (start_offset
& OHCI_OFFSET_MASK
);
750 start_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
751 (start_offset
& OHCI_OFFSET_MASK
);
754 if (relative_frame_number
< frame_count
) {
755 end_offset
= next_offset
- 1;
756 if ((end_offset
& 0x1000) == 0) {
757 end_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
758 (end_offset
& OHCI_OFFSET_MASK
);
760 end_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
761 (end_offset
& OHCI_OFFSET_MASK
);
764 /* Last packet in the ISO TD */
765 end_addr
= iso_td
.be
;
768 if ((start_addr
& OHCI_PAGE_MASK
) != (end_addr
& OHCI_PAGE_MASK
)) {
769 len
= (end_addr
& OHCI_OFFSET_MASK
) + 0x1001
770 - (start_addr
& OHCI_OFFSET_MASK
);
772 len
= end_addr
- start_addr
+ 1;
775 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
776 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, len
,
777 DMA_DIRECTION_TO_DEVICE
)) {
784 bool int_req
= relative_frame_number
== frame_count
&&
785 OHCI_BM(iso_td
.flags
, TD_DI
) == 0;
786 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
788 trace_usb_ohci_td_dev_error();
791 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
792 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, false, int_req
);
793 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, len
);
794 usb_handle_packet(dev
, &ohci
->usb_packet
);
795 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
796 usb_device_flush_ep_queue(dev
, ep
);
800 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
801 ret
= ohci
->usb_packet
.actual_length
;
803 ret
= ohci
->usb_packet
.status
;
806 trace_usb_ohci_iso_td_so(start_offset
, end_offset
, start_addr
, end_addr
,
810 if (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && ret
<= len
) {
811 /* IN transfer succeeded */
812 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, ret
,
813 DMA_DIRECTION_FROM_DEVICE
)) {
817 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
819 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, ret
);
820 } else if (dir
== OHCI_TD_DIR_OUT
&& ret
== len
) {
821 /* OUT transfer succeeded */
822 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
824 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, 0);
826 if (ret
> (ssize_t
) len
) {
827 trace_usb_ohci_iso_td_data_overrun(ret
, len
);
828 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
829 OHCI_CC_DATAOVERRUN
);
830 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
832 } else if (ret
>= 0) {
833 trace_usb_ohci_iso_td_data_underrun(ret
);
834 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
835 OHCI_CC_DATAUNDERRUN
);
838 case USB_RET_IOERROR
:
840 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
841 OHCI_CC_DEVICENOTRESPONDING
);
842 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
847 trace_usb_ohci_iso_td_nak(ret
);
848 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
850 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
854 trace_usb_ohci_iso_td_bad_response(ret
);
855 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
856 OHCI_CC_UNDEXPETEDPID
);
862 if (relative_frame_number
== frame_count
) {
863 /* Last data packet of ISO TD - retire the TD to the Done Queue */
864 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
865 ed
->head
&= ~OHCI_DPTR_MASK
;
866 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
867 iso_td
.next
= ohci
->done
;
869 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
870 if (i
< ohci
->done_count
)
871 ohci
->done_count
= i
;
873 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
879 static void ohci_td_pkt(const char *msg
, const uint8_t *buf
, size_t len
)
883 const int width
= 16;
885 char tmp
[3 * width
+ 1];
888 print16
= !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT
);
889 printall
= !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL
);
891 if (!printall
&& !print16
) {
896 if (i
&& (!(i
% width
) || (i
== len
))) {
898 trace_usb_ohci_td_pkt_short(msg
, tmp
);
901 trace_usb_ohci_td_pkt_full(msg
, tmp
);
909 p
+= sprintf(p
, " %.2x", buf
[i
]);
913 /* Service a transport descriptor.
914 Returns nonzero to terminate processing of this endpoint. */
916 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
919 size_t len
= 0, pktlen
= 0;
920 const char *str
= NULL
;
931 addr
= ed
->head
& OHCI_DPTR_MASK
;
932 /* See if this TD has already been submitted to the device. */
933 completion
= (addr
== ohci
->async_td
);
934 if (completion
&& !ohci
->async_complete
) {
935 trace_usb_ohci_td_skip_async();
938 if (ohci_read_td(ohci
, addr
, &td
)) {
939 trace_usb_ohci_td_read_error(addr
);
944 dir
= OHCI_BM(ed
->flags
, ED_D
);
946 case OHCI_TD_DIR_OUT
:
951 dir
= OHCI_BM(td
.flags
, TD_DP
);
960 case OHCI_TD_DIR_OUT
:
964 case OHCI_TD_DIR_SETUP
:
966 pid
= USB_TOKEN_SETUP
;
969 trace_usb_ohci_td_bad_direction(dir
);
972 if (td
.cbp
&& td
.be
) {
973 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
974 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
976 len
= (td
.be
- td
.cbp
) + 1;
980 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
981 /* The endpoint may not allow us to transfer it all now */
982 pktlen
= (ed
->flags
& OHCI_ED_MPS_MASK
) >> OHCI_ED_MPS_SHIFT
;
987 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, pktlen
,
988 DMA_DIRECTION_TO_DEVICE
)) {
995 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
996 trace_usb_ohci_td_pkt_hdr(addr
, (int64_t)pktlen
, (int64_t)len
, str
,
997 flag_r
, td
.cbp
, td
.be
);
998 ohci_td_pkt("OUT", ohci
->usb_buf
, pktlen
);
1002 ohci
->async_complete
= false;
1004 if (ohci
->async_td
) {
1005 /* ??? The hardware should allow one active packet per
1006 endpoint. We only allow one active packet per controller.
1007 This should be sufficient as long as devices respond in a
1010 trace_usb_ohci_td_too_many_pending();
1013 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
1015 trace_usb_ohci_td_dev_error();
1018 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
1019 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, !flag_r
,
1020 OHCI_BM(td
.flags
, TD_DI
) == 0);
1021 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, pktlen
);
1022 usb_handle_packet(dev
, &ohci
->usb_packet
);
1023 trace_usb_ohci_td_packet_status(ohci
->usb_packet
.status
);
1025 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
1026 usb_device_flush_ep_queue(dev
, ep
);
1027 ohci
->async_td
= addr
;
1031 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
1032 ret
= ohci
->usb_packet
.actual_length
;
1034 ret
= ohci
->usb_packet
.status
;
1038 if (dir
== OHCI_TD_DIR_IN
) {
1039 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, ret
,
1040 DMA_DIRECTION_FROM_DEVICE
)) {
1043 ohci_td_pkt("IN", ohci
->usb_buf
, pktlen
);
1050 if (ret
== pktlen
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
1051 /* Transmission succeeded. */
1055 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
1056 td
.cbp
= (td
.be
& ~0xfff) + ((td
.cbp
+ ret
) & 0xfff);
1061 td
.flags
|= OHCI_TD_T1
;
1062 td
.flags
^= OHCI_TD_T0
;
1063 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
1064 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
1066 if ((dir
!= OHCI_TD_DIR_IN
) && (ret
!= len
)) {
1067 /* Partial packet transfer: TD not ready to retire yet */
1068 goto exit_no_retire
;
1071 /* Setting ED_C is part of the TD retirement process */
1072 ed
->head
&= ~OHCI_ED_C
;
1073 if (td
.flags
& OHCI_TD_T0
)
1074 ed
->head
|= OHCI_ED_C
;
1077 trace_usb_ohci_td_underrun();
1078 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
1081 case USB_RET_IOERROR
:
1083 trace_usb_ohci_td_dev_error();
1084 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
1087 trace_usb_ohci_td_nak();
1090 trace_usb_ohci_td_stall();
1091 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
1093 case USB_RET_BABBLE
:
1094 trace_usb_ohci_td_babble();
1095 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
1098 trace_usb_ohci_td_bad_device_response(ret
);
1099 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
1100 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
1103 /* An error occured so we have to clear the interrupt counter. See
1104 * spec at 6.4.4 on page 104 */
1105 ohci
->done_count
= 0;
1107 ed
->head
|= OHCI_ED_H
;
1110 /* Retire this TD */
1111 ed
->head
&= ~OHCI_DPTR_MASK
;
1112 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
1113 td
.next
= ohci
->done
;
1115 i
= OHCI_BM(td
.flags
, TD_DI
);
1116 if (i
< ohci
->done_count
)
1117 ohci
->done_count
= i
;
1119 if (ohci_put_td(ohci
, addr
, &td
)) {
1123 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
1126 /* Service an endpoint list. Returns nonzero if active TD were found. */
1127 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
, int completion
)
1133 uint32_t link_cnt
= 0;
1139 for (cur
= head
; cur
&& link_cnt
++ < ED_LINK_LIMIT
; cur
= next_ed
) {
1140 if (ohci_read_ed(ohci
, cur
, &ed
)) {
1141 trace_usb_ohci_ed_read_error(cur
);
1146 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
1148 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
1150 /* Cancel pending packets for ED that have been paused. */
1151 addr
= ed
.head
& OHCI_DPTR_MASK
;
1152 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
1153 usb_cancel_packet(&ohci
->usb_packet
);
1155 usb_device_ep_stopped(ohci
->usb_packet
.ep
->dev
,
1156 ohci
->usb_packet
.ep
);
1161 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
1162 trace_usb_ohci_ed_pkt(cur
, (ed
.head
& OHCI_ED_H
) != 0,
1163 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
1164 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
1165 trace_usb_ohci_ed_pkt_flags(
1166 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
1167 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
1168 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
1169 OHCI_BM(ed
.flags
, ED_MPS
));
1173 if ((ed
.flags
& OHCI_ED_F
) == 0) {
1174 if (ohci_service_td(ohci
, &ed
))
1177 /* Handle isochronous endpoints */
1178 if (ohci_service_iso_td(ohci
, &ed
, completion
))
1183 if (ohci_put_ed(ohci
, cur
, &ed
)) {
1192 /* set a timer for EOF */
1193 static void ohci_eof_timer(OHCIState
*ohci
)
1195 timer_mod(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
1197 /* Set a timer for EOF and generate a SOF event */
1198 static void ohci_sof(OHCIState
*ohci
)
1200 ohci
->sof_time
+= usb_frame_time
;
1201 ohci_eof_timer(ohci
);
1202 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
1205 /* Process Control and Bulk lists. */
1206 static void ohci_process_lists(OHCIState
*ohci
, int completion
)
1208 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
1209 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
) {
1210 trace_usb_ohci_process_lists(ohci
->ctrl_head
, ohci
->ctrl_cur
);
1212 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
, completion
)) {
1214 ohci
->status
&= ~OHCI_STATUS_CLF
;
1218 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
1219 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
, completion
)) {
1221 ohci
->status
&= ~OHCI_STATUS_BLF
;
1226 /* Do frame processing on frame boundary */
1227 static void ohci_frame_boundary(void *opaque
)
1229 OHCIState
*ohci
= opaque
;
1230 struct ohci_hcca hcca
;
1232 if (ohci_read_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1233 trace_usb_ohci_hcca_read_error(ohci
->hcca
);
1238 /* Process all the lists at the end of the frame */
1239 if (ohci
->ctl
& OHCI_CTL_PLE
) {
1242 n
= ohci
->frame_number
& 0x1f;
1243 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]), 0);
1246 /* Cancel all pending packets if either of the lists has been disabled. */
1247 if (ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
1248 if (ohci
->async_td
) {
1249 usb_cancel_packet(&ohci
->usb_packet
);
1252 ohci_stop_endpoints(ohci
);
1254 ohci
->old_ctl
= ohci
->ctl
;
1255 ohci_process_lists(ohci
, 0);
1257 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1258 if (ohci
->intr_status
& OHCI_INTR_UE
) {
1262 /* Frame boundary, so do EOF stuf here */
1263 ohci
->frt
= ohci
->fit
;
1265 /* Increment frame number and take care of endianness. */
1266 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
1267 hcca
.frame
= cpu_to_le16(ohci
->frame_number
);
1269 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
1272 if (ohci
->intr
& ohci
->intr_status
)
1274 hcca
.done
= cpu_to_le32(ohci
->done
);
1276 ohci
->done_count
= 7;
1277 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
1280 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
1283 /* Do SOF stuff here */
1286 /* Writeback HCCA */
1287 if (ohci_put_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1292 /* Start sending SOF tokens across the USB bus, lists are processed in
1295 static int ohci_bus_start(OHCIState
*ohci
)
1297 trace_usb_ohci_start(ohci
->name
);
1299 /* Delay the first SOF event by one frame time as
1300 * linux driver is not ready to receive it and
1301 * can meet some race conditions
1304 ohci
->sof_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1305 ohci_eof_timer(ohci
);
1310 /* Stop sending SOF tokens on the bus */
1311 void ohci_bus_stop(OHCIState
*ohci
)
1313 trace_usb_ohci_stop(ohci
->name
);
1314 timer_del(ohci
->eof_timer
);
1317 /* Sets a flag in a port status register but only set it if the port is
1318 * connected, if not set ConnectStatusChange flag. If flag is enabled
1321 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
1325 /* writing a 0 has no effect */
1329 /* If CurrentConnectStatus is cleared we set
1330 * ConnectStatusChange
1332 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
1333 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
1334 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
1335 /* TODO: CSC is a wakeup event */
1340 if (ohci
->rhport
[i
].ctrl
& val
)
1344 ohci
->rhport
[i
].ctrl
|= val
;
1349 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1350 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
1354 if (val
!= ohci
->fi
) {
1355 trace_usb_ohci_set_frame_interval(ohci
->name
, ohci
->fi
, ohci
->fi
);
1361 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
1364 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
1366 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
1373 /* Set HcControlRegister */
1374 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
1379 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1381 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1383 /* no state change */
1384 if (old_state
== new_state
)
1387 trace_usb_ohci_set_ctl(ohci
->name
, new_state
);
1388 switch (new_state
) {
1389 case OHCI_USB_OPERATIONAL
:
1390 ohci_bus_start(ohci
);
1392 case OHCI_USB_SUSPEND
:
1393 ohci_bus_stop(ohci
);
1394 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1395 ohci
->intr_status
&= ~OHCI_INTR_SF
;
1396 ohci_intr_update(ohci
);
1398 case OHCI_USB_RESUME
:
1399 trace_usb_ohci_resume(ohci
->name
);
1401 case OHCI_USB_RESET
:
1402 ohci_roothub_reset(ohci
);
1407 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
1412 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
1413 return (ohci
->frt
<< 31);
1415 /* Being in USB operational state guarnatees sof_time was
1418 tks
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - ohci
->sof_time
;
1423 /* avoid muldiv if possible */
1424 if (tks
>= usb_frame_time
)
1425 return (ohci
->frt
<< 31);
1427 tks
= tks
/ usb_bit_time
;
1428 fr
= (uint16_t)(ohci
->fi
- tks
);
1430 return (ohci
->frt
<< 31) | fr
;
1434 /* Set root hub status */
1435 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
1439 old_state
= ohci
->rhstatus
;
1441 /* write 1 to clear OCIC */
1442 if (val
& OHCI_RHS_OCIC
)
1443 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
1445 if (val
& OHCI_RHS_LPS
) {
1448 for (i
= 0; i
< ohci
->num_ports
; i
++)
1449 ohci_port_power(ohci
, i
, 0);
1450 trace_usb_ohci_hub_power_down();
1453 if (val
& OHCI_RHS_LPSC
) {
1456 for (i
= 0; i
< ohci
->num_ports
; i
++)
1457 ohci_port_power(ohci
, i
, 1);
1458 trace_usb_ohci_hub_power_up();
1461 if (val
& OHCI_RHS_DRWE
)
1462 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
1464 if (val
& OHCI_RHS_CRWE
)
1465 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
1467 if (old_state
!= ohci
->rhstatus
)
1468 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1471 /* Set root hub port status */
1472 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
1477 port
= &ohci
->rhport
[portnum
];
1478 old_state
= port
->ctrl
;
1480 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1481 if (val
& OHCI_PORT_WTC
)
1482 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1484 if (val
& OHCI_PORT_CCS
)
1485 port
->ctrl
&= ~OHCI_PORT_PES
;
1487 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1489 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
)) {
1490 trace_usb_ohci_port_suspend(portnum
);
1493 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1494 trace_usb_ohci_port_reset(portnum
);
1495 usb_device_reset(port
->port
.dev
);
1496 port
->ctrl
&= ~OHCI_PORT_PRS
;
1497 /* ??? Should this also set OHCI_PORT_PESC. */
1498 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1501 /* Invert order here to ensure in ambiguous case, device is
1504 if (val
& OHCI_PORT_LSDA
)
1505 ohci_port_power(ohci
, portnum
, 0);
1506 if (val
& OHCI_PORT_PPS
)
1507 ohci_port_power(ohci
, portnum
, 1);
1509 if (old_state
!= port
->ctrl
)
1510 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1513 static uint64_t ohci_mem_read(void *opaque
,
1517 OHCIState
*ohci
= opaque
;
1520 /* Only aligned reads are allowed on OHCI */
1522 trace_usb_ohci_mem_read_unaligned(addr
);
1524 } else if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1525 /* HcRhPortStatus */
1526 retval
= ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1528 switch (addr
>> 2) {
1529 case 0: /* HcRevision */
1533 case 1: /* HcControl */
1537 case 2: /* HcCommandStatus */
1538 retval
= ohci
->status
;
1541 case 3: /* HcInterruptStatus */
1542 retval
= ohci
->intr_status
;
1545 case 4: /* HcInterruptEnable */
1546 case 5: /* HcInterruptDisable */
1547 retval
= ohci
->intr
;
1550 case 6: /* HcHCCA */
1551 retval
= ohci
->hcca
;
1554 case 7: /* HcPeriodCurrentED */
1555 retval
= ohci
->per_cur
;
1558 case 8: /* HcControlHeadED */
1559 retval
= ohci
->ctrl_head
;
1562 case 9: /* HcControlCurrentED */
1563 retval
= ohci
->ctrl_cur
;
1566 case 10: /* HcBulkHeadED */
1567 retval
= ohci
->bulk_head
;
1570 case 11: /* HcBulkCurrentED */
1571 retval
= ohci
->bulk_cur
;
1574 case 12: /* HcDoneHead */
1575 retval
= ohci
->done
;
1578 case 13: /* HcFmInterretval */
1579 retval
= (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1582 case 14: /* HcFmRemaining */
1583 retval
= ohci_get_frame_remaining(ohci
);
1586 case 15: /* HcFmNumber */
1587 retval
= ohci
->frame_number
;
1590 case 16: /* HcPeriodicStart */
1591 retval
= ohci
->pstart
;
1594 case 17: /* HcLSThreshold */
1598 case 18: /* HcRhDescriptorA */
1599 retval
= ohci
->rhdesc_a
;
1602 case 19: /* HcRhDescriptorB */
1603 retval
= ohci
->rhdesc_b
;
1606 case 20: /* HcRhStatus */
1607 retval
= ohci
->rhstatus
;
1610 /* PXA27x specific registers */
1611 case 24: /* HcStatus */
1612 retval
= ohci
->hstatus
& ohci
->hmask
;
1615 case 25: /* HcHReset */
1616 retval
= ohci
->hreset
;
1619 case 26: /* HcHInterruptEnable */
1620 retval
= ohci
->hmask
;
1623 case 27: /* HcHInterruptTest */
1624 retval
= ohci
->htest
;
1628 trace_usb_ohci_mem_read_bad_offset(addr
);
1629 retval
= 0xffffffff;
1636 static void ohci_mem_write(void *opaque
,
1641 OHCIState
*ohci
= opaque
;
1643 /* Only aligned reads are allowed on OHCI */
1645 trace_usb_ohci_mem_write_unaligned(addr
);
1649 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1650 /* HcRhPortStatus */
1651 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1655 switch (addr
>> 2) {
1656 case 1: /* HcControl */
1657 ohci_set_ctl(ohci
, val
);
1660 case 2: /* HcCommandStatus */
1661 /* SOC is read-only */
1662 val
= (val
& ~OHCI_STATUS_SOC
);
1664 /* Bits written as '0' remain unchanged in the register */
1665 ohci
->status
|= val
;
1667 if (ohci
->status
& OHCI_STATUS_HCR
)
1668 ohci_soft_reset(ohci
);
1671 case 3: /* HcInterruptStatus */
1672 ohci
->intr_status
&= ~val
;
1673 ohci_intr_update(ohci
);
1676 case 4: /* HcInterruptEnable */
1678 ohci_intr_update(ohci
);
1681 case 5: /* HcInterruptDisable */
1683 ohci_intr_update(ohci
);
1686 case 6: /* HcHCCA */
1687 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1690 case 7: /* HcPeriodCurrentED */
1691 /* Ignore writes to this read-only register, Linux does them */
1694 case 8: /* HcControlHeadED */
1695 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1698 case 9: /* HcControlCurrentED */
1699 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1702 case 10: /* HcBulkHeadED */
1703 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1706 case 11: /* HcBulkCurrentED */
1707 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1710 case 13: /* HcFmInterval */
1711 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1712 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1713 ohci_set_frame_interval(ohci
, val
);
1716 case 15: /* HcFmNumber */
1719 case 16: /* HcPeriodicStart */
1720 ohci
->pstart
= val
& 0xffff;
1723 case 17: /* HcLSThreshold */
1724 ohci
->lst
= val
& 0xffff;
1727 case 18: /* HcRhDescriptorA */
1728 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1729 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1732 case 19: /* HcRhDescriptorB */
1735 case 20: /* HcRhStatus */
1736 ohci_set_hub_status(ohci
, val
);
1739 /* PXA27x specific registers */
1740 case 24: /* HcStatus */
1741 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1744 case 25: /* HcHReset */
1745 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1746 if (val
& OHCI_HRESET_FSBIR
)
1747 ohci_hard_reset(ohci
);
1750 case 26: /* HcHInterruptEnable */
1754 case 27: /* HcHInterruptTest */
1759 trace_usb_ohci_mem_write_bad_offset(addr
);
1764 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
)
1766 if (ohci
->async_td
&&
1767 usb_packet_is_inflight(&ohci
->usb_packet
) &&
1768 ohci
->usb_packet
.ep
->dev
== dev
) {
1769 usb_cancel_packet(&ohci
->usb_packet
);
1774 static const MemoryRegionOps ohci_mem_ops
= {
1775 .read
= ohci_mem_read
,
1776 .write
= ohci_mem_write
,
1777 .endianness
= DEVICE_LITTLE_ENDIAN
,
1780 static USBPortOps ohci_port_ops
= {
1781 .attach
= ohci_attach
,
1782 .detach
= ohci_detach
,
1783 .child_detach
= ohci_child_detach
,
1784 .wakeup
= ohci_wakeup
,
1785 .complete
= ohci_async_complete_packet
,
1788 static USBBusOps ohci_bus_ops
= {
1791 void usb_ohci_init(OHCIState
*ohci
, DeviceState
*dev
, uint32_t num_ports
,
1792 dma_addr_t localmem_base
, char *masterbus
,
1793 uint32_t firstport
, AddressSpace
*as
,
1794 void (*ohci_die_fn
)(struct OHCIState
*), Error
**errp
)
1800 ohci
->ohci_die
= ohci_die_fn
;
1802 if (num_ports
> OHCI_MAX_PORTS
) {
1803 error_setg(errp
, "OHCI num-ports=%u is too big (limit is %u ports)",
1804 num_ports
, OHCI_MAX_PORTS
);
1808 if (usb_frame_time
== 0) {
1809 #ifdef OHCI_TIME_WARP
1810 usb_frame_time
= NANOSECONDS_PER_SECOND
;
1811 usb_bit_time
= NANOSECONDS_PER_SECOND
/ (USB_HZ
/ 1000);
1813 usb_frame_time
= NANOSECONDS_PER_SECOND
/ 1000;
1814 if (NANOSECONDS_PER_SECOND
>= USB_HZ
) {
1815 usb_bit_time
= NANOSECONDS_PER_SECOND
/ USB_HZ
;
1820 trace_usb_ohci_init_time(usb_frame_time
, usb_bit_time
);
1823 ohci
->num_ports
= num_ports
;
1825 USBPort
*ports
[OHCI_MAX_PORTS
];
1826 for(i
= 0; i
< num_ports
; i
++) {
1827 ports
[i
] = &ohci
->rhport
[i
].port
;
1829 usb_register_companion(masterbus
, ports
, num_ports
,
1830 firstport
, ohci
, &ohci_port_ops
,
1831 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1834 error_propagate(errp
, err
);
1838 usb_bus_new(&ohci
->bus
, sizeof(ohci
->bus
), &ohci_bus_ops
, dev
);
1839 for (i
= 0; i
< num_ports
; i
++) {
1840 usb_register_port(&ohci
->bus
, &ohci
->rhport
[i
].port
,
1841 ohci
, i
, &ohci_port_ops
,
1842 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1846 memory_region_init_io(&ohci
->mem
, OBJECT(dev
), &ohci_mem_ops
,
1848 ohci
->localmem_base
= localmem_base
;
1850 ohci
->name
= object_get_typename(OBJECT(dev
));
1851 usb_packet_init(&ohci
->usb_packet
);
1855 ohci
->eof_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1856 ohci_frame_boundary
, ohci
);
1860 * A typical OHCI will stop operating and set itself into error state
1861 * (which can be queried by MMIO) to signal that it got an error.
1863 void ohci_sysbus_die(struct OHCIState
*ohci
)
1865 trace_usb_ohci_die();
1867 ohci_set_interrupt(ohci
, OHCI_INTR_UE
);
1868 ohci_bus_stop(ohci
);
1871 #define TYPE_SYSBUS_OHCI "sysbus-ohci"
1872 #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI)
1876 SysBusDevice parent_obj
;
1883 dma_addr_t dma_offset
;
1886 static void ohci_realize_pxa(DeviceState
*dev
, Error
**errp
)
1888 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
1889 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1892 usb_ohci_init(&s
->ohci
, dev
, s
->num_ports
, s
->dma_offset
,
1893 s
->masterbus
, s
->firstport
,
1894 &address_space_memory
, ohci_sysbus_die
, &err
);
1896 error_propagate(errp
, err
);
1899 sysbus_init_irq(sbd
, &s
->ohci
.irq
);
1900 sysbus_init_mmio(sbd
, &s
->ohci
.mem
);
1903 static void usb_ohci_reset_sysbus(DeviceState
*dev
)
1905 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
1906 OHCIState
*ohci
= &s
->ohci
;
1908 ohci_hard_reset(ohci
);
1911 static const VMStateDescription vmstate_ohci_state_port
= {
1912 .name
= "ohci-core/port",
1914 .minimum_version_id
= 1,
1915 .fields
= (VMStateField
[]) {
1916 VMSTATE_UINT32(ctrl
, OHCIPort
),
1917 VMSTATE_END_OF_LIST()
1921 static bool ohci_eof_timer_needed(void *opaque
)
1923 OHCIState
*ohci
= opaque
;
1925 return timer_pending(ohci
->eof_timer
);
1928 static const VMStateDescription vmstate_ohci_eof_timer
= {
1929 .name
= "ohci-core/eof-timer",
1931 .minimum_version_id
= 1,
1932 .needed
= ohci_eof_timer_needed
,
1933 .fields
= (VMStateField
[]) {
1934 VMSTATE_TIMER_PTR(eof_timer
, OHCIState
),
1935 VMSTATE_END_OF_LIST()
1939 const VMStateDescription vmstate_ohci_state
= {
1940 .name
= "ohci-core",
1942 .minimum_version_id
= 1,
1943 .fields
= (VMStateField
[]) {
1944 VMSTATE_INT64(sof_time
, OHCIState
),
1945 VMSTATE_UINT32(ctl
, OHCIState
),
1946 VMSTATE_UINT32(status
, OHCIState
),
1947 VMSTATE_UINT32(intr_status
, OHCIState
),
1948 VMSTATE_UINT32(intr
, OHCIState
),
1949 VMSTATE_UINT32(hcca
, OHCIState
),
1950 VMSTATE_UINT32(ctrl_head
, OHCIState
),
1951 VMSTATE_UINT32(ctrl_cur
, OHCIState
),
1952 VMSTATE_UINT32(bulk_head
, OHCIState
),
1953 VMSTATE_UINT32(bulk_cur
, OHCIState
),
1954 VMSTATE_UINT32(per_cur
, OHCIState
),
1955 VMSTATE_UINT32(done
, OHCIState
),
1956 VMSTATE_INT32(done_count
, OHCIState
),
1957 VMSTATE_UINT16(fsmps
, OHCIState
),
1958 VMSTATE_UINT8(fit
, OHCIState
),
1959 VMSTATE_UINT16(fi
, OHCIState
),
1960 VMSTATE_UINT8(frt
, OHCIState
),
1961 VMSTATE_UINT16(frame_number
, OHCIState
),
1962 VMSTATE_UINT16(padding
, OHCIState
),
1963 VMSTATE_UINT32(pstart
, OHCIState
),
1964 VMSTATE_UINT32(lst
, OHCIState
),
1965 VMSTATE_UINT32(rhdesc_a
, OHCIState
),
1966 VMSTATE_UINT32(rhdesc_b
, OHCIState
),
1967 VMSTATE_UINT32(rhstatus
, OHCIState
),
1968 VMSTATE_STRUCT_ARRAY(rhport
, OHCIState
, OHCI_MAX_PORTS
, 0,
1969 vmstate_ohci_state_port
, OHCIPort
),
1970 VMSTATE_UINT32(hstatus
, OHCIState
),
1971 VMSTATE_UINT32(hmask
, OHCIState
),
1972 VMSTATE_UINT32(hreset
, OHCIState
),
1973 VMSTATE_UINT32(htest
, OHCIState
),
1974 VMSTATE_UINT32(old_ctl
, OHCIState
),
1975 VMSTATE_UINT8_ARRAY(usb_buf
, OHCIState
, 8192),
1976 VMSTATE_UINT32(async_td
, OHCIState
),
1977 VMSTATE_BOOL(async_complete
, OHCIState
),
1978 VMSTATE_END_OF_LIST()
1980 .subsections
= (const VMStateDescription
*[]) {
1981 &vmstate_ohci_eof_timer
,
1986 static Property ohci_sysbus_properties
[] = {
1987 DEFINE_PROP_STRING("masterbus", OHCISysBusState
, masterbus
),
1988 DEFINE_PROP_UINT32("num-ports", OHCISysBusState
, num_ports
, 3),
1989 DEFINE_PROP_UINT32("firstport", OHCISysBusState
, firstport
, 0),
1990 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState
, dma_offset
, 0),
1991 DEFINE_PROP_END_OF_LIST(),
1994 static void ohci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1996 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1998 dc
->realize
= ohci_realize_pxa
;
1999 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
2000 dc
->desc
= "OHCI USB Controller";
2001 dc
->props
= ohci_sysbus_properties
;
2002 dc
->reset
= usb_ohci_reset_sysbus
;
2005 static const TypeInfo ohci_sysbus_info
= {
2006 .name
= TYPE_SYSBUS_OHCI
,
2007 .parent
= TYPE_SYS_BUS_DEVICE
,
2008 .instance_size
= sizeof(OHCISysBusState
),
2009 .class_init
= ohci_sysbus_class_init
,
2012 static void ohci_register_types(void)
2014 type_register_static(&ohci_sysbus_info
);
2017 type_init(ohci_register_types
)