hw/timer/pxa2xx_timer.c

   1 /*
   2  * Intel XScale PXA255/270 OS Timers.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/hw.h"
  12 #include "qemu/timer.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/arm/pxa.h"
  15 #include "hw/sysbus.h"
  16 #include "qemu/log.h"
  17 #include "qemu/module.h"
  18
  19 #define OSMR0   0x00
  20 #define OSMR1   0x04
  21 #define OSMR2   0x08
  22 #define OSMR3   0x0c
  23 #define OSMR4   0x80
  24 #define OSMR5   0x84
  25 #define OSMR6   0x88
  26 #define OSMR7   0x8c
  27 #define OSMR8   0x90
  28 #define OSMR9   0x94
  29 #define OSMR10  0x98
  30 #define OSMR11  0x9c
  31 #define OSCR    0x10    /* OS Timer Count */
  32 #define OSCR4   0x40
  33 #define OSCR5   0x44
  34 #define OSCR6   0x48
  35 #define OSCR7   0x4c
  36 #define OSCR8   0x50
  37 #define OSCR9   0x54
  38 #define OSCR10  0x58
  39 #define OSCR11  0x5c
  40 #define OSSR    0x14    /* Timer status register */
  41 #define OWER    0x18
  42 #define OIER    0x1c    /* Interrupt enable register  3-0 to E3-E0 */
  43 #define OMCR4   0xc0    /* OS Match Control registers */
  44 #define OMCR5   0xc4
  45 #define OMCR6   0xc8
  46 #define OMCR7   0xcc
  47 #define OMCR8   0xd0
  48 #define OMCR9   0xd4
  49 #define OMCR10  0xd8
  50 #define OMCR11  0xdc
  51 #define OSNR    0x20
  52
  53 #define PXA25X_FREQ     3686400 /* 3.6864 MHz */
  54 #define PXA27X_FREQ     3250000 /* 3.25 MHz */
  55
  56 static int pxa2xx_timer4_freq[8] = {
  57     [0] = 0,
  58     [1] = 32768,
  59     [2] = 1000,
  60     [3] = 1,
  61     [4] = 1000000,
  62     /* [5] is the "Externally supplied clock".  Assign if necessary.  */
  63     [5 ... 7] = 0,
  64 };
  65
  66 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
  67 #define PXA2XX_TIMER(obj) \
  68     OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
  69
  70 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
  71
  72 typedef struct {
  73     uint32_t value;
  74     qemu_irq irq;
  75     QEMUTimer *qtimer;
  76     int num;
  77     PXA2xxTimerInfo *info;
  78 } PXA2xxTimer0;
  79
  80 typedef struct {
  81     PXA2xxTimer0 tm;
  82     int32_t oldclock;
  83     int32_t clock;
  84     uint64_t lastload;
  85     uint32_t freq;
  86     uint32_t control;
  87 } PXA2xxTimer4;
  88
  89 struct PXA2xxTimerInfo {
  90     SysBusDevice parent_obj;
  91
  92     MemoryRegion iomem;
  93     uint32_t flags;
  94
  95     int32_t clock;
  96     int32_t oldclock;
  97     uint64_t lastload;
  98     uint32_t freq;
  99     PXA2xxTimer0 timer[4];
 100     uint32_t events;
 101     uint32_t irq_enabled;
 102     uint32_t reset3;
 103     uint32_t snapshot;
 104
 105     qemu_irq irq4;
 106     PXA2xxTimer4 tm4[8];
 107 };
 108
 109 #define PXA2XX_TIMER_HAVE_TM4   0
 110
 111 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
 112 {
 113     return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
 114 }
 115
 116 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
 117 {
 118     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 119     int i;
 120     uint32_t now_vm;
 121     uint64_t new_qemu;
 122
 123     now_vm = s->clock +
 124             muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 125
 126     for (i = 0; i < 4; i ++) {
 127         new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
 128                         NANOSECONDS_PER_SECOND, s->freq);
 129         timer_mod(s->timer[i].qtimer, new_qemu);
 130     }
 131 }
 132
 133 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
 134 {
 135     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 136     uint32_t now_vm;
 137     uint64_t new_qemu;
 138     static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
 139     int counter;
 140
 141     if (s->tm4[n].control & (1 << 7))
 142         counter = n;
 143     else
 144         counter = counters[n];
 145
 146     if (!s->tm4[counter].freq) {
 147         timer_del(s->tm4[n].tm.qtimer);
 148         return;
 149     }
 150
 151     now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
 152                     s->tm4[counter].lastload,
 153                     s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
 154
 155     new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
 156                     NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
 157     timer_mod(s->tm4[n].tm.qtimer, new_qemu);
 158 }
 159
 160 static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
 161                                   unsigned size)
 162 {
 163     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 164     int tm = 0;
 165
 166     switch (offset) {
 167     case OSMR3:  tm ++;
 168         /* fall through */
 169     case OSMR2:  tm ++;
 170         /* fall through */
 171     case OSMR1:  tm ++;
 172         /* fall through */
 173     case OSMR0:
 174         return s->timer[tm].value;
 175     case OSMR11: tm ++;
 176         /* fall through */
 177     case OSMR10: tm ++;
 178         /* fall through */
 179     case OSMR9:  tm ++;
 180         /* fall through */
 181     case OSMR8:  tm ++;
 182         /* fall through */
 183     case OSMR7:  tm ++;
 184         /* fall through */
 185     case OSMR6:  tm ++;
 186         /* fall through */
 187     case OSMR5:  tm ++;
 188         /* fall through */
 189     case OSMR4:
 190         if (!pxa2xx_timer_has_tm4(s))
 191             goto badreg;
 192         return s->tm4[tm].tm.value;
 193     case OSCR:
 194         return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 195                         s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 196     case OSCR11: tm ++;
 197         /* fall through */
 198     case OSCR10: tm ++;
 199         /* fall through */
 200     case OSCR9:  tm ++;
 201         /* fall through */
 202     case OSCR8:  tm ++;
 203         /* fall through */
 204     case OSCR7:  tm ++;
 205         /* fall through */
 206     case OSCR6:  tm ++;
 207         /* fall through */
 208     case OSCR5:  tm ++;
 209         /* fall through */
 210     case OSCR4:
 211         if (!pxa2xx_timer_has_tm4(s))
 212             goto badreg;
 213
 214         if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
 215             if (s->tm4[tm - 1].freq)
 216                 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
 217                                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 218                                 s->tm4[tm - 1].lastload,
 219                                 s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
 220             else
 221                 s->snapshot = s->tm4[tm - 1].clock;
 222         }
 223
 224         if (!s->tm4[tm].freq)
 225             return s->tm4[tm].clock;
 226         return s->tm4[tm].clock +
 227             muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 228                      s->tm4[tm].lastload, s->tm4[tm].freq,
 229                      NANOSECONDS_PER_SECOND);
 230     case OIER:
 231         return s->irq_enabled;
 232     case OSSR:  /* Status register */
 233         return s->events;
 234     case OWER:
 235         return s->reset3;
 236     case OMCR11: tm ++;
 237         /* fall through */
 238     case OMCR10: tm ++;
 239         /* fall through */
 240     case OMCR9:  tm ++;
 241         /* fall through */
 242     case OMCR8:  tm ++;
 243         /* fall through */
 244     case OMCR7:  tm ++;
 245         /* fall through */
 246     case OMCR6:  tm ++;
 247         /* fall through */
 248     case OMCR5:  tm ++;
 249         /* fall through */
 250     case OMCR4:
 251         if (!pxa2xx_timer_has_tm4(s))
 252             goto badreg;
 253         return s->tm4[tm].control;
 254     case OSNR:
 255         return s->snapshot;
 256     default:
 257         qemu_log_mask(LOG_UNIMP,
 258                       "%s: unknown register 0x%02" HWADDR_PRIx "\n",
 259                       __func__, offset);
 260         break;
 261     badreg:
 262         qemu_log_mask(LOG_GUEST_ERROR,
 263                       "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
 264                       __func__, offset);
 265     }
 266
 267     return 0;
 268 }
 269
 270 static void pxa2xx_timer_write(void *opaque, hwaddr offset,
 271                                uint64_t value, unsigned size)
 272 {
 273     int i, tm = 0;
 274     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 275
 276     switch (offset) {
 277     case OSMR3:  tm ++;
 278         /* fall through */
 279     case OSMR2:  tm ++;
 280         /* fall through */
 281     case OSMR1:  tm ++;
 282         /* fall through */
 283     case OSMR0:
 284         s->timer[tm].value = value;
 285         pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 286         break;
 287     case OSMR11: tm ++;
 288         /* fall through */
 289     case OSMR10: tm ++;
 290         /* fall through */
 291     case OSMR9:  tm ++;
 292         /* fall through */
 293     case OSMR8:  tm ++;
 294         /* fall through */
 295     case OSMR7:  tm ++;
 296         /* fall through */
 297     case OSMR6:  tm ++;
 298         /* fall through */
 299     case OSMR5:  tm ++;
 300         /* fall through */
 301     case OSMR4:
 302         if (!pxa2xx_timer_has_tm4(s))
 303             goto badreg;
 304         s->tm4[tm].tm.value = value;
 305         pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 306         break;
 307     case OSCR:
 308         s->oldclock = s->clock;
 309         s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 310         s->clock = value;
 311         pxa2xx_timer_update(s, s->lastload);
 312         break;
 313     case OSCR11: tm ++;
 314         /* fall through */
 315     case OSCR10: tm ++;
 316         /* fall through */
 317     case OSCR9:  tm ++;
 318         /* fall through */
 319     case OSCR8:  tm ++;
 320         /* fall through */
 321     case OSCR7:  tm ++;
 322         /* fall through */
 323     case OSCR6:  tm ++;
 324         /* fall through */
 325     case OSCR5:  tm ++;
 326         /* fall through */
 327     case OSCR4:
 328         if (!pxa2xx_timer_has_tm4(s))
 329             goto badreg;
 330         s->tm4[tm].oldclock = s->tm4[tm].clock;
 331         s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 332         s->tm4[tm].clock = value;
 333         pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
 334         break;
 335     case OIER:
 336         s->irq_enabled = value & 0xfff;
 337         break;
 338     case OSSR:  /* Status register */
 339         value &= s->events;
 340         s->events &= ~value;
 341         for (i = 0; i < 4; i ++, value >>= 1)
 342             if (value & 1)
 343                 qemu_irq_lower(s->timer[i].irq);
 344         if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
 345             qemu_irq_lower(s->irq4);
 346         break;
 347     case OWER:  /* XXX: Reset on OSMR3 match? */
 348         s->reset3 = value;
 349         break;
 350     case OMCR7:  tm ++;
 351         /* fall through */
 352     case OMCR6:  tm ++;
 353         /* fall through */
 354     case OMCR5:  tm ++;
 355         /* fall through */
 356     case OMCR4:
 357         if (!pxa2xx_timer_has_tm4(s))
 358             goto badreg;
 359         s->tm4[tm].control = value & 0x0ff;
 360         /* XXX Stop if running (shouldn't happen) */
 361         if ((value & (1 << 7)) || tm == 0)
 362             s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
 363         else {
 364             s->tm4[tm].freq = 0;
 365             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 366         }
 367         break;
 368     case OMCR11: tm ++;
 369         /* fall through */
 370     case OMCR10: tm ++;
 371         /* fall through */
 372     case OMCR9:  tm ++;
 373         /* fall through */
 374     case OMCR8:  tm += 4;
 375         if (!pxa2xx_timer_has_tm4(s))
 376             goto badreg;
 377         s->tm4[tm].control = value & 0x3ff;
 378         /* XXX Stop if running (shouldn't happen) */
 379         if ((value & (1 << 7)) || !(tm & 1))
 380             s->tm4[tm].freq =
 381                     pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
 382         else {
 383             s->tm4[tm].freq = 0;
 384             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 385         }
 386         break;
 387     default:
 388         qemu_log_mask(LOG_UNIMP,
 389                       "%s: unknown register 0x%02" HWADDR_PRIx " "
 390                       "(value 0x%08" PRIx64 ")\n",  __func__, offset, value);
 391         break;
 392     badreg:
 393         qemu_log_mask(LOG_GUEST_ERROR,
 394                       "%s: incorrect register 0x%02" HWADDR_PRIx " "
 395                       "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
 396     }
 397 }
 398
 399 static const MemoryRegionOps pxa2xx_timer_ops = {
 400     .read = pxa2xx_timer_read,
 401     .write = pxa2xx_timer_write,
 402     .endianness = DEVICE_NATIVE_ENDIAN,
 403 };
 404
 405 static void pxa2xx_timer_tick(void *opaque)
 406 {
 407     PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
 408     PXA2xxTimerInfo *i = t->info;
 409
 410     if (i->irq_enabled & (1 << t->num)) {
 411         i->events |= 1 << t->num;
 412         qemu_irq_raise(t->irq);
 413     }
 414
 415     if (t->num == 3)
 416         if (i->reset3 & 1) {
 417             i->reset3 = 0;
 418             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 419         }
 420 }
 421
 422 static void pxa2xx_timer_tick4(void *opaque)
 423 {
 424     PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
 425     PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
 426
 427     pxa2xx_timer_tick(&t->tm);
 428     if (t->control & (1 << 3))
 429         t->clock = 0;
 430     if (t->control & (1 << 6))
 431         pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
 432     if (i->events & 0xff0)
 433         qemu_irq_raise(i->irq4);
 434 }
 435
 436 static int pxa25x_timer_post_load(void *opaque, int version_id)
 437 {
 438     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 439     int64_t now;
 440     int i;
 441
 442     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 443     pxa2xx_timer_update(s, now);
 444
 445     if (pxa2xx_timer_has_tm4(s))
 446         for (i = 0; i < 8; i ++)
 447             pxa2xx_timer_update4(s, now, i);
 448
 449     return 0;
 450 }
 451
 452 static void pxa2xx_timer_init(Object *obj)
 453 {
 454     PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
 455     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 456
 457     s->irq_enabled = 0;
 458     s->oldclock = 0;
 459     s->clock = 0;
 460     s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 461     s->reset3 = 0;
 462
 463     memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
 464                           "pxa2xx-timer", 0x00001000);
 465     sysbus_init_mmio(dev, &s->iomem);
 466 }
 467
 468 static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
 469 {
 470     PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
 471     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 472     int i;
 473
 474     for (i = 0; i < 4; i ++) {
 475         s->timer[i].value = 0;
 476         sysbus_init_irq(sbd, &s->timer[i].irq);
 477         s->timer[i].info = s;
 478         s->timer[i].num = i;
 479         s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 480                                           pxa2xx_timer_tick, &s->timer[i]);
 481     }
 482
 483     if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
 484         sysbus_init_irq(sbd, &s->irq4);
 485
 486         for (i = 0; i < 8; i ++) {
 487             s->tm4[i].tm.value = 0;
 488             s->tm4[i].tm.info = s;
 489             s->tm4[i].tm.num = i + 4;
 490             s->tm4[i].freq = 0;
 491             s->tm4[i].control = 0x0;
 492             s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 493                                                pxa2xx_timer_tick4, &s->tm4[i]);
 494         }
 495     }
 496 }
 497
 498 static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
 499     .name = "pxa2xx_timer0",
 500     .version_id = 2,
 501     .minimum_version_id = 2,
 502     .fields = (VMStateField[]) {
 503         VMSTATE_UINT32(value, PXA2xxTimer0),
 504         VMSTATE_END_OF_LIST(),
 505     },
 506 };
 507
 508 static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
 509     .name = "pxa2xx_timer4",
 510     .version_id = 1,
 511     .minimum_version_id = 1,
 512     .fields = (VMStateField[]) {
 513         VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
 514                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 515         VMSTATE_INT32(oldclock, PXA2xxTimer4),
 516         VMSTATE_INT32(clock, PXA2xxTimer4),
 517         VMSTATE_UINT64(lastload, PXA2xxTimer4),
 518         VMSTATE_UINT32(freq, PXA2xxTimer4),
 519         VMSTATE_UINT32(control, PXA2xxTimer4),
 520         VMSTATE_END_OF_LIST(),
 521     },
 522 };
 523
 524 static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
 525 {
 526     return pxa2xx_timer_has_tm4(opaque);
 527 }
 528
 529 static const VMStateDescription vmstate_pxa2xx_timer_regs = {
 530     .name = "pxa2xx_timer",
 531     .version_id = 1,
 532     .minimum_version_id = 1,
 533     .post_load = pxa25x_timer_post_load,
 534     .fields = (VMStateField[]) {
 535         VMSTATE_INT32(clock, PXA2xxTimerInfo),
 536         VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
 537         VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
 538         VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
 539                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 540         VMSTATE_UINT32(events, PXA2xxTimerInfo),
 541         VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
 542         VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
 543         VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
 544         VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
 545                         pxa2xx_timer_has_tm4_test, 0,
 546                         vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
 547         VMSTATE_END_OF_LIST(),
 548     }
 549 };
 550
 551 static Property pxa25x_timer_dev_properties[] = {
 552     DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
 553     DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 554                     PXA2XX_TIMER_HAVE_TM4, false),
 555     DEFINE_PROP_END_OF_LIST(),
 556 };
 557
 558 static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
 559 {
 560     DeviceClass *dc = DEVICE_CLASS(klass);
 561
 562     dc->desc = "PXA25x timer";
 563     dc->props = pxa25x_timer_dev_properties;
 564 }
 565
 566 static const TypeInfo pxa25x_timer_dev_info = {
 567     .name          = "pxa25x-timer",
 568     .parent        = TYPE_PXA2XX_TIMER,
 569     .instance_size = sizeof(PXA2xxTimerInfo),
 570     .class_init    = pxa25x_timer_dev_class_init,
 571 };
 572
 573 static Property pxa27x_timer_dev_properties[] = {
 574     DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
 575     DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 576                     PXA2XX_TIMER_HAVE_TM4, true),
 577     DEFINE_PROP_END_OF_LIST(),
 578 };
 579
 580 static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
 581 {
 582     DeviceClass *dc = DEVICE_CLASS(klass);
 583
 584     dc->desc = "PXA27x timer";
 585     dc->props = pxa27x_timer_dev_properties;
 586 }
 587
 588 static const TypeInfo pxa27x_timer_dev_info = {
 589     .name          = "pxa27x-timer",
 590     .parent        = TYPE_PXA2XX_TIMER,
 591     .instance_size = sizeof(PXA2xxTimerInfo),
 592     .class_init    = pxa27x_timer_dev_class_init,
 593 };
 594
 595 static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
 596 {
 597     DeviceClass *dc = DEVICE_CLASS(oc);
 598
 599     dc->realize  = pxa2xx_timer_realize;
 600     dc->vmsd = &vmstate_pxa2xx_timer_regs;
 601 }
 602
 603 static const TypeInfo pxa2xx_timer_type_info = {
 604     .name          = TYPE_PXA2XX_TIMER,
 605     .parent        = TYPE_SYS_BUS_DEVICE,
 606     .instance_size = sizeof(PXA2xxTimerInfo),
 607     .instance_init = pxa2xx_timer_init,
 608     .abstract      = true,
 609     .class_init    = pxa2xx_timer_class_init,
 610 };
 611
 612 static void pxa2xx_timer_register_types(void)
 613 {
 614     type_register_static(&pxa2xx_timer_type_info);
 615     type_register_static(&pxa25x_timer_dev_info);
 616     type_register_static(&pxa27x_timer_dev_info);
 617 }
 618
 619 type_init(pxa2xx_timer_register_types)