include/hw/arm/raspi_platform.h

   1 /*
   2  * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
   3  *
   4  * These definitions are derived from those in Linux at
   5  * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
   6  * where they carry the following notice:
   7  */
   8
   9 /*
  10  * arch/arm/mach-bcm2708/include/mach/platform.h
  11  *
  12  * Copyright (C) 2010 Broadcom
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27  */
  28
  29 /* Peripheral base address on the VC (GPU) system bus */
  30 #define BCM2835_VC_PERI_BASE 0x7e000000
  31
  32 /* Peripheral base addresses seen by the CPU: Pi1 and Pi2 differ */
  33 #define BCM2835_PERI_BASE       0x20000000
  34 #define BCM2836_PERI_BASE       0x3F000000
  35
  36 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
  37 #define BCM2836_CONTROL_BASE    0x40000000
  38
  39 #define MCORE_OFFSET            0x0000   /* Fake frame buffer device
  40                                           * (the multicore sync block) */
  41 #define IC0_OFFSET              0x2000
  42 #define ST_OFFSET               0x3000   /* System Timer */
  43 #define MPHI_OFFSET             0x6000   /* Message-based Parallel Host Intf. */
  44 #define DMA_OFFSET              0x7000   /* DMA controller */
  45 #define ARM_OFFSET              0xB000   /* BCM2708 ARM control block */
  46 #define ARMCTRL_OFFSET          (ARM_OFFSET + 0x000)
  47 #define ARMCTRL_IC_OFFSET       (ARM_OFFSET + 0x200) /* Interrupt controller */
  48 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
  49 #define ARMCTRL_0_SBM_OFFSET    (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
  50                                                       * Doorbells & Mailboxes */
  51 #define PM_OFFSET               0x100000 /* Power Management, Reset controller
  52                                           * and Watchdog registers */
  53 #define PCM_CLOCK_OFFSET        0x101098 /* PCM Clock */
  54 #define RNG_OFFSET              0x104000 /* Hardware RNG */
  55 #define GPIO_OFFSET             0x200000 /* GPIO */
  56 #define UART0_OFFSET            0x201000 /* Uart 0 */
  57 #define MMCI0_OFFSET            0x202000 /* MMC interface */
  58 #define I2S_OFFSET              0x203000 /* I2S */
  59 #define SPI0_OFFSET             0x204000 /* SPI0 */
  60 #define BSC0_OFFSET             0x205000 /* BSC0 I2C/TWI */
  61 #define UART1_OFFSET            0x215000 /* Uart 1 */
  62 #define EMMC_OFFSET             0x300000 /* eMMC interface */
  63 #define SMI_OFFSET              0x600000 /* SMI */
  64 #define BSC1_OFFSET             0x804000 /* BSC1 I2C/TWI */
  65 #define USB_OFFSET              0x980000 /* DTC_OTG USB controller */
  66
  67 /*
  68  * Interrupt assignments
  69  */
  70
  71 #define ARM_IRQ1_BASE                  0
  72 #define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
  73 #define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
  74 #define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
  75 #define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
  76 #define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
  77 #define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
  78 #define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
  79 #define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
  80 #define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
  81 #define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
  82 #define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
  83 #define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
  84 #define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
  85 #define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
  86 #define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
  87 #define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
  88 #define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
  89 #define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
  90 #define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
  91 #define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
  92 #define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
  93 #define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
  94 #define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
  95 #define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
  96 #define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
  97 #define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
  98 #define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
  99 #define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
 100 #define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
 101 #define INTERRUPT_AUX                  (ARM_IRQ1_BASE + 29)
 102 #define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
 103 #define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
 104
 105 #define ARM_IRQ2_BASE                  32
 106 #define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
 107 #define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
 108 #define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
 109 #define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
 110 #define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
 111 #define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
 112 #define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
 113 #define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
 114 #define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
 115 #define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
 116 #define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
 117 #define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
 118 #define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
 119 #define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
 120 #define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
 121 #define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
 122 #define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
 123 #define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
 124 #define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
 125 #define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
 126 #define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
 127 #define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
 128 #define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
 129 #define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
 130 #define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
 131 #define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
 132 #define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
 133 #define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
 134 #define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
 135 #define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
 136 #define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
 137 #define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
 138
 139 #define ARM_IRQ0_BASE                  64
 140 #define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
 141 #define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
 142 #define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
 143 #define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
 144 #define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
 145 #define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
 146 #define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
 147 #define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
 148 #define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
 149 #define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
 150 #define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
 151 #define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
 152 #define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
 153 #define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
 154 #define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
 155 #define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
 156 #define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
 157 #define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
 158 #define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
 159 #define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
 160 #define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)