hw/dma/bcm2835_dma.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * This code is licensed under the GNU GPLv2 and later.
   4  */
   5
   6 #include "hw/sysbus.h"
   7 #include "exec/address-spaces.h"
   8
   9 // XXX: FIXME:
  10 extern AddressSpace *bcm2835_peripheral_as;
  11
  12 /* DMA CS Control and Status bits */
  13 #define BCM2708_DMA_ACTIVE      (1 << 0)
  14 #define BCM2708_DMA_INT         (1 << 2)
  15 #define BCM2708_DMA_ISPAUSED    (1 << 4)  /* Pause requested or not active */
  16 #define BCM2708_DMA_ISHELD      (1 << 5)  /* Is held by DREQ flow control */
  17 #define BCM2708_DMA_ERR         (1 << 8)
  18 #define BCM2708_DMA_ABORT       (1 << 30) /* stop current CB, go to next, WO */
  19 #define BCM2708_DMA_RESET       (1 << 31) /* WO, self clearing */
  20
  21 #define BCM2708_DMA_END         (1 << 1) /* GE */
  22
  23 /* DMA control block "info" field bits */
  24 #define BCM2708_DMA_INT_EN      (1 << 0)
  25 #define BCM2708_DMA_TDMODE      (1 << 1)
  26 #define BCM2708_DMA_WAIT_RESP   (1 << 3)
  27 #define BCM2708_DMA_D_INC       (1 << 4)
  28 #define BCM2708_DMA_D_WIDTH     (1 << 5)
  29 #define BCM2708_DMA_D_DREQ      (1 << 6)
  30 #define BCM2708_DMA_S_INC       (1 << 8)
  31 #define BCM2708_DMA_S_WIDTH     (1 << 9)
  32 #define BCM2708_DMA_S_DREQ      (1 << 10)
  33
  34 #define BCM2708_DMA_BURST(x)    (((x)&0xf) << 12)
  35 #define BCM2708_DMA_PER_MAP(x)  ((x) << 16)
  36 #define BCM2708_DMA_WAITS(x)    (((x)&0x1f) << 21)
  37
  38 #define BCM2708_DMA_DREQ_EMMC   11
  39 #define BCM2708_DMA_DREQ_SDHOST 13
  40
  41 #define BCM2708_DMA_CS          0x00 /* Control and Status */
  42 #define BCM2708_DMA_ADDR        0x04
  43 /* the current control block appears in the following registers - read only */
  44 #define BCM2708_DMA_INFO        0x08
  45 #define BCM2708_DMA_NEXTCB      0x1C
  46 #define BCM2708_DMA_DEBUG       0x20
  47
  48 #define BCM2708_DMA4_CS         (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
  49 #define BCM2708_DMA4_ADDR       (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
  50
  51 #define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
  52
  53 typedef struct {
  54     uint32_t cs;
  55     uint32_t conblk_ad;
  56     uint32_t ti;
  57     uint32_t source_ad;
  58     uint32_t dest_ad;
  59     uint32_t txfr_len;
  60     uint32_t stride;
  61     uint32_t nextconbk;
  62     uint32_t debug;
  63
  64     qemu_irq irq;
  65 } DmaChan;
  66
  67 #define TYPE_BCM2835_DMA "bcm2835_dma"
  68 #define BCM2835_DMA(obj) \
  69         OBJECT_CHECK(Bcm2835DmaState, (obj), TYPE_BCM2835_DMA)
  70
  71 typedef struct {
  72     SysBusDevice busdev;
  73     MemoryRegion iomem0_14;
  74     MemoryRegion iomem15;
  75
  76     DmaChan chan[16];
  77     uint32_t int_status;
  78     uint32_t enable;
  79
  80 } Bcm2835DmaState;
  81
  82
  83 static void bcm2835_dma_update(Bcm2835DmaState *s, int c)
  84 {
  85     DmaChan *ch = &s->chan[c];
  86     uint32_t data;
  87
  88     if (!(s->enable & (1 << c))) {
  89         return;
  90     }
  91
  92     while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
  93         /* CB fetch */
  94         ch->ti = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad);
  95         ch->source_ad = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad + 4);
  96         ch->dest_ad = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad + 8);
  97         ch->txfr_len = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad + 12);
  98         ch->stride = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad + 16);
  99         ch->nextconbk = ldl_phys(bcm2835_peripheral_as, ch->conblk_ad + 20);
 100
 101         assert(!(ch->ti & BCM2708_DMA_TDMODE));
 102
 103         while (ch->txfr_len != 0) {
 104             data = 0;
 105             if (ch->ti & (1 << 11)) {
 106                 /* Ignore reads */
 107             } else {
 108                 data = ldl_phys(bcm2835_peripheral_as, ch->source_ad);
 109             }
 110             if (ch->ti & BCM2708_DMA_S_INC) {
 111                 ch->source_ad += 4;
 112             }
 113
 114             if (ch->ti & (1 << 7)) {
 115                 /* Ignore writes */
 116             } else {
 117                 stl_phys(bcm2835_peripheral_as, ch->dest_ad, data);
 118             }
 119             if (ch->ti & BCM2708_DMA_D_INC) {
 120                 ch->dest_ad += 4;
 121             }
 122             ch->txfr_len -= 4;
 123         }
 124         ch->cs |= BCM2708_DMA_END;
 125         if (ch->ti & BCM2708_DMA_INT_EN) {
 126             ch->cs |= BCM2708_DMA_INT;
 127             s->int_status |= (1 << c);
 128             qemu_set_irq(ch->irq, 1);
 129         }
 130
 131         /* Process next CB */
 132         ch->conblk_ad = ch->nextconbk;
 133     }
 134     ch->cs &= ~BCM2708_DMA_ACTIVE;
 135 }
 136
 137 static uint64_t bcm2835_dma_read(Bcm2835DmaState *s, hwaddr offset,
 138     unsigned size, int c)
 139 {
 140     DmaChan *ch = &s->chan[c];
 141     uint32_t res = 0;
 142
 143     assert(size == 4);
 144
 145     switch (offset) {
 146     case 0x0:
 147         res = ch->cs;
 148         break;
 149     case 0x4:
 150         res = ch->conblk_ad;
 151         break;
 152     case 0x8:
 153         res = ch->ti;
 154         break;
 155     case 0xc:
 156         res = ch->source_ad;
 157         break;
 158     case 0x10:
 159         res = ch->dest_ad;
 160         break;
 161     case 0x14:
 162         res = ch->txfr_len;
 163         break;
 164     case 0x18:
 165         res = ch->stride;
 166         break;
 167     case 0x1c:
 168         res = ch->nextconbk;
 169         break;
 170     case 0x20:
 171         res = ch->debug;
 172         break;
 173     default:
 174         qemu_log_mask(LOG_GUEST_ERROR,
 175             "bcm2835_dma_read: Bad offset %x\n", (int)offset);
 176         break;
 177     }
 178     return res;
 179 }
 180
 181 static void bcm2835_dma_write(Bcm2835DmaState *s, hwaddr offset,
 182     uint64_t value, unsigned size, int c)
 183 {
 184     DmaChan *ch = &s->chan[c];
 185     uint32_t oldcs = ch->cs;
 186
 187     assert(size == 4);
 188
 189     switch (offset) {
 190     case 0x0:
 191         if (value & BCM2708_DMA_RESET) {
 192             ch->cs |= BCM2708_DMA_RESET;
 193         }
 194         if (value & BCM2708_DMA_ABORT) {
 195             ch->cs |= BCM2708_DMA_ABORT;
 196         }
 197         if (value & BCM2708_DMA_END) {
 198             ch->cs &= ~BCM2708_DMA_END;
 199         }
 200         if (value & BCM2708_DMA_INT) {
 201             ch->cs &= ~BCM2708_DMA_INT;
 202             s->int_status &= ~(1 << c);
 203             qemu_set_irq(ch->irq, 0);
 204         }
 205         ch->cs &= ~0x30ff0001;
 206         ch->cs |= (value & 0x30ff0001);
 207         if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
 208             bcm2835_dma_update(s, c);
 209         }
 210         break;
 211     case 0x4:
 212         ch->conblk_ad = value;
 213         break;
 214     case 0x8:
 215         ch->ti = value;
 216         break;
 217     case 0xc:
 218         ch->source_ad = value;
 219         break;
 220     case 0x10:
 221         ch->dest_ad = value;
 222         break;
 223     case 0x14:
 224         ch->txfr_len = value;
 225         break;
 226     case 0x18:
 227         ch->stride = value;
 228         break;
 229     case 0x1c:
 230         ch->nextconbk = value;
 231         break;
 232     case 0x20:
 233         ch->debug = value;
 234         break;
 235     default:
 236         qemu_log_mask(LOG_GUEST_ERROR,
 237             "bcm2835_dma_write: Bad offset %x\n", (int)offset);
 238         break;
 239     }
 240 }
 241
 242 /* ==================================================================== */
 243
 244 static uint64_t bcm2835_dma0_14_read(void *opaque, hwaddr offset,
 245     unsigned size)
 246 {
 247     Bcm2835DmaState *s = (Bcm2835DmaState *)opaque;
 248     if (offset == 0xfe0) {
 249         return s->int_status;
 250     }
 251     if (offset == 0xff0) {
 252         return s->enable;
 253     }
 254     return bcm2835_dma_read(s, (offset & 0xff),
 255         size, (offset >> 8) & 0xf);
 256 }
 257
 258 static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset,
 259                            unsigned size)
 260 {
 261     return bcm2835_dma_read((Bcm2835DmaState *)opaque, (offset & 0xff),
 262         size, 15);
 263 }
 264
 265 static void bcm2835_dma0_14_write(void *opaque, hwaddr offset,
 266     uint64_t value, unsigned size)
 267 {
 268     Bcm2835DmaState *s = (Bcm2835DmaState *)opaque;
 269     if (offset == 0xfe0) {
 270         return;
 271     }
 272     if (offset == 0xff0) {
 273         s->enable = (value & 0xffff);
 274         return;
 275     }
 276     bcm2835_dma_write(s, (offset & 0xff),
 277         value, size, (offset >> 8) & 0xf);
 278 }
 279
 280 static void bcm2835_dma15_write(void *opaque, hwaddr offset,
 281     uint64_t value, unsigned size)
 282 {
 283     bcm2835_dma_write((Bcm2835DmaState *)opaque, (offset & 0xff),
 284         value, size, 15);
 285 }
 286
 287
 288 static const MemoryRegionOps bcm2835_dma0_14_ops = {
 289     .read = bcm2835_dma0_14_read,
 290     .write = bcm2835_dma0_14_write,
 291     .endianness = DEVICE_NATIVE_ENDIAN,
 292 };
 293
 294 static const MemoryRegionOps bcm2835_dma15_ops = {
 295     .read = bcm2835_dma15_read,
 296     .write = bcm2835_dma15_write,
 297     .endianness = DEVICE_NATIVE_ENDIAN,
 298 };
 299
 300 static const VMStateDescription vmstate_bcm2835_dma = {
 301     .name = TYPE_BCM2835_DMA,
 302     .version_id = 1,
 303     .minimum_version_id = 1,
 304     .minimum_version_id_old = 1,
 305     .fields      = (VMStateField[]) {
 306         VMSTATE_END_OF_LIST()
 307     }
 308 };
 309
 310 static int bcm2835_dma_init(SysBusDevice *sbd)
 311 {
 312     int n;
 313     DeviceState *dev = DEVICE(sbd);
 314     Bcm2835DmaState *s = BCM2835_DMA(dev);
 315
 316     s->enable = 0xffff;
 317     s->int_status = 0;
 318     for (n = 0; n < 16; n++) {
 319         s->chan[n].cs = 0;
 320         s->chan[n].conblk_ad = 0;
 321         sysbus_init_irq(sbd, &s->chan[n].irq);
 322     }
 323
 324     memory_region_init_io(&s->iomem0_14, OBJECT(s), &bcm2835_dma0_14_ops, s,
 325         "bcm2835_dma0_14", 0xf00);
 326     sysbus_init_mmio(sbd, &s->iomem0_14);
 327     memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
 328         "bcm2835_dma15", 0x100);
 329     sysbus_init_mmio(sbd, &s->iomem15);
 330
 331     vmstate_register(dev, -1, &vmstate_bcm2835_dma, s);
 332
 333     return 0;
 334 }
 335
 336 static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
 337 {
 338     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 339
 340     sdc->init = bcm2835_dma_init;
 341 }
 342
 343 static TypeInfo bcm2835_dma_info = {
 344     .name          = TYPE_BCM2835_DMA,
 345     .parent        = TYPE_SYS_BUS_DEVICE,
 346     .instance_size = sizeof(Bcm2835DmaState),
 347     .class_init    = bcm2835_dma_class_init,
 348 };
 349
 350 static void bcm2835_dma_register_types(void)
 351 {
 352     type_register_static(&bcm2835_dma_info);
 353 }
 354
 355 type_init(bcm2835_dma_register_types)