target-microblaze/helper.c

   1 /*
   2  *  MicroBlaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "host-utils.h"
  22
  23 #define D(x)
  24 #define DMMU(x)
  25
  26 #if defined(CONFIG_USER_ONLY)
  27
  28 void do_interrupt (CPUMBState *env)
  29 {
  30     env->exception_index = -1;
  31     env->regs[14] = env->sregs[SR_PC];
  32 }
  33
  34 int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
  35                             int mmu_idx)
  36 {
  37     env->exception_index = 0xaa;
  38     cpu_dump_state(env, stderr, fprintf, 0);
  39     return 1;
  40 }
  41
  42 #else /* !CONFIG_USER_ONLY */
  43
  44 int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
  45                              int mmu_idx)
  46 {
  47     unsigned int hit;
  48     unsigned int mmu_available;
  49     int r = 1;
  50     int prot;
  51
  52     mmu_available = 0;
  53     if (env->pvr.regs[0] & PVR0_USE_MMU) {
  54         mmu_available = 1;
  55         if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
  56             && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  57             mmu_available = 0;
  58         }
  59     }
  60
  61     /* Translate if the MMU is available and enabled.  */
  62     if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  63         target_ulong vaddr, paddr;
  64         struct microblaze_mmu_lookup lu;
  65
  66         hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  67         if (hit) {
  68             vaddr = address & TARGET_PAGE_MASK;
  69             paddr = lu.paddr + vaddr - lu.vaddr;
  70
  71             DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
  72                      mmu_idx, vaddr, paddr, lu.prot));
  73             tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  74             r = 0;
  75         } else {
  76             env->sregs[SR_EAR] = address;
  77             DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
  78
  79             switch (lu.err) {
  80                 case ERR_PROT:
  81                     env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  82                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  83                     break;
  84                 case ERR_MISS:
  85                     env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  86                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  87                     break;
  88                 default:
  89                     abort();
  90                     break;
  91             }
  92
  93             if (env->exception_index == EXCP_MMU) {
  94                 cpu_abort(env, "recursive faults\n");
  95             }
  96
  97             /* TLB miss.  */
  98             env->exception_index = EXCP_MMU;
  99         }
 100     } else {
 101         /* MMU disabled or not available.  */
 102         address &= TARGET_PAGE_MASK;
 103         prot = PAGE_BITS;
 104         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 105         r = 0;
 106     }
 107     return r;
 108 }
 109
 110 void do_interrupt(CPUMBState *env)
 111 {
 112     uint32_t t;
 113
 114     /* IMM flag cannot propagate across a branch and into the dslot.  */
 115     assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 116     assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 117 /*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 118     switch (env->exception_index) {
 119         case EXCP_HW_EXCP:
 120             if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 121                 qemu_log("Exception raised on system without exceptions!\n");
 122                 return;
 123             }
 124
 125             env->regs[17] = env->sregs[SR_PC] + 4;
 126             env->sregs[SR_ESR] &= ~(1 << 12);
 127
 128             /* Exception breaks branch + dslot sequence?  */
 129             if (env->iflags & D_FLAG) {
 130                 env->sregs[SR_ESR] |= 1 << 12 ;
 131                 env->sregs[SR_BTR] = env->btarget;
 132             }
 133
 134             /* Disable the MMU.  */
 135             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 136             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 137             env->sregs[SR_MSR] |= t;
 138             /* Exception in progress.  */
 139             env->sregs[SR_MSR] |= MSR_EIP;
 140
 141             qemu_log_mask(CPU_LOG_INT,
 142                           "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 143                           env->sregs[SR_PC], env->sregs[SR_EAR],
 144                           env->sregs[SR_ESR], env->iflags);
 145             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 146             env->iflags &= ~(IMM_FLAG | D_FLAG);
 147             env->sregs[SR_PC] = 0x20;
 148             break;
 149
 150         case EXCP_MMU:
 151             env->regs[17] = env->sregs[SR_PC];
 152
 153             env->sregs[SR_ESR] &= ~(1 << 12);
 154             /* Exception breaks branch + dslot sequence?  */
 155             if (env->iflags & D_FLAG) {
 156                 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 157                 env->sregs[SR_ESR] |= 1 << 12 ;
 158                 env->sregs[SR_BTR] = env->btarget;
 159
 160                 /* Reexecute the branch.  */
 161                 env->regs[17] -= 4;
 162                 /* was the branch immprefixed?.  */
 163                 if (env->bimm) {
 164                     qemu_log_mask(CPU_LOG_INT,
 165                                   "bimm exception at pc=%x iflags=%x\n",
 166                                   env->sregs[SR_PC], env->iflags);
 167                     env->regs[17] -= 4;
 168                     log_cpu_state_mask(CPU_LOG_INT, env, 0);
 169                 }
 170             } else if (env->iflags & IMM_FLAG) {
 171                 D(qemu_log("IMM_FLAG set at exception\n"));
 172                 env->regs[17] -= 4;
 173             }
 174
 175             /* Disable the MMU.  */
 176             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 177             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 178             env->sregs[SR_MSR] |= t;
 179             /* Exception in progress.  */
 180             env->sregs[SR_MSR] |= MSR_EIP;
 181
 182             qemu_log_mask(CPU_LOG_INT,
 183                           "exception at pc=%x ear=%x iflags=%x\n",
 184                           env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 185             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 186             env->iflags &= ~(IMM_FLAG | D_FLAG);
 187             env->sregs[SR_PC] = 0x20;
 188             break;
 189
 190         case EXCP_IRQ:
 191             assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 192             assert(env->sregs[SR_MSR] & MSR_IE);
 193             assert(!(env->iflags & D_FLAG));
 194
 195             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 196
 197 #if 0
 198 #include "disas.h"
 199
 200 /* Useful instrumentation when debugging interrupt issues in either
 201    the models or in sw.  */
 202             {
 203                 const char *sym;
 204
 205                 sym = lookup_symbol(env->sregs[SR_PC]);
 206                 if (sym
 207                     && (!strcmp("netif_rx", sym)
 208                         || !strcmp("process_backlog", sym))) {
 209
 210                     qemu_log(
 211                          "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 212                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 213                          sym);
 214
 215                     log_cpu_state(env, 0);
 216                 }
 217             }
 218 #endif
 219             qemu_log_mask(CPU_LOG_INT,
 220                          "interrupt at pc=%x msr=%x %x iflags=%x\n",
 221                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 222
 223             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 224                                     | MSR_UM | MSR_IE);
 225             env->sregs[SR_MSR] |= t;
 226
 227             env->regs[14] = env->sregs[SR_PC];
 228             env->sregs[SR_PC] = 0x10;
 229             //log_cpu_state_mask(CPU_LOG_INT, env, 0);
 230             break;
 231
 232         case EXCP_BREAK:
 233         case EXCP_HW_BREAK:
 234             assert(!(env->iflags & IMM_FLAG));
 235             assert(!(env->iflags & D_FLAG));
 236             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 237             qemu_log_mask(CPU_LOG_INT,
 238                         "break at pc=%x msr=%x %x iflags=%x\n",
 239                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 240             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 241             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 242             env->sregs[SR_MSR] |= t;
 243             env->sregs[SR_MSR] |= MSR_BIP;
 244             if (env->exception_index == EXCP_HW_BREAK) {
 245                 env->regs[16] = env->sregs[SR_PC];
 246                 env->sregs[SR_MSR] |= MSR_BIP;
 247                 env->sregs[SR_PC] = 0x18;
 248             } else
 249                 env->sregs[SR_PC] = env->btarget;
 250             break;
 251         default:
 252             cpu_abort(env, "unhandled exception type=%d\n",
 253                       env->exception_index);
 254             break;
 255     }
 256 }
 257
 258 target_phys_addr_t cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
 259 {
 260     target_ulong vaddr, paddr = 0;
 261     struct microblaze_mmu_lookup lu;
 262     unsigned int hit;
 263
 264     if (env->sregs[SR_MSR] & MSR_VM) {
 265         hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 266         if (hit) {
 267             vaddr = addr & TARGET_PAGE_MASK;
 268             paddr = lu.paddr + vaddr - lu.vaddr;
 269         } else
 270             paddr = 0; /* ???.  */
 271     } else
 272         paddr = addr & TARGET_PAGE_MASK;
 273
 274     return paddr;
 275 }
 276 #endif