include/hw/ppc/spapr_irq.h

   1 /*
   2  * QEMU PowerPC sPAPR IRQ backend definitions
   3  *
   4  * Copyright (c) 2018, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef HW_SPAPR_IRQ_H
  11 #define HW_SPAPR_IRQ_H
  12
  13 #include "target/ppc/cpu-qom.h"
  14
  15 /*
  16  * IRQ range offsets per device type
  17  */
  18 #define SPAPR_IRQ_IPI        0x0
  19
  20 #define SPAPR_XIRQ_BASE      XICS_IRQ_BASE /* 0x1000 */
  21 #define SPAPR_IRQ_EPOW       (SPAPR_XIRQ_BASE + 0x0000)
  22 #define SPAPR_IRQ_HOTPLUG    (SPAPR_XIRQ_BASE + 0x0001)
  23 #define SPAPR_IRQ_VIO        (SPAPR_XIRQ_BASE + 0x0100)  /* 256 VIO devices */
  24 #define SPAPR_IRQ_PCI_LSI    (SPAPR_XIRQ_BASE + 0x0200)  /* 32+ PHBs devices */
  25
  26 /* Offset of the dynamic range covered by the bitmap allocator */
  27 #define SPAPR_IRQ_MSI        (SPAPR_XIRQ_BASE + 0x0300)
  28
  29 #define SPAPR_NR_XIRQS       0x1000
  30 #define SPAPR_NR_MSIS        (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
  31
  32 typedef struct SpaprMachineState SpaprMachineState;
  33
  34 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
  35 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
  36                         Error **errp);
  37 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
  38
  39 typedef struct SpaprIrq {
  40     uint32_t    nr_xirqs;
  41     uint32_t    nr_msis;
  42     uint8_t     ov5;
  43
  44     void (*init)(SpaprMachineState *spapr, Error **errp);
  45     int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
  46     void (*free)(SpaprMachineState *spapr, int irq);
  47     void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
  48     void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
  49                         void *fdt, uint32_t phandle);
  50     void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu,
  51                             Error **errp);
  52     int (*post_load)(SpaprMachineState *spapr, int version_id);
  53     void (*reset)(SpaprMachineState *spapr, Error **errp);
  54     void (*set_irq)(void *opaque, int srcno, int val);
  55     void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
  56 } SpaprIrq;
  57
  58 extern SpaprIrq spapr_irq_xics;
  59 extern SpaprIrq spapr_irq_xics_legacy;
  60 extern SpaprIrq spapr_irq_xive;
  61 extern SpaprIrq spapr_irq_dual;
  62
  63 void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
  64 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
  65 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
  66 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
  67 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
  68 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
  69 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
  70
  71 /*
  72  * XICS legacy routines
  73  */
  74 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
  75 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
  76
  77 #endif