hw/mips/gt64xxx_pci.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu/units.h"
  28 #include "qemu/log.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "migration/vmstate.h"
  32 #include "hw/intc/i8259.h"
  33 #include "hw/irq.h"
  34 #include "trace.h"
  35 #include "qom/object.h"
  36
  37 #define GT_REGS                 (0x1000 >> 2)
  38
  39 /* CPU Configuration */
  40 #define GT_CPU                  (0x000 >> 2)
  41 #define GT_MULTI                (0x120 >> 2)
  42
  43 /* CPU Address Decode */
  44 #define GT_SCS10LD              (0x008 >> 2)
  45 #define GT_SCS10HD              (0x010 >> 2)
  46 #define GT_SCS32LD              (0x018 >> 2)
  47 #define GT_SCS32HD              (0x020 >> 2)
  48 #define GT_CS20LD               (0x028 >> 2)
  49 #define GT_CS20HD               (0x030 >> 2)
  50 #define GT_CS3BOOTLD            (0x038 >> 2)
  51 #define GT_CS3BOOTHD            (0x040 >> 2)
  52 #define GT_PCI0IOLD             (0x048 >> 2)
  53 #define GT_PCI0IOHD             (0x050 >> 2)
  54 #define GT_PCI0M0LD             (0x058 >> 2)
  55 #define GT_PCI0M0HD             (0x060 >> 2)
  56 #define GT_PCI0M1LD             (0x080 >> 2)
  57 #define GT_PCI0M1HD             (0x088 >> 2)
  58 #define GT_PCI1IOLD             (0x090 >> 2)
  59 #define GT_PCI1IOHD             (0x098 >> 2)
  60 #define GT_PCI1M0LD             (0x0a0 >> 2)
  61 #define GT_PCI1M0HD             (0x0a8 >> 2)
  62 #define GT_PCI1M1LD             (0x0b0 >> 2)
  63 #define GT_PCI1M1HD             (0x0b8 >> 2)
  64 #define GT_ISD                  (0x068 >> 2)
  65
  66 #define GT_SCS10AR              (0x0d0 >> 2)
  67 #define GT_SCS32AR              (0x0d8 >> 2)
  68 #define GT_CS20R                (0x0e0 >> 2)
  69 #define GT_CS3BOOTR             (0x0e8 >> 2)
  70
  71 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  72 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  73 #define GT_PCI0M1REMAP          (0x100 >> 2)
  74 #define GT_PCI1IOREMAP          (0x108 >> 2)
  75 #define GT_PCI1M0REMAP          (0x110 >> 2)
  76 #define GT_PCI1M1REMAP          (0x118 >> 2)
  77
  78 /* CPU Error Report */
  79 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  80 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  81 #define GT_CPUERR_DATALO        (0x128 >> 2)        /* GT-64120A only  */
  82 #define GT_CPUERR_DATAHI        (0x130 >> 2)        /* GT-64120A only  */
  83 #define GT_CPUERR_PARITY        (0x138 >> 2)        /* GT-64120A only  */
  84
  85 /* CPU Sync Barrier */
  86 #define GT_PCI0SYNC             (0x0c0 >> 2)
  87 #define GT_PCI1SYNC             (0x0c8 >> 2)
  88
  89 /* SDRAM and Device Address Decode */
  90 #define GT_SCS0LD               (0x400 >> 2)
  91 #define GT_SCS0HD               (0x404 >> 2)
  92 #define GT_SCS1LD               (0x408 >> 2)
  93 #define GT_SCS1HD               (0x40c >> 2)
  94 #define GT_SCS2LD               (0x410 >> 2)
  95 #define GT_SCS2HD               (0x414 >> 2)
  96 #define GT_SCS3LD               (0x418 >> 2)
  97 #define GT_SCS3HD               (0x41c >> 2)
  98 #define GT_CS0LD                (0x420 >> 2)
  99 #define GT_CS0HD                (0x424 >> 2)
 100 #define GT_CS1LD                (0x428 >> 2)
 101 #define GT_CS1HD                (0x42c >> 2)
 102 #define GT_CS2LD                (0x430 >> 2)
 103 #define GT_CS2HD                (0x434 >> 2)
 104 #define GT_CS3LD                (0x438 >> 2)
 105 #define GT_CS3HD                (0x43c >> 2)
 106 #define GT_BOOTLD               (0x440 >> 2)
 107 #define GT_BOOTHD               (0x444 >> 2)
 108 #define GT_ADERR                (0x470 >> 2)
 109
 110 /* SDRAM Configuration */
 111 #define GT_SDRAM_CFG            (0x448 >> 2)
 112 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 113 #define GT_SDRAM_BM             (0x478 >> 2)
 114 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 115
 116 /* SDRAM Parameters */
 117 #define GT_SDRAM_B0             (0x44c >> 2)
 118 #define GT_SDRAM_B1             (0x450 >> 2)
 119 #define GT_SDRAM_B2             (0x454 >> 2)
 120 #define GT_SDRAM_B3             (0x458 >> 2)
 121
 122 /* Device Parameters */
 123 #define GT_DEV_B0               (0x45c >> 2)
 124 #define GT_DEV_B1               (0x460 >> 2)
 125 #define GT_DEV_B2               (0x464 >> 2)
 126 #define GT_DEV_B3               (0x468 >> 2)
 127 #define GT_DEV_BOOT             (0x46c >> 2)
 128
 129 /* ECC */
 130 #define GT_ECC_ERRDATALO        (0x480 >> 2)        /* GT-64120A only  */
 131 #define GT_ECC_ERRDATAHI        (0x484 >> 2)        /* GT-64120A only  */
 132 #define GT_ECC_MEM              (0x488 >> 2)        /* GT-64120A only  */
 133 #define GT_ECC_CALC             (0x48c >> 2)        /* GT-64120A only  */
 134 #define GT_ECC_ERRADDR          (0x490 >> 2)        /* GT-64120A only  */
 135
 136 /* DMA Record */
 137 #define GT_DMA0_CNT             (0x800 >> 2)
 138 #define GT_DMA1_CNT             (0x804 >> 2)
 139 #define GT_DMA2_CNT             (0x808 >> 2)
 140 #define GT_DMA3_CNT             (0x80c >> 2)
 141 #define GT_DMA0_SA              (0x810 >> 2)
 142 #define GT_DMA1_SA              (0x814 >> 2)
 143 #define GT_DMA2_SA              (0x818 >> 2)
 144 #define GT_DMA3_SA              (0x81c >> 2)
 145 #define GT_DMA0_DA              (0x820 >> 2)
 146 #define GT_DMA1_DA              (0x824 >> 2)
 147 #define GT_DMA2_DA              (0x828 >> 2)
 148 #define GT_DMA3_DA              (0x82c >> 2)
 149 #define GT_DMA0_NEXT            (0x830 >> 2)
 150 #define GT_DMA1_NEXT            (0x834 >> 2)
 151 #define GT_DMA2_NEXT            (0x838 >> 2)
 152 #define GT_DMA3_NEXT            (0x83c >> 2)
 153 #define GT_DMA0_CUR             (0x870 >> 2)
 154 #define GT_DMA1_CUR             (0x874 >> 2)
 155 #define GT_DMA2_CUR             (0x878 >> 2)
 156 #define GT_DMA3_CUR             (0x87c >> 2)
 157
 158 /* DMA Channel Control */
 159 #define GT_DMA0_CTRL            (0x840 >> 2)
 160 #define GT_DMA1_CTRL            (0x844 >> 2)
 161 #define GT_DMA2_CTRL            (0x848 >> 2)
 162 #define GT_DMA3_CTRL            (0x84c >> 2)
 163
 164 /* DMA Arbiter */
 165 #define GT_DMA_ARB              (0x860 >> 2)
 166
 167 /* Timer/Counter */
 168 #define GT_TC0                  (0x850 >> 2)
 169 #define GT_TC1                  (0x854 >> 2)
 170 #define GT_TC2                  (0x858 >> 2)
 171 #define GT_TC3                  (0x85c >> 2)
 172 #define GT_TC_CONTROL           (0x864 >> 2)
 173
 174 /* PCI Internal */
 175 #define GT_PCI0_CMD             (0xc00 >> 2)
 176 #define GT_PCI0_TOR             (0xc04 >> 2)
 177 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 178 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 179 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 180 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 181 #define GT_PCI1_IACK            (0xc30 >> 2)
 182 #define GT_PCI0_IACK            (0xc34 >> 2)
 183 #define GT_PCI0_BARE            (0xc3c >> 2)
 184 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 185 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 186 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 187 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 188 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 189 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 190 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 191 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 192 #define GT_PCI1_CMD             (0xc80 >> 2)
 193 #define GT_PCI1_TOR             (0xc84 >> 2)
 194 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 195 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 196 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 197 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 198 #define GT_PCI1_BARE            (0xcbc >> 2)
 199 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 200 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 201 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 202 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 203 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 204 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 205 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 206 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 207 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 208 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 209 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 210 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 211
 212 /* Interrupts */
 213 #define GT_INTRCAUSE            (0xc18 >> 2)
 214 #define GT_INTRMASK             (0xc1c >> 2)
 215 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 216 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 217 #define GT_CPU_INTSEL           (0xc70 >> 2)
 218 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 219 #define GT_HINTRCAUSE           (0xc98 >> 2)
 220 #define GT_HINTRMASK            (0xc9c >> 2)
 221 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 222 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 223
 224 #define PCI_MAPPING_ENTRY(regname)            \
 225     hwaddr regname ##_start;      \
 226     hwaddr regname ##_length;     \
 227     MemoryRegion regname ##_mem
 228
 229 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
 230
 231 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
 232
 233 struct GT64120State {
 234     PCIHostState parent_obj;
 235
 236     uint32_t regs[GT_REGS];
 237     PCI_MAPPING_ENTRY(PCI0IO);
 238     PCI_MAPPING_ENTRY(PCI0M0);
 239     PCI_MAPPING_ENTRY(PCI0M1);
 240     PCI_MAPPING_ENTRY(ISD);
 241     MemoryRegion pci0_mem;
 242     AddressSpace pci0_mem_as;
 243 };
 244
 245 /* Adjust range to avoid touching space which isn't mappable via PCI */
 246 /*
 247  * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 248  *                                  0x1fc00000 - 0x1fd00000
 249  */
 250 static void check_reserved_space(hwaddr *start, hwaddr *length)
 251 {
 252     hwaddr begin = *start;
 253     hwaddr end = *start + *length;
 254
 255     if (end >= 0x1e000000LL && end < 0x1f100000LL) {
 256         end = 0x1e000000LL;
 257     }
 258     if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
 259         begin = 0x1f100000LL;
 260     }
 261     if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
 262         end = 0x1fc00000LL;
 263     }
 264     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
 265         begin = 0x1fd00000LL;
 266     }
 267     /* XXX: This is broken when a reserved range splits the requested range */
 268     if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
 269         end = 0x1e000000LL;
 270     }
 271     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
 272         end = 0x1fc00000LL;
 273     }
 274
 275     *start = begin;
 276     *length = end - begin;
 277 }
 278
 279 static void gt64120_isd_mapping(GT64120State *s)
 280 {
 281     /* Bits 14:0 of ISD map to bits 35:21 of the start address.  */
 282     hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
 283     hwaddr length = 0x1000;
 284
 285     if (s->ISD_length) {
 286         memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
 287     }
 288     check_reserved_space(&start, &length);
 289     length = 0x1000;
 290     /* Map new address */
 291     trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
 292     s->ISD_start = start;
 293     s->ISD_length = length;
 294     memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
 295 }
 296
 297 static void gt64120_pci_mapping(GT64120State *s)
 298 {
 299     /* Update PCI0IO mapping */
 300     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
 301         /* Unmap old IO address */
 302         if (s->PCI0IO_length) {
 303             memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
 304             object_unparent(OBJECT(&s->PCI0IO_mem));
 305         }
 306         /* Map new IO address */
 307         s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 308         s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
 309                             (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 310         if (s->PCI0IO_length) {
 311             memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
 312                                      get_system_io(), 0, s->PCI0IO_length);
 313             memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
 314                                         &s->PCI0IO_mem);
 315         }
 316     }
 317
 318     /* Update PCI0M0 mapping */
 319     if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
 320         /* Unmap old MEM address */
 321         if (s->PCI0M0_length) {
 322             memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
 323             object_unparent(OBJECT(&s->PCI0M0_mem));
 324         }
 325         /* Map new mem address */
 326         s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
 327         s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
 328                             (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
 329         if (s->PCI0M0_length) {
 330             memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
 331                                      &s->pci0_mem, s->PCI0M0_start,
 332                                      s->PCI0M0_length);
 333             memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
 334                                         &s->PCI0M0_mem);
 335         }
 336     }
 337
 338     /* Update PCI0M1 mapping */
 339     if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
 340         /* Unmap old MEM address */
 341         if (s->PCI0M1_length) {
 342             memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
 343             object_unparent(OBJECT(&s->PCI0M1_mem));
 344         }
 345         /* Map new mem address */
 346         s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
 347         s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
 348                             (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
 349         if (s->PCI0M1_length) {
 350             memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
 351                                      &s->pci0_mem, s->PCI0M1_start,
 352                                      s->PCI0M1_length);
 353             memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
 354                                         &s->PCI0M1_mem);
 355         }
 356     }
 357 }
 358
 359 static int gt64120_post_load(void *opaque, int version_id)
 360 {
 361     GT64120State *s = opaque;
 362
 363     gt64120_isd_mapping(s);
 364     gt64120_pci_mapping(s);
 365
 366     return 0;
 367 }
 368
 369 static const VMStateDescription vmstate_gt64120 = {
 370     .name = "gt64120",
 371     .version_id = 1,
 372     .minimum_version_id = 1,
 373     .post_load = gt64120_post_load,
 374     .fields = (VMStateField[]) {
 375         VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
 376         VMSTATE_END_OF_LIST()
 377     }
 378 };
 379
 380 static void gt64120_writel(void *opaque, hwaddr addr,
 381                            uint64_t val, unsigned size)
 382 {
 383     GT64120State *s = opaque;
 384     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 385     uint32_t saddr = addr >> 2;
 386
 387     trace_gt64120_write(addr, val);
 388     if (!(s->regs[GT_CPU] & 0x00001000)) {
 389         val = bswap32(val);
 390     }
 391
 392     switch (saddr) {
 393
 394     /* CPU Configuration */
 395     case GT_CPU:
 396         s->regs[GT_CPU] = val;
 397         break;
 398     case GT_MULTI:
 399         /* Read-only register as only one GT64xxx is present on the CPU bus */
 400         break;
 401
 402     /* CPU Address Decode */
 403     case GT_PCI0IOLD:
 404         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 405         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 406         gt64120_pci_mapping(s);
 407         break;
 408     case GT_PCI0M0LD:
 409         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 410         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 411         gt64120_pci_mapping(s);
 412         break;
 413     case GT_PCI0M1LD:
 414         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 415         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 416         gt64120_pci_mapping(s);
 417         break;
 418     case GT_PCI1IOLD:
 419         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 420         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 421         break;
 422     case GT_PCI1M0LD:
 423         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 424         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 425         break;
 426     case GT_PCI1M1LD:
 427         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 428         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 429         break;
 430     case GT_PCI0M0HD:
 431     case GT_PCI0M1HD:
 432     case GT_PCI0IOHD:
 433         s->regs[saddr] = val & 0x0000007f;
 434         gt64120_pci_mapping(s);
 435         break;
 436     case GT_PCI1IOHD:
 437     case GT_PCI1M0HD:
 438     case GT_PCI1M1HD:
 439         s->regs[saddr] = val & 0x0000007f;
 440         break;
 441     case GT_ISD:
 442         s->regs[saddr] = val & 0x00007fff;
 443         gt64120_isd_mapping(s);
 444         break;
 445
 446     case GT_PCI0IOREMAP:
 447     case GT_PCI0M0REMAP:
 448     case GT_PCI0M1REMAP:
 449     case GT_PCI1IOREMAP:
 450     case GT_PCI1M0REMAP:
 451     case GT_PCI1M1REMAP:
 452         s->regs[saddr] = val & 0x000007ff;
 453         break;
 454
 455     /* CPU Error Report */
 456     case GT_CPUERR_ADDRLO:
 457     case GT_CPUERR_ADDRHI:
 458     case GT_CPUERR_DATALO:
 459     case GT_CPUERR_DATAHI:
 460     case GT_CPUERR_PARITY:
 461         /* Read-only registers, do nothing */
 462         qemu_log_mask(LOG_GUEST_ERROR,
 463                       "gt64120: Read-only register write "
 464                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 465                       saddr << 2, size, size << 1, val);
 466         break;
 467
 468     /* CPU Sync Barrier */
 469     case GT_PCI0SYNC:
 470     case GT_PCI1SYNC:
 471         /* Read-only registers, do nothing */
 472         qemu_log_mask(LOG_GUEST_ERROR,
 473                       "gt64120: Read-only register write "
 474                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 475                       saddr << 2, size, size << 1, val);
 476         break;
 477
 478     /* SDRAM and Device Address Decode */
 479     case GT_SCS0LD:
 480     case GT_SCS0HD:
 481     case GT_SCS1LD:
 482     case GT_SCS1HD:
 483     case GT_SCS2LD:
 484     case GT_SCS2HD:
 485     case GT_SCS3LD:
 486     case GT_SCS3HD:
 487     case GT_CS0LD:
 488     case GT_CS0HD:
 489     case GT_CS1LD:
 490     case GT_CS1HD:
 491     case GT_CS2LD:
 492     case GT_CS2HD:
 493     case GT_CS3LD:
 494     case GT_CS3HD:
 495     case GT_BOOTLD:
 496     case GT_BOOTHD:
 497     case GT_ADERR:
 498     /* SDRAM Configuration */
 499     case GT_SDRAM_CFG:
 500     case GT_SDRAM_OPMODE:
 501     case GT_SDRAM_BM:
 502     case GT_SDRAM_ADDRDECODE:
 503         /* Accept and ignore SDRAM interleave configuration */
 504         s->regs[saddr] = val;
 505         break;
 506
 507     /* Device Parameters */
 508     case GT_DEV_B0:
 509     case GT_DEV_B1:
 510     case GT_DEV_B2:
 511     case GT_DEV_B3:
 512     case GT_DEV_BOOT:
 513         /* Not implemented */
 514         qemu_log_mask(LOG_UNIMP,
 515                       "gt64120: Unimplemented device register write "
 516                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 517                       saddr << 2, size, size << 1, val);
 518         break;
 519
 520     /* ECC */
 521     case GT_ECC_ERRDATALO:
 522     case GT_ECC_ERRDATAHI:
 523     case GT_ECC_MEM:
 524     case GT_ECC_CALC:
 525     case GT_ECC_ERRADDR:
 526         /* Read-only registers, do nothing */
 527         qemu_log_mask(LOG_GUEST_ERROR,
 528                       "gt64120: Read-only register write "
 529                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 530                       saddr << 2, size, size << 1, val);
 531         break;
 532
 533     /* DMA Record */
 534     case GT_DMA0_CNT:
 535     case GT_DMA1_CNT:
 536     case GT_DMA2_CNT:
 537     case GT_DMA3_CNT:
 538     case GT_DMA0_SA:
 539     case GT_DMA1_SA:
 540     case GT_DMA2_SA:
 541     case GT_DMA3_SA:
 542     case GT_DMA0_DA:
 543     case GT_DMA1_DA:
 544     case GT_DMA2_DA:
 545     case GT_DMA3_DA:
 546     case GT_DMA0_NEXT:
 547     case GT_DMA1_NEXT:
 548     case GT_DMA2_NEXT:
 549     case GT_DMA3_NEXT:
 550     case GT_DMA0_CUR:
 551     case GT_DMA1_CUR:
 552     case GT_DMA2_CUR:
 553     case GT_DMA3_CUR:
 554
 555     /* DMA Channel Control */
 556     case GT_DMA0_CTRL:
 557     case GT_DMA1_CTRL:
 558     case GT_DMA2_CTRL:
 559     case GT_DMA3_CTRL:
 560
 561     /* DMA Arbiter */
 562     case GT_DMA_ARB:
 563         /* Not implemented */
 564         qemu_log_mask(LOG_UNIMP,
 565                       "gt64120: Unimplemented DMA register write "
 566                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 567                       saddr << 2, size, size << 1, val);
 568         break;
 569
 570     /* Timer/Counter */
 571     case GT_TC0:
 572     case GT_TC1:
 573     case GT_TC2:
 574     case GT_TC3:
 575     case GT_TC_CONTROL:
 576         /* Not implemented */
 577         qemu_log_mask(LOG_UNIMP,
 578                       "gt64120: Unimplemented timer register write "
 579                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 580                       saddr << 2, size, size << 1, val);
 581         break;
 582
 583     /* PCI Internal */
 584     case GT_PCI0_CMD:
 585     case GT_PCI1_CMD:
 586         s->regs[saddr] = val & 0x0401fc0f;
 587         break;
 588     case GT_PCI0_TOR:
 589     case GT_PCI0_BS_SCS10:
 590     case GT_PCI0_BS_SCS32:
 591     case GT_PCI0_BS_CS20:
 592     case GT_PCI0_BS_CS3BT:
 593     case GT_PCI1_IACK:
 594     case GT_PCI0_IACK:
 595     case GT_PCI0_BARE:
 596     case GT_PCI0_PREFMBR:
 597     case GT_PCI0_SCS10_BAR:
 598     case GT_PCI0_SCS32_BAR:
 599     case GT_PCI0_CS20_BAR:
 600     case GT_PCI0_CS3BT_BAR:
 601     case GT_PCI0_SSCS10_BAR:
 602     case GT_PCI0_SSCS32_BAR:
 603     case GT_PCI0_SCS3BT_BAR:
 604     case GT_PCI1_TOR:
 605     case GT_PCI1_BS_SCS10:
 606     case GT_PCI1_BS_SCS32:
 607     case GT_PCI1_BS_CS20:
 608     case GT_PCI1_BS_CS3BT:
 609     case GT_PCI1_BARE:
 610     case GT_PCI1_PREFMBR:
 611     case GT_PCI1_SCS10_BAR:
 612     case GT_PCI1_SCS32_BAR:
 613     case GT_PCI1_CS20_BAR:
 614     case GT_PCI1_CS3BT_BAR:
 615     case GT_PCI1_SSCS10_BAR:
 616     case GT_PCI1_SSCS32_BAR:
 617     case GT_PCI1_SCS3BT_BAR:
 618     case GT_PCI1_CFGADDR:
 619     case GT_PCI1_CFGDATA:
 620         /* not implemented */
 621         qemu_log_mask(LOG_UNIMP,
 622                       "gt64120: Unimplemented PCI register write "
 623                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 624                       saddr << 2, size, size << 1, val);
 625         break;
 626     case GT_PCI0_CFGADDR:
 627         phb->config_reg = val & 0x80fffffc;
 628         break;
 629     case GT_PCI0_CFGDATA:
 630         if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 631             val = bswap32(val);
 632         }
 633         if (phb->config_reg & (1u << 31)) {
 634             pci_data_write(phb->bus, phb->config_reg, val, 4);
 635         }
 636         break;
 637
 638     /* Interrupts */
 639     case GT_INTRCAUSE:
 640         /* not really implemented */
 641         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 642         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 643         trace_gt64120_write_intreg("INTRCAUSE", size, val);
 644         break;
 645     case GT_INTRMASK:
 646         s->regs[saddr] = val & 0x3c3ffffe;
 647         trace_gt64120_write_intreg("INTRMASK", size, val);
 648         break;
 649     case GT_PCI0_ICMASK:
 650         s->regs[saddr] = val & 0x03fffffe;
 651         trace_gt64120_write_intreg("ICMASK", size, val);
 652         break;
 653     case GT_PCI0_SERR0MASK:
 654         s->regs[saddr] = val & 0x0000003f;
 655         trace_gt64120_write_intreg("SERR0MASK", size, val);
 656         break;
 657
 658     /* Reserved when only PCI_0 is configured. */
 659     case GT_HINTRCAUSE:
 660     case GT_CPU_INTSEL:
 661     case GT_PCI0_INTSEL:
 662     case GT_HINTRMASK:
 663     case GT_PCI0_HICMASK:
 664     case GT_PCI1_SERR1MASK:
 665         /* not implemented */
 666         break;
 667
 668     /* SDRAM Parameters */
 669     case GT_SDRAM_B0:
 670     case GT_SDRAM_B1:
 671     case GT_SDRAM_B2:
 672     case GT_SDRAM_B3:
 673         /*
 674          * We don't simulate electrical parameters of the SDRAM.
 675          * Accept, but ignore the values.
 676          */
 677         s->regs[saddr] = val;
 678         break;
 679
 680     default:
 681         qemu_log_mask(LOG_GUEST_ERROR,
 682                       "gt64120: Illegal register write "
 683                       "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
 684                       saddr << 2, size, size << 1, val);
 685         break;
 686     }
 687 }
 688
 689 static uint64_t gt64120_readl(void *opaque,
 690                               hwaddr addr, unsigned size)
 691 {
 692     GT64120State *s = opaque;
 693     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 694     uint32_t val;
 695     uint32_t saddr = addr >> 2;
 696
 697     switch (saddr) {
 698
 699     /* CPU Configuration */
 700     case GT_MULTI:
 701         /*
 702          * Only one GT64xxx is present on the CPU bus, return
 703          * the initial value.
 704          */
 705         val = s->regs[saddr];
 706         break;
 707
 708     /* CPU Error Report */
 709     case GT_CPUERR_ADDRLO:
 710     case GT_CPUERR_ADDRHI:
 711     case GT_CPUERR_DATALO:
 712     case GT_CPUERR_DATAHI:
 713     case GT_CPUERR_PARITY:
 714         /* Emulated memory has no error, always return the initial values. */
 715         val = s->regs[saddr];
 716         break;
 717
 718     /* CPU Sync Barrier */
 719     case GT_PCI0SYNC:
 720     case GT_PCI1SYNC:
 721         /*
 722          * Reading those register should empty all FIFO on the PCI
 723          * bus, which are not emulated. The return value should be
 724          * a random value that should be ignored.
 725          */
 726         val = 0xc000ffee;
 727         break;
 728
 729     /* ECC */
 730     case GT_ECC_ERRDATALO:
 731     case GT_ECC_ERRDATAHI:
 732     case GT_ECC_MEM:
 733     case GT_ECC_CALC:
 734     case GT_ECC_ERRADDR:
 735         /* Emulated memory has no error, always return the initial values. */
 736         val = s->regs[saddr];
 737         break;
 738
 739     case GT_CPU:
 740     case GT_SCS10LD:
 741     case GT_SCS10HD:
 742     case GT_SCS32LD:
 743     case GT_SCS32HD:
 744     case GT_CS20LD:
 745     case GT_CS20HD:
 746     case GT_CS3BOOTLD:
 747     case GT_CS3BOOTHD:
 748     case GT_SCS10AR:
 749     case GT_SCS32AR:
 750     case GT_CS20R:
 751     case GT_CS3BOOTR:
 752     case GT_PCI0IOLD:
 753     case GT_PCI0M0LD:
 754     case GT_PCI0M1LD:
 755     case GT_PCI1IOLD:
 756     case GT_PCI1M0LD:
 757     case GT_PCI1M1LD:
 758     case GT_PCI0IOHD:
 759     case GT_PCI0M0HD:
 760     case GT_PCI0M1HD:
 761     case GT_PCI1IOHD:
 762     case GT_PCI1M0HD:
 763     case GT_PCI1M1HD:
 764     case GT_PCI0IOREMAP:
 765     case GT_PCI0M0REMAP:
 766     case GT_PCI0M1REMAP:
 767     case GT_PCI1IOREMAP:
 768     case GT_PCI1M0REMAP:
 769     case GT_PCI1M1REMAP:
 770     case GT_ISD:
 771         val = s->regs[saddr];
 772         break;
 773     case GT_PCI0_IACK:
 774         /* Read the IRQ number */
 775         val = pic_read_irq(isa_pic);
 776         break;
 777
 778     /* SDRAM and Device Address Decode */
 779     case GT_SCS0LD:
 780     case GT_SCS0HD:
 781     case GT_SCS1LD:
 782     case GT_SCS1HD:
 783     case GT_SCS2LD:
 784     case GT_SCS2HD:
 785     case GT_SCS3LD:
 786     case GT_SCS3HD:
 787     case GT_CS0LD:
 788     case GT_CS0HD:
 789     case GT_CS1LD:
 790     case GT_CS1HD:
 791     case GT_CS2LD:
 792     case GT_CS2HD:
 793     case GT_CS3LD:
 794     case GT_CS3HD:
 795     case GT_BOOTLD:
 796     case GT_BOOTHD:
 797     case GT_ADERR:
 798         val = s->regs[saddr];
 799         break;
 800
 801     /* SDRAM Configuration */
 802     case GT_SDRAM_CFG:
 803     case GT_SDRAM_OPMODE:
 804     case GT_SDRAM_BM:
 805     case GT_SDRAM_ADDRDECODE:
 806         val = s->regs[saddr];
 807         break;
 808
 809     /* SDRAM Parameters */
 810     case GT_SDRAM_B0:
 811     case GT_SDRAM_B1:
 812     case GT_SDRAM_B2:
 813     case GT_SDRAM_B3:
 814         /*
 815          * We don't simulate electrical parameters of the SDRAM.
 816          * Just return the last written value.
 817          */
 818         val = s->regs[saddr];
 819         break;
 820
 821     /* Device Parameters */
 822     case GT_DEV_B0:
 823     case GT_DEV_B1:
 824     case GT_DEV_B2:
 825     case GT_DEV_B3:
 826     case GT_DEV_BOOT:
 827         val = s->regs[saddr];
 828         break;
 829
 830     /* DMA Record */
 831     case GT_DMA0_CNT:
 832     case GT_DMA1_CNT:
 833     case GT_DMA2_CNT:
 834     case GT_DMA3_CNT:
 835     case GT_DMA0_SA:
 836     case GT_DMA1_SA:
 837     case GT_DMA2_SA:
 838     case GT_DMA3_SA:
 839     case GT_DMA0_DA:
 840     case GT_DMA1_DA:
 841     case GT_DMA2_DA:
 842     case GT_DMA3_DA:
 843     case GT_DMA0_NEXT:
 844     case GT_DMA1_NEXT:
 845     case GT_DMA2_NEXT:
 846     case GT_DMA3_NEXT:
 847     case GT_DMA0_CUR:
 848     case GT_DMA1_CUR:
 849     case GT_DMA2_CUR:
 850     case GT_DMA3_CUR:
 851         val = s->regs[saddr];
 852         break;
 853
 854     /* DMA Channel Control */
 855     case GT_DMA0_CTRL:
 856     case GT_DMA1_CTRL:
 857     case GT_DMA2_CTRL:
 858     case GT_DMA3_CTRL:
 859         val = s->regs[saddr];
 860         break;
 861
 862     /* DMA Arbiter */
 863     case GT_DMA_ARB:
 864         val = s->regs[saddr];
 865         break;
 866
 867     /* Timer/Counter */
 868     case GT_TC0:
 869     case GT_TC1:
 870     case GT_TC2:
 871     case GT_TC3:
 872     case GT_TC_CONTROL:
 873         val = s->regs[saddr];
 874         break;
 875
 876     /* PCI Internal */
 877     case GT_PCI0_CFGADDR:
 878         val = phb->config_reg;
 879         break;
 880     case GT_PCI0_CFGDATA:
 881         if (!(phb->config_reg & (1 << 31))) {
 882             val = 0xffffffff;
 883         } else {
 884             val = pci_data_read(phb->bus, phb->config_reg, 4);
 885         }
 886         if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 887             val = bswap32(val);
 888         }
 889         break;
 890
 891     case GT_PCI0_CMD:
 892     case GT_PCI0_TOR:
 893     case GT_PCI0_BS_SCS10:
 894     case GT_PCI0_BS_SCS32:
 895     case GT_PCI0_BS_CS20:
 896     case GT_PCI0_BS_CS3BT:
 897     case GT_PCI1_IACK:
 898     case GT_PCI0_BARE:
 899     case GT_PCI0_PREFMBR:
 900     case GT_PCI0_SCS10_BAR:
 901     case GT_PCI0_SCS32_BAR:
 902     case GT_PCI0_CS20_BAR:
 903     case GT_PCI0_CS3BT_BAR:
 904     case GT_PCI0_SSCS10_BAR:
 905     case GT_PCI0_SSCS32_BAR:
 906     case GT_PCI0_SCS3BT_BAR:
 907     case GT_PCI1_CMD:
 908     case GT_PCI1_TOR:
 909     case GT_PCI1_BS_SCS10:
 910     case GT_PCI1_BS_SCS32:
 911     case GT_PCI1_BS_CS20:
 912     case GT_PCI1_BS_CS3BT:
 913     case GT_PCI1_BARE:
 914     case GT_PCI1_PREFMBR:
 915     case GT_PCI1_SCS10_BAR:
 916     case GT_PCI1_SCS32_BAR:
 917     case GT_PCI1_CS20_BAR:
 918     case GT_PCI1_CS3BT_BAR:
 919     case GT_PCI1_SSCS10_BAR:
 920     case GT_PCI1_SSCS32_BAR:
 921     case GT_PCI1_SCS3BT_BAR:
 922     case GT_PCI1_CFGADDR:
 923     case GT_PCI1_CFGDATA:
 924         val = s->regs[saddr];
 925         break;
 926
 927     /* Interrupts */
 928     case GT_INTRCAUSE:
 929         val = s->regs[saddr];
 930         trace_gt64120_read_intreg("INTRCAUSE", size, val);
 931         break;
 932     case GT_INTRMASK:
 933         val = s->regs[saddr];
 934         trace_gt64120_read_intreg("INTRMASK", size, val);
 935         break;
 936     case GT_PCI0_ICMASK:
 937         val = s->regs[saddr];
 938         trace_gt64120_read_intreg("ICMASK", size, val);
 939         break;
 940     case GT_PCI0_SERR0MASK:
 941         val = s->regs[saddr];
 942         trace_gt64120_read_intreg("SERR0MASK", size, val);
 943         break;
 944
 945     /* Reserved when only PCI_0 is configured. */
 946     case GT_HINTRCAUSE:
 947     case GT_CPU_INTSEL:
 948     case GT_PCI0_INTSEL:
 949     case GT_HINTRMASK:
 950     case GT_PCI0_HICMASK:
 951     case GT_PCI1_SERR1MASK:
 952         val = s->regs[saddr];
 953         break;
 954
 955     default:
 956         val = s->regs[saddr];
 957         qemu_log_mask(LOG_GUEST_ERROR,
 958                       "gt64120: Illegal register read "
 959                       "reg:0x%03x size:%u value:0x%0*x\n",
 960                       saddr << 2, size, size << 1, val);
 961         break;
 962     }
 963
 964     if (!(s->regs[GT_CPU] & 0x00001000)) {
 965         val = bswap32(val);
 966     }
 967     trace_gt64120_read(addr, val);
 968
 969     return val;
 970 }
 971
 972 static const MemoryRegionOps isd_mem_ops = {
 973     .read = gt64120_readl,
 974     .write = gt64120_writel,
 975     .endianness = DEVICE_NATIVE_ENDIAN,
 976     .impl = {
 977         .min_access_size = 4,
 978         .max_access_size = 4,
 979     },
 980 };
 981
 982 static void gt64120_reset(DeviceState *dev)
 983 {
 984     GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
 985
 986     /* FIXME: Malta specific hw assumptions ahead */
 987
 988     /* CPU Configuration */
 989 #if TARGET_BIG_ENDIAN
 990     s->regs[GT_CPU]           = 0x00000000;
 991 #else
 992     s->regs[GT_CPU]           = 0x00001000;
 993 #endif
 994     s->regs[GT_MULTI]         = 0x00000003;
 995
 996     /* CPU Address decode */
 997     s->regs[GT_SCS10LD]       = 0x00000000;
 998     s->regs[GT_SCS10HD]       = 0x00000007;
 999     s->regs[GT_SCS32LD]       = 0x00000008;
1000     s->regs[GT_SCS32HD]       = 0x0000000f;
1001     s->regs[GT_CS20LD]        = 0x000000e0;
1002     s->regs[GT_CS20HD]        = 0x00000070;
1003     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
1004     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
1005
1006     s->regs[GT_PCI0IOLD]      = 0x00000080;
1007     s->regs[GT_PCI0IOHD]      = 0x0000000f;
1008     s->regs[GT_PCI0M0LD]      = 0x00000090;
1009     s->regs[GT_PCI0M0HD]      = 0x0000001f;
1010     s->regs[GT_ISD]           = 0x000000a0;
1011     s->regs[GT_PCI0M1LD]      = 0x00000790;
1012     s->regs[GT_PCI0M1HD]      = 0x0000001f;
1013     s->regs[GT_PCI1IOLD]      = 0x00000100;
1014     s->regs[GT_PCI1IOHD]      = 0x0000000f;
1015     s->regs[GT_PCI1M0LD]      = 0x00000110;
1016     s->regs[GT_PCI1M0HD]      = 0x0000001f;
1017     s->regs[GT_PCI1M1LD]      = 0x00000120;
1018     s->regs[GT_PCI1M1HD]      = 0x0000002f;
1019
1020     s->regs[GT_SCS10AR]       = 0x00000000;
1021     s->regs[GT_SCS32AR]       = 0x00000008;
1022     s->regs[GT_CS20R]         = 0x000000e0;
1023     s->regs[GT_CS3BOOTR]      = 0x000000f8;
1024
1025     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
1026     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
1027     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
1028     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
1029     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
1030     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
1031
1032     /* CPU Error Report */
1033     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1034     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1035     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1036     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1037     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1038
1039     /* CPU Sync Barrier */
1040     s->regs[GT_PCI0SYNC]      = 0x00000000;
1041     s->regs[GT_PCI1SYNC]      = 0x00000000;
1042
1043     /* SDRAM and Device Address Decode */
1044     s->regs[GT_SCS0LD]        = 0x00000000;
1045     s->regs[GT_SCS0HD]        = 0x00000007;
1046     s->regs[GT_SCS1LD]        = 0x00000008;
1047     s->regs[GT_SCS1HD]        = 0x0000000f;
1048     s->regs[GT_SCS2LD]        = 0x00000010;
1049     s->regs[GT_SCS2HD]        = 0x00000017;
1050     s->regs[GT_SCS3LD]        = 0x00000018;
1051     s->regs[GT_SCS3HD]        = 0x0000001f;
1052     s->regs[GT_CS0LD]         = 0x000000c0;
1053     s->regs[GT_CS0HD]         = 0x000000c7;
1054     s->regs[GT_CS1LD]         = 0x000000c8;
1055     s->regs[GT_CS1HD]         = 0x000000cf;
1056     s->regs[GT_CS2LD]         = 0x000000d0;
1057     s->regs[GT_CS2HD]         = 0x000000df;
1058     s->regs[GT_CS3LD]         = 0x000000f0;
1059     s->regs[GT_CS3HD]         = 0x000000fb;
1060     s->regs[GT_BOOTLD]        = 0x000000fc;
1061     s->regs[GT_BOOTHD]        = 0x000000ff;
1062     s->regs[GT_ADERR]         = 0xffffffff;
1063
1064     /* SDRAM Configuration */
1065     s->regs[GT_SDRAM_CFG]     = 0x00000200;
1066     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1067     s->regs[GT_SDRAM_BM]      = 0x00000007;
1068     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1069
1070     /* SDRAM Parameters */
1071     s->regs[GT_SDRAM_B0]      = 0x00000005;
1072     s->regs[GT_SDRAM_B1]      = 0x00000005;
1073     s->regs[GT_SDRAM_B2]      = 0x00000005;
1074     s->regs[GT_SDRAM_B3]      = 0x00000005;
1075
1076     /* ECC */
1077     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1078     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1079     s->regs[GT_ECC_MEM]       = 0x00000000;
1080     s->regs[GT_ECC_CALC]      = 0x00000000;
1081     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1082
1083     /* Device Parameters */
1084     s->regs[GT_DEV_B0]        = 0x386fffff;
1085     s->regs[GT_DEV_B1]        = 0x386fffff;
1086     s->regs[GT_DEV_B2]        = 0x386fffff;
1087     s->regs[GT_DEV_B3]        = 0x386fffff;
1088     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1089
1090     /* DMA registers are all zeroed at reset */
1091
1092     /* Timer/Counter */
1093     s->regs[GT_TC0]           = 0xffffffff;
1094     s->regs[GT_TC1]           = 0x00ffffff;
1095     s->regs[GT_TC2]           = 0x00ffffff;
1096     s->regs[GT_TC3]           = 0x00ffffff;
1097     s->regs[GT_TC_CONTROL]    = 0x00000000;
1098
1099     /* PCI Internal */
1100 #if TARGET_BIG_ENDIAN
1101     s->regs[GT_PCI0_CMD]      = 0x00000000;
1102 #else
1103     s->regs[GT_PCI0_CMD]      = 0x00010001;
1104 #endif
1105     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1106     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1107     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1108     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1109     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1110     s->regs[GT_PCI1_IACK]     = 0x00000000;
1111     s->regs[GT_PCI0_IACK]     = 0x00000000;
1112     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1113     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1114     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1115     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1116     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1117     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1118     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1119     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1120     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1121 #if TARGET_BIG_ENDIAN
1122     s->regs[GT_PCI1_CMD]      = 0x00000000;
1123 #else
1124     s->regs[GT_PCI1_CMD]      = 0x00010001;
1125 #endif
1126     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1127     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1128     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1129     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1130     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1131     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1132     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1133     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1134     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1135     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1136     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1137     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1138     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1139     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1140     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1141     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1142     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1143
1144     /* Interrupt registers are all zeroed at reset */
1145
1146     gt64120_isd_mapping(s);
1147     gt64120_pci_mapping(s);
1148 }
1149
1150 static void gt64120_realize(DeviceState *dev, Error **errp)
1151 {
1152     GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1153     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
1154
1155     memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1156                           "gt64120-isd", 0x1000);
1157     memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1158     address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
1159     phb->bus = pci_root_bus_new(dev, "pci",
1160                                 &s->pci0_mem,
1161                                 get_system_io(),
1162                                 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
1163
1164     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1165 }
1166
1167 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1168 {
1169     /* FIXME: Malta specific hw assumptions ahead */
1170     pci_set_word(d->config + PCI_COMMAND, 0);
1171     pci_set_word(d->config + PCI_STATUS,
1172                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1173     pci_config_set_prog_interface(d->config, 0);
1174     pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1175     pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1176     pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1177     pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1178     pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1179     pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1180     pci_set_byte(d->config + 0x3d, 0x01);
1181 }
1182
1183 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1184 {
1185     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1186     DeviceClass *dc = DEVICE_CLASS(klass);
1187
1188     k->realize = gt64120_pci_realize;
1189     k->vendor_id = PCI_VENDOR_ID_MARVELL;
1190     k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1191     k->revision = 0x10;
1192     k->class_id = PCI_CLASS_BRIDGE_HOST;
1193     /*
1194      * PCI-facing part of the host bridge, not usable without the
1195      * host-facing part, which can't be device_add'ed, yet.
1196      */
1197     dc->user_creatable = false;
1198 }
1199
1200 static const TypeInfo gt64120_pci_info = {
1201     .name          = "gt64120_pci",
1202     .parent        = TYPE_PCI_DEVICE,
1203     .instance_size = sizeof(PCIDevice),
1204     .class_init    = gt64120_pci_class_init,
1205     .interfaces = (InterfaceInfo[]) {
1206         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1207         { },
1208     },
1209 };
1210
1211 static void gt64120_class_init(ObjectClass *klass, void *data)
1212 {
1213     DeviceClass *dc = DEVICE_CLASS(klass);
1214
1215     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1216     dc->realize = gt64120_realize;
1217     dc->reset = gt64120_reset;
1218     dc->vmsd = &vmstate_gt64120;
1219 }
1220
1221 static const TypeInfo gt64120_info = {
1222     .name          = TYPE_GT64120_PCI_HOST_BRIDGE,
1223     .parent        = TYPE_PCI_HOST_BRIDGE,
1224     .instance_size = sizeof(GT64120State),
1225     .class_init    = gt64120_class_init,
1226 };
1227
1228 static void gt64120_pci_register_types(void)
1229 {
1230     type_register_static(&gt64120_info);
1231     type_register_static(&gt64120_pci_info);
1232 }
1233
1234 type_init(gt64120_pci_register_types)