target-openrisc/cpu.h

   1 /*
   2  * OpenRISC virtual CPU header.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_OPENRISC_H
  21 #define CPU_OPENRISC_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPUOpenRISCState
  26
  27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
  28 struct OpenRISCCPU;
  29
  30 #include "config.h"
  31 #include "qemu-common.h"
  32 #include "exec/cpu-defs.h"
  33 #include "fpu/softfloat.h"
  34 #include "qom/cpu.h"
  35
  36 #define TYPE_OPENRISC_CPU "or32-cpu"
  37
  38 #define OPENRISC_CPU_CLASS(klass) \
  39     OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  40 #define OPENRISC_CPU(obj) \
  41     OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  42 #define OPENRISC_CPU_GET_CLASS(obj) \
  43     OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  44
  45 /**
  46  * OpenRISCCPUClass:
  47  * @parent_realize: The parent class' realize handler.
  48  * @parent_reset: The parent class' reset handler.
  49  *
  50  * A OpenRISC CPU model.
  51  */
  52 typedef struct OpenRISCCPUClass {
  53     /*< private >*/
  54     CPUClass parent_class;
  55     /*< public >*/
  56
  57     DeviceRealize parent_realize;
  58     void (*parent_reset)(CPUState *cpu);
  59 } OpenRISCCPUClass;
  60
  61 #define NB_MMU_MODES    3
  62
  63 enum {
  64     MMU_NOMMU_IDX = 0,
  65     MMU_SUPERVISOR_IDX = 1,
  66     MMU_USER_IDX = 2,
  67 };
  68
  69 #define TARGET_PAGE_BITS 13
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #define SET_FP_CAUSE(reg, v)    do {\
  75                                     (reg) = ((reg) & ~(0x3f << 12)) | \
  76                                             ((v & 0x3f) << 12);\
  77                                 } while (0)
  78 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  79 #define UPDATE_FP_FLAGS(reg, v)   do {\
  80                                       (reg) |= ((v & 0x1f) << 2);\
  81                                   } while (0)
  82
  83 /* Version Register */
  84 #define SPR_VR 0xFFFF003F
  85
  86 /* Internal flags, delay slot flag */
  87 #define D_FLAG    1
  88
  89 /* Interrupt */
  90 #define NR_IRQS  32
  91
  92 /* Unit presece register */
  93 enum {
  94     UPR_UP = (1 << 0),
  95     UPR_DCP = (1 << 1),
  96     UPR_ICP = (1 << 2),
  97     UPR_DMP = (1 << 3),
  98     UPR_IMP = (1 << 4),
  99     UPR_MP = (1 << 5),
 100     UPR_DUP = (1 << 6),
 101     UPR_PCUR = (1 << 7),
 102     UPR_PMP = (1 << 8),
 103     UPR_PICP = (1 << 9),
 104     UPR_TTP = (1 << 10),
 105     UPR_CUP = (255 << 24),
 106 };
 107
 108 /* CPU configure register */
 109 enum {
 110     CPUCFGR_NSGF = (15 << 0),
 111     CPUCFGR_CGF = (1 << 4),
 112     CPUCFGR_OB32S = (1 << 5),
 113     CPUCFGR_OB64S = (1 << 6),
 114     CPUCFGR_OF32S = (1 << 7),
 115     CPUCFGR_OF64S = (1 << 8),
 116     CPUCFGR_OV64S = (1 << 9),
 117 };
 118
 119 /* DMMU configure register */
 120 enum {
 121     DMMUCFGR_NTW = (3 << 0),
 122     DMMUCFGR_NTS = (7 << 2),
 123     DMMUCFGR_NAE = (7 << 5),
 124     DMMUCFGR_CRI = (1 << 8),
 125     DMMUCFGR_PRI = (1 << 9),
 126     DMMUCFGR_TEIRI = (1 << 10),
 127     DMMUCFGR_HTR = (1 << 11),
 128 };
 129
 130 /* IMMU configure register */
 131 enum {
 132     IMMUCFGR_NTW = (3 << 0),
 133     IMMUCFGR_NTS = (7 << 2),
 134     IMMUCFGR_NAE = (7 << 5),
 135     IMMUCFGR_CRI = (1 << 8),
 136     IMMUCFGR_PRI = (1 << 9),
 137     IMMUCFGR_TEIRI = (1 << 10),
 138     IMMUCFGR_HTR = (1 << 11),
 139 };
 140
 141 /* Float point control status register */
 142 enum {
 143     FPCSR_FPEE = 1,
 144     FPCSR_RM = (3 << 1),
 145     FPCSR_OVF = (1 << 3),
 146     FPCSR_UNF = (1 << 4),
 147     FPCSR_SNF = (1 << 5),
 148     FPCSR_QNF = (1 << 6),
 149     FPCSR_ZF = (1 << 7),
 150     FPCSR_IXF = (1 << 8),
 151     FPCSR_IVF = (1 << 9),
 152     FPCSR_INF = (1 << 10),
 153     FPCSR_DZF = (1 << 11),
 154 };
 155
 156 /* Exceptions indices */
 157 enum {
 158     EXCP_RESET    = 0x1,
 159     EXCP_BUSERR   = 0x2,
 160     EXCP_DPF      = 0x3,
 161     EXCP_IPF      = 0x4,
 162     EXCP_TICK     = 0x5,
 163     EXCP_ALIGN    = 0x6,
 164     EXCP_ILLEGAL  = 0x7,
 165     EXCP_INT      = 0x8,
 166     EXCP_DTLBMISS = 0x9,
 167     EXCP_ITLBMISS = 0xa,
 168     EXCP_RANGE    = 0xb,
 169     EXCP_SYSCALL  = 0xc,
 170     EXCP_FPE      = 0xd,
 171     EXCP_TRAP     = 0xe,
 172     EXCP_NR,
 173 };
 174
 175 /* Supervisor register */
 176 enum {
 177     SR_SM = (1 << 0),
 178     SR_TEE = (1 << 1),
 179     SR_IEE = (1 << 2),
 180     SR_DCE = (1 << 3),
 181     SR_ICE = (1 << 4),
 182     SR_DME = (1 << 5),
 183     SR_IME = (1 << 6),
 184     SR_LEE = (1 << 7),
 185     SR_CE  = (1 << 8),
 186     SR_F   = (1 << 9),
 187     SR_CY  = (1 << 10),
 188     SR_OV  = (1 << 11),
 189     SR_OVE = (1 << 12),
 190     SR_DSX = (1 << 13),
 191     SR_EPH = (1 << 14),
 192     SR_FO  = (1 << 15),
 193     SR_SUMRA = (1 << 16),
 194     SR_SCE = (1 << 17),
 195 };
 196
 197 /* OpenRISC Hardware Capabilities */
 198 enum {
 199     OPENRISC_FEATURE_NSGF = (15 << 0),
 200     OPENRISC_FEATURE_CGF = (1 << 4),
 201     OPENRISC_FEATURE_OB32S = (1 << 5),
 202     OPENRISC_FEATURE_OB64S = (1 << 6),
 203     OPENRISC_FEATURE_OF32S = (1 << 7),
 204     OPENRISC_FEATURE_OF64S = (1 << 8),
 205     OPENRISC_FEATURE_OV64S = (1 << 9),
 206 };
 207
 208 /* Tick Timer Mode Register */
 209 enum {
 210     TTMR_TP = (0xfffffff),
 211     TTMR_IP = (1 << 28),
 212     TTMR_IE = (1 << 29),
 213     TTMR_M  = (3 << 30),
 214 };
 215
 216 /* Timer Mode */
 217 enum {
 218     TIMER_NONE = (0 << 30),
 219     TIMER_INTR = (1 << 30),
 220     TIMER_SHOT = (2 << 30),
 221     TIMER_CONT = (3 << 30),
 222 };
 223
 224 /* TLB size */
 225 enum {
 226     DTLB_WAYS = 1,
 227     DTLB_SIZE = 64,
 228     DTLB_MASK = (DTLB_SIZE-1),
 229     ITLB_WAYS = 1,
 230     ITLB_SIZE = 64,
 231     ITLB_MASK = (ITLB_SIZE-1),
 232 };
 233
 234 /* TLB prot */
 235 enum {
 236     URE = (1 << 6),
 237     UWE = (1 << 7),
 238     SRE = (1 << 8),
 239     SWE = (1 << 9),
 240
 241     SXE = (1 << 6),
 242     UXE = (1 << 7),
 243 };
 244
 245 /* check if tlb available */
 246 enum {
 247     TLBRET_INVALID = -3,
 248     TLBRET_NOMATCH = -2,
 249     TLBRET_BADADDR = -1,
 250     TLBRET_MATCH = 0
 251 };
 252
 253 typedef struct OpenRISCTLBEntry {
 254     uint32_t mr;
 255     uint32_t tr;
 256 } OpenRISCTLBEntry;
 257
 258 #ifndef CONFIG_USER_ONLY
 259 typedef struct CPUOpenRISCTLBContext {
 260     OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
 261     OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
 262
 263     int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
 264                                          hwaddr *physical,
 265                                          int *prot,
 266                                          target_ulong address, int rw);
 267     int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
 268                                          hwaddr *physical,
 269                                          int *prot,
 270                                          target_ulong address, int rw);
 271 } CPUOpenRISCTLBContext;
 272 #endif
 273
 274 typedef struct CPUOpenRISCState {
 275     target_ulong gpr[32];     /* General registers */
 276     target_ulong pc;          /* Program counter */
 277     target_ulong npc;         /* Next PC */
 278     target_ulong ppc;         /* Prev PC */
 279     target_ulong jmp_pc;      /* Jump PC */
 280
 281     target_ulong machi;       /* Multiply register MACHI */
 282     target_ulong maclo;       /* Multiply register MACLO */
 283
 284     target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
 285     target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
 286
 287     target_ulong epcr;        /* Exception PC register */
 288     target_ulong eear;        /* Exception EA register */
 289
 290     uint32_t sr;              /* Supervisor register */
 291     uint32_t vr;              /* Version register */
 292     uint32_t upr;             /* Unit presence register */
 293     uint32_t cpucfgr;         /* CPU configure register */
 294     uint32_t dmmucfgr;        /* DMMU configure register */
 295     uint32_t immucfgr;        /* IMMU configure register */
 296     uint32_t esr;             /* Exception supervisor register */
 297     uint32_t fpcsr;           /* Float register */
 298     float_status fp_status;
 299
 300     uint32_t flags;           /* cpu_flags, we only use it for exception
 301                                  in solt so far.  */
 302     uint32_t btaken;          /* the SR_F bit */
 303
 304     CPU_COMMON
 305
 306     /* Fields from here on are preserved across CPU reset. */
 307 #ifndef CONFIG_USER_ONLY
 308     CPUOpenRISCTLBContext * tlb;
 309
 310     QEMUTimer *timer;
 311     uint32_t ttmr;          /* Timer tick mode register */
 312     uint32_t ttcr;          /* Timer tick count register */
 313
 314     uint32_t picmr;         /* Interrupt mask register */
 315     uint32_t picsr;         /* Interrupt contrl register*/
 316 #endif
 317     void *irq[32];          /* Interrupt irq input */
 318 } CPUOpenRISCState;
 319
 320 /**
 321  * OpenRISCCPU:
 322  * @env: #CPUOpenRISCState
 323  *
 324  * A OpenRISC CPU.
 325  */
 326 typedef struct OpenRISCCPU {
 327     /*< private >*/
 328     CPUState parent_obj;
 329     /*< public >*/
 330
 331     CPUOpenRISCState env;
 332
 333     uint32_t feature;       /* CPU Capabilities */
 334 } OpenRISCCPU;
 335
 336 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 337 {
 338     return container_of(env, OpenRISCCPU, env);
 339 }
 340
 341 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 342
 343 #define ENV_OFFSET offsetof(OpenRISCCPU, env)
 344
 345 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 346
 347 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 348 int cpu_openrisc_exec(CPUState *cpu);
 349 void openrisc_cpu_do_interrupt(CPUState *cpu);
 350 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
 351 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
 352                              fprintf_function cpu_fprintf, int flags);
 353 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 354 int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 355 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 356 void openrisc_translate_init(void);
 357 int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
 358                                   int rw, int mmu_idx);
 359 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
 360
 361 #define cpu_list cpu_openrisc_list
 362 #define cpu_exec cpu_openrisc_exec
 363 #define cpu_signal_handler cpu_openrisc_signal_handler
 364
 365 #ifndef CONFIG_USER_ONLY
 366 extern const struct VMStateDescription vmstate_openrisc_cpu;
 367
 368 /* hw/openrisc_pic.c */
 369 void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 370
 371 /* hw/openrisc_timer.c */
 372 void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
 373 void cpu_openrisc_count_update(OpenRISCCPU *cpu);
 374 void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
 375 void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 376 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 377
 378 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 379 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
 380                                 hwaddr *physical,
 381                                 int *prot, target_ulong address, int rw);
 382 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
 383                                hwaddr *physical,
 384                                int *prot, target_ulong address, int rw);
 385 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
 386                                hwaddr *physical,
 387                                int *prot, target_ulong address, int rw);
 388 #endif
 389
 390 #define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
 391
 392 #include "exec/cpu-all.h"
 393
 394 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 395                                         target_ulong *pc,
 396                                         target_ulong *cs_base, int *flags)
 397 {
 398     *pc = env->pc;
 399     *cs_base = 0;
 400     /* D_FLAG -- branch instruction exception */
 401     *flags = (env->flags & D_FLAG);
 402 }
 403
 404 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
 405 {
 406     if (!(env->sr & SR_IME)) {
 407         return MMU_NOMMU_IDX;
 408     }
 409     return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 410 }
 411
 412 #define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
 413
 414 #include "exec/exec-all.h"
 415
 416 #endif /* CPU_OPENRISC_H */