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qapi-schema: dump-guest-memory: Improve text
[qemu/ar7.git] / hw / ppc / spapr.c
blob50e5a268da42a83ae38a85b926c8f3fd896a46c5
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "hw/hw.h"
30 #include "hw/fw-path-provider.h"
31 #include "elf.h"
32 #include "net/net.h"
33 #include "sysemu/device_tree.h"
34 #include "sysemu/block-backend.h"
35 #include "sysemu/cpus.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/device_tree.h"
38 #include "kvm_ppc.h"
39 #include "migration/migration.h"
40 #include "mmu-hash64.h"
41 #include "qom/cpu.h"
42
43 #include "hw/boards.h"
44 #include "hw/ppc/ppc.h"
45 #include "hw/loader.h"
46
47 #include "hw/ppc/spapr.h"
48 #include "hw/ppc/spapr_vio.h"
49 #include "hw/pci-host/spapr.h"
50 #include "hw/ppc/xics.h"
51 #include "hw/pci/msi.h"
52
53 #include "hw/pci/pci.h"
54 #include "hw/scsi/scsi.h"
55 #include "hw/virtio/virtio-scsi.h"
56
57 #include "exec/address-spaces.h"
58 #include "hw/usb.h"
59 #include "qemu/config-file.h"
60 #include "qemu/error-report.h"
61 #include "trace.h"
62 #include "hw/nmi.h"
63
64 #include "hw/compat.h"
65 #include "qemu-common.h"
66
67 #include <libfdt.h>
68
69 /* SLOF memory layout:
70 *
71 * SLOF raw image loaded at 0, copies its romfs right below the flat
72 * device-tree, then position SLOF itself 31M below that
73 *
74 * So we set FW_OVERHEAD to 40MB which should account for all of that
75 * and more
76 *
77 * We load our kernel at 4M, leaving space for SLOF initial image
78 */
79 #define FDT_MAX_SIZE 0x100000
80 #define RTAS_MAX_SIZE 0x10000
81 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
82 #define FW_MAX_SIZE 0x400000
83 #define FW_FILE_NAME "slof.bin"
84 #define FW_OVERHEAD 0x2800000
85 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
86
87 #define MIN_RMA_SLOF 128UL
88
89 #define TIMEBASE_FREQ 512000000ULL
90
91 #define PHANDLE_XICP 0x00001111
92
93 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
94
95 static XICSState *try_create_xics(const char *type, int nr_servers,
96 int nr_irqs, Error **errp)
97 {
98 Error *err = NULL;
99 DeviceState *dev;
100
101 dev = qdev_create(NULL, type);
102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
104 object_property_set_bool(OBJECT(dev), true, "realized", &err);
105 if (err) {
106 error_propagate(errp, err);
107 object_unparent(OBJECT(dev));
108 return NULL;
109 }
110 return XICS_COMMON(dev);
111 }
112
113 static XICSState *xics_system_init(MachineState *machine,
114 int nr_servers, int nr_irqs)
115 {
116 XICSState *icp = NULL;
117
118 if (kvm_enabled()) {
119 Error *err = NULL;
120
121 if (machine_kernel_irqchip_allowed(machine)) {
122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
123 }
124 if (machine_kernel_irqchip_required(machine) && !icp) {
125 error_reportf_err(err,
126 "kernel_irqchip requested but unavailable: ");
127 } else {
128 error_free(err);
129 }
130 }
131
132 if (!icp) {
133 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort);
134 }
135
136 return icp;
137 }
138
139 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
140 int smt_threads)
141 {
142 int i, ret = 0;
143 uint32_t servers_prop[smt_threads];
144 uint32_t gservers_prop[smt_threads * 2];
145 int index = ppc_get_vcpu_dt_id(cpu);
146
147 if (cpu->cpu_version) {
148 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
149 if (ret < 0) {
150 return ret;
151 }
152 }
153
154 /* Build interrupt servers and gservers properties */
155 for (i = 0; i < smt_threads; i++) {
156 servers_prop[i] = cpu_to_be32(index + i);
157 /* Hack, direct the group queues back to cpu 0 */
158 gservers_prop[i*2] = cpu_to_be32(index + i);
159 gservers_prop[i*2 + 1] = 0;
160 }
161 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
162 servers_prop, sizeof(servers_prop));
163 if (ret < 0) {
164 return ret;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
167 gservers_prop, sizeof(gservers_prop));
168
169 return ret;
170 }
171
172 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
173 {
174 int ret = 0;
175 PowerPCCPU *cpu = POWERPC_CPU(cs);
176 int index = ppc_get_vcpu_dt_id(cpu);
177 uint32_t associativity[] = {cpu_to_be32(0x5),
178 cpu_to_be32(0x0),
179 cpu_to_be32(0x0),
180 cpu_to_be32(0x0),
181 cpu_to_be32(cs->numa_node),
182 cpu_to_be32(index)};
183
184 /* Advertise NUMA via ibm,associativity */
185 if (nb_numa_nodes > 1) {
186 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
187 sizeof(associativity));
188 }
189
190 return ret;
191 }
192
193 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
194 {
195 int ret = 0, offset, cpus_offset;
196 CPUState *cs;
197 char cpu_model[32];
198 int smt = kvmppc_smt_threads();
199 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
200
201 CPU_FOREACH(cs) {
202 PowerPCCPU *cpu = POWERPC_CPU(cs);
203 DeviceClass *dc = DEVICE_GET_CLASS(cs);
204 int index = ppc_get_vcpu_dt_id(cpu);
205
206 if ((index % smt) != 0) {
207 continue;
208 }
209
210 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
211
212 cpus_offset = fdt_path_offset(fdt, "/cpus");
213 if (cpus_offset < 0) {
214 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
215 "cpus");
216 if (cpus_offset < 0) {
217 return cpus_offset;
218 }
219 }
220 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
221 if (offset < 0) {
222 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
223 if (offset < 0) {
224 return offset;
225 }
226 }
227
228 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
229 pft_size_prop, sizeof(pft_size_prop));
230 if (ret < 0) {
231 return ret;
232 }
233
234 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
240 ppc_get_compat_smt_threads(cpu));
241 if (ret < 0) {
242 return ret;
243 }
244 }
245 return ret;
246 }
247
248
249 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
250 size_t maxsize)
251 {
252 size_t maxcells = maxsize / sizeof(uint32_t);
253 int i, j, count;
254 uint32_t *p = prop;
255
256 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
257 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
258
259 if (!sps->page_shift) {
260 break;
261 }
262 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
263 if (sps->enc[count].page_shift == 0) {
264 break;
265 }
266 }
267 if ((p - prop) >= (maxcells - 3 - count * 2)) {
268 break;
269 }
270 *(p++) = cpu_to_be32(sps->page_shift);
271 *(p++) = cpu_to_be32(sps->slb_enc);
272 *(p++) = cpu_to_be32(count);
273 for (j = 0; j < count; j++) {
274 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
275 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
276 }
277 }
278
279 return (p - prop) * sizeof(uint32_t);
280 }
281
282 static hwaddr spapr_node0_size(void)
283 {
284 MachineState *machine = MACHINE(qdev_get_machine());
285
286 if (nb_numa_nodes) {
287 int i;
288 for (i = 0; i < nb_numa_nodes; ++i) {
289 if (numa_info[i].node_mem) {
290 return MIN(pow2floor(numa_info[i].node_mem),
291 machine->ram_size);
292 }
293 }
294 }
295 return machine->ram_size;
296 }
297
298 #define _FDT(exp) \
299 do { \
300 int ret = (exp); \
301 if (ret < 0) { \
302 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
303 #exp, fdt_strerror(ret)); \
304 exit(1); \
305 } \
306 } while (0)
307
308 static void add_str(GString *s, const gchar *s1)
309 {
310 g_string_append_len(s, s1, strlen(s1) + 1);
311 }
312
313 static void *spapr_create_fdt_skel(hwaddr initrd_base,
314 hwaddr initrd_size,
315 hwaddr kernel_size,
316 bool little_endian,
317 const char *kernel_cmdline,
318 uint32_t epow_irq)
319 {
320 void *fdt;
321 uint32_t start_prop = cpu_to_be32(initrd_base);
322 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
323 GString *hypertas = g_string_sized_new(256);
324 GString *qemu_hypertas = g_string_sized_new(256);
325 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
326 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
327 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
328 char *buf;
329
330 add_str(hypertas, "hcall-pft");
331 add_str(hypertas, "hcall-term");
332 add_str(hypertas, "hcall-dabr");
333 add_str(hypertas, "hcall-interrupt");
334 add_str(hypertas, "hcall-tce");
335 add_str(hypertas, "hcall-vio");
336 add_str(hypertas, "hcall-splpar");
337 add_str(hypertas, "hcall-bulk");
338 add_str(hypertas, "hcall-set-mode");
339 add_str(qemu_hypertas, "hcall-memop1");
340
341 fdt = g_malloc0(FDT_MAX_SIZE);
342 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
343
344 if (kernel_size) {
345 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
346 }
347 if (initrd_size) {
348 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
349 }
350 _FDT((fdt_finish_reservemap(fdt)));
351
352 /* Root node */
353 _FDT((fdt_begin_node(fdt, "")));
354 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
355 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
356 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
357
358 /*
359 * Add info to guest to indentify which host is it being run on
360 * and what is the uuid of the guest
361 */
362 if (kvmppc_get_host_model(&buf)) {
363 _FDT((fdt_property_string(fdt, "host-model", buf)));
364 g_free(buf);
365 }
366 if (kvmppc_get_host_serial(&buf)) {
367 _FDT((fdt_property_string(fdt, "host-serial", buf)));
368 g_free(buf);
369 }
370
371 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
372 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
373 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
374 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
375 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
376 qemu_uuid[14], qemu_uuid[15]);
377
378 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
379 if (qemu_uuid_set) {
380 _FDT((fdt_property_string(fdt, "system-id", buf)));
381 }
382 g_free(buf);
383
384 if (qemu_get_vm_name()) {
385 _FDT((fdt_property_string(fdt, "ibm,partition-name",
386 qemu_get_vm_name())));
387 }
388
389 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
390 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
391
392 /* /chosen */
393 _FDT((fdt_begin_node(fdt, "chosen")));
394
395 /* Set Form1_affinity */
396 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
397
398 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
399 _FDT((fdt_property(fdt, "linux,initrd-start",
400 &start_prop, sizeof(start_prop))));
401 _FDT((fdt_property(fdt, "linux,initrd-end",
402 &end_prop, sizeof(end_prop))));
403 if (kernel_size) {
404 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
405 cpu_to_be64(kernel_size) };
406
407 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
408 if (little_endian) {
409 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
410 }
411 }
412 if (boot_menu) {
413 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
414 }
415 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
416 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
417 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
418
419 _FDT((fdt_end_node(fdt)));
420
421 /* RTAS */
422 _FDT((fdt_begin_node(fdt, "rtas")));
423
424 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
425 add_str(hypertas, "hcall-multi-tce");
426 }
427 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
428 hypertas->len)));
429 g_string_free(hypertas, TRUE);
430 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
431 qemu_hypertas->len)));
432 g_string_free(qemu_hypertas, TRUE);
433
434 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
435 refpoints, sizeof(refpoints))));
436
437 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
438 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
439 RTAS_EVENT_SCAN_RATE)));
440
441 if (msi_supported) {
442 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
443 }
444
445 /*
446 * According to PAPR, rtas ibm,os-term does not guarantee a return
447 * back to the guest cpu.
448 *
449 * While an additional ibm,extended-os-term property indicates that
450 * rtas call return will always occur. Set this property.
451 */
452 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
453
454 _FDT((fdt_end_node(fdt)));
455
456 /* interrupt controller */
457 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
458
459 _FDT((fdt_property_string(fdt, "device_type",
460 "PowerPC-External-Interrupt-Presentation")));
461 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
462 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
463 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
464 interrupt_server_ranges_prop,
465 sizeof(interrupt_server_ranges_prop))));
466 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
467 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
468 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
469
470 _FDT((fdt_end_node(fdt)));
471
472 /* vdevice */
473 _FDT((fdt_begin_node(fdt, "vdevice")));
474
475 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
476 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
477 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
478 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
479 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
480 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
481
482 _FDT((fdt_end_node(fdt)));
483
484 /* event-sources */
485 spapr_events_fdt_skel(fdt, epow_irq);
486
487 /* /hypervisor node */
488 if (kvm_enabled()) {
489 uint8_t hypercall[16];
490
491 /* indicate KVM hypercall interface */
492 _FDT((fdt_begin_node(fdt, "hypervisor")));
493 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
494 if (kvmppc_has_cap_fixup_hcalls()) {
495 /*
496 * Older KVM versions with older guest kernels were broken with the
497 * magic page, don't allow the guest to map it.
498 */
499 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
500 sizeof(hypercall));
501 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
502 sizeof(hypercall))));
503 }
504 _FDT((fdt_end_node(fdt)));
505 }
506
507 _FDT((fdt_end_node(fdt))); /* close root node */
508 _FDT((fdt_finish(fdt)));
509
510 return fdt;
511 }
512
513 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
514 hwaddr size)
515 {
516 uint32_t associativity[] = {
517 cpu_to_be32(0x4), /* length */
518 cpu_to_be32(0x0), cpu_to_be32(0x0),
519 cpu_to_be32(0x0), cpu_to_be32(nodeid)
520 };
521 char mem_name[32];
522 uint64_t mem_reg_property[2];
523 int off;
524
525 mem_reg_property[0] = cpu_to_be64(start);
526 mem_reg_property[1] = cpu_to_be64(size);
527
528 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
529 off = fdt_add_subnode(fdt, 0, mem_name);
530 _FDT(off);
531 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
532 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
533 sizeof(mem_reg_property))));
534 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
535 sizeof(associativity))));
536 return off;
537 }
538
539 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
540 {
541 MachineState *machine = MACHINE(spapr);
542 hwaddr mem_start, node_size;
543 int i, nb_nodes = nb_numa_nodes;
544 NodeInfo *nodes = numa_info;
545 NodeInfo ramnode;
546
547 /* No NUMA nodes, assume there is just one node with whole RAM */
548 if (!nb_numa_nodes) {
549 nb_nodes = 1;
550 ramnode.node_mem = machine->ram_size;
551 nodes = &ramnode;
552 }
553
554 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
555 if (!nodes[i].node_mem) {
556 continue;
557 }
558 if (mem_start >= machine->ram_size) {
559 node_size = 0;
560 } else {
561 node_size = nodes[i].node_mem;
562 if (node_size > machine->ram_size - mem_start) {
563 node_size = machine->ram_size - mem_start;
564 }
565 }
566 if (!mem_start) {
567 /* ppc_spapr_init() checks for rma_size <= node0_size already */
568 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
569 mem_start += spapr->rma_size;
570 node_size -= spapr->rma_size;
571 }
572 for ( ; node_size; ) {
573 hwaddr sizetmp = pow2floor(node_size);
574
575 /* mem_start != 0 here */
576 if (ctzl(mem_start) < ctzl(sizetmp)) {
577 sizetmp = 1ULL << ctzl(mem_start);
578 }
579
580 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
581 node_size -= sizetmp;
582 mem_start += sizetmp;
583 }
584 }
585
586 return 0;
587 }
588
589 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
590 sPAPRMachineState *spapr)
591 {
592 PowerPCCPU *cpu = POWERPC_CPU(cs);
593 CPUPPCState *env = &cpu->env;
594 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
595 int index = ppc_get_vcpu_dt_id(cpu);
596 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
597 0xffffffff, 0xffffffff};
598 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
599 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
600 uint32_t page_sizes_prop[64];
601 size_t page_sizes_prop_size;
602 uint32_t vcpus_per_socket = smp_threads * smp_cores;
603 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
604
605 /* Note: we keep CI large pages off for now because a 64K capable guest
606 * provisioned with large pages might otherwise try to map a qemu
607 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
608 * even if that qemu runs on a 4k host.
609 *
610 * We can later add this bit back when we are confident this is not
611 * an issue (!HV KVM or 64K host)
612 */
613 uint8_t pa_features_206[] = { 6, 0,
614 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
615 uint8_t pa_features_207[] = { 24, 0,
616 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
617 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
618 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
619 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
620 uint8_t *pa_features;
621 size_t pa_size;
622
623 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
624 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
625
626 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
627 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
628 env->dcache_line_size)));
629 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
630 env->dcache_line_size)));
631 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
632 env->icache_line_size)));
633 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
634 env->icache_line_size)));
635
636 if (pcc->l1_dcache_size) {
637 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
638 pcc->l1_dcache_size)));
639 } else {
640 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
641 }
642 if (pcc->l1_icache_size) {
643 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
644 pcc->l1_icache_size)));
645 } else {
646 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
647 }
648
649 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
650 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
651 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
652 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
653 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
654 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
655
656 if (env->spr_cb[SPR_PURR].oea_read) {
657 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
658 }
659
660 if (env->mmu_model & POWERPC_MMU_1TSEG) {
661 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
662 segs, sizeof(segs))));
663 }
664
665 /* Advertise VMX/VSX (vector extensions) if available
666 * 0 / no property == no vector extensions
667 * 1 == VMX / Altivec available
668 * 2 == VSX available */
669 if (env->insns_flags & PPC_ALTIVEC) {
670 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
671
672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
673 }
674
675 /* Advertise DFP (Decimal Floating Point) if available
676 * 0 / no property == no DFP
677 * 1 == DFP available */
678 if (env->insns_flags2 & PPC2_DFP) {
679 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
680 }
681
682 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
683 sizeof(page_sizes_prop));
684 if (page_sizes_prop_size) {
685 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
686 page_sizes_prop, page_sizes_prop_size)));
687 }
688
689 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
690 if (env->mmu_model == POWERPC_MMU_2_06) {
691 pa_features = pa_features_206;
692 pa_size = sizeof(pa_features_206);
693 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
694 pa_features = pa_features_207;
695 pa_size = sizeof(pa_features_207);
696 }
697 if (env->ci_large_pages) {
698 pa_features[3] |= 0x20;
699 }
700 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
701
702 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
703 cs->cpu_index / vcpus_per_socket)));
704
705 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
706 pft_size_prop, sizeof(pft_size_prop))));
707
708 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
709
710 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
711 ppc_get_compat_smt_threads(cpu)));
712 }
713
714 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
715 {
716 CPUState *cs;
717 int cpus_offset;
718 char *nodename;
719 int smt = kvmppc_smt_threads();
720
721 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
722 _FDT(cpus_offset);
723 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
724 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
725
726 /*
727 * We walk the CPUs in reverse order to ensure that CPU DT nodes
728 * created by fdt_add_subnode() end up in the right order in FDT
729 * for the guest kernel the enumerate the CPUs correctly.
730 */
731 CPU_FOREACH_REVERSE(cs) {
732 PowerPCCPU *cpu = POWERPC_CPU(cs);
733 int index = ppc_get_vcpu_dt_id(cpu);
734 DeviceClass *dc = DEVICE_GET_CLASS(cs);
735 int offset;
736
737 if ((index % smt) != 0) {
738 continue;
739 }
740
741 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
742 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
743 g_free(nodename);
744 _FDT(offset);
745 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
746 }
747
748 }
749
750 /*
751 * Adds ibm,dynamic-reconfiguration-memory node.
752 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
753 * of this device tree node.
754 */
755 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
756 {
757 MachineState *machine = MACHINE(spapr);
758 int ret, i, offset;
759 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
760 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
761 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
762 uint32_t *int_buf, *cur_index, buf_len;
763 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
764
765 /*
766 * Allocate enough buffer size to fit in ibm,dynamic-memory
767 * or ibm,associativity-lookup-arrays
768 */
769 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
770 * sizeof(uint32_t);
771 cur_index = int_buf = g_malloc0(buf_len);
772
773 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
774
775 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
776 sizeof(prop_lmb_size));
777 if (ret < 0) {
778 goto out;
779 }
780
781 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
782 if (ret < 0) {
783 goto out;
784 }
785
786 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
787 if (ret < 0) {
788 goto out;
789 }
790
791 /* ibm,dynamic-memory */
792 int_buf[0] = cpu_to_be32(nr_lmbs);
793 cur_index++;
794 for (i = 0; i < nr_lmbs; i++) {
795 sPAPRDRConnector *drc;
796 sPAPRDRConnectorClass *drck;
797 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
798 uint32_t *dynamic_memory = cur_index;
799
800 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
801 addr/lmb_size);
802 g_assert(drc);
803 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
804
805 dynamic_memory[0] = cpu_to_be32(addr >> 32);
806 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
807 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
808 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
809 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
810 if (addr < machine->ram_size ||
811 memory_region_present(get_system_memory(), addr)) {
812 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
813 } else {
814 dynamic_memory[5] = cpu_to_be32(0);
815 }
816
817 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
818 }
819 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
820 if (ret < 0) {
821 goto out;
822 }
823
824 /* ibm,associativity-lookup-arrays */
825 cur_index = int_buf;
826 int_buf[0] = cpu_to_be32(nr_nodes);
827 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
828 cur_index += 2;
829 for (i = 0; i < nr_nodes; i++) {
830 uint32_t associativity[] = {
831 cpu_to_be32(0x0),
832 cpu_to_be32(0x0),
833 cpu_to_be32(0x0),
834 cpu_to_be32(i)
835 };
836 memcpy(cur_index, associativity, sizeof(associativity));
837 cur_index += 4;
838 }
839 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
840 (cur_index - int_buf) * sizeof(uint32_t));
841 out:
842 g_free(int_buf);
843 return ret;
844 }
845
846 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
847 target_ulong addr, target_ulong size,
848 bool cpu_update, bool memory_update)
849 {
850 void *fdt, *fdt_skel;
851 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
852 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
853
854 size -= sizeof(hdr);
855
856 /* Create sceleton */
857 fdt_skel = g_malloc0(size);
858 _FDT((fdt_create(fdt_skel, size)));
859 _FDT((fdt_begin_node(fdt_skel, "")));
860 _FDT((fdt_end_node(fdt_skel)));
861 _FDT((fdt_finish(fdt_skel)));
862 fdt = g_malloc0(size);
863 _FDT((fdt_open_into(fdt_skel, fdt, size)));
864 g_free(fdt_skel);
865
866 /* Fixup cpu nodes */
867 if (cpu_update) {
868 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
869 }
870
871 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */
872 if (memory_update && smc->dr_lmb_enabled) {
873 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
874 }
875
876 /* Pack resulting tree */
877 _FDT((fdt_pack(fdt)));
878
879 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
880 trace_spapr_cas_failed(size);
881 return -1;
882 }
883
884 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
885 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
886 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
887 g_free(fdt);
888
889 return 0;
890 }
891
892 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
893 hwaddr fdt_addr,
894 hwaddr rtas_addr,
895 hwaddr rtas_size)
896 {
897 MachineState *machine = MACHINE(qdev_get_machine());
898 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
899 const char *boot_device = machine->boot_order;
900 int ret, i;
901 size_t cb = 0;
902 char *bootlist;
903 void *fdt;
904 sPAPRPHBState *phb;
905
906 fdt = g_malloc(FDT_MAX_SIZE);
907
908 /* open out the base tree into a temp buffer for the final tweaks */
909 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
910
911 ret = spapr_populate_memory(spapr, fdt);
912 if (ret < 0) {
913 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
914 exit(1);
915 }
916
917 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
918 if (ret < 0) {
919 fprintf(stderr, "couldn't setup vio devices in fdt\n");
920 exit(1);
921 }
922
923 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
924 ret = spapr_rng_populate_dt(fdt);
925 if (ret < 0) {
926 fprintf(stderr, "could not set up rng device in the fdt\n");
927 exit(1);
928 }
929 }
930
931 QLIST_FOREACH(phb, &spapr->phbs, list) {
932 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
933 }
934
935 if (ret < 0) {
936 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
937 exit(1);
938 }
939
940 /* RTAS */
941 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
942 if (ret < 0) {
943 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
944 }
945
946 /* cpus */
947 spapr_populate_cpus_dt_node(fdt, spapr);
948
949 bootlist = get_boot_devices_list(&cb, true);
950 if (cb && bootlist) {
951 int offset = fdt_path_offset(fdt, "/chosen");
952 if (offset < 0) {
953 exit(1);
954 }
955 for (i = 0; i < cb; i++) {
956 if (bootlist[i] == '\n') {
957 bootlist[i] = ' ';
958 }
959
960 }
961 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
962 }
963
964 if (boot_device && strlen(boot_device)) {
965 int offset = fdt_path_offset(fdt, "/chosen");
966
967 if (offset < 0) {
968 exit(1);
969 }
970 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
971 }
972
973 if (!spapr->has_graphics) {
974 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
975 }
976
977 if (smc->dr_lmb_enabled) {
978 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
979 }
980
981 _FDT((fdt_pack(fdt)));
982
983 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
984 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
985 fdt_totalsize(fdt), FDT_MAX_SIZE);
986 exit(1);
987 }
988
989 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
990 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
991
992 g_free(bootlist);
993 g_free(fdt);
994 }
995
996 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
997 {
998 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
999 }
1000
1001 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1002 {
1003 CPUPPCState *env = &cpu->env;
1004
1005 if (msr_pr) {
1006 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1007 env->gpr[3] = H_PRIVILEGE;
1008 } else {
1009 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1010 }
1011 }
1012
1013 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1014 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1015 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1016 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1017 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1018
1019 static void spapr_alloc_htab(sPAPRMachineState *spapr)
1020 {
1021 long shift;
1022 int index;
1023
1024 /* allocate hash page table. For now we always make this 16mb,
1025 * later we should probably make it scale to the size of guest
1026 * RAM */
1027
1028 shift = kvmppc_reset_htab(spapr->htab_shift);
1029 if (shift < 0) {
1030 /*
1031 * For HV KVM, host kernel will return -ENOMEM when requested
1032 * HTAB size can't be allocated.
1033 */
1034 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem");
1035 } else if (shift > 0) {
1036 /*
1037 * Kernel handles htab, we don't need to allocate one
1038 *
1039 * Older kernels can fall back to lower HTAB shift values,
1040 * but we don't allow booting of such guests.
1041 */
1042 if (shift != spapr->htab_shift) {
1043 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem");
1044 }
1045
1046 spapr->htab_shift = shift;
1047 kvmppc_kern_htab = true;
1048 } else {
1049 /* Allocate htab */
1050 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
1051
1052 /* And clear it */
1053 memset(spapr->htab, 0, HTAB_SIZE(spapr));
1054
1055 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
1056 DIRTY_HPTE(HPTE(spapr->htab, index));
1057 }
1058 }
1059 }
1060
1061 /*
1062 * Clear HTAB entries during reset.
1063 *
1064 * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is
1065 * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually.
1066 */
1067 static void spapr_reset_htab(sPAPRMachineState *spapr)
1068 {
1069 long shift;
1070 int index;
1071
1072 shift = kvmppc_reset_htab(spapr->htab_shift);
1073 if (shift < 0) {
1074 error_setg(&error_abort, "Failed to reset HTAB");
1075 } else if (shift > 0) {
1076 if (shift != spapr->htab_shift) {
1077 error_setg(&error_abort, "Requested HTAB allocation failed during reset");
1078 }
1079
1080 /* Tell readers to update their file descriptor */
1081 if (spapr->htab_fd >= 0) {
1082 spapr->htab_fd_stale = true;
1083 }
1084 } else {
1085 memset(spapr->htab, 0, HTAB_SIZE(spapr));
1086
1087 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
1088 DIRTY_HPTE(HPTE(spapr->htab, index));
1089 }
1090 }
1091
1092 /* Update the RMA size if necessary */
1093 if (spapr->vrma_adjust) {
1094 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1095 spapr->htab_shift);
1096 }
1097 }
1098
1099 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1100 {
1101 bool matched = false;
1102
1103 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1104 matched = true;
1105 }
1106
1107 if (!matched) {
1108 error_report("Device %s is not supported by this machine yet.",
1109 qdev_fw_name(DEVICE(sbdev)));
1110 exit(1);
1111 }
1112
1113 return 0;
1114 }
1115
1116 /*
1117 * A guest reset will cause spapr->htab_fd to become stale if being used.
1118 * Reopen the file descriptor to make sure the whole HTAB is properly read.
1119 */
1120 static int spapr_check_htab_fd(sPAPRMachineState *spapr)
1121 {
1122 int rc = 0;
1123
1124 if (spapr->htab_fd_stale) {
1125 close(spapr->htab_fd);
1126 spapr->htab_fd = kvmppc_get_htab_fd(false);
1127 if (spapr->htab_fd < 0) {
1128 error_report("Unable to open fd for reading hash table from KVM: "
1129 "%s", strerror(errno));
1130 rc = -1;
1131 }
1132 spapr->htab_fd_stale = false;
1133 }
1134
1135 return rc;
1136 }
1137
1138 static void ppc_spapr_reset(void)
1139 {
1140 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1141 PowerPCCPU *first_ppc_cpu;
1142 uint32_t rtas_limit;
1143
1144 /* Check for unknown sysbus devices */
1145 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1146
1147 /* Reset the hash table & recalc the RMA */
1148 spapr_reset_htab(spapr);
1149
1150 qemu_devices_reset();
1151
1152 /*
1153 * We place the device tree and RTAS just below either the top of the RMA,
1154 * or just below 2GB, whichever is lowere, so that it can be
1155 * processed with 32-bit real mode code if necessary
1156 */
1157 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1158 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1159 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1160
1161 /* Load the fdt */
1162 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1163 spapr->rtas_size);
1164
1165 /* Copy RTAS over */
1166 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1167 spapr->rtas_size);
1168
1169 /* Set up the entry state */
1170 first_ppc_cpu = POWERPC_CPU(first_cpu);
1171 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1172 first_ppc_cpu->env.gpr[5] = 0;
1173 first_cpu->halted = 0;
1174 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1175
1176 }
1177
1178 static void spapr_cpu_reset(void *opaque)
1179 {
1180 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1181 PowerPCCPU *cpu = opaque;
1182 CPUState *cs = CPU(cpu);
1183 CPUPPCState *env = &cpu->env;
1184
1185 cpu_reset(cs);
1186
1187 /* All CPUs start halted. CPU0 is unhalted from the machine level
1188 * reset code and the rest are explicitly started up by the guest
1189 * using an RTAS call */
1190 cs->halted = 1;
1191
1192 env->spr[SPR_HIOR] = 0;
1193
1194 env->external_htab = (uint8_t *)spapr->htab;
1195 if (kvm_enabled() && !env->external_htab) {
1196 /*
1197 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
1198 * functions do the right thing.
1199 */
1200 env->external_htab = (void *)1;
1201 }
1202 env->htab_base = -1;
1203 /*
1204 * htab_mask is the mask used to normalize hash value to PTEG index.
1205 * htab_shift is log2 of hash table size.
1206 * We have 8 hpte per group, and each hpte is 16 bytes.
1207 * ie have 128 bytes per hpte entry.
1208 */
1209 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1;
1210 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
1211 (spapr->htab_shift - 18);
1212 }
1213
1214 static void spapr_create_nvram(sPAPRMachineState *spapr)
1215 {
1216 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1217 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1218
1219 if (dinfo) {
1220 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1221 &error_fatal);
1222 }
1223
1224 qdev_init_nofail(dev);
1225
1226 spapr->nvram = (struct sPAPRNVRAM *)dev;
1227 }
1228
1229 static void spapr_rtc_create(sPAPRMachineState *spapr)
1230 {
1231 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1232
1233 qdev_init_nofail(dev);
1234 spapr->rtc = dev;
1235
1236 object_property_add_alias(qdev_get_machine(), "rtc-time",
1237 OBJECT(spapr->rtc), "date", NULL);
1238 }
1239
1240 /* Returns whether we want to use VGA or not */
1241 static int spapr_vga_init(PCIBus *pci_bus)
1242 {
1243 switch (vga_interface_type) {
1244 case VGA_NONE:
1245 return false;
1246 case VGA_DEVICE:
1247 return true;
1248 case VGA_STD:
1249 case VGA_VIRTIO:
1250 return pci_vga_init(pci_bus) != NULL;
1251 default:
1252 fprintf(stderr, "This vga model is not supported,"
1253 "currently it only supports -vga std\n");
1254 exit(0);
1255 }
1256 }
1257
1258 static int spapr_post_load(void *opaque, int version_id)
1259 {
1260 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1261 int err = 0;
1262
1263 /* In earlier versions, there was no separate qdev for the PAPR
1264 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1265 * So when migrating from those versions, poke the incoming offset
1266 * value into the RTC device */
1267 if (version_id < 3) {
1268 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1269 }
1270
1271 return err;
1272 }
1273
1274 static bool version_before_3(void *opaque, int version_id)
1275 {
1276 return version_id < 3;
1277 }
1278
1279 static const VMStateDescription vmstate_spapr = {
1280 .name = "spapr",
1281 .version_id = 3,
1282 .minimum_version_id = 1,
1283 .post_load = spapr_post_load,
1284 .fields = (VMStateField[]) {
1285 /* used to be @next_irq */
1286 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1287
1288 /* RTC offset */
1289 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1290
1291 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1292 VMSTATE_END_OF_LIST()
1293 },
1294 };
1295
1296 static int htab_save_setup(QEMUFile *f, void *opaque)
1297 {
1298 sPAPRMachineState *spapr = opaque;
1299
1300 /* "Iteration" header */
1301 qemu_put_be32(f, spapr->htab_shift);
1302
1303 if (spapr->htab) {
1304 spapr->htab_save_index = 0;
1305 spapr->htab_first_pass = true;
1306 } else {
1307 assert(kvm_enabled());
1308
1309 spapr->htab_fd = kvmppc_get_htab_fd(false);
1310 spapr->htab_fd_stale = false;
1311 if (spapr->htab_fd < 0) {
1312 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
1313 strerror(errno));
1314 return -1;
1315 }
1316 }
1317
1318
1319 return 0;
1320 }
1321
1322 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1323 int64_t max_ns)
1324 {
1325 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1326 int index = spapr->htab_save_index;
1327 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1328
1329 assert(spapr->htab_first_pass);
1330
1331 do {
1332 int chunkstart;
1333
1334 /* Consume invalid HPTEs */
1335 while ((index < htabslots)
1336 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1337 index++;
1338 CLEAN_HPTE(HPTE(spapr->htab, index));
1339 }
1340
1341 /* Consume valid HPTEs */
1342 chunkstart = index;
1343 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1344 && HPTE_VALID(HPTE(spapr->htab, index))) {
1345 index++;
1346 CLEAN_HPTE(HPTE(spapr->htab, index));
1347 }
1348
1349 if (index > chunkstart) {
1350 int n_valid = index - chunkstart;
1351
1352 qemu_put_be32(f, chunkstart);
1353 qemu_put_be16(f, n_valid);
1354 qemu_put_be16(f, 0);
1355 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1356 HASH_PTE_SIZE_64 * n_valid);
1357
1358 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1359 break;
1360 }
1361 }
1362 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1363
1364 if (index >= htabslots) {
1365 assert(index == htabslots);
1366 index = 0;
1367 spapr->htab_first_pass = false;
1368 }
1369 spapr->htab_save_index = index;
1370 }
1371
1372 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1373 int64_t max_ns)
1374 {
1375 bool final = max_ns < 0;
1376 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1377 int examined = 0, sent = 0;
1378 int index = spapr->htab_save_index;
1379 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1380
1381 assert(!spapr->htab_first_pass);
1382
1383 do {
1384 int chunkstart, invalidstart;
1385
1386 /* Consume non-dirty HPTEs */
1387 while ((index < htabslots)
1388 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1389 index++;
1390 examined++;
1391 }
1392
1393 chunkstart = index;
1394 /* Consume valid dirty HPTEs */
1395 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1396 && HPTE_DIRTY(HPTE(spapr->htab, index))
1397 && HPTE_VALID(HPTE(spapr->htab, index))) {
1398 CLEAN_HPTE(HPTE(spapr->htab, index));
1399 index++;
1400 examined++;
1401 }
1402
1403 invalidstart = index;
1404 /* Consume invalid dirty HPTEs */
1405 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1406 && HPTE_DIRTY(HPTE(spapr->htab, index))
1407 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1408 CLEAN_HPTE(HPTE(spapr->htab, index));
1409 index++;
1410 examined++;
1411 }
1412
1413 if (index > chunkstart) {
1414 int n_valid = invalidstart - chunkstart;
1415 int n_invalid = index - invalidstart;
1416
1417 qemu_put_be32(f, chunkstart);
1418 qemu_put_be16(f, n_valid);
1419 qemu_put_be16(f, n_invalid);
1420 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1421 HASH_PTE_SIZE_64 * n_valid);
1422 sent += index - chunkstart;
1423
1424 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1425 break;
1426 }
1427 }
1428
1429 if (examined >= htabslots) {
1430 break;
1431 }
1432
1433 if (index >= htabslots) {
1434 assert(index == htabslots);
1435 index = 0;
1436 }
1437 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1438
1439 if (index >= htabslots) {
1440 assert(index == htabslots);
1441 index = 0;
1442 }
1443
1444 spapr->htab_save_index = index;
1445
1446 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1447 }
1448
1449 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1450 #define MAX_KVM_BUF_SIZE 2048
1451
1452 static int htab_save_iterate(QEMUFile *f, void *opaque)
1453 {
1454 sPAPRMachineState *spapr = opaque;
1455 int rc = 0;
1456
1457 /* Iteration header */
1458 qemu_put_be32(f, 0);
1459
1460 if (!spapr->htab) {
1461 assert(kvm_enabled());
1462
1463 rc = spapr_check_htab_fd(spapr);
1464 if (rc < 0) {
1465 return rc;
1466 }
1467
1468 rc = kvmppc_save_htab(f, spapr->htab_fd,
1469 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1470 if (rc < 0) {
1471 return rc;
1472 }
1473 } else if (spapr->htab_first_pass) {
1474 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1475 } else {
1476 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1477 }
1478
1479 /* End marker */
1480 qemu_put_be32(f, 0);
1481 qemu_put_be16(f, 0);
1482 qemu_put_be16(f, 0);
1483
1484 return rc;
1485 }
1486
1487 static int htab_save_complete(QEMUFile *f, void *opaque)
1488 {
1489 sPAPRMachineState *spapr = opaque;
1490
1491 /* Iteration header */
1492 qemu_put_be32(f, 0);
1493
1494 if (!spapr->htab) {
1495 int rc;
1496
1497 assert(kvm_enabled());
1498
1499 rc = spapr_check_htab_fd(spapr);
1500 if (rc < 0) {
1501 return rc;
1502 }
1503
1504 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
1505 if (rc < 0) {
1506 return rc;
1507 }
1508 close(spapr->htab_fd);
1509 spapr->htab_fd = -1;
1510 } else {
1511 htab_save_later_pass(f, spapr, -1);
1512 }
1513
1514 /* End marker */
1515 qemu_put_be32(f, 0);
1516 qemu_put_be16(f, 0);
1517 qemu_put_be16(f, 0);
1518
1519 return 0;
1520 }
1521
1522 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1523 {
1524 sPAPRMachineState *spapr = opaque;
1525 uint32_t section_hdr;
1526 int fd = -1;
1527
1528 if (version_id < 1 || version_id > 1) {
1529 fprintf(stderr, "htab_load() bad version\n");
1530 return -EINVAL;
1531 }
1532
1533 section_hdr = qemu_get_be32(f);
1534
1535 if (section_hdr) {
1536 /* First section, just the hash shift */
1537 if (spapr->htab_shift != section_hdr) {
1538 error_report("htab_shift mismatch: source %d target %d",
1539 section_hdr, spapr->htab_shift);
1540 return -EINVAL;
1541 }
1542 return 0;
1543 }
1544
1545 if (!spapr->htab) {
1546 assert(kvm_enabled());
1547
1548 fd = kvmppc_get_htab_fd(true);
1549 if (fd < 0) {
1550 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
1551 strerror(errno));
1552 }
1553 }
1554
1555 while (true) {
1556 uint32_t index;
1557 uint16_t n_valid, n_invalid;
1558
1559 index = qemu_get_be32(f);
1560 n_valid = qemu_get_be16(f);
1561 n_invalid = qemu_get_be16(f);
1562
1563 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1564 /* End of Stream */
1565 break;
1566 }
1567
1568 if ((index + n_valid + n_invalid) >
1569 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1570 /* Bad index in stream */
1571 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
1572 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
1573 spapr->htab_shift);
1574 return -EINVAL;
1575 }
1576
1577 if (spapr->htab) {
1578 if (n_valid) {
1579 qemu_get_buffer(f, HPTE(spapr->htab, index),
1580 HASH_PTE_SIZE_64 * n_valid);
1581 }
1582 if (n_invalid) {
1583 memset(HPTE(spapr->htab, index + n_valid), 0,
1584 HASH_PTE_SIZE_64 * n_invalid);
1585 }
1586 } else {
1587 int rc;
1588
1589 assert(fd >= 0);
1590
1591 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1592 if (rc < 0) {
1593 return rc;
1594 }
1595 }
1596 }
1597
1598 if (!spapr->htab) {
1599 assert(fd >= 0);
1600 close(fd);
1601 }
1602
1603 return 0;
1604 }
1605
1606 static SaveVMHandlers savevm_htab_handlers = {
1607 .save_live_setup = htab_save_setup,
1608 .save_live_iterate = htab_save_iterate,
1609 .save_live_complete_precopy = htab_save_complete,
1610 .load_state = htab_load,
1611 };
1612
1613 static void spapr_boot_set(void *opaque, const char *boot_device,
1614 Error **errp)
1615 {
1616 MachineState *machine = MACHINE(qdev_get_machine());
1617 machine->boot_order = g_strdup(boot_device);
1618 }
1619
1620 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
1621 {
1622 CPUPPCState *env = &cpu->env;
1623
1624 /* Set time-base frequency to 512 MHz */
1625 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1626
1627 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1628 * MSR[IP] should never be set.
1629 */
1630 env->msr_mask &= ~(1 << 6);
1631
1632 /* Tell KVM that we're in PAPR mode */
1633 if (kvm_enabled()) {
1634 kvmppc_set_papr(cpu);
1635 }
1636
1637 if (cpu->max_compat) {
1638 if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
1639 exit(1);
1640 }
1641 }
1642
1643 xics_cpu_setup(spapr->icp, cpu);
1644
1645 qemu_register_reset(spapr_cpu_reset, cpu);
1646 }
1647
1648 /*
1649 * Reset routine for LMB DR devices.
1650 *
1651 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1652 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1653 * when it walks all its children devices. LMB devices reset occurs
1654 * as part of spapr_ppc_reset().
1655 */
1656 static void spapr_drc_reset(void *opaque)
1657 {
1658 sPAPRDRConnector *drc = opaque;
1659 DeviceState *d = DEVICE(drc);
1660
1661 if (d) {
1662 device_reset(d);
1663 }
1664 }
1665
1666 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1667 {
1668 MachineState *machine = MACHINE(spapr);
1669 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1670 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1671 int i;
1672
1673 for (i = 0; i < nr_lmbs; i++) {
1674 sPAPRDRConnector *drc;
1675 uint64_t addr;
1676
1677 addr = i * lmb_size + spapr->hotplug_memory.base;
1678 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1679 addr/lmb_size);
1680 qemu_register_reset(spapr_drc_reset, drc);
1681 }
1682 }
1683
1684 /*
1685 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1686 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1687 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1688 */
1689 static void spapr_validate_node_memory(MachineState *machine)
1690 {
1691 int i;
1692
1693 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE ||
1694 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1695 error_report("Can't support memory configuration where RAM size "
1696 "0x" RAM_ADDR_FMT " or maxmem size "
1697 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB",
1698 machine->ram_size, machine->maxram_size,
1699 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1700 exit(EXIT_FAILURE);
1701 }
1702
1703 for (i = 0; i < nb_numa_nodes; i++) {
1704 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1705 error_report("Can't support memory configuration where memory size"
1706 " %" PRIx64 " of node %d isn't aligned to %llu MB",
1707 numa_info[i].node_mem, i,
1708 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1709 exit(EXIT_FAILURE);
1710 }
1711 }
1712 }
1713
1714 /* pSeries LPAR / sPAPR hardware init */
1715 static void ppc_spapr_init(MachineState *machine)
1716 {
1717 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1718 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1719 const char *kernel_filename = machine->kernel_filename;
1720 const char *kernel_cmdline = machine->kernel_cmdline;
1721 const char *initrd_filename = machine->initrd_filename;
1722 PowerPCCPU *cpu;
1723 PCIHostState *phb;
1724 int i;
1725 MemoryRegion *sysmem = get_system_memory();
1726 MemoryRegion *ram = g_new(MemoryRegion, 1);
1727 MemoryRegion *rma_region;
1728 void *rma = NULL;
1729 hwaddr rma_alloc_size;
1730 hwaddr node0_size = spapr_node0_size();
1731 uint32_t initrd_base = 0;
1732 long kernel_size = 0, initrd_size = 0;
1733 long load_limit, fw_size;
1734 bool kernel_le = false;
1735 char *filename;
1736
1737 msi_supported = true;
1738
1739 QLIST_INIT(&spapr->phbs);
1740
1741 cpu_ppc_hypercall = emulate_spapr_hypercall;
1742
1743 /* Allocate RMA if necessary */
1744 rma_alloc_size = kvmppc_alloc_rma(&rma);
1745
1746 if (rma_alloc_size == -1) {
1747 error_report("Unable to create RMA");
1748 exit(1);
1749 }
1750
1751 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1752 spapr->rma_size = rma_alloc_size;
1753 } else {
1754 spapr->rma_size = node0_size;
1755
1756 /* With KVM, we don't actually know whether KVM supports an
1757 * unbounded RMA (PR KVM) or is limited by the hash table size
1758 * (HV KVM using VRMA), so we always assume the latter
1759 *
1760 * In that case, we also limit the initial allocations for RTAS
1761 * etc... to 256M since we have no way to know what the VRMA size
1762 * is going to be as it depends on the size of the hash table
1763 * isn't determined yet.
1764 */
1765 if (kvm_enabled()) {
1766 spapr->vrma_adjust = 1;
1767 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1768 }
1769 }
1770
1771 if (spapr->rma_size > node0_size) {
1772 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
1773 spapr->rma_size);
1774 exit(1);
1775 }
1776
1777 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1778 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1779
1780 /* We aim for a hash table of size 1/128 the size of RAM. The
1781 * normal rule of thumb is 1/64 the size of RAM, but that's much
1782 * more than needed for the Linux guests we support. */
1783 spapr->htab_shift = 18; /* Minimum architected size */
1784 while (spapr->htab_shift <= 46) {
1785 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) {
1786 break;
1787 }
1788 spapr->htab_shift++;
1789 }
1790 spapr_alloc_htab(spapr);
1791
1792 /* Set up Interrupt Controller before we create the VCPUs */
1793 spapr->icp = xics_system_init(machine,
1794 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
1795 smp_threads),
1796 XICS_IRQS);
1797
1798 if (smc->dr_lmb_enabled) {
1799 spapr_validate_node_memory(machine);
1800 }
1801
1802 /* init CPUs */
1803 if (machine->cpu_model == NULL) {
1804 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1805 }
1806 for (i = 0; i < smp_cpus; i++) {
1807 cpu = cpu_ppc_init(machine->cpu_model);
1808 if (cpu == NULL) {
1809 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
1810 exit(1);
1811 }
1812 spapr_cpu_init(spapr, cpu);
1813 }
1814
1815 if (kvm_enabled()) {
1816 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1817 kvmppc_enable_logical_ci_hcalls();
1818 kvmppc_enable_set_mode_hcall();
1819 }
1820
1821 /* allocate RAM */
1822 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1823 machine->ram_size);
1824 memory_region_add_subregion(sysmem, 0, ram);
1825
1826 if (rma_alloc_size && rma) {
1827 rma_region = g_new(MemoryRegion, 1);
1828 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1829 rma_alloc_size, rma);
1830 vmstate_register_ram_global(rma_region);
1831 memory_region_add_subregion(sysmem, 0, rma_region);
1832 }
1833
1834 /* initialize hotplug memory address space */
1835 if (machine->ram_size < machine->maxram_size) {
1836 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1837
1838 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
1839 error_report("Specified number of memory slots %" PRIu64
1840 " exceeds max supported %d",
1841 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
1842 exit(EXIT_FAILURE);
1843 }
1844
1845 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1846 SPAPR_HOTPLUG_MEM_ALIGN);
1847 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1848 "hotplug-memory", hotplug_mem_size);
1849 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1850 &spapr->hotplug_memory.mr);
1851 }
1852
1853 if (smc->dr_lmb_enabled) {
1854 spapr_create_lmb_dr_connectors(spapr);
1855 }
1856
1857 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1858 if (!filename) {
1859 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1860 exit(1);
1861 }
1862 spapr->rtas_size = get_image_size(filename);
1863 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1864 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1865 error_report("Could not load LPAR rtas '%s'", filename);
1866 exit(1);
1867 }
1868 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1869 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1870 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1871 exit(1);
1872 }
1873 g_free(filename);
1874
1875 /* Set up EPOW events infrastructure */
1876 spapr_events_init(spapr);
1877
1878 /* Set up the RTC RTAS interfaces */
1879 spapr_rtc_create(spapr);
1880
1881 /* Set up VIO bus */
1882 spapr->vio_bus = spapr_vio_bus_init();
1883
1884 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1885 if (serial_hds[i]) {
1886 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1887 }
1888 }
1889
1890 /* We always have at least the nvram device on VIO */
1891 spapr_create_nvram(spapr);
1892
1893 /* Set up PCI */
1894 spapr_pci_rtas_init();
1895
1896 phb = spapr_create_phb(spapr, 0);
1897
1898 for (i = 0; i < nb_nics; i++) {
1899 NICInfo *nd = &nd_table[i];
1900
1901 if (!nd->model) {
1902 nd->model = g_strdup("ibmveth");
1903 }
1904
1905 if (strcmp(nd->model, "ibmveth") == 0) {
1906 spapr_vlan_create(spapr->vio_bus, nd);
1907 } else {
1908 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1909 }
1910 }
1911
1912 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1913 spapr_vscsi_create(spapr->vio_bus);
1914 }
1915
1916 /* Graphics */
1917 if (spapr_vga_init(phb->bus)) {
1918 spapr->has_graphics = true;
1919 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1920 }
1921
1922 if (machine->usb) {
1923 if (smc->use_ohci_by_default) {
1924 pci_create_simple(phb->bus, -1, "pci-ohci");
1925 } else {
1926 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1927 }
1928
1929 if (spapr->has_graphics) {
1930 USBBus *usb_bus = usb_bus_find(-1);
1931
1932 usb_create_simple(usb_bus, "usb-kbd");
1933 usb_create_simple(usb_bus, "usb-mouse");
1934 }
1935 }
1936
1937 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1938 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
1939 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
1940 exit(1);
1941 }
1942
1943 if (kernel_filename) {
1944 uint64_t lowaddr = 0;
1945
1946 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1947 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
1948 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1949 kernel_size = load_elf(kernel_filename,
1950 translate_kernel_address, NULL,
1951 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0);
1952 kernel_le = kernel_size > 0;
1953 }
1954 if (kernel_size < 0) {
1955 fprintf(stderr, "qemu: error loading %s: %s\n",
1956 kernel_filename, load_elf_strerror(kernel_size));
1957 exit(1);
1958 }
1959
1960 /* load initrd */
1961 if (initrd_filename) {
1962 /* Try to locate the initrd in the gap between the kernel
1963 * and the firmware. Add a bit of space just in case
1964 */
1965 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1966 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1967 load_limit - initrd_base);
1968 if (initrd_size < 0) {
1969 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1970 initrd_filename);
1971 exit(1);
1972 }
1973 } else {
1974 initrd_base = 0;
1975 initrd_size = 0;
1976 }
1977 }
1978
1979 if (bios_name == NULL) {
1980 bios_name = FW_FILE_NAME;
1981 }
1982 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1983 if (!filename) {
1984 error_report("Could not find LPAR firmware '%s'", bios_name);
1985 exit(1);
1986 }
1987 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1988 if (fw_size <= 0) {
1989 error_report("Could not load LPAR firmware '%s'", filename);
1990 exit(1);
1991 }
1992 g_free(filename);
1993
1994 /* FIXME: Should register things through the MachineState's qdev
1995 * interface, this is a legacy from the sPAPREnvironment structure
1996 * which predated MachineState but had a similar function */
1997 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1998 register_savevm_live(NULL, "spapr/htab", -1, 1,
1999 &savevm_htab_handlers, spapr);
2000
2001 /* Prepare the device tree */
2002 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2003 kernel_size, kernel_le,
2004 kernel_cmdline,
2005 spapr->check_exception_irq);
2006 assert(spapr->fdt_skel != NULL);
2007
2008 /* used by RTAS */
2009 QTAILQ_INIT(&spapr->ccs_list);
2010 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2011
2012 qemu_register_boot_set(spapr_boot_set, spapr);
2013 }
2014
2015 static int spapr_kvm_type(const char *vm_type)
2016 {
2017 if (!vm_type) {
2018 return 0;
2019 }
2020
2021 if (!strcmp(vm_type, "HV")) {
2022 return 1;
2023 }
2024
2025 if (!strcmp(vm_type, "PR")) {
2026 return 2;
2027 }
2028
2029 error_report("Unknown kvm-type specified '%s'", vm_type);
2030 exit(1);
2031 }
2032
2033 /*
2034 * Implementation of an interface to adjust firmware path
2035 * for the bootindex property handling.
2036 */
2037 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2038 DeviceState *dev)
2039 {
2040 #define CAST(type, obj, name) \
2041 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2042 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2043 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2044
2045 if (d) {
2046 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2047 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2048 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2049
2050 if (spapr) {
2051 /*
2052 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2053 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2054 * in the top 16 bits of the 64-bit LUN
2055 */
2056 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2057 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2058 (uint64_t)id << 48);
2059 } else if (virtio) {
2060 /*
2061 * We use SRP luns of the form 01000000 | (target << 8) | lun
2062 * in the top 32 bits of the 64-bit LUN
2063 * Note: the quote above is from SLOF and it is wrong,
2064 * the actual binding is:
2065 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2066 */
2067 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2068 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2069 (uint64_t)id << 32);
2070 } else if (usb) {
2071 /*
2072 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2073 * in the top 32 bits of the 64-bit LUN
2074 */
2075 unsigned usb_port = atoi(usb->port->path);
2076 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2077 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2078 (uint64_t)id << 32);
2079 }
2080 }
2081
2082 if (phb) {
2083 /* Replace "pci" with "pci@800000020000000" */
2084 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2085 }
2086
2087 return NULL;
2088 }
2089
2090 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2091 {
2092 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2093
2094 return g_strdup(spapr->kvm_type);
2095 }
2096
2097 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2098 {
2099 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2100
2101 g_free(spapr->kvm_type);
2102 spapr->kvm_type = g_strdup(value);
2103 }
2104
2105 static void spapr_machine_initfn(Object *obj)
2106 {
2107 object_property_add_str(obj, "kvm-type",
2108 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2109 object_property_set_description(obj, "kvm-type",
2110 "Specifies the KVM virtualization mode (HV, PR)",
2111 NULL);
2112 }
2113
2114 static void spapr_machine_finalizefn(Object *obj)
2115 {
2116 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2117
2118 g_free(spapr->kvm_type);
2119 }
2120
2121 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2122 {
2123 CPUState *cs = arg;
2124
2125 cpu_synchronize_state(cs);
2126 ppc_cpu_do_system_reset(cs);
2127 }
2128
2129 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2130 {
2131 CPUState *cs;
2132
2133 CPU_FOREACH(cs) {
2134 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2135 }
2136 }
2137
2138 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2139 uint32_t node, Error **errp)
2140 {
2141 sPAPRDRConnector *drc;
2142 sPAPRDRConnectorClass *drck;
2143 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2144 int i, fdt_offset, fdt_size;
2145 void *fdt;
2146
2147 /*
2148 * Check for DRC connectors and send hotplug notification to the
2149 * guest only in case of hotplugged memory. This allows cold plugged
2150 * memory to be specified at boot time.
2151 */
2152 if (!dev->hotplugged) {
2153 return;
2154 }
2155
2156 for (i = 0; i < nr_lmbs; i++) {
2157 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2158 addr/SPAPR_MEMORY_BLOCK_SIZE);
2159 g_assert(drc);
2160
2161 fdt = create_device_tree(&fdt_size);
2162 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2163 SPAPR_MEMORY_BLOCK_SIZE);
2164
2165 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2166 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2167 addr += SPAPR_MEMORY_BLOCK_SIZE;
2168 }
2169 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2170 }
2171
2172 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2173 uint32_t node, Error **errp)
2174 {
2175 Error *local_err = NULL;
2176 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2177 PCDIMMDevice *dimm = PC_DIMM(dev);
2178 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2179 MemoryRegion *mr = ddc->get_memory_region(dimm);
2180 uint64_t align = memory_region_get_alignment(mr);
2181 uint64_t size = memory_region_size(mr);
2182 uint64_t addr;
2183
2184 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2185 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2186 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2187 goto out;
2188 }
2189
2190 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2191 if (local_err) {
2192 goto out;
2193 }
2194
2195 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2196 if (local_err) {
2197 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2198 goto out;
2199 }
2200
2201 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2202
2203 out:
2204 error_propagate(errp, local_err);
2205 }
2206
2207 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2208 DeviceState *dev, Error **errp)
2209 {
2210 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2211
2212 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2213 int node;
2214
2215 if (!smc->dr_lmb_enabled) {
2216 error_setg(errp, "Memory hotplug not supported for this machine");
2217 return;
2218 }
2219 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2220 if (*errp) {
2221 return;
2222 }
2223
2224 /*
2225 * Currently PowerPC kernel doesn't allow hot-adding memory to
2226 * memory-less node, but instead will silently add the memory
2227 * to the first node that has some memory. This causes two
2228 * unexpected behaviours for the user.
2229 *
2230 * - Memory gets hotplugged to a different node than what the user
2231 * specified.
2232 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2233 * to memory-less node, a reboot will set things accordingly
2234 * and the previously hotplugged memory now ends in the right node.
2235 * This appears as if some memory moved from one node to another.
2236 *
2237 * So until kernel starts supporting memory hotplug to memory-less
2238 * nodes, just prevent such attempts upfront in QEMU.
2239 */
2240 if (nb_numa_nodes && !numa_info[node].node_mem) {
2241 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2242 node);
2243 return;
2244 }
2245
2246 spapr_memory_plug(hotplug_dev, dev, node, errp);
2247 }
2248 }
2249
2250 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2251 DeviceState *dev, Error **errp)
2252 {
2253 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2254 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2255 }
2256 }
2257
2258 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2259 DeviceState *dev)
2260 {
2261 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2262 return HOTPLUG_HANDLER(machine);
2263 }
2264 return NULL;
2265 }
2266
2267 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2268 {
2269 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2270 * socket means much for the paravirtualized PAPR platform) */
2271 return cpu_index / smp_threads / smp_cores;
2272 }
2273
2274 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2275 {
2276 MachineClass *mc = MACHINE_CLASS(oc);
2277 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2278 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2279 NMIClass *nc = NMI_CLASS(oc);
2280 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2281
2282 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2283
2284 /*
2285 * We set up the default / latest behaviour here. The class_init
2286 * functions for the specific versioned machine types can override
2287 * these details for backwards compatibility
2288 */
2289 mc->init = ppc_spapr_init;
2290 mc->reset = ppc_spapr_reset;
2291 mc->block_default_type = IF_SCSI;
2292 mc->max_cpus = MAX_CPUMASK_BITS;
2293 mc->no_parallel = 1;
2294 mc->default_boot_order = "";
2295 mc->default_ram_size = 512 * M_BYTE;
2296 mc->kvm_type = spapr_kvm_type;
2297 mc->has_dynamic_sysbus = true;
2298 mc->pci_allow_0_address = true;
2299 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2300 hc->plug = spapr_machine_device_plug;
2301 hc->unplug = spapr_machine_device_unplug;
2302 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2303
2304 smc->dr_lmb_enabled = true;
2305 fwc->get_dev_path = spapr_get_fw_dev_path;
2306 nc->nmi_monitor_handler = spapr_nmi;
2307 }
2308
2309 static const TypeInfo spapr_machine_info = {
2310 .name = TYPE_SPAPR_MACHINE,
2311 .parent = TYPE_MACHINE,
2312 .abstract = true,
2313 .instance_size = sizeof(sPAPRMachineState),
2314 .instance_init = spapr_machine_initfn,
2315 .instance_finalize = spapr_machine_finalizefn,
2316 .class_size = sizeof(sPAPRMachineClass),
2317 .class_init = spapr_machine_class_init,
2318 .interfaces = (InterfaceInfo[]) {
2319 { TYPE_FW_PATH_PROVIDER },
2320 { TYPE_NMI },
2321 { TYPE_HOTPLUG_HANDLER },
2322 { }
2323 },
2324 };
2325
2326 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2327 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2328 void *data) \
2329 { \
2330 MachineClass *mc = MACHINE_CLASS(oc); \
2331 spapr_machine_##suffix##_class_options(mc); \
2332 if (latest) { \
2333 mc->alias = "pseries"; \
2334 mc->is_default = 1; \
2335 } \
2336 } \
2337 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2338 { \
2339 MachineState *machine = MACHINE(obj); \
2340 spapr_machine_##suffix##_instance_options(machine); \
2341 } \
2342 static const TypeInfo spapr_machine_##suffix##_info = { \
2343 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2344 .parent = TYPE_SPAPR_MACHINE, \
2345 .class_init = spapr_machine_##suffix##_class_init, \
2346 .instance_init = spapr_machine_##suffix##_instance_init, \
2347 }; \
2348 static void spapr_machine_register_##suffix(void) \
2349 { \
2350 type_register(&spapr_machine_##suffix##_info); \
2351 } \
2352 machine_init(spapr_machine_register_##suffix)
2353
2354 /*
2355 * pseries-2.6
2356 */
2357 static void spapr_machine_2_6_instance_options(MachineState *machine)
2358 {
2359 }
2360
2361 static void spapr_machine_2_6_class_options(MachineClass *mc)
2362 {
2363 /* Defaults for the latest behaviour inherited from the base class */
2364 }
2365
2366 DEFINE_SPAPR_MACHINE(2_6, "2.6", true);
2367
2368 /*
2369 * pseries-2.5
2370 */
2371 #define SPAPR_COMPAT_2_5 \
2372 HW_COMPAT_2_5
2373
2374 static void spapr_machine_2_5_instance_options(MachineState *machine)
2375 {
2376 }
2377
2378 static void spapr_machine_2_5_class_options(MachineClass *mc)
2379 {
2380 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2381
2382 spapr_machine_2_6_class_options(mc);
2383 smc->use_ohci_by_default = true;
2384 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2385 }
2386
2387 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2388
2389 /*
2390 * pseries-2.4
2391 */
2392 #define SPAPR_COMPAT_2_4 \
2393 HW_COMPAT_2_4
2394
2395 static void spapr_machine_2_4_instance_options(MachineState *machine)
2396 {
2397 spapr_machine_2_5_instance_options(machine);
2398 }
2399
2400 static void spapr_machine_2_4_class_options(MachineClass *mc)
2401 {
2402 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2403
2404 spapr_machine_2_5_class_options(mc);
2405 smc->dr_lmb_enabled = false;
2406 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2407 }
2408
2409 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2410
2411 /*
2412 * pseries-2.3
2413 */
2414 #define SPAPR_COMPAT_2_3 \
2415 SPAPR_COMPAT_2_4 \
2416 HW_COMPAT_2_3 \
2417 {\
2418 .driver = "spapr-pci-host-bridge",\
2419 .property = "dynamic-reconfiguration",\
2420 .value = "off",\
2421 },
2422
2423 static void spapr_machine_2_3_instance_options(MachineState *machine)
2424 {
2425 spapr_machine_2_4_instance_options(machine);
2426 savevm_skip_section_footers();
2427 global_state_set_optional();
2428 }
2429
2430 static void spapr_machine_2_3_class_options(MachineClass *mc)
2431 {
2432 spapr_machine_2_4_class_options(mc);
2433 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2434 }
2435 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2436
2437 /*
2438 * pseries-2.2
2439 */
2440
2441 #define SPAPR_COMPAT_2_2 \
2442 SPAPR_COMPAT_2_3 \
2443 HW_COMPAT_2_2 \
2444 {\
2445 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2446 .property = "mem_win_size",\
2447 .value = "0x20000000",\
2448 },
2449
2450 static void spapr_machine_2_2_instance_options(MachineState *machine)
2451 {
2452 spapr_machine_2_3_instance_options(machine);
2453 }
2454
2455 static void spapr_machine_2_2_class_options(MachineClass *mc)
2456 {
2457 spapr_machine_2_3_class_options(mc);
2458 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2459 }
2460 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2461
2462 /*
2463 * pseries-2.1
2464 */
2465 #define SPAPR_COMPAT_2_1 \
2466 SPAPR_COMPAT_2_2 \
2467 HW_COMPAT_2_1
2468
2469 static void spapr_machine_2_1_instance_options(MachineState *machine)
2470 {
2471 spapr_machine_2_2_instance_options(machine);
2472 }
2473
2474 static void spapr_machine_2_1_class_options(MachineClass *mc)
2475 {
2476 spapr_machine_2_2_class_options(mc);
2477 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2478 }
2479 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2480
2481 static void spapr_machine_register_types(void)
2482 {
2483 type_register_static(&spapr_machine_info);
2484 }
2485
2486 type_init(spapr_machine_register_types)
AR7 emulation for QEMU