hw/pci-host/apb.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /* XXX This file and most of its contents are somewhat misnamed.  The
  27    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  28    the secondary PCI bridge.  */
  29
  30 #include "hw/sysbus.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_host.h"
  33 #include "hw/pci/pci_bridge.h"
  34 #include "hw/pci/pci_bus.h"
  35 #include "hw/pci-host/apb.h"
  36 #include "sysemu/sysemu.h"
  37 #include "exec/address-spaces.h"
  38
  39 /* debug APB */
  40 //#define DEBUG_APB
  41
  42 #ifdef DEBUG_APB
  43 #define APB_DPRINTF(fmt, ...) \
  44 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  45 #else
  46 #define APB_DPRINTF(fmt, ...)
  47 #endif
  48
  49 /* debug IOMMU */
  50 //#define DEBUG_IOMMU
  51
  52 #ifdef DEBUG_IOMMU
  53 #define IOMMU_DPRINTF(fmt, ...) \
  54 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define IOMMU_DPRINTF(fmt, ...)
  57 #endif
  58
  59 /*
  60  * Chipset docs:
  61  * PBM: "UltraSPARC IIi User's Manual",
  62  * http://www.sun.com/processors/manuals/805-0087.pdf
  63  *
  64  * APB: "Advanced PCI Bridge (APB) User's Manual",
  65  * http://www.sun.com/processors/manuals/805-1251.pdf
  66  */
  67
  68 #define PBM_PCI_IMR_MASK    0x7fffffff
  69 #define PBM_PCI_IMR_ENABLED 0x80000000
  70
  71 #define POR          (1U << 31)
  72 #define SOFT_POR     (1U << 30)
  73 #define SOFT_XIR     (1U << 29)
  74 #define BTN_POR      (1U << 28)
  75 #define BTN_XIR      (1U << 27)
  76 #define RESET_MASK   0xf8000000
  77 #define RESET_WCMASK 0x98000000
  78 #define RESET_WMASK  0x60000000
  79
  80 #define MAX_IVEC 0x40
  81 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
  82
  83 #define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
  84 #define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
  85 #define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
  86 #define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))
  87
  88 #define IOMMU_NREGS             3
  89
  90 #define IOMMU_CTRL              0x0
  91 #define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
  92 #define IOMMU_CTRL_MMU_EN       (1ULL)
  93
  94 #define IOMMU_CTRL_TSB_SHIFT    16
  95
  96 #define IOMMU_BASE              0x8
  97 #define IOMMU_FLUSH             0x10
  98
  99 #define IOMMU_TTE_DATA_V        (1ULL << 63)
 100 #define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
 101 #define IOMMU_TTE_DATA_W        (1ULL << 1)
 102
 103 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
 104 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
 105
 106 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
 107 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
 108 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
 109 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
 110 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
 111 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
 112 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
 113 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
 114
 115 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
 116 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
 117 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
 118 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
 119 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
 120 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
 121
 122 typedef struct IOMMUState {
 123     AddressSpace iommu_as;
 124     MemoryRegion iommu;
 125
 126     uint64_t regs[IOMMU_NREGS];
 127 } IOMMUState;
 128
 129 #define TYPE_APB "pbm"
 130
 131 #define APB_DEVICE(obj) \
 132     OBJECT_CHECK(APBState, (obj), TYPE_APB)
 133
 134 typedef struct APBState {
 135     PCIHostState parent_obj;
 136
 137     MemoryRegion apb_config;
 138     MemoryRegion pci_config;
 139     MemoryRegion pci_mmio;
 140     MemoryRegion pci_ioport;
 141     uint64_t pci_irq_in;
 142     IOMMUState iommu;
 143     uint32_t pci_control[16];
 144     uint32_t pci_irq_map[8];
 145     uint32_t pci_err_irq_map[4];
 146     uint32_t obio_irq_map[32];
 147     qemu_irq *pbm_irqs;
 148     qemu_irq *ivec_irqs;
 149     unsigned int irq_request;
 150     uint32_t reset_control;
 151     unsigned int nr_resets;
 152 } APBState;
 153
 154 static inline void pbm_set_request(APBState *s, unsigned int irq_num)
 155 {
 156     APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
 157
 158     s->irq_request = irq_num;
 159     qemu_set_irq(s->ivec_irqs[irq_num], 1);
 160 }
 161
 162 static inline void pbm_check_irqs(APBState *s)
 163 {
 164
 165     unsigned int i;
 166
 167     /* Previous request is not acknowledged, resubmit */
 168     if (s->irq_request != NO_IRQ_REQUEST) {
 169         pbm_set_request(s, s->irq_request);
 170         return;
 171     }
 172     /* no request pending */
 173     if (s->pci_irq_in == 0ULL) {
 174         return;
 175     }
 176     for (i = 0; i < 32; i++) {
 177         if (s->pci_irq_in & (1ULL << i)) {
 178             if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
 179                 pbm_set_request(s, i);
 180                 return;
 181             }
 182         }
 183     }
 184     for (i = 32; i < 64; i++) {
 185         if (s->pci_irq_in & (1ULL << i)) {
 186             if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
 187                 pbm_set_request(s, i);
 188                 break;
 189             }
 190         }
 191     }
 192 }
 193
 194 static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
 195 {
 196     APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
 197     qemu_set_irq(s->ivec_irqs[irq_num], 0);
 198     s->irq_request = NO_IRQ_REQUEST;
 199 }
 200
 201 static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 202 {
 203     IOMMUState *is = opaque;
 204
 205     return &is->iommu_as;
 206 }
 207
 208 /* Called from RCU critical section */
 209 static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 210                                          bool is_write)
 211 {
 212     IOMMUState *is = container_of(iommu, IOMMUState, iommu);
 213     hwaddr baseaddr, offset;
 214     uint64_t tte;
 215     uint32_t tsbsize;
 216     IOMMUTLBEntry ret = {
 217         .target_as = &address_space_memory,
 218         .iova = 0,
 219         .translated_addr = 0,
 220         .addr_mask = ~(hwaddr)0,
 221         .perm = IOMMU_NONE,
 222     };
 223
 224     if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
 225         /* IOMMU disabled, passthrough using standard 8K page */
 226         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 227         ret.translated_addr = addr;
 228         ret.addr_mask = IOMMU_PAGE_MASK_8K;
 229         ret.perm = IOMMU_RW;
 230
 231         return ret;
 232     }
 233
 234     baseaddr = is->regs[IOMMU_BASE >> 3];
 235     tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
 236
 237     if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
 238         /* 64K */
 239         switch (tsbsize) {
 240         case 0:
 241             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
 242             break;
 243         case 1:
 244             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
 245             break;
 246         case 2:
 247             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
 248             break;
 249         case 3:
 250             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
 251             break;
 252         case 4:
 253             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
 254             break;
 255         case 5:
 256             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
 257             break;
 258         default:
 259             /* Not implemented, error */
 260             return ret;
 261         }
 262     } else {
 263         /* 8K */
 264         switch (tsbsize) {
 265         case 0:
 266             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
 267             break;
 268         case 1:
 269             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
 270             break;
 271         case 2:
 272             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
 273             break;
 274         case 3:
 275             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
 276             break;
 277         case 4:
 278             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
 279             break;
 280         case 5:
 281             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
 282             break;
 283         case 6:
 284             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
 285             break;
 286         case 7:
 287             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
 288             break;
 289         }
 290     }
 291
 292     tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
 293                                MEMTXATTRS_UNSPECIFIED, NULL);
 294
 295     if (!(tte & IOMMU_TTE_DATA_V)) {
 296         /* Invalid mapping */
 297         return ret;
 298     }
 299
 300     if (tte & IOMMU_TTE_DATA_W) {
 301         /* Writeable */
 302         ret.perm = IOMMU_RW;
 303     } else {
 304         ret.perm = IOMMU_RO;
 305     }
 306
 307     /* Extract phys */
 308     if (tte & IOMMU_TTE_DATA_SIZE) {
 309         /* 64K */
 310         ret.iova = addr & IOMMU_PAGE_MASK_64K;
 311         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
 312         ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
 313     } else {
 314         /* 8K */
 315         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 316         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
 317         ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
 318     }
 319
 320     return ret;
 321 }
 322
 323 static MemoryRegionIOMMUOps pbm_iommu_ops = {
 324     .translate = pbm_translate_iommu,
 325 };
 326
 327 static void iommu_config_write(void *opaque, hwaddr addr,
 328                                uint64_t val, unsigned size)
 329 {
 330     IOMMUState *is = opaque;
 331
 332     IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
 333                   " size: %d\n", addr, val, size);
 334
 335     switch (addr) {
 336     case IOMMU_CTRL:
 337         if (size == 4) {
 338             is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
 339             is->regs[IOMMU_CTRL >> 3] |= val << 32;
 340         } else {
 341             is->regs[IOMMU_CTRL >> 3] = val;
 342         }
 343         break;
 344     case IOMMU_CTRL + 0x4:
 345         is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
 346         is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
 347         break;
 348     case IOMMU_BASE:
 349         if (size == 4) {
 350             is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
 351             is->regs[IOMMU_BASE >> 3] |= val << 32;
 352         } else {
 353             is->regs[IOMMU_BASE >> 3] = val;
 354         }
 355         break;
 356     case IOMMU_BASE + 0x4:
 357         is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
 358         is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
 359         break;
 360     case IOMMU_FLUSH:
 361     case IOMMU_FLUSH + 0x4:
 362         break;
 363     default:
 364         qemu_log_mask(LOG_UNIMP,
 365                   "apb iommu: Unimplemented register write "
 366                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 367                   addr, size, val);
 368         break;
 369     }
 370 }
 371
 372 static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
 373 {
 374     IOMMUState *is = opaque;
 375     uint64_t val;
 376
 377     switch (addr) {
 378     case IOMMU_CTRL:
 379         if (size == 4) {
 380             val = is->regs[IOMMU_CTRL >> 3] >> 32;
 381         } else {
 382             val = is->regs[IOMMU_CTRL >> 3];
 383         }
 384         break;
 385     case IOMMU_CTRL + 0x4:
 386         val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
 387         break;
 388     case IOMMU_BASE:
 389         if (size == 4) {
 390             val = is->regs[IOMMU_BASE >> 3] >> 32;
 391         } else {
 392             val = is->regs[IOMMU_BASE >> 3];
 393         }
 394         break;
 395     case IOMMU_BASE + 0x4:
 396         val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
 397         break;
 398     case IOMMU_FLUSH:
 399     case IOMMU_FLUSH + 0x4:
 400         val = 0;
 401         break;
 402     default:
 403         qemu_log_mask(LOG_UNIMP,
 404                       "apb iommu: Unimplemented register read "
 405                       "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 406                       addr, size);
 407         val = 0;
 408         break;
 409     }
 410
 411     IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
 412                   " size: %d\n", addr, val, size);
 413
 414     return val;
 415 }
 416
 417 static void apb_config_writel (void *opaque, hwaddr addr,
 418                                uint64_t val, unsigned size)
 419 {
 420     APBState *s = opaque;
 421     IOMMUState *is = &s->iommu;
 422
 423     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 424
 425     switch (addr & 0xffff) {
 426     case 0x30 ... 0x4f: /* DMA error registers */
 427         /* XXX: not implemented yet */
 428         break;
 429     case 0x200 ... 0x217: /* IOMMU */
 430         iommu_config_write(is, (addr & 0x1f), val, size);
 431         break;
 432     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 433         if (addr & 4) {
 434             unsigned int ino = (addr & 0x3f) >> 3;
 435             s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 436             s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 437             if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
 438                 pbm_clear_request(s, ino);
 439             }
 440             pbm_check_irqs(s);
 441         }
 442         break;
 443     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 444         if (addr & 4) {
 445             unsigned int ino = ((addr & 0xff) >> 3);
 446             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
 447             s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 448             if ((s->irq_request == (ino | 0x20))
 449                  && !(val & ~PBM_PCI_IMR_MASK)) {
 450                 pbm_clear_request(s, ino | 0x20);
 451             }
 452             pbm_check_irqs(s);
 453         }
 454         break;
 455     case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 456         if (addr & 4) {
 457             unsigned int ino = (addr & 0xff) >> 5;
 458             if ((s->irq_request / 4)  == ino) {
 459                 pbm_clear_request(s, s->irq_request);
 460                 pbm_check_irqs(s);
 461             }
 462         }
 463         break;
 464     case 0x1800 ... 0x1860: /* OBIO interrupt clear */
 465         if (addr & 4) {
 466             unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 467             if (s->irq_request == ino) {
 468                 pbm_clear_request(s, ino);
 469                 pbm_check_irqs(s);
 470             }
 471         }
 472         break;
 473     case 0x2000 ... 0x202f: /* PCI control */
 474         s->pci_control[(addr & 0x3f) >> 2] = val;
 475         break;
 476     case 0xf020 ... 0xf027: /* Reset control */
 477         if (addr & 4) {
 478             val &= RESET_MASK;
 479             s->reset_control &= ~(val & RESET_WCMASK);
 480             s->reset_control |= val & RESET_WMASK;
 481             if (val & SOFT_POR) {
 482                 s->nr_resets = 0;
 483                 qemu_system_reset_request();
 484             } else if (val & SOFT_XIR) {
 485                 qemu_system_reset_request();
 486             }
 487         }
 488         break;
 489     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 490     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 491     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 492     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 493         /* we don't care */
 494     default:
 495         break;
 496     }
 497 }
 498
 499 static uint64_t apb_config_readl (void *opaque,
 500                                   hwaddr addr, unsigned size)
 501 {
 502     APBState *s = opaque;
 503     IOMMUState *is = &s->iommu;
 504     uint32_t val;
 505
 506     switch (addr & 0xffff) {
 507     case 0x30 ... 0x4f: /* DMA error registers */
 508         val = 0;
 509         /* XXX: not implemented yet */
 510         break;
 511     case 0x200 ... 0x217: /* IOMMU */
 512         val = iommu_config_read(is, (addr & 0x1f), size);
 513         break;
 514     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 515         if (addr & 4) {
 516             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 517         } else {
 518             val = 0;
 519         }
 520         break;
 521     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 522         if (addr & 4) {
 523             val = s->obio_irq_map[(addr & 0xff) >> 3];
 524         } else {
 525             val = 0;
 526         }
 527         break;
 528     case 0x1080 ... 0x108f: /* PCI bus error */
 529         if (addr & 4) {
 530             val = s->pci_err_irq_map[(addr & 0xf) >> 3];
 531         } else {
 532             val = 0;
 533         }
 534         break;
 535     case 0x2000 ... 0x202f: /* PCI control */
 536         val = s->pci_control[(addr & 0x3f) >> 2];
 537         break;
 538     case 0xf020 ... 0xf027: /* Reset control */
 539         if (addr & 4) {
 540             val = s->reset_control;
 541         } else {
 542             val = 0;
 543         }
 544         break;
 545     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 546     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 547     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 548     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 549         /* we don't care */
 550     default:
 551         val = 0;
 552         break;
 553     }
 554     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
 555
 556     return val;
 557 }
 558
 559 static const MemoryRegionOps apb_config_ops = {
 560     .read = apb_config_readl,
 561     .write = apb_config_writel,
 562     .endianness = DEVICE_NATIVE_ENDIAN,
 563 };
 564
 565 static void apb_pci_config_write(void *opaque, hwaddr addr,
 566                                  uint64_t val, unsigned size)
 567 {
 568     APBState *s = opaque;
 569     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 570
 571     val = qemu_bswap_len(val, size);
 572     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 573     pci_data_write(phb->bus, addr, val, size);
 574 }
 575
 576 static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
 577                                     unsigned size)
 578 {
 579     uint32_t ret;
 580     APBState *s = opaque;
 581     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 582
 583     ret = pci_data_read(phb->bus, addr, size);
 584     ret = qemu_bswap_len(ret, size);
 585     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
 586     return ret;
 587 }
 588
 589 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 590 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 591 {
 592     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 593 }
 594
 595 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 596 {
 597     int bus_offset;
 598     if (pci_dev->devfn & 1)
 599         bus_offset = 16;
 600     else
 601         bus_offset = 0;
 602     return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 603 }
 604
 605 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 606 {
 607     APBState *s = opaque;
 608
 609     APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
 610     /* PCI IRQ map onto the first 32 INO.  */
 611     if (irq_num < 32) {
 612         if (level) {
 613             s->pci_irq_in |= 1ULL << irq_num;
 614             if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 615                 pbm_set_request(s, irq_num);
 616             }
 617         } else {
 618             s->pci_irq_in &= ~(1ULL << irq_num);
 619         }
 620     } else {
 621         /* OBIO IRQ map onto the next 32 INO.  */
 622         if (level) {
 623             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 624             s->pci_irq_in |= 1ULL << irq_num;
 625             if ((s->irq_request == NO_IRQ_REQUEST)
 626                 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
 627                 pbm_set_request(s, irq_num);
 628             }
 629         } else {
 630             s->pci_irq_in &= ~(1ULL << irq_num);
 631         }
 632     }
 633 }
 634
 635 static int apb_pci_bridge_initfn(PCIDevice *dev)
 636 {
 637     int rc;
 638
 639     rc = pci_bridge_initfn(dev, TYPE_PCI_BUS);
 640     if (rc < 0) {
 641         return rc;
 642     }
 643
 644     /*
 645      * command register:
 646      * According to PCI bridge spec, after reset
 647      *   bus master bit is off
 648      *   memory space enable bit is off
 649      * According to manual (805-1251.pdf).
 650      *   the reset value should be zero unless the boot pin is tied high
 651      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 652      */
 653     pci_set_word(dev->config + PCI_COMMAND,
 654                  PCI_COMMAND_MEMORY);
 655     pci_set_word(dev->config + PCI_STATUS,
 656                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 657                  PCI_STATUS_DEVSEL_MEDIUM);
 658     return 0;
 659 }
 660
 661 PCIBus *pci_apb_init(hwaddr special_base,
 662                      hwaddr mem_base,
 663                      qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
 664                      qemu_irq **pbm_irqs)
 665 {
 666     DeviceState *dev;
 667     SysBusDevice *s;
 668     PCIHostState *phb;
 669     APBState *d;
 670     IOMMUState *is;
 671     PCIDevice *pci_dev;
 672     PCIBridge *br;
 673
 674     /* Ultrasparc PBM main bus */
 675     dev = qdev_create(NULL, TYPE_APB);
 676     qdev_init_nofail(dev);
 677     s = SYS_BUS_DEVICE(dev);
 678     /* apb_config */
 679     sysbus_mmio_map(s, 0, special_base);
 680     /* PCI configuration space */
 681     sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
 682     /* pci_ioport */
 683     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
 684     d = APB_DEVICE(dev);
 685
 686     memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
 687     memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
 688
 689     phb = PCI_HOST_BRIDGE(dev);
 690     phb->bus = pci_register_bus(DEVICE(phb), "pci",
 691                                 pci_apb_set_irq, pci_pbm_map_irq, d,
 692                                 &d->pci_mmio,
 693                                 get_system_io(),
 694                                 0, 32, TYPE_PCI_BUS);
 695
 696     *pbm_irqs = d->pbm_irqs;
 697     d->ivec_irqs = ivec_irqs;
 698
 699     pci_create_simple(phb->bus, 0, "pbm-pci");
 700
 701     /* APB IOMMU */
 702     is = &d->iommu;
 703     memset(is, 0, sizeof(IOMMUState));
 704
 705     memory_region_init_iommu(&is->iommu, OBJECT(dev), &pbm_iommu_ops,
 706                              "iommu-apb", UINT64_MAX);
 707     address_space_init(&is->iommu_as, &is->iommu, "pbm-as");
 708     pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
 709
 710     /* APB secondary busses */
 711     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
 712                                    "pbm-bridge");
 713     br = PCI_BRIDGE(pci_dev);
 714     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
 715                        pci_apb_map_irq);
 716     qdev_init_nofail(&pci_dev->qdev);
 717     *bus2 = pci_bridge_get_sec_bus(br);
 718
 719     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
 720                                    "pbm-bridge");
 721     br = PCI_BRIDGE(pci_dev);
 722     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
 723                        pci_apb_map_irq);
 724     qdev_init_nofail(&pci_dev->qdev);
 725     *bus3 = pci_bridge_get_sec_bus(br);
 726
 727     return phb->bus;
 728 }
 729
 730 static void pci_pbm_reset(DeviceState *d)
 731 {
 732     unsigned int i;
 733     APBState *s = APB_DEVICE(d);
 734
 735     for (i = 0; i < 8; i++) {
 736         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 737     }
 738     for (i = 0; i < 32; i++) {
 739         s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
 740     }
 741
 742     s->irq_request = NO_IRQ_REQUEST;
 743     s->pci_irq_in = 0ULL;
 744
 745     if (s->nr_resets++ == 0) {
 746         /* Power on reset */
 747         s->reset_control = POR;
 748     }
 749 }
 750
 751 static const MemoryRegionOps pci_config_ops = {
 752     .read = apb_pci_config_read,
 753     .write = apb_pci_config_write,
 754     .endianness = DEVICE_NATIVE_ENDIAN,
 755 };
 756
 757 static int pci_pbm_init_device(SysBusDevice *dev)
 758 {
 759     APBState *s;
 760     unsigned int i;
 761
 762     s = APB_DEVICE(dev);
 763     for (i = 0; i < 8; i++) {
 764         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 765     }
 766     for (i = 0; i < 2; i++) {
 767         s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
 768     }
 769     for (i = 0; i < 32; i++) {
 770         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
 771     }
 772     s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
 773     s->irq_request = NO_IRQ_REQUEST;
 774     s->pci_irq_in = 0ULL;
 775
 776     /* apb_config */
 777     memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
 778                           "apb-config", 0x10000);
 779     /* at region 0 */
 780     sysbus_init_mmio(dev, &s->apb_config);
 781
 782     memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
 783                           "apb-pci-config", 0x1000000);
 784     /* at region 1 */
 785     sysbus_init_mmio(dev, &s->pci_config);
 786
 787     /* pci_ioport */
 788     memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
 789                              get_system_io(), 0, 0x10000);
 790     /* at region 2 */
 791     sysbus_init_mmio(dev, &s->pci_ioport);
 792
 793     return 0;
 794 }
 795
 796 static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
 797 {
 798     pci_set_word(d->config + PCI_COMMAND,
 799                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 800     pci_set_word(d->config + PCI_STATUS,
 801                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 802                  PCI_STATUS_DEVSEL_MEDIUM);
 803 }
 804
 805 static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
 806 {
 807     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 808     DeviceClass *dc = DEVICE_CLASS(klass);
 809
 810     k->realize = pbm_pci_host_realize;
 811     k->vendor_id = PCI_VENDOR_ID_SUN;
 812     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
 813     k->class_id = PCI_CLASS_BRIDGE_HOST;
 814     /*
 815      * PCI-facing part of the host bridge, not usable without the
 816      * host-facing part, which can't be device_add'ed, yet.
 817      */
 818     dc->cannot_instantiate_with_device_add_yet = true;
 819 }
 820
 821 static const TypeInfo pbm_pci_host_info = {
 822     .name          = "pbm-pci",
 823     .parent        = TYPE_PCI_DEVICE,
 824     .instance_size = sizeof(PCIDevice),
 825     .class_init    = pbm_pci_host_class_init,
 826 };
 827
 828 static void pbm_host_class_init(ObjectClass *klass, void *data)
 829 {
 830     DeviceClass *dc = DEVICE_CLASS(klass);
 831     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 832
 833     k->init = pci_pbm_init_device;
 834     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 835     dc->reset = pci_pbm_reset;
 836 }
 837
 838 static const TypeInfo pbm_host_info = {
 839     .name          = TYPE_APB,
 840     .parent        = TYPE_PCI_HOST_BRIDGE,
 841     .instance_size = sizeof(APBState),
 842     .class_init    = pbm_host_class_init,
 843 };
 844
 845 static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
 846 {
 847     DeviceClass *dc = DEVICE_CLASS(klass);
 848     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 849
 850     k->init = apb_pci_bridge_initfn;
 851     k->exit = pci_bridge_exitfn;
 852     k->vendor_id = PCI_VENDOR_ID_SUN;
 853     k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
 854     k->revision = 0x11;
 855     k->config_write = pci_bridge_write_config;
 856     k->is_bridge = 1;
 857     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 858     dc->reset = pci_bridge_reset;
 859     dc->vmsd = &vmstate_pci_device;
 860 }
 861
 862 static const TypeInfo pbm_pci_bridge_info = {
 863     .name          = "pbm-bridge",
 864     .parent        = TYPE_PCI_BRIDGE,
 865     .class_init    = pbm_pci_bridge_class_init,
 866 };
 867
 868 static void pbm_register_types(void)
 869 {
 870     type_register_static(&pbm_host_info);
 871     type_register_static(&pbm_pci_host_info);
 872     type_register_static(&pbm_pci_bridge_info);
 873 }
 874
 875 type_init(pbm_register_types)