target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27
  28 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     AVRCPU *cpu = AVR_CPU(cs);
  31
  32     cpu->env.pc_w = value / 2; /* internally PC points to words */
  33 }
  34
  35 static bool avr_cpu_has_work(CPUState *cs)
  36 {
  37     AVRCPU *cpu = AVR_CPU(cs);
  38     CPUAVRState *env = &cpu->env;
  39
  40     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  41             && cpu_interrupts_enabled(env);
  42 }
  43
  44 static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  45 {
  46     AVRCPU *cpu = AVR_CPU(cs);
  47     CPUAVRState *env = &cpu->env;
  48
  49     env->pc_w = tb->pc / 2; /* internally PC points to words */
  50 }
  51
  52 static void avr_cpu_reset(DeviceState *ds)
  53 {
  54     CPUState *cs = CPU(ds);
  55     AVRCPU *cpu = AVR_CPU(cs);
  56     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  57     CPUAVRState *env = &cpu->env;
  58
  59     mcc->parent_reset(ds);
  60
  61     env->pc_w = 0;
  62     env->sregI = 1;
  63     env->sregC = 0;
  64     env->sregZ = 0;
  65     env->sregN = 0;
  66     env->sregV = 0;
  67     env->sregS = 0;
  68     env->sregH = 0;
  69     env->sregT = 0;
  70
  71     env->rampD = 0;
  72     env->rampX = 0;
  73     env->rampY = 0;
  74     env->rampZ = 0;
  75     env->eind = 0;
  76     env->sp = 0;
  77
  78     env->skip = 0;
  79
  80     memset(env->r, 0, sizeof(env->r));
  81
  82     tlb_flush(cs);
  83 }
  84
  85 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  86 {
  87     info->mach = bfd_arch_avr;
  88     info->print_insn = NULL;
  89 }
  90
  91 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
  92 {
  93     CPUState *cs = CPU(dev);
  94     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
  95     Error *local_err = NULL;
  96
  97     cpu_exec_realizefn(cs, &local_err);
  98     if (local_err != NULL) {
  99         error_propagate(errp, local_err);
 100         return;
 101     }
 102     qemu_init_vcpu(cs);
 103     cpu_reset(cs);
 104
 105     mcc->parent_realize(dev, errp);
 106 }
 107
 108 static void avr_cpu_set_int(void *opaque, int irq, int level)
 109 {
 110     AVRCPU *cpu = opaque;
 111     CPUAVRState *env = &cpu->env;
 112     CPUState *cs = CPU(cpu);
 113     uint64_t mask = (1ull << irq);
 114
 115     if (level) {
 116         env->intsrc |= mask;
 117         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 118     } else {
 119         env->intsrc &= ~mask;
 120         if (env->intsrc == 0) {
 121             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 122         }
 123     }
 124 }
 125
 126 static void avr_cpu_initfn(Object *obj)
 127 {
 128     AVRCPU *cpu = AVR_CPU(obj);
 129
 130     cpu_set_cpustate_pointers(cpu);
 131
 132     /* Set the number of interrupts supported by the CPU. */
 133     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 134                       sizeof(cpu->env.intsrc) * 8);
 135 }
 136
 137 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 138 {
 139     ObjectClass *oc;
 140
 141     oc = object_class_by_name(cpu_model);
 142     if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
 143         object_class_is_abstract(oc)) {
 144         oc = NULL;
 145     }
 146     return oc;
 147 }
 148
 149 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 150 {
 151     AVRCPU *cpu = AVR_CPU(cs);
 152     CPUAVRState *env = &cpu->env;
 153     int i;
 154
 155     qemu_fprintf(f, "\n");
 156     qemu_fprintf(f, "PC:    %06x\n", env->pc_w);
 157     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 158     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 159     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 160     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 161     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 162     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 163     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 164     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 165     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 166     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 167                  env->sregI ? 'I' : '-',
 168                  env->sregT ? 'T' : '-',
 169                  env->sregH ? 'H' : '-',
 170                  env->sregS ? 'S' : '-',
 171                  env->sregV ? 'V' : '-',
 172                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 173                  env->sregZ ? 'Z' : '-',
 174                  env->sregC ? 'I' : '-');
 175     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 176
 177     qemu_fprintf(f, "\n");
 178     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 179         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 180
 181         if ((i % 8) == 7) {
 182             qemu_fprintf(f, "\n");
 183         }
 184     }
 185     qemu_fprintf(f, "\n");
 186 }
 187
 188 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 189 {
 190     DeviceClass *dc = DEVICE_CLASS(oc);
 191     CPUClass *cc = CPU_CLASS(oc);
 192     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 193
 194     mcc->parent_realize = dc->realize;
 195     dc->realize = avr_cpu_realizefn;
 196
 197     device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
 198
 199     cc->class_by_name = avr_cpu_class_by_name;
 200
 201     cc->has_work = avr_cpu_has_work;
 202     cc->dump_state = avr_cpu_dump_state;
 203     cc->set_pc = avr_cpu_set_pc;
 204     cc->disas_set_info = avr_cpu_disas_set_info;
 205     cc->tcg_initialize = avr_cpu_tcg_init;
 206     cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
 207 }