target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 #define SIGNBIT (uint32_t)0x80000000
  23 #define SIGNBIT64 ((uint64_t)1 << 63)
  24
  25 static void raise_exception(CPUARMState *env, int tt)
  26 {
  27     ARMCPU *cpu = arm_env_get_cpu(env);
  28     CPUState *cs = CPU(cpu);
  29
  30     cs->exception_index = tt;
  31     cpu_loop_exit(cs);
  32 }
  33
  34 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  35                           uint32_t rn, uint32_t maxindex)
  36 {
  37     uint32_t val;
  38     uint32_t tmp;
  39     int index;
  40     int shift;
  41     uint64_t *table;
  42     table = (uint64_t *)&env->vfp.regs[rn];
  43     val = 0;
  44     for (shift = 0; shift < 32; shift += 8) {
  45         index = (ireg >> shift) & 0xff;
  46         if (index < maxindex) {
  47             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  48             val |= tmp << shift;
  49         } else {
  50             val |= def & (0xff << shift);
  51         }
  52     }
  53     return val;
  54 }
  55
  56 #if !defined(CONFIG_USER_ONLY)
  57
  58 #include "exec/softmmu_exec.h"
  59
  60 #define MMUSUFFIX _mmu
  61
  62 #define SHIFT 0
  63 #include "exec/softmmu_template.h"
  64
  65 #define SHIFT 1
  66 #include "exec/softmmu_template.h"
  67
  68 #define SHIFT 2
  69 #include "exec/softmmu_template.h"
  70
  71 #define SHIFT 3
  72 #include "exec/softmmu_template.h"
  73
  74 /* try to fill the TLB and return an exception if error. If retaddr is
  75  * NULL, it means that the function was called in C code (i.e. not
  76  * from generated code or from helper.c)
  77  */
  78 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  79               uintptr_t retaddr)
  80 {
  81     int ret;
  82
  83     ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  84     if (unlikely(ret)) {
  85         ARMCPU *cpu = ARM_CPU(cs);
  86         CPUARMState *env = &cpu->env;
  87
  88         if (retaddr) {
  89             /* now we have a real cpu fault */
  90             cpu_restore_state(cs, retaddr);
  91         }
  92         raise_exception(env, cs->exception_index);
  93     }
  94 }
  95 #endif
  96
  97 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
  98 {
  99     uint32_t res = a + b;
 100     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
 101         env->QF = 1;
 102     return res;
 103 }
 104
 105 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 106 {
 107     uint32_t res = a + b;
 108     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 109         env->QF = 1;
 110         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 111     }
 112     return res;
 113 }
 114
 115 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 116 {
 117     uint32_t res = a - b;
 118     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 119         env->QF = 1;
 120         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 121     }
 122     return res;
 123 }
 124
 125 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 126 {
 127     uint32_t res;
 128     if (val >= 0x40000000) {
 129         res = ~SIGNBIT;
 130         env->QF = 1;
 131     } else if (val <= (int32_t)0xc0000000) {
 132         res = SIGNBIT;
 133         env->QF = 1;
 134     } else {
 135         res = val << 1;
 136     }
 137     return res;
 138 }
 139
 140 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 141 {
 142     uint32_t res = a + b;
 143     if (res < a) {
 144         env->QF = 1;
 145         res = ~0;
 146     }
 147     return res;
 148 }
 149
 150 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 151 {
 152     uint32_t res = a - b;
 153     if (res > a) {
 154         env->QF = 1;
 155         res = 0;
 156     }
 157     return res;
 158 }
 159
 160 /* Signed saturation.  */
 161 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 162 {
 163     int32_t top;
 164     uint32_t mask;
 165
 166     top = val >> shift;
 167     mask = (1u << shift) - 1;
 168     if (top > 0) {
 169         env->QF = 1;
 170         return mask;
 171     } else if (top < -1) {
 172         env->QF = 1;
 173         return ~mask;
 174     }
 175     return val;
 176 }
 177
 178 /* Unsigned saturation.  */
 179 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 180 {
 181     uint32_t max;
 182
 183     max = (1u << shift) - 1;
 184     if (val < 0) {
 185         env->QF = 1;
 186         return 0;
 187     } else if (val > max) {
 188         env->QF = 1;
 189         return max;
 190     }
 191     return val;
 192 }
 193
 194 /* Signed saturate.  */
 195 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 196 {
 197     return do_ssat(env, x, shift);
 198 }
 199
 200 /* Dual halfword signed saturate.  */
 201 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 202 {
 203     uint32_t res;
 204
 205     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 206     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 207     return res;
 208 }
 209
 210 /* Unsigned saturate.  */
 211 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 212 {
 213     return do_usat(env, x, shift);
 214 }
 215
 216 /* Dual halfword unsigned saturate.  */
 217 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 218 {
 219     uint32_t res;
 220
 221     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 222     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 223     return res;
 224 }
 225
 226 void HELPER(wfi)(CPUARMState *env)
 227 {
 228     CPUState *cs = CPU(arm_env_get_cpu(env));
 229
 230     cs->exception_index = EXCP_HLT;
 231     cs->halted = 1;
 232     cpu_loop_exit(cs);
 233 }
 234
 235 void HELPER(wfe)(CPUARMState *env)
 236 {
 237     CPUState *cs = CPU(arm_env_get_cpu(env));
 238
 239     /* Don't actually halt the CPU, just yield back to top
 240      * level loop
 241      */
 242     cs->exception_index = EXCP_YIELD;
 243     cpu_loop_exit(cs);
 244 }
 245
 246 void HELPER(exception)(CPUARMState *env, uint32_t excp)
 247 {
 248     CPUState *cs = CPU(arm_env_get_cpu(env));
 249
 250     cs->exception_index = excp;
 251     cpu_loop_exit(cs);
 252 }
 253
 254 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 255 {
 256     return cpsr_read(env) & ~CPSR_EXEC;
 257 }
 258
 259 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 260 {
 261     cpsr_write(env, val, mask);
 262 }
 263
 264 /* Access to user mode registers from privileged modes.  */
 265 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 266 {
 267     uint32_t val;
 268
 269     if (regno == 13) {
 270         val = env->banked_r13[0];
 271     } else if (regno == 14) {
 272         val = env->banked_r14[0];
 273     } else if (regno >= 8
 274                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 275         val = env->usr_regs[regno - 8];
 276     } else {
 277         val = env->regs[regno];
 278     }
 279     return val;
 280 }
 281
 282 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 283 {
 284     if (regno == 13) {
 285         env->banked_r13[0] = val;
 286     } else if (regno == 14) {
 287         env->banked_r14[0] = val;
 288     } else if (regno >= 8
 289                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 290         env->usr_regs[regno - 8] = val;
 291     } else {
 292         env->regs[regno] = val;
 293     }
 294 }
 295
 296 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip)
 297 {
 298     const ARMCPRegInfo *ri = rip;
 299     switch (ri->accessfn(env, ri)) {
 300     case CP_ACCESS_OK:
 301         return;
 302     case CP_ACCESS_TRAP:
 303     case CP_ACCESS_TRAP_UNCATEGORIZED:
 304         /* These cases will eventually need to generate different
 305          * syndrome information.
 306          */
 307         break;
 308     default:
 309         g_assert_not_reached();
 310     }
 311     raise_exception(env, EXCP_UDEF);
 312 }
 313
 314 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 315 {
 316     const ARMCPRegInfo *ri = rip;
 317
 318     ri->writefn(env, ri, value);
 319 }
 320
 321 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 322 {
 323     const ARMCPRegInfo *ri = rip;
 324
 325     return ri->readfn(env, ri);
 326 }
 327
 328 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 329 {
 330     const ARMCPRegInfo *ri = rip;
 331
 332     ri->writefn(env, ri, value);
 333 }
 334
 335 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 336 {
 337     const ARMCPRegInfo *ri = rip;
 338
 339     return ri->readfn(env, ri);
 340 }
 341
 342 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 343 {
 344     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 345      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 346      * to catch that case at translate time.
 347      */
 348     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
 349         raise_exception(env, EXCP_UDEF);
 350     }
 351
 352     switch (op) {
 353     case 0x05: /* SPSel */
 354         env->pstate = deposit32(env->pstate, 0, 1, imm);
 355         break;
 356     case 0x1e: /* DAIFSet */
 357         env->daif |= (imm << 6) & PSTATE_DAIF;
 358         break;
 359     case 0x1f: /* DAIFClear */
 360         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 361         break;
 362     default:
 363         g_assert_not_reached();
 364     }
 365 }
 366
 367 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
 368    The only way to do that in TCG is a conditional branch, which clobbers
 369    all our temporaries.  For now implement these as helper functions.  */
 370
 371 /* Similarly for variable shift instructions.  */
 372
 373 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 374 {
 375     int shift = i & 0xff;
 376     if (shift >= 32) {
 377         if (shift == 32)
 378             env->CF = x & 1;
 379         else
 380             env->CF = 0;
 381         return 0;
 382     } else if (shift != 0) {
 383         env->CF = (x >> (32 - shift)) & 1;
 384         return x << shift;
 385     }
 386     return x;
 387 }
 388
 389 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 390 {
 391     int shift = i & 0xff;
 392     if (shift >= 32) {
 393         if (shift == 32)
 394             env->CF = (x >> 31) & 1;
 395         else
 396             env->CF = 0;
 397         return 0;
 398     } else if (shift != 0) {
 399         env->CF = (x >> (shift - 1)) & 1;
 400         return x >> shift;
 401     }
 402     return x;
 403 }
 404
 405 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 406 {
 407     int shift = i & 0xff;
 408     if (shift >= 32) {
 409         env->CF = (x >> 31) & 1;
 410         return (int32_t)x >> 31;
 411     } else if (shift != 0) {
 412         env->CF = (x >> (shift - 1)) & 1;
 413         return (int32_t)x >> shift;
 414     }
 415     return x;
 416 }
 417
 418 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 419 {
 420     int shift1, shift;
 421     shift1 = i & 0xff;
 422     shift = shift1 & 0x1f;
 423     if (shift == 0) {
 424         if (shift1 != 0)
 425             env->CF = (x >> 31) & 1;
 426         return x;
 427     } else {
 428         env->CF = (x >> (shift - 1)) & 1;
 429         return ((uint32_t)x >> shift) | (x << (32 - shift));
 430     }
 431 }