hw/s390x/s390-pci-inst.h

   1 /*
   2  * s390 PCI instruction definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_INST_H
  15 #define HW_S390_PCI_INST_H
  16
  17 #include "s390-pci-bus.h"
  18 #include "sysemu/dma.h"
  19
  20 /* CLP common request & response block size */
  21 #define CLP_BLK_SIZE 4096
  22 #define PCI_BAR_COUNT 6
  23 #define PCI_MAX_FUNCTIONS 4096
  24
  25 typedef struct ClpReqHdr {
  26     uint16_t len;
  27     uint16_t cmd;
  28 } QEMU_PACKED ClpReqHdr;
  29
  30 typedef struct ClpRspHdr {
  31     uint16_t len;
  32     uint16_t rsp;
  33 } QEMU_PACKED ClpRspHdr;
  34
  35 /* CLP Response Codes */
  36 #define CLP_RC_OK         0x0010  /* Command request successfully */
  37 #define CLP_RC_CMD        0x0020  /* Command code not recognized */
  38 #define CLP_RC_PERM       0x0030  /* Command not authorized */
  39 #define CLP_RC_FMT        0x0040  /* Invalid command request format */
  40 #define CLP_RC_LEN        0x0050  /* Invalid command request length */
  41 #define CLP_RC_8K         0x0060  /* Command requires 8K LPCB */
  42 #define CLP_RC_RESNOT0    0x0070  /* Reserved field not zero */
  43 #define CLP_RC_NODATA     0x0080  /* No data available */
  44 #define CLP_RC_FC_UNKNOWN 0x0100  /* Function code not recognized */
  45
  46 /*
  47  * Call Logical Processor - Command Codes
  48  */
  49 #define CLP_LIST_PCI            0x0002
  50 #define CLP_QUERY_PCI_FN        0x0003
  51 #define CLP_QUERY_PCI_FNGRP     0x0004
  52 #define CLP_SET_PCI_FN          0x0005
  53
  54 /* PCI function handle list entry */
  55 typedef struct ClpFhListEntry {
  56     uint16_t device_id;
  57     uint16_t vendor_id;
  58 #define CLP_FHLIST_MASK_CONFIG 0x80000000
  59     uint32_t config;
  60     uint32_t fid;
  61     uint32_t fh;
  62 } QEMU_PACKED ClpFhListEntry;
  63
  64 #define CLP_RC_SETPCIFN_FH      0x0101 /* Invalid PCI fn handle */
  65 #define CLP_RC_SETPCIFN_FHOP    0x0102 /* Fn handle not valid for op */
  66 #define CLP_RC_SETPCIFN_DMAAS   0x0103 /* Invalid DMA addr space */
  67 #define CLP_RC_SETPCIFN_RES     0x0104 /* Insufficient resources */
  68 #define CLP_RC_SETPCIFN_ALRDY   0x0105 /* Fn already in requested state */
  69 #define CLP_RC_SETPCIFN_ERR     0x0106 /* Fn in permanent error state */
  70 #define CLP_RC_SETPCIFN_RECPND  0x0107 /* Error recovery pending */
  71 #define CLP_RC_SETPCIFN_BUSY    0x0108 /* Fn busy */
  72 #define CLP_RC_LISTPCI_BADRT    0x010a /* Resume token not recognized */
  73 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
  74
  75 /* request or response block header length */
  76 #define LIST_PCI_HDR_LEN 32
  77
  78 /* Number of function handles fitting in response block */
  79 #define CLP_FH_LIST_NR_ENTRIES \
  80     ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
  81         / sizeof(ClpFhListEntry))
  82
  83 #define CLP_SET_ENABLE_PCI_FN  0 /* Yes, 0 enables it */
  84 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
  85
  86 #define CLP_UTIL_STR_LEN 64
  87
  88 #define CLP_MASK_FMT 0xf0000000
  89
  90 /* List PCI functions request */
  91 typedef struct ClpReqListPci {
  92     ClpReqHdr hdr;
  93     uint32_t fmt;
  94     uint64_t reserved1;
  95     uint64_t resume_token;
  96     uint64_t reserved2;
  97 } QEMU_PACKED ClpReqListPci;
  98
  99 /* List PCI functions response */
 100 typedef struct ClpRspListPci {
 101     ClpRspHdr hdr;
 102     uint32_t fmt;
 103     uint64_t reserved1;
 104     uint64_t resume_token;
 105     uint32_t mdd;
 106     uint16_t max_fn;
 107     uint8_t flags;
 108     uint8_t entry_size;
 109     ClpFhListEntry fh_list[CLP_FH_LIST_NR_ENTRIES];
 110 } QEMU_PACKED ClpRspListPci;
 111
 112 /* Query PCI function request */
 113 typedef struct ClpReqQueryPci {
 114     ClpReqHdr hdr;
 115     uint32_t fmt;
 116     uint64_t reserved1;
 117     uint32_t fh; /* function handle */
 118     uint32_t reserved2;
 119     uint64_t reserved3;
 120 } QEMU_PACKED ClpReqQueryPci;
 121
 122 /* Query PCI function response */
 123 typedef struct ClpRspQueryPci {
 124     ClpRspHdr hdr;
 125     uint32_t fmt;
 126     uint64_t reserved1;
 127     uint16_t vfn; /* virtual fn number */
 128 #define CLP_RSP_QPCI_MASK_UTIL  0x100
 129 #define CLP_RSP_QPCI_MASK_PFGID 0xff
 130     uint16_t ug;
 131     uint32_t fid; /* pci function id */
 132     uint8_t bar_size[PCI_BAR_COUNT];
 133     uint16_t pchid;
 134     uint32_t bar[PCI_BAR_COUNT];
 135     uint64_t reserved2;
 136     uint64_t sdma; /* start dma as */
 137     uint64_t edma; /* end dma as */
 138     uint32_t reserved3[11];
 139     uint32_t uid;
 140     uint8_t util_str[CLP_UTIL_STR_LEN]; /* utility string */
 141 } QEMU_PACKED ClpRspQueryPci;
 142
 143 /* Query PCI function group request */
 144 typedef struct ClpReqQueryPciGrp {
 145     ClpReqHdr hdr;
 146     uint32_t fmt;
 147     uint64_t reserved1;
 148 #define CLP_REQ_QPCIG_MASK_PFGID 0xff
 149     uint32_t g;
 150     uint32_t reserved2;
 151     uint64_t reserved3;
 152 } QEMU_PACKED ClpReqQueryPciGrp;
 153
 154 /* Query PCI function group response */
 155 typedef struct ClpRspQueryPciGrp {
 156     ClpRspHdr hdr;
 157     uint32_t fmt;
 158     uint64_t reserved1;
 159 #define CLP_RSP_QPCIG_MASK_NOI 0xfff
 160     uint16_t i;
 161     uint8_t version;
 162 #define CLP_RSP_QPCIG_MASK_FRAME   0x2
 163 #define CLP_RSP_QPCIG_MASK_REFRESH 0x1
 164     uint8_t fr;
 165     uint16_t maxstbl;
 166     uint16_t mui;
 167     uint64_t reserved3;
 168     uint64_t dasm; /* dma address space mask */
 169     uint64_t msia; /* MSI address */
 170     uint64_t reserved4;
 171     uint64_t reserved5;
 172 } QEMU_PACKED ClpRspQueryPciGrp;
 173
 174 /* Set PCI function request */
 175 typedef struct ClpReqSetPci {
 176     ClpReqHdr hdr;
 177     uint32_t fmt;
 178     uint64_t reserved1;
 179     uint32_t fh; /* function handle */
 180     uint16_t reserved2;
 181     uint8_t oc; /* operation controls */
 182     uint8_t ndas; /* number of dma spaces */
 183     uint64_t reserved3;
 184 } QEMU_PACKED ClpReqSetPci;
 185
 186 /* Set PCI function response */
 187 typedef struct ClpRspSetPci {
 188     ClpRspHdr hdr;
 189     uint32_t fmt;
 190     uint64_t reserved1;
 191     uint32_t fh; /* function handle */
 192     uint32_t reserved3;
 193     uint64_t reserved4;
 194 } QEMU_PACKED ClpRspSetPci;
 195
 196 typedef struct ClpReqRspListPci {
 197     ClpReqListPci request;
 198     ClpRspListPci response;
 199 } QEMU_PACKED ClpReqRspListPci;
 200
 201 typedef struct ClpReqRspSetPci {
 202     ClpReqSetPci request;
 203     ClpRspSetPci response;
 204 } QEMU_PACKED ClpReqRspSetPci;
 205
 206 typedef struct ClpReqRspQueryPci {
 207     ClpReqQueryPci request;
 208     ClpRspQueryPci response;
 209 } QEMU_PACKED ClpReqRspQueryPci;
 210
 211 typedef struct ClpReqRspQueryPciGrp {
 212     ClpReqQueryPciGrp request;
 213     ClpRspQueryPciGrp response;
 214 } QEMU_PACKED ClpReqRspQueryPciGrp;
 215
 216 /* Load/Store status codes */
 217 #define ZPCI_PCI_ST_FUNC_NOT_ENABLED        4
 218 #define ZPCI_PCI_ST_FUNC_IN_ERR             8
 219 #define ZPCI_PCI_ST_BLOCKED                 12
 220 #define ZPCI_PCI_ST_INSUF_RES               16
 221 #define ZPCI_PCI_ST_INVAL_AS                20
 222 #define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED    24
 223 #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED      28
 224 #define ZPCI_PCI_ST_2ND_OP_IN_INV_AS        36
 225 #define ZPCI_PCI_ST_FUNC_NOT_AVAIL          40
 226 #define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE     44
 227
 228 /* Load/Store return codes */
 229 #define ZPCI_PCI_LS_OK              0
 230 #define ZPCI_PCI_LS_ERR             1
 231 #define ZPCI_PCI_LS_BUSY            2
 232 #define ZPCI_PCI_LS_INVAL_HANDLE    3
 233
 234 /* Modify PCI status codes */
 235 #define ZPCI_MOD_ST_RES_NOT_AVAIL 4
 236 #define ZPCI_MOD_ST_INSUF_RES     16
 237 #define ZPCI_MOD_ST_SEQUENCE      24
 238 #define ZPCI_MOD_ST_DMAAS_INVAL   28
 239 #define ZPCI_MOD_ST_FRAME_INVAL   32
 240 #define ZPCI_MOD_ST_ERROR_RECOVER 40
 241
 242 /* Modify PCI Function Controls */
 243 #define ZPCI_MOD_FC_REG_INT     2
 244 #define ZPCI_MOD_FC_DEREG_INT   3
 245 #define ZPCI_MOD_FC_REG_IOAT    4
 246 #define ZPCI_MOD_FC_DEREG_IOAT  5
 247 #define ZPCI_MOD_FC_REREG_IOAT  6
 248 #define ZPCI_MOD_FC_RESET_ERROR 7
 249 #define ZPCI_MOD_FC_RESET_BLOCK 9
 250 #define ZPCI_MOD_FC_SET_MEASURE 10
 251
 252 /* Store PCI Function Controls status codes */
 253 #define ZPCI_STPCIFC_ST_PERM_ERROR    8
 254 #define ZPCI_STPCIFC_ST_INVAL_DMAAS   28
 255 #define ZPCI_STPCIFC_ST_ERROR_RECOVER 40
 256
 257 /* FIB function controls */
 258 #define ZPCI_FIB_FC_ENABLED     0x80
 259 #define ZPCI_FIB_FC_ERROR       0x40
 260 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
 261 #define ZPCI_FIB_FC_DMAAS_REG   0x10
 262
 263 /* FIB function controls */
 264 #define ZPCI_FIB_FC_ENABLED     0x80
 265 #define ZPCI_FIB_FC_ERROR       0x40
 266 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
 267 #define ZPCI_FIB_FC_DMAAS_REG   0x10
 268
 269 /* Function Information Block */
 270 typedef struct ZpciFib {
 271     uint8_t fmt;   /* format */
 272     uint8_t reserved1[7];
 273     uint8_t fc;                  /* function controls */
 274     uint8_t reserved2;
 275     uint16_t reserved3;
 276     uint32_t reserved4;
 277     uint64_t pba;                /* PCI base address */
 278     uint64_t pal;                /* PCI address limit */
 279     uint64_t iota;               /* I/O Translation Anchor */
 280 #define FIB_DATA_ISC(x)    (((x) >> 28) & 0x7)
 281 #define FIB_DATA_NOI(x)    (((x) >> 16) & 0xfff)
 282 #define FIB_DATA_AIBVO(x) (((x) >> 8) & 0x3f)
 283 #define FIB_DATA_SUM(x)    (((x) >> 7) & 0x1)
 284 #define FIB_DATA_AISBO(x)  ((x) & 0x3f)
 285     uint32_t data;
 286     uint32_t reserved5;
 287     uint64_t aibv;               /* Adapter int bit vector address */
 288     uint64_t aisb;               /* Adapter int summary bit address */
 289     uint64_t fmb_addr;           /* Function measurement address and key */
 290     uint32_t reserved6;
 291     uint32_t gd;
 292 } QEMU_PACKED ZpciFib;
 293
 294 int pci_dereg_irqs(S390PCIBusDevice *pbdev);
 295 void pci_dereg_ioat(S390PCIIOMMU *iommu);
 296 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra);
 297 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
 298 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
 299 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
 300 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 301                         uint8_t ar, uintptr_t ra);
 302 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
 303                         uintptr_t ra);
 304 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
 305                          uintptr_t ra);
 306 void fmb_timer_free(S390PCIBusDevice *pbdev);
 307
 308 #define ZPCI_IO_BAR_MIN 0
 309 #define ZPCI_IO_BAR_MAX 5
 310 #define ZPCI_CONFIG_BAR 15
 311
 312 #endif