target/riscv/translate.c

   1 /*
   2  * RISC-V emulation for qemu: main translation routines.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "cpu.h"
  22 #include "tcg-op.h"
  23 #include "disas/disas.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/helper-proto.h"
  27 #include "exec/helper-gen.h"
  28
  29 #include "exec/translator.h"
  30 #include "exec/log.h"
  31
  32 #include "instmap.h"
  33
  34 /* global register indices */
  35 static TCGv cpu_gpr[32], cpu_pc;
  36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
  37 static TCGv load_res;
  38 static TCGv load_val;
  39
  40 #include "exec/gen-icount.h"
  41
  42 typedef struct DisasContext {
  43     DisasContextBase base;
  44     /* pc_succ_insn points to the instruction following base.pc_next */
  45     target_ulong pc_succ_insn;
  46     target_ulong priv_ver;
  47     uint32_t opcode;
  48     uint32_t mstatus_fs;
  49     uint32_t misa;
  50     uint32_t mem_idx;
  51     /* Remember the rounding mode encoded in the previous fp instruction,
  52        which we have already installed into env->fp_status.  Or -1 for
  53        no previous fp instruction.  Note that we exit the TB when writing
  54        to any system register, which includes CSR_FRM, so we do not have
  55        to reset this known value.  */
  56     int frm;
  57     bool ext_ifencei;
  58 } DisasContext;
  59
  60 #ifdef TARGET_RISCV64
  61 /* convert riscv funct3 to qemu memop for load/store */
  62 static const int tcg_memop_lookup[8] = {
  63     [0 ... 7] = -1,
  64     [0] = MO_SB,
  65     [1] = MO_TESW,
  66     [2] = MO_TESL,
  67     [4] = MO_UB,
  68     [5] = MO_TEUW,
  69 #ifdef TARGET_RISCV64
  70     [3] = MO_TEQ,
  71     [6] = MO_TEUL,
  72 #endif
  73 };
  74 #endif
  75
  76 #ifdef TARGET_RISCV64
  77 #define CASE_OP_32_64(X) case X: case glue(X, W)
  78 #else
  79 #define CASE_OP_32_64(X) case X
  80 #endif
  81
  82 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  83 {
  84     return ctx->misa & ext;
  85 }
  86
  87 static void generate_exception(DisasContext *ctx, int excp)
  88 {
  89     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
  90     TCGv_i32 helper_tmp = tcg_const_i32(excp);
  91     gen_helper_raise_exception(cpu_env, helper_tmp);
  92     tcg_temp_free_i32(helper_tmp);
  93     ctx->base.is_jmp = DISAS_NORETURN;
  94 }
  95
  96 static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
  97 {
  98     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
  99     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 100     TCGv_i32 helper_tmp = tcg_const_i32(excp);
 101     gen_helper_raise_exception(cpu_env, helper_tmp);
 102     tcg_temp_free_i32(helper_tmp);
 103     ctx->base.is_jmp = DISAS_NORETURN;
 104 }
 105
 106 static void gen_exception_debug(void)
 107 {
 108     TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
 109     gen_helper_raise_exception(cpu_env, helper_tmp);
 110     tcg_temp_free_i32(helper_tmp);
 111 }
 112
 113 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
 114 static void exit_tb(DisasContext *ctx)
 115 {
 116     if (ctx->base.singlestep_enabled) {
 117         gen_exception_debug();
 118     } else {
 119         tcg_gen_exit_tb(NULL, 0);
 120     }
 121 }
 122
 123 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
 124 static void lookup_and_goto_ptr(DisasContext *ctx)
 125 {
 126     if (ctx->base.singlestep_enabled) {
 127         gen_exception_debug();
 128     } else {
 129         tcg_gen_lookup_and_goto_ptr();
 130     }
 131 }
 132
 133 static void gen_exception_illegal(DisasContext *ctx)
 134 {
 135     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 136 }
 137
 138 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 139 {
 140     generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
 141 }
 142
 143 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 144 {
 145     if (unlikely(ctx->base.singlestep_enabled)) {
 146         return false;
 147     }
 148
 149 #ifndef CONFIG_USER_ONLY
 150     return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 151 #else
 152     return true;
 153 #endif
 154 }
 155
 156 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 157 {
 158     if (use_goto_tb(ctx, dest)) {
 159         /* chaining is only allowed when the jump is to the same page */
 160         tcg_gen_goto_tb(n);
 161         tcg_gen_movi_tl(cpu_pc, dest);
 162
 163         /* No need to check for single stepping here as use_goto_tb() will
 164          * return false in case of single stepping.
 165          */
 166         tcg_gen_exit_tb(ctx->base.tb, n);
 167     } else {
 168         tcg_gen_movi_tl(cpu_pc, dest);
 169         lookup_and_goto_ptr(ctx);
 170     }
 171 }
 172
 173 /* Wrapper for getting reg values - need to check of reg is zero since
 174  * cpu_gpr[0] is not actually allocated
 175  */
 176 static inline void gen_get_gpr(TCGv t, int reg_num)
 177 {
 178     if (reg_num == 0) {
 179         tcg_gen_movi_tl(t, 0);
 180     } else {
 181         tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
 182     }
 183 }
 184
 185 /* Wrapper for setting reg values - need to check of reg is zero since
 186  * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
 187  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
 188  * $zero
 189  */
 190 static inline void gen_set_gpr(int reg_num_dst, TCGv t)
 191 {
 192     if (reg_num_dst != 0) {
 193         tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
 194     }
 195 }
 196
 197 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 198 {
 199     TCGv rl = tcg_temp_new();
 200     TCGv rh = tcg_temp_new();
 201
 202     tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
 203     /* fix up for one negative */
 204     tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
 205     tcg_gen_and_tl(rl, rl, arg2);
 206     tcg_gen_sub_tl(ret, rh, rl);
 207
 208     tcg_temp_free(rl);
 209     tcg_temp_free(rh);
 210 }
 211
 212 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 213 {
 214     TCGv cond1, cond2, zeroreg, resultopt1;
 215     /*
 216      * Handle by altering args to tcg_gen_div to produce req'd results:
 217      * For overflow: want source1 in source1 and 1 in source2
 218      * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
 219      */
 220     cond1 = tcg_temp_new();
 221     cond2 = tcg_temp_new();
 222     zeroreg = tcg_const_tl(0);
 223     resultopt1 = tcg_temp_new();
 224
 225     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 226     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
 227     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 228                         ((target_ulong)1) << (TARGET_LONG_BITS - 1));
 229     tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
 230     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
 231     /* if div by zero, set source1 to -1, otherwise don't change */
 232     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
 233             resultopt1);
 234     /* if overflow or div by zero, set source2 to 1, else don't change */
 235     tcg_gen_or_tl(cond1, cond1, cond2);
 236     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 237     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 238             resultopt1);
 239     tcg_gen_div_tl(ret, source1, source2);
 240
 241     tcg_temp_free(cond1);
 242     tcg_temp_free(cond2);
 243     tcg_temp_free(zeroreg);
 244     tcg_temp_free(resultopt1);
 245 }
 246
 247 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
 248 {
 249     TCGv cond1, zeroreg, resultopt1;
 250     cond1 = tcg_temp_new();
 251
 252     zeroreg = tcg_const_tl(0);
 253     resultopt1 = tcg_temp_new();
 254
 255     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 256     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 257     tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
 258             resultopt1);
 259     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 260     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 261             resultopt1);
 262     tcg_gen_divu_tl(ret, source1, source2);
 263
 264     tcg_temp_free(cond1);
 265     tcg_temp_free(zeroreg);
 266     tcg_temp_free(resultopt1);
 267 }
 268
 269 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 270 {
 271     TCGv cond1, cond2, zeroreg, resultopt1;
 272
 273     cond1 = tcg_temp_new();
 274     cond2 = tcg_temp_new();
 275     zeroreg = tcg_const_tl(0);
 276     resultopt1 = tcg_temp_new();
 277
 278     tcg_gen_movi_tl(resultopt1, 1L);
 279     tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
 280     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 281                         (target_ulong)1 << (TARGET_LONG_BITS - 1));
 282     tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
 283     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
 284     /* if overflow or div by zero, set source2 to 1, else don't change */
 285     tcg_gen_or_tl(cond2, cond1, cond2);
 286     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
 287             resultopt1);
 288     tcg_gen_rem_tl(resultopt1, source1, source2);
 289     /* if div by zero, just return the original dividend */
 290     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 291             source1);
 292
 293     tcg_temp_free(cond1);
 294     tcg_temp_free(cond2);
 295     tcg_temp_free(zeroreg);
 296     tcg_temp_free(resultopt1);
 297 }
 298
 299 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 300 {
 301     TCGv cond1, zeroreg, resultopt1;
 302     cond1 = tcg_temp_new();
 303     zeroreg = tcg_const_tl(0);
 304     resultopt1 = tcg_temp_new();
 305
 306     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 307     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 308     tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 309             resultopt1);
 310     tcg_gen_remu_tl(resultopt1, source1, source2);
 311     /* if div by zero, just return the original dividend */
 312     tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 313             source1);
 314
 315     tcg_temp_free(cond1);
 316     tcg_temp_free(zeroreg);
 317     tcg_temp_free(resultopt1);
 318 }
 319
 320 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 321 {
 322     target_ulong next_pc;
 323
 324     /* check misaligned: */
 325     next_pc = ctx->base.pc_next + imm;
 326     if (!has_ext(ctx, RVC)) {
 327         if ((next_pc & 0x3) != 0) {
 328             gen_exception_inst_addr_mis(ctx);
 329             return;
 330         }
 331     }
 332     if (rd != 0) {
 333         tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
 334     }
 335
 336     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
 337     ctx->base.is_jmp = DISAS_NORETURN;
 338 }
 339
 340 #ifdef TARGET_RISCV64
 341 static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 342         target_long imm)
 343 {
 344     TCGv t0 = tcg_temp_new();
 345     TCGv t1 = tcg_temp_new();
 346     gen_get_gpr(t0, rs1);
 347     tcg_gen_addi_tl(t0, t0, imm);
 348     int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 349
 350     if (memop < 0) {
 351         gen_exception_illegal(ctx);
 352         return;
 353     }
 354
 355     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 356     gen_set_gpr(rd, t1);
 357     tcg_temp_free(t0);
 358     tcg_temp_free(t1);
 359 }
 360
 361 static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 362         target_long imm)
 363 {
 364     TCGv t0 = tcg_temp_new();
 365     TCGv dat = tcg_temp_new();
 366     gen_get_gpr(t0, rs1);
 367     tcg_gen_addi_tl(t0, t0, imm);
 368     gen_get_gpr(dat, rs2);
 369     int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 370
 371     if (memop < 0) {
 372         gen_exception_illegal(ctx);
 373         return;
 374     }
 375
 376     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 377     tcg_temp_free(t0);
 378     tcg_temp_free(dat);
 379 }
 380 #endif
 381
 382 #ifndef CONFIG_USER_ONLY
 383 /* The states of mstatus_fs are:
 384  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
 385  * We will have already diagnosed disabled state,
 386  * and need to turn initial/clean into dirty.
 387  */
 388 static void mark_fs_dirty(DisasContext *ctx)
 389 {
 390     TCGv tmp;
 391     if (ctx->mstatus_fs == MSTATUS_FS) {
 392         return;
 393     }
 394     /* Remember the state change for the rest of the TB.  */
 395     ctx->mstatus_fs = MSTATUS_FS;
 396
 397     tmp = tcg_temp_new();
 398     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 399     tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
 400     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 401     tcg_temp_free(tmp);
 402 }
 403 #else
 404 static inline void mark_fs_dirty(DisasContext *ctx) { }
 405 #endif
 406
 407 #if !defined(TARGET_RISCV64)
 408 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 409         int rs1, target_long imm)
 410 {
 411     TCGv t0;
 412
 413     if (ctx->mstatus_fs == 0) {
 414         gen_exception_illegal(ctx);
 415         return;
 416     }
 417
 418     t0 = tcg_temp_new();
 419     gen_get_gpr(t0, rs1);
 420     tcg_gen_addi_tl(t0, t0, imm);
 421
 422     switch (opc) {
 423     case OPC_RISC_FLW:
 424         if (!has_ext(ctx, RVF)) {
 425             goto do_illegal;
 426         }
 427         tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 428         /* RISC-V requires NaN-boxing of narrower width floating point values */
 429         tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 430         break;
 431     case OPC_RISC_FLD:
 432         if (!has_ext(ctx, RVD)) {
 433             goto do_illegal;
 434         }
 435         tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 436         break;
 437     do_illegal:
 438     default:
 439         gen_exception_illegal(ctx);
 440         break;
 441     }
 442     tcg_temp_free(t0);
 443
 444     mark_fs_dirty(ctx);
 445 }
 446
 447 static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 448         int rs2, target_long imm)
 449 {
 450     TCGv t0;
 451
 452     if (ctx->mstatus_fs == 0) {
 453         gen_exception_illegal(ctx);
 454         return;
 455     }
 456
 457     t0 = tcg_temp_new();
 458     gen_get_gpr(t0, rs1);
 459     tcg_gen_addi_tl(t0, t0, imm);
 460
 461     switch (opc) {
 462     case OPC_RISC_FSW:
 463         if (!has_ext(ctx, RVF)) {
 464             goto do_illegal;
 465         }
 466         tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 467         break;
 468     case OPC_RISC_FSD:
 469         if (!has_ext(ctx, RVD)) {
 470             goto do_illegal;
 471         }
 472         tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 473         break;
 474     do_illegal:
 475     default:
 476         gen_exception_illegal(ctx);
 477         break;
 478     }
 479
 480     tcg_temp_free(t0);
 481 }
 482 #endif
 483
 484 static void gen_set_rm(DisasContext *ctx, int rm)
 485 {
 486     TCGv_i32 t0;
 487
 488     if (ctx->frm == rm) {
 489         return;
 490     }
 491     ctx->frm = rm;
 492     t0 = tcg_const_i32(rm);
 493     gen_helper_set_rounding_mode(cpu_env, t0);
 494     tcg_temp_free_i32(t0);
 495 }
 496
 497 static void decode_RV32_64C0(DisasContext *ctx)
 498 {
 499     uint8_t funct3 = extract32(ctx->opcode, 13, 3);
 500     uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
 501     uint8_t rs1s = GET_C_RS1S(ctx->opcode);
 502
 503     switch (funct3) {
 504     case 3:
 505 #if defined(TARGET_RISCV64)
 506         /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 507         gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 508                  GET_C_LD_IMM(ctx->opcode));
 509 #else
 510         /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 511         gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 512                     GET_C_LW_IMM(ctx->opcode));
 513 #endif
 514         break;
 515     case 7:
 516 #if defined(TARGET_RISCV64)
 517         /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 518         gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 519                   GET_C_LD_IMM(ctx->opcode));
 520 #else
 521         /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 522         gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 523                      GET_C_LW_IMM(ctx->opcode));
 524 #endif
 525         break;
 526     }
 527 }
 528
 529 static void decode_RV32_64C(DisasContext *ctx)
 530 {
 531     uint8_t op = extract32(ctx->opcode, 0, 2);
 532
 533     switch (op) {
 534     case 0:
 535         decode_RV32_64C0(ctx);
 536         break;
 537     }
 538 }
 539
 540 #define EX_SH(amount) \
 541     static int ex_shift_##amount(DisasContext *ctx, int imm) \
 542     {                                         \
 543         return imm << amount;                 \
 544     }
 545 EX_SH(1)
 546 EX_SH(2)
 547 EX_SH(3)
 548 EX_SH(4)
 549 EX_SH(12)
 550
 551 #define REQUIRE_EXT(ctx, ext) do { \
 552     if (!has_ext(ctx, ext)) {      \
 553         return false;              \
 554     }                              \
 555 } while (0)
 556
 557 static int ex_rvc_register(DisasContext *ctx, int reg)
 558 {
 559     return 8 + reg;
 560 }
 561
 562 static int ex_rvc_shifti(DisasContext *ctx, int imm)
 563 {
 564     /* For RV128 a shamt of 0 means a shift by 64. */
 565     return imm ? imm : 64;
 566 }
 567
 568 /* Include the auto-generated decoder for 32 bit insn */
 569 #include "decode_insn32.inc.c"
 570
 571 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
 572                              void (*func)(TCGv, TCGv, target_long))
 573 {
 574     TCGv source1;
 575     source1 = tcg_temp_new();
 576
 577     gen_get_gpr(source1, a->rs1);
 578
 579     (*func)(source1, source1, a->imm);
 580
 581     gen_set_gpr(a->rd, source1);
 582     tcg_temp_free(source1);
 583     return true;
 584 }
 585
 586 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
 587                              void (*func)(TCGv, TCGv, TCGv))
 588 {
 589     TCGv source1, source2;
 590     source1 = tcg_temp_new();
 591     source2 = tcg_temp_new();
 592
 593     gen_get_gpr(source1, a->rs1);
 594     tcg_gen_movi_tl(source2, a->imm);
 595
 596     (*func)(source1, source1, source2);
 597
 598     gen_set_gpr(a->rd, source1);
 599     tcg_temp_free(source1);
 600     tcg_temp_free(source2);
 601     return true;
 602 }
 603
 604 #ifdef TARGET_RISCV64
 605 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 606 {
 607     tcg_gen_add_tl(ret, arg1, arg2);
 608     tcg_gen_ext32s_tl(ret, ret);
 609 }
 610
 611 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
 612 {
 613     tcg_gen_sub_tl(ret, arg1, arg2);
 614     tcg_gen_ext32s_tl(ret, ret);
 615 }
 616
 617 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
 618 {
 619     tcg_gen_mul_tl(ret, arg1, arg2);
 620     tcg_gen_ext32s_tl(ret, ret);
 621 }
 622
 623 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
 624                             void(*func)(TCGv, TCGv, TCGv))
 625 {
 626     TCGv source1, source2;
 627     source1 = tcg_temp_new();
 628     source2 = tcg_temp_new();
 629
 630     gen_get_gpr(source1, a->rs1);
 631     gen_get_gpr(source2, a->rs2);
 632     tcg_gen_ext32s_tl(source1, source1);
 633     tcg_gen_ext32s_tl(source2, source2);
 634
 635     (*func)(source1, source1, source2);
 636
 637     tcg_gen_ext32s_tl(source1, source1);
 638     gen_set_gpr(a->rd, source1);
 639     tcg_temp_free(source1);
 640     tcg_temp_free(source2);
 641     return true;
 642 }
 643
 644 static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 645                             void(*func)(TCGv, TCGv, TCGv))
 646 {
 647     TCGv source1, source2;
 648     source1 = tcg_temp_new();
 649     source2 = tcg_temp_new();
 650
 651     gen_get_gpr(source1, a->rs1);
 652     gen_get_gpr(source2, a->rs2);
 653     tcg_gen_ext32u_tl(source1, source1);
 654     tcg_gen_ext32u_tl(source2, source2);
 655
 656     (*func)(source1, source1, source2);
 657
 658     tcg_gen_ext32s_tl(source1, source1);
 659     gen_set_gpr(a->rd, source1);
 660     tcg_temp_free(source1);
 661     tcg_temp_free(source2);
 662     return true;
 663 }
 664
 665 #endif
 666
 667 static bool gen_arith(DisasContext *ctx, arg_r *a,
 668                       void(*func)(TCGv, TCGv, TCGv))
 669 {
 670     TCGv source1, source2;
 671     source1 = tcg_temp_new();
 672     source2 = tcg_temp_new();
 673
 674     gen_get_gpr(source1, a->rs1);
 675     gen_get_gpr(source2, a->rs2);
 676
 677     (*func)(source1, source1, source2);
 678
 679     gen_set_gpr(a->rd, source1);
 680     tcg_temp_free(source1);
 681     tcg_temp_free(source2);
 682     return true;
 683 }
 684
 685 static bool gen_shift(DisasContext *ctx, arg_r *a,
 686                         void(*func)(TCGv, TCGv, TCGv))
 687 {
 688     TCGv source1 = tcg_temp_new();
 689     TCGv source2 = tcg_temp_new();
 690
 691     gen_get_gpr(source1, a->rs1);
 692     gen_get_gpr(source2, a->rs2);
 693
 694     tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
 695     (*func)(source1, source1, source2);
 696
 697     gen_set_gpr(a->rd, source1);
 698     tcg_temp_free(source1);
 699     tcg_temp_free(source2);
 700     return true;
 701 }
 702
 703 /* Include insn module translation function */
 704 #include "insn_trans/trans_rvi.inc.c"
 705 #include "insn_trans/trans_rvm.inc.c"
 706 #include "insn_trans/trans_rva.inc.c"
 707 #include "insn_trans/trans_rvf.inc.c"
 708 #include "insn_trans/trans_rvd.inc.c"
 709 #include "insn_trans/trans_privileged.inc.c"
 710
 711 /* Include the auto-generated decoder for 16 bit insn */
 712 #include "decode_insn16.inc.c"
 713
 714 static void decode_opc(DisasContext *ctx)
 715 {
 716     /* check for compressed insn */
 717     if (extract32(ctx->opcode, 0, 2) != 3) {
 718         if (!has_ext(ctx, RVC)) {
 719             gen_exception_illegal(ctx);
 720         } else {
 721             ctx->pc_succ_insn = ctx->base.pc_next + 2;
 722             if (!decode_insn16(ctx, ctx->opcode)) {
 723                 /* fall back to old decoder */
 724                 decode_RV32_64C(ctx);
 725             }
 726         }
 727     } else {
 728         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 729         if (!decode_insn32(ctx, ctx->opcode)) {
 730             gen_exception_illegal(ctx);
 731         }
 732     }
 733 }
 734
 735 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 736 {
 737     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 738     CPURISCVState *env = cs->env_ptr;
 739     RISCVCPU *cpu = RISCV_CPU(cs);
 740
 741     ctx->pc_succ_insn = ctx->base.pc_first;
 742     ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
 743     ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
 744     ctx->priv_ver = env->priv_ver;
 745     ctx->misa = env->misa;
 746     ctx->frm = -1;  /* unknown rounding mode */
 747     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 748 }
 749
 750 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 751 {
 752 }
 753
 754 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 755 {
 756     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 757
 758     tcg_gen_insn_start(ctx->base.pc_next);
 759 }
 760
 761 static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
 762                                       const CPUBreakpoint *bp)
 763 {
 764     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 765
 766     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 767     ctx->base.is_jmp = DISAS_NORETURN;
 768     gen_exception_debug();
 769     /* The address covered by the breakpoint must be included in
 770        [tb->pc, tb->pc + tb->size) in order to for it to be
 771        properly cleared -- thus we increment the PC here so that
 772        the logic setting tb->size below does the right thing.  */
 773     ctx->base.pc_next += 4;
 774     return true;
 775 }
 776
 777 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 778 {
 779     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 780     CPURISCVState *env = cpu->env_ptr;
 781
 782     ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
 783     decode_opc(ctx);
 784     ctx->base.pc_next = ctx->pc_succ_insn;
 785
 786     if (ctx->base.is_jmp == DISAS_NEXT) {
 787         target_ulong page_start;
 788
 789         page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
 790         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
 791             ctx->base.is_jmp = DISAS_TOO_MANY;
 792         }
 793     }
 794 }
 795
 796 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 797 {
 798     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 799
 800     switch (ctx->base.is_jmp) {
 801     case DISAS_TOO_MANY:
 802         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 803         break;
 804     case DISAS_NORETURN:
 805         break;
 806     default:
 807         g_assert_not_reached();
 808     }
 809 }
 810
 811 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 812 {
 813     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 814     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 815 }
 816
 817 static const TranslatorOps riscv_tr_ops = {
 818     .init_disas_context = riscv_tr_init_disas_context,
 819     .tb_start           = riscv_tr_tb_start,
 820     .insn_start         = riscv_tr_insn_start,
 821     .breakpoint_check   = riscv_tr_breakpoint_check,
 822     .translate_insn     = riscv_tr_translate_insn,
 823     .tb_stop            = riscv_tr_tb_stop,
 824     .disas_log          = riscv_tr_disas_log,
 825 };
 826
 827 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 828 {
 829     DisasContext ctx;
 830
 831     translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
 832 }
 833
 834 void riscv_translate_init(void)
 835 {
 836     int i;
 837
 838     /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
 839     /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
 840     /* registers, unless you specifically block reads/writes to reg 0 */
 841     cpu_gpr[0] = NULL;
 842
 843     for (i = 1; i < 32; i++) {
 844         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 845             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
 846     }
 847
 848     for (i = 0; i < 32; i++) {
 849         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 850             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
 851     }
 852
 853     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
 854     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
 855                              "load_res");
 856     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
 857                              "load_val");
 858 }