tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "tcg-target.h"
  33
  34 /* XXX: make safe guess about sizes */
  35 #define MAX_OP_PER_INSTR 266
  36
  37 #if HOST_LONG_BITS == 32
  38 #define MAX_OPC_PARAM_PER_ARG 2
  39 #else
  40 #define MAX_OPC_PARAM_PER_ARG 1
  41 #endif
  42 #define MAX_OPC_PARAM_IARGS 5
  43 #define MAX_OPC_PARAM_OARGS 1
  44 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  45
  46 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  47  * and up to 4 + N parameters on 64-bit archs
  48  * (N = number of input arguments + output arguments).  */
  49 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  50 #define OPC_BUF_SIZE 640
  51 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  52
  53 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  54
  55 #define CPU_TEMP_BUF_NLONGS 128
  56
  57 /* Default target word size to pointer size.  */
  58 #ifndef TCG_TARGET_REG_BITS
  59 # if UINTPTR_MAX == UINT32_MAX
  60 #  define TCG_TARGET_REG_BITS 32
  61 # elif UINTPTR_MAX == UINT64_MAX
  62 #  define TCG_TARGET_REG_BITS 64
  63 # else
  64 #  error Unknown pointer size for tcg target
  65 # endif
  66 #endif
  67
  68 #if TCG_TARGET_REG_BITS == 32
  69 typedef int32_t tcg_target_long;
  70 typedef uint32_t tcg_target_ulong;
  71 #define TCG_PRIlx PRIx32
  72 #define TCG_PRIld PRId32
  73 #elif TCG_TARGET_REG_BITS == 64
  74 typedef int64_t tcg_target_long;
  75 typedef uint64_t tcg_target_ulong;
  76 #define TCG_PRIlx PRIx64
  77 #define TCG_PRIld PRId64
  78 #else
  79 #error unsupported
  80 #endif
  81
  82 #if TCG_TARGET_NB_REGS <= 32
  83 typedef uint32_t TCGRegSet;
  84 #elif TCG_TARGET_NB_REGS <= 64
  85 typedef uint64_t TCGRegSet;
  86 #else
  87 #error unsupported
  88 #endif
  89
  90 #if TCG_TARGET_REG_BITS == 32
  91 /* Turn some undef macros into false macros.  */
  92 #define TCG_TARGET_HAS_extrl_i64_i32    0
  93 #define TCG_TARGET_HAS_extrh_i64_i32    0
  94 #define TCG_TARGET_HAS_div_i64          0
  95 #define TCG_TARGET_HAS_rem_i64          0
  96 #define TCG_TARGET_HAS_div2_i64         0
  97 #define TCG_TARGET_HAS_rot_i64          0
  98 #define TCG_TARGET_HAS_ext8s_i64        0
  99 #define TCG_TARGET_HAS_ext16s_i64       0
 100 #define TCG_TARGET_HAS_ext32s_i64       0
 101 #define TCG_TARGET_HAS_ext8u_i64        0
 102 #define TCG_TARGET_HAS_ext16u_i64       0
 103 #define TCG_TARGET_HAS_ext32u_i64       0
 104 #define TCG_TARGET_HAS_bswap16_i64      0
 105 #define TCG_TARGET_HAS_bswap32_i64      0
 106 #define TCG_TARGET_HAS_bswap64_i64      0
 107 #define TCG_TARGET_HAS_neg_i64          0
 108 #define TCG_TARGET_HAS_not_i64          0
 109 #define TCG_TARGET_HAS_andc_i64         0
 110 #define TCG_TARGET_HAS_orc_i64          0
 111 #define TCG_TARGET_HAS_eqv_i64          0
 112 #define TCG_TARGET_HAS_nand_i64         0
 113 #define TCG_TARGET_HAS_nor_i64          0
 114 #define TCG_TARGET_HAS_deposit_i64      0
 115 #define TCG_TARGET_HAS_movcond_i64      0
 116 #define TCG_TARGET_HAS_add2_i64         0
 117 #define TCG_TARGET_HAS_sub2_i64         0
 118 #define TCG_TARGET_HAS_mulu2_i64        0
 119 #define TCG_TARGET_HAS_muls2_i64        0
 120 #define TCG_TARGET_HAS_muluh_i64        0
 121 #define TCG_TARGET_HAS_mulsh_i64        0
 122 /* Turn some undef macros into true macros.  */
 123 #define TCG_TARGET_HAS_add2_i32         1
 124 #define TCG_TARGET_HAS_sub2_i32         1
 125 #endif
 126
 127 #ifndef TCG_TARGET_deposit_i32_valid
 128 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 129 #endif
 130 #ifndef TCG_TARGET_deposit_i64_valid
 131 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 132 #endif
 133
 134 /* Only one of DIV or DIV2 should be defined.  */
 135 #if defined(TCG_TARGET_HAS_div_i32)
 136 #define TCG_TARGET_HAS_div2_i32         0
 137 #elif defined(TCG_TARGET_HAS_div2_i32)
 138 #define TCG_TARGET_HAS_div_i32          0
 139 #define TCG_TARGET_HAS_rem_i32          0
 140 #endif
 141 #if defined(TCG_TARGET_HAS_div_i64)
 142 #define TCG_TARGET_HAS_div2_i64         0
 143 #elif defined(TCG_TARGET_HAS_div2_i64)
 144 #define TCG_TARGET_HAS_div_i64          0
 145 #define TCG_TARGET_HAS_rem_i64          0
 146 #endif
 147
 148 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 149 #if TCG_TARGET_REG_BITS == 32 \
 150     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 151          || defined(TCG_TARGET_HAS_muluh_i32))
 152 # error "Missing unsigned widening multiply"
 153 #endif
 154
 155 #ifndef TARGET_INSN_START_EXTRA_WORDS
 156 # define TARGET_INSN_START_WORDS 1
 157 #else
 158 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 159 #endif
 160
 161 typedef enum TCGOpcode {
 162 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 163 #include "tcg-opc.h"
 164 #undef DEF
 165     NB_OPS,
 166 } TCGOpcode;
 167
 168 #define tcg_regset_clear(d) (d) = 0
 169 #define tcg_regset_set(d, s) (d) = (s)
 170 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
 171 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
 172 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
 173 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
 174 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
 175 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
 176 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
 177 #define tcg_regset_not(d, a) (d) = ~(a)
 178
 179 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 180 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 181 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 182 typedef uint8_t tcg_insn_unit;
 183 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 184 typedef uint16_t tcg_insn_unit;
 185 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 186 typedef uint32_t tcg_insn_unit;
 187 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 188 typedef uint64_t tcg_insn_unit;
 189 #else
 190 /* The port better have done this.  */
 191 #endif
 192
 193
 194 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 195 # define tcg_debug_assert(X) do { assert(X); } while (0)
 196 #elif QEMU_GNUC_PREREQ(4, 5)
 197 # define tcg_debug_assert(X) \
 198     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 199 #else
 200 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 201 #endif
 202
 203 typedef struct TCGRelocation {
 204     struct TCGRelocation *next;
 205     int type;
 206     tcg_insn_unit *ptr;
 207     intptr_t addend;
 208 } TCGRelocation;
 209
 210 typedef struct TCGLabel {
 211     unsigned has_value : 1;
 212     unsigned id : 31;
 213     union {
 214         uintptr_t value;
 215         tcg_insn_unit *value_ptr;
 216         TCGRelocation *first_reloc;
 217     } u;
 218 } TCGLabel;
 219
 220 typedef struct TCGPool {
 221     struct TCGPool *next;
 222     int size;
 223     uint8_t data[0] __attribute__ ((aligned));
 224 } TCGPool;
 225
 226 #define TCG_POOL_CHUNK_SIZE 32768
 227
 228 #define TCG_MAX_TEMPS 512
 229 #define TCG_MAX_INSNS 512
 230
 231 /* when the size of the arguments of a called function is smaller than
 232    this value, they are statically allocated in the TB stack frame */
 233 #define TCG_STATIC_CALL_ARGS_SIZE 128
 234
 235 typedef enum TCGType {
 236     TCG_TYPE_I32,
 237     TCG_TYPE_I64,
 238     TCG_TYPE_COUNT, /* number of different types */
 239
 240     /* An alias for the size of the host register.  */
 241 #if TCG_TARGET_REG_BITS == 32
 242     TCG_TYPE_REG = TCG_TYPE_I32,
 243 #else
 244     TCG_TYPE_REG = TCG_TYPE_I64,
 245 #endif
 246
 247     /* An alias for the size of the native pointer.  */
 248 #if UINTPTR_MAX == UINT32_MAX
 249     TCG_TYPE_PTR = TCG_TYPE_I32,
 250 #else
 251     TCG_TYPE_PTR = TCG_TYPE_I64,
 252 #endif
 253
 254     /* An alias for the size of the target "long", aka register.  */
 255 #if TARGET_LONG_BITS == 64
 256     TCG_TYPE_TL = TCG_TYPE_I64,
 257 #else
 258     TCG_TYPE_TL = TCG_TYPE_I32,
 259 #endif
 260 } TCGType;
 261
 262 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 263 typedef enum TCGMemOp {
 264     MO_8     = 0,
 265     MO_16    = 1,
 266     MO_32    = 2,
 267     MO_64    = 3,
 268     MO_SIZE  = 3,   /* Mask for the above.  */
 269
 270     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 271
 272     MO_BSWAP = 8,   /* Host reverse endian.  */
 273 #ifdef HOST_WORDS_BIGENDIAN
 274     MO_LE    = MO_BSWAP,
 275     MO_BE    = 0,
 276 #else
 277     MO_LE    = 0,
 278     MO_BE    = MO_BSWAP,
 279 #endif
 280 #ifdef TARGET_WORDS_BIGENDIAN
 281     MO_TE    = MO_BE,
 282 #else
 283     MO_TE    = MO_LE,
 284 #endif
 285
 286     /* MO_UNALN accesses are never checked for alignment.
 287      * MO_ALIGN accesses will result in a call to the CPU's
 288      * do_unaligned_access hook if the guest address is not aligned.
 289      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 290      *
 291      * Some architectures (e.g. ARMv8) need the address which is aligned
 292      * to a size more than the size of the memory access.
 293      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 294      * but less strictly than the natural alignment.
 295      *
 296      * MO_ALIGN supposes the alignment size is the size of a memory access.
 297      *
 298      * There are three options:
 299      * - unaligned access permitted (MO_UNALN).
 300      * - an alignment to the size of an access (MO_ALIGN);
 301      * - an alignment to a specified size, which may be more or less than
 302      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 303      */
 304     MO_ASHIFT = 4,
 305     MO_AMASK = 7 << MO_ASHIFT,
 306 #ifdef ALIGNED_ONLY
 307     MO_ALIGN = 0,
 308     MO_UNALN = MO_AMASK,
 309 #else
 310     MO_ALIGN = MO_AMASK,
 311     MO_UNALN = 0,
 312 #endif
 313     MO_ALIGN_2  = 1 << MO_ASHIFT,
 314     MO_ALIGN_4  = 2 << MO_ASHIFT,
 315     MO_ALIGN_8  = 3 << MO_ASHIFT,
 316     MO_ALIGN_16 = 4 << MO_ASHIFT,
 317     MO_ALIGN_32 = 5 << MO_ASHIFT,
 318     MO_ALIGN_64 = 6 << MO_ASHIFT,
 319
 320     /* Combinations of the above, for ease of use.  */
 321     MO_UB    = MO_8,
 322     MO_UW    = MO_16,
 323     MO_UL    = MO_32,
 324     MO_SB    = MO_SIGN | MO_8,
 325     MO_SW    = MO_SIGN | MO_16,
 326     MO_SL    = MO_SIGN | MO_32,
 327     MO_Q     = MO_64,
 328
 329     MO_LEUW  = MO_LE | MO_UW,
 330     MO_LEUL  = MO_LE | MO_UL,
 331     MO_LESW  = MO_LE | MO_SW,
 332     MO_LESL  = MO_LE | MO_SL,
 333     MO_LEQ   = MO_LE | MO_Q,
 334
 335     MO_BEUW  = MO_BE | MO_UW,
 336     MO_BEUL  = MO_BE | MO_UL,
 337     MO_BESW  = MO_BE | MO_SW,
 338     MO_BESL  = MO_BE | MO_SL,
 339     MO_BEQ   = MO_BE | MO_Q,
 340
 341     MO_TEUW  = MO_TE | MO_UW,
 342     MO_TEUL  = MO_TE | MO_UL,
 343     MO_TESW  = MO_TE | MO_SW,
 344     MO_TESL  = MO_TE | MO_SL,
 345     MO_TEQ   = MO_TE | MO_Q,
 346
 347     MO_SSIZE = MO_SIZE | MO_SIGN,
 348 } TCGMemOp;
 349
 350 /**
 351  * get_alignment_bits
 352  * @memop: TCGMemOp value
 353  *
 354  * Extract the alignment size from the memop.
 355  */
 356 static inline unsigned get_alignment_bits(TCGMemOp memop)
 357 {
 358     unsigned a = memop & MO_AMASK;
 359
 360     if (a == MO_UNALN) {
 361         /* No alignment required.  */
 362         a = 0;
 363     } else if (a == MO_ALIGN) {
 364         /* A natural alignment requirement.  */
 365         a = memop & MO_SIZE;
 366     } else {
 367         /* A specific alignment requirement.  */
 368         a = a >> MO_ASHIFT;
 369     }
 370 #if defined(CONFIG_SOFTMMU)
 371     /* The requested alignment cannot overlap the TLB flags.  */
 372     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 373 #endif
 374     return a;
 375 }
 376
 377 typedef tcg_target_ulong TCGArg;
 378
 379 /* Define a type and accessor macros for variables.  Using pointer types
 380    is nice because it gives some level of type safely.  Converting to and
 381    from intptr_t rather than int reduces the number of sign-extension
 382    instructions that get implied on 64-bit hosts.  Users of tcg_gen_* don't
 383    need to know about any of this, and should treat TCGv as an opaque type.
 384    In addition we do typechecking for different types of variables.  TCGv_i32
 385    and TCGv_i64 are 32/64-bit variables respectively.  TCGv and TCGv_ptr
 386    are aliases for target_ulong and host pointer sized values respectively.  */
 387
 388 typedef struct TCGv_i32_d *TCGv_i32;
 389 typedef struct TCGv_i64_d *TCGv_i64;
 390 typedef struct TCGv_ptr_d *TCGv_ptr;
 391 typedef TCGv_ptr TCGv_env;
 392 #if TARGET_LONG_BITS == 32
 393 #define TCGv TCGv_i32
 394 #elif TARGET_LONG_BITS == 64
 395 #define TCGv TCGv_i64
 396 #else
 397 #error Unhandled TARGET_LONG_BITS value
 398 #endif
 399
 400 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 401 {
 402     return (TCGv_i32)i;
 403 }
 404
 405 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 406 {
 407     return (TCGv_i64)i;
 408 }
 409
 410 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 411 {
 412     return (TCGv_ptr)i;
 413 }
 414
 415 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 416 {
 417     return (intptr_t)t;
 418 }
 419
 420 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 421 {
 422     return (intptr_t)t;
 423 }
 424
 425 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 426 {
 427     return (intptr_t)t;
 428 }
 429
 430 #if TCG_TARGET_REG_BITS == 32
 431 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 432 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 433 #endif
 434
 435 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 436 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 437 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 438
 439 /* Dummy definition to avoid compiler warnings.  */
 440 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 441 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 442 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 443
 444 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 445 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 446 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 447
 448 /* call flags */
 449 /* Helper does not read globals (either directly or through an exception). It
 450    implies TCG_CALL_NO_WRITE_GLOBALS. */
 451 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 452 /* Helper does not write globals */
 453 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 454 /* Helper can be safely suppressed if the return value is not used. */
 455 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 456
 457 /* convenience version of most used call flags */
 458 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 459 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 460 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 461 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 462 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 463
 464 /* used to align parameters */
 465 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 466 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 467
 468 typedef enum {
 469     /* Used to indicate the type of accesses on which ordering
 470        is to be ensured.  Modeled after SPARC barriers.  */
 471     TCG_MO_LD_LD  = 0x01,
 472     TCG_MO_ST_LD  = 0x02,
 473     TCG_MO_LD_ST  = 0x04,
 474     TCG_MO_ST_ST  = 0x08,
 475     TCG_MO_ALL    = 0x0F,  /* OR of the above */
 476
 477     /* Used to indicate the kind of ordering which is to be ensured by the
 478        instruction.  These types are derived from x86/aarch64 instructions.
 479        It should be noted that these are different from C11 semantics.  */
 480     TCG_BAR_LDAQ  = 0x10,  /* Following ops will not come forward */
 481     TCG_BAR_STRL  = 0x20,  /* Previous ops will not be delayed */
 482     TCG_BAR_SC    = 0x30,  /* No ops cross barrier; OR of the above */
 483 } TCGBar;
 484
 485 /* Conditions.  Note that these are laid out for easy manipulation by
 486    the functions below:
 487      bit 0 is used for inverting;
 488      bit 1 is signed,
 489      bit 2 is unsigned,
 490      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 491 typedef enum {
 492     /* non-signed */
 493     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 494     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 495     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 496     TCG_COND_NE     = 8 | 0 | 0 | 1,
 497     /* signed */
 498     TCG_COND_LT     = 0 | 0 | 2 | 0,
 499     TCG_COND_GE     = 0 | 0 | 2 | 1,
 500     TCG_COND_LE     = 8 | 0 | 2 | 0,
 501     TCG_COND_GT     = 8 | 0 | 2 | 1,
 502     /* unsigned */
 503     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 504     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 505     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 506     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 507 } TCGCond;
 508
 509 /* Invert the sense of the comparison.  */
 510 static inline TCGCond tcg_invert_cond(TCGCond c)
 511 {
 512     return (TCGCond)(c ^ 1);
 513 }
 514
 515 /* Swap the operands in a comparison.  */
 516 static inline TCGCond tcg_swap_cond(TCGCond c)
 517 {
 518     return c & 6 ? (TCGCond)(c ^ 9) : c;
 519 }
 520
 521 /* Create an "unsigned" version of a "signed" comparison.  */
 522 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 523 {
 524     return c & 2 ? (TCGCond)(c ^ 6) : c;
 525 }
 526
 527 /* Must a comparison be considered unsigned?  */
 528 static inline bool is_unsigned_cond(TCGCond c)
 529 {
 530     return (c & 4) != 0;
 531 }
 532
 533 /* Create a "high" version of a double-word comparison.
 534    This removes equality from a LTE or GTE comparison.  */
 535 static inline TCGCond tcg_high_cond(TCGCond c)
 536 {
 537     switch (c) {
 538     case TCG_COND_GE:
 539     case TCG_COND_LE:
 540     case TCG_COND_GEU:
 541     case TCG_COND_LEU:
 542         return (TCGCond)(c ^ 8);
 543     default:
 544         return c;
 545     }
 546 }
 547
 548 typedef enum TCGTempVal {
 549     TEMP_VAL_DEAD,
 550     TEMP_VAL_REG,
 551     TEMP_VAL_MEM,
 552     TEMP_VAL_CONST,
 553 } TCGTempVal;
 554
 555 typedef struct TCGTemp {
 556     TCGReg reg:8;
 557     TCGTempVal val_type:8;
 558     TCGType base_type:8;
 559     TCGType type:8;
 560     unsigned int fixed_reg:1;
 561     unsigned int indirect_reg:1;
 562     unsigned int indirect_base:1;
 563     unsigned int mem_coherent:1;
 564     unsigned int mem_allocated:1;
 565     unsigned int temp_local:1; /* If true, the temp is saved across
 566                                   basic blocks. Otherwise, it is not
 567                                   preserved across basic blocks. */
 568     unsigned int temp_allocated:1; /* never used for code gen */
 569
 570     tcg_target_long val;
 571     struct TCGTemp *mem_base;
 572     intptr_t mem_offset;
 573     const char *name;
 574 } TCGTemp;
 575
 576 typedef struct TCGContext TCGContext;
 577
 578 typedef struct TCGTempSet {
 579     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 580 } TCGTempSet;
 581
 582 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 583    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 584    There are never more than 2 outputs, which means that we can store all
 585    dead + sync data within 16 bits.  */
 586 #define DEAD_ARG  4
 587 #define SYNC_ARG  1
 588 typedef uint16_t TCGLifeData;
 589
 590 /* The layout here is designed to avoid crossing of a 32-bit boundary.
 591    If we do so, gcc adds padding, expanding the size to 12.  */
 592 typedef struct TCGOp {
 593     TCGOpcode opc   : 8;        /*  8 */
 594
 595     /* Index of the prev/next op, or 0 for the end of the list.  */
 596     unsigned prev   : 10;       /* 18 */
 597     unsigned next   : 10;       /* 28 */
 598
 599     /* The number of out and in parameter for a call.  */
 600     unsigned calli  : 4;        /* 32 */
 601     unsigned callo  : 2;        /* 34 */
 602
 603     /* Index of the arguments for this op, or 0 for zero-operand ops.  */
 604     unsigned args   : 14;       /* 48 */
 605
 606     /* Lifetime data of the operands.  */
 607     unsigned life   : 16;       /* 64 */
 608 } TCGOp;
 609
 610 /* Make sure operands fit in the bitfields above.  */
 611 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 612 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10));
 613 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));
 614
 615 /* Make sure that we don't overflow 64 bits without noticing.  */
 616 QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
 617
 618 struct TCGContext {
 619     uint8_t *pool_cur, *pool_end;
 620     TCGPool *pool_first, *pool_current, *pool_first_large;
 621     int nb_labels;
 622     int nb_globals;
 623     int nb_temps;
 624     int nb_indirects;
 625
 626     /* goto_tb support */
 627     tcg_insn_unit *code_buf;
 628     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 629     uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */
 630     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */
 631
 632     TCGRegSet reserved_regs;
 633     intptr_t current_frame_offset;
 634     intptr_t frame_start;
 635     intptr_t frame_end;
 636     TCGTemp *frame_temp;
 637
 638     tcg_insn_unit *code_ptr;
 639
 640     GHashTable *helpers;
 641
 642 #ifdef CONFIG_PROFILER
 643     /* profiling info */
 644     int64_t tb_count1;
 645     int64_t tb_count;
 646     int64_t op_count; /* total insn count */
 647     int op_count_max; /* max insn per TB */
 648     int64_t temp_count;
 649     int temp_count_max;
 650     int64_t del_op_count;
 651     int64_t code_in_len;
 652     int64_t code_out_len;
 653     int64_t search_out_len;
 654     int64_t interm_time;
 655     int64_t code_time;
 656     int64_t la_time;
 657     int64_t opt_time;
 658     int64_t restore_count;
 659     int64_t restore_time;
 660 #endif
 661
 662 #ifdef CONFIG_DEBUG_TCG
 663     int temps_in_use;
 664     int goto_tb_issue_mask;
 665 #endif
 666
 667     int gen_next_op_idx;
 668     int gen_next_parm_idx;
 669
 670     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 671        here, because there's too much arithmetic throughout that relies
 672        on addition and subtraction working on bytes.  Rely on the GCC
 673        extension that allows arithmetic on void*.  */
 674     int code_gen_max_blocks;
 675     void *code_gen_prologue;
 676     void *code_gen_buffer;
 677     size_t code_gen_buffer_size;
 678     void *code_gen_ptr;
 679
 680     /* Threshold to flush the translated code buffer.  */
 681     void *code_gen_highwater;
 682
 683     TBContext tb_ctx;
 684
 685     /* Track which vCPU triggers events */
 686     CPUState *cpu;                      /* *_trans */
 687     TCGv_env tcg_env;                   /* *_exec  */
 688
 689     /* The TCGBackendData structure is private to tcg-target.inc.c.  */
 690     struct TCGBackendData *be;
 691
 692     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 693     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 694
 695     /* Tells which temporary holds a given register.
 696        It does not take into account fixed registers */
 697     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 698
 699     TCGOp gen_op_buf[OPC_BUF_SIZE];
 700     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 701
 702     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 703     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 704 };
 705
 706 extern TCGContext tcg_ctx;
 707 extern bool parallel_cpus;
 708
 709 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
 710 {
 711     int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
 712     tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
 713 }
 714
 715 /* The number of opcodes emitted so far.  */
 716 static inline int tcg_op_buf_count(void)
 717 {
 718     return tcg_ctx.gen_next_op_idx;
 719 }
 720
 721 /* Test for whether to terminate the TB for using too many opcodes.  */
 722 static inline bool tcg_op_buf_full(void)
 723 {
 724     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 725 }
 726
 727 /* pool based memory allocation */
 728
 729 void *tcg_malloc_internal(TCGContext *s, int size);
 730 void tcg_pool_reset(TCGContext *s);
 731
 732 void tb_lock(void);
 733 void tb_unlock(void);
 734 void tb_lock_reset(void);
 735
 736 static inline void *tcg_malloc(int size)
 737 {
 738     TCGContext *s = &tcg_ctx;
 739     uint8_t *ptr, *ptr_end;
 740     size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
 741     ptr = s->pool_cur;
 742     ptr_end = ptr + size;
 743     if (unlikely(ptr_end > s->pool_end)) {
 744         return tcg_malloc_internal(&tcg_ctx, size);
 745     } else {
 746         s->pool_cur = ptr_end;
 747         return ptr;
 748     }
 749 }
 750
 751 void tcg_context_init(TCGContext *s);
 752 void tcg_prologue_init(TCGContext *s);
 753 void tcg_func_start(TCGContext *s);
 754
 755 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 756
 757 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 758
 759 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
 760
 761 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
 762 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
 763
 764 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 765 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 766
 767 void tcg_temp_free_i32(TCGv_i32 arg);
 768 void tcg_temp_free_i64(TCGv_i64 arg);
 769
 770 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 771                                               const char *name)
 772 {
 773     int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 774     return MAKE_TCGV_I32(idx);
 775 }
 776
 777 static inline TCGv_i32 tcg_temp_new_i32(void)
 778 {
 779     return tcg_temp_new_internal_i32(0);
 780 }
 781
 782 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 783 {
 784     return tcg_temp_new_internal_i32(1);
 785 }
 786
 787 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 788                                               const char *name)
 789 {
 790     int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 791     return MAKE_TCGV_I64(idx);
 792 }
 793
 794 static inline TCGv_i64 tcg_temp_new_i64(void)
 795 {
 796     return tcg_temp_new_internal_i64(0);
 797 }
 798
 799 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 800 {
 801     return tcg_temp_new_internal_i64(1);
 802 }
 803
 804 #if defined(CONFIG_DEBUG_TCG)
 805 /* If you call tcg_clear_temp_count() at the start of a section of
 806  * code which is not supposed to leak any TCG temporaries, then
 807  * calling tcg_check_temp_count() at the end of the section will
 808  * return 1 if the section did in fact leak a temporary.
 809  */
 810 void tcg_clear_temp_count(void);
 811 int tcg_check_temp_count(void);
 812 #else
 813 #define tcg_clear_temp_count() do { } while (0)
 814 #define tcg_check_temp_count() 0
 815 #endif
 816
 817 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 818 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 819
 820 #define TCG_CT_ALIAS  0x80
 821 #define TCG_CT_IALIAS 0x40
 822 #define TCG_CT_REG    0x01
 823 #define TCG_CT_CONST  0x02 /* any constant of register size */
 824
 825 typedef struct TCGArgConstraint {
 826     uint16_t ct;
 827     uint8_t alias_index;
 828     union {
 829         TCGRegSet regs;
 830     } u;
 831 } TCGArgConstraint;
 832
 833 #define TCG_MAX_OP_ARGS 16
 834
 835 /* Bits for TCGOpDef->flags, 8 bits available.  */
 836 enum {
 837     /* Instruction defines the end of a basic block.  */
 838     TCG_OPF_BB_END       = 0x01,
 839     /* Instruction clobbers call registers and potentially update globals.  */
 840     TCG_OPF_CALL_CLOBBER = 0x02,
 841     /* Instruction has side effects: it cannot be removed if its outputs
 842        are not used, and might trigger exceptions.  */
 843     TCG_OPF_SIDE_EFFECTS = 0x04,
 844     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 845     TCG_OPF_64BIT        = 0x08,
 846     /* Instruction is optional and not implemented by the host, or insn
 847        is generic and should not be implemened by the host.  */
 848     TCG_OPF_NOT_PRESENT  = 0x10,
 849 };
 850
 851 typedef struct TCGOpDef {
 852     const char *name;
 853     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 854     uint8_t flags;
 855     TCGArgConstraint *args_ct;
 856     int *sorted_args;
 857 #if defined(CONFIG_DEBUG_TCG)
 858     int used;
 859 #endif
 860 } TCGOpDef;
 861
 862 extern TCGOpDef tcg_op_defs[];
 863 extern const size_t tcg_op_defs_max;
 864
 865 typedef struct TCGTargetOpDef {
 866     TCGOpcode op;
 867     const char *args_ct_str[TCG_MAX_OP_ARGS];
 868 } TCGTargetOpDef;
 869
 870 #define tcg_abort() \
 871 do {\
 872     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 873     abort();\
 874 } while (0)
 875
 876 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
 877
 878 #if UINTPTR_MAX == UINT32_MAX
 879 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 880 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 881
 882 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 883 #define tcg_global_reg_new_ptr(R, N) \
 884     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 885 #define tcg_global_mem_new_ptr(R, O, N) \
 886     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 887 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 888 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 889 #else
 890 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 891 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 892
 893 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 894 #define tcg_global_reg_new_ptr(R, N) \
 895     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 896 #define tcg_global_mem_new_ptr(R, O, N) \
 897     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 898 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 899 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 900 #endif
 901
 902 void tcg_gen_callN(TCGContext *s, void *func,
 903                    TCGArg ret, int nargs, TCGArg *args);
 904
 905 void tcg_op_remove(TCGContext *s, TCGOp *op);
 906 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 907 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 908
 909 void tcg_optimize(TCGContext *s);
 910
 911 /* only used for debugging purposes */
 912 void tcg_dump_ops(TCGContext *s);
 913
 914 TCGv_i32 tcg_const_i32(int32_t val);
 915 TCGv_i64 tcg_const_i64(int64_t val);
 916 TCGv_i32 tcg_const_local_i32(int32_t val);
 917 TCGv_i64 tcg_const_local_i64(int64_t val);
 918
 919 TCGLabel *gen_new_label(void);
 920
 921 /**
 922  * label_arg
 923  * @l: label
 924  *
 925  * Encode a label for storage in the TCG opcode stream.
 926  */
 927
 928 static inline TCGArg label_arg(TCGLabel *l)
 929 {
 930     return (uintptr_t)l;
 931 }
 932
 933 /**
 934  * arg_label
 935  * @i: value
 936  *
 937  * The opposite of label_arg.  Retrieve a label from the
 938  * encoding of the TCG opcode stream.
 939  */
 940
 941 static inline TCGLabel *arg_label(TCGArg i)
 942 {
 943     return (TCGLabel *)(uintptr_t)i;
 944 }
 945
 946 /**
 947  * tcg_ptr_byte_diff
 948  * @a, @b: addresses to be differenced
 949  *
 950  * There are many places within the TCG backends where we need a byte
 951  * difference between two pointers.  While this can be accomplished
 952  * with local casting, it's easy to get wrong -- especially if one is
 953  * concerned with the signedness of the result.
 954  *
 955  * This version relies on GCC's void pointer arithmetic to get the
 956  * correct result.
 957  */
 958
 959 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 960 {
 961     return a - b;
 962 }
 963
 964 /**
 965  * tcg_pcrel_diff
 966  * @s: the tcg context
 967  * @target: address of the target
 968  *
 969  * Produce a pc-relative difference, from the current code_ptr
 970  * to the destination address.
 971  */
 972
 973 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
 974 {
 975     return tcg_ptr_byte_diff(target, s->code_ptr);
 976 }
 977
 978 /**
 979  * tcg_current_code_size
 980  * @s: the tcg context
 981  *
 982  * Compute the current code size within the translation block.
 983  * This is used to fill in qemu's data structures for goto_tb.
 984  */
 985
 986 static inline size_t tcg_current_code_size(TCGContext *s)
 987 {
 988     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
 989 }
 990
 991 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
 992 typedef uint32_t TCGMemOpIdx;
 993
 994 /**
 995  * make_memop_idx
 996  * @op: memory operation
 997  * @idx: mmu index
 998  *
 999  * Encode these values into a single parameter.
1000  */
1001 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1002 {
1003     tcg_debug_assert(idx <= 15);
1004     return (op << 4) | idx;
1005 }
1006
1007 /**
1008  * get_memop
1009  * @oi: combined op/idx parameter
1010  *
1011  * Extract the memory operation from the combined value.
1012  */
1013 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1014 {
1015     return oi >> 4;
1016 }
1017
1018 /**
1019  * get_mmuidx
1020  * @oi: combined op/idx parameter
1021  *
1022  * Extract the mmu index from the combined value.
1023  */
1024 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1025 {
1026     return oi & 15;
1027 }
1028
1029 /**
1030  * tcg_qemu_tb_exec:
1031  * @env: pointer to CPUArchState for the CPU
1032  * @tb_ptr: address of generated code for the TB to execute
1033  *
1034  * Start executing code from a given translation block.
1035  * Where translation blocks have been linked, execution
1036  * may proceed from the given TB into successive ones.
1037  * Control eventually returns only when some action is needed
1038  * from the top-level loop: either control must pass to a TB
1039  * which has not yet been directly linked, or an asynchronous
1040  * event such as an interrupt needs handling.
1041  *
1042  * Return: The return value is the value passed to the corresponding
1043  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1044  * The value is either zero or a 4-byte aligned pointer to that TB combined
1045  * with additional information in its two least significant bits. The
1046  * additional information is encoded as follows:
1047  *  0, 1: the link between this TB and the next is via the specified
1048  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1049  *        of) "goto_tb <index>". The main loop uses this to determine
1050  *        how to link the TB just executed to the next.
1051  *  2:    we are using instruction counting code generation, and we
1052  *        did not start executing this TB because the instruction counter
1053  *        would hit zero midway through it. In this case the pointer
1054  *        returned is the TB we were about to execute, and the caller must
1055  *        arrange to execute the remaining count of instructions.
1056  *  3:    we stopped because the CPU's exit_request flag was set
1057  *        (usually meaning that there is an interrupt that needs to be
1058  *        handled). The pointer returned is the TB we were about to execute
1059  *        when we noticed the pending exit request.
1060  *
1061  * If the bottom two bits indicate an exit-via-index then the CPU
1062  * state is correctly synchronised and ready for execution of the next
1063  * TB (and in particular the guest PC is the address to execute next).
1064  * Otherwise, we gave up on execution of this TB before it started, and
1065  * the caller must fix up the CPU state by calling the CPU's
1066  * synchronize_from_tb() method with the TB pointer we return (falling
1067  * back to calling the CPU's set_pc method with tb->pb if no
1068  * synchronize_from_tb() method exists).
1069  *
1070  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1071  * to this default (which just calls the prologue.code emitted by
1072  * tcg_target_qemu_prologue()).
1073  */
1074 #define TB_EXIT_MASK 3
1075 #define TB_EXIT_IDX0 0
1076 #define TB_EXIT_IDX1 1
1077 #define TB_EXIT_ICOUNT_EXPIRED 2
1078 #define TB_EXIT_REQUESTED 3
1079
1080 #ifdef HAVE_TCG_QEMU_TB_EXEC
1081 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1082 #else
1083 # define tcg_qemu_tb_exec(env, tb_ptr) \
1084     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1085 #endif
1086
1087 void tcg_register_jit(void *buf, size_t buf_size);
1088
1089 /*
1090  * Memory helpers that will be used by TCG generated code.
1091  */
1092 #ifdef CONFIG_SOFTMMU
1093 /* Value zero-extended to tcg register size.  */
1094 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1095                                      TCGMemOpIdx oi, uintptr_t retaddr);
1096 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1097                                     TCGMemOpIdx oi, uintptr_t retaddr);
1098 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1099                                     TCGMemOpIdx oi, uintptr_t retaddr);
1100 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1101                            TCGMemOpIdx oi, uintptr_t retaddr);
1102 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1103                                     TCGMemOpIdx oi, uintptr_t retaddr);
1104 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1105                                     TCGMemOpIdx oi, uintptr_t retaddr);
1106 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1107                            TCGMemOpIdx oi, uintptr_t retaddr);
1108
1109 /* Value sign-extended to tcg register size.  */
1110 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1111                                      TCGMemOpIdx oi, uintptr_t retaddr);
1112 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1113                                     TCGMemOpIdx oi, uintptr_t retaddr);
1114 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1115                                     TCGMemOpIdx oi, uintptr_t retaddr);
1116 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1117                                     TCGMemOpIdx oi, uintptr_t retaddr);
1118 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1119                                     TCGMemOpIdx oi, uintptr_t retaddr);
1120
1121 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1122                         TCGMemOpIdx oi, uintptr_t retaddr);
1123 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1124                        TCGMemOpIdx oi, uintptr_t retaddr);
1125 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1126                        TCGMemOpIdx oi, uintptr_t retaddr);
1127 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1128                        TCGMemOpIdx oi, uintptr_t retaddr);
1129 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1130                        TCGMemOpIdx oi, uintptr_t retaddr);
1131 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1132                        TCGMemOpIdx oi, uintptr_t retaddr);
1133 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1134                        TCGMemOpIdx oi, uintptr_t retaddr);
1135
1136 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1137                             TCGMemOpIdx oi, uintptr_t retaddr);
1138 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1139                             TCGMemOpIdx oi, uintptr_t retaddr);
1140 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1141                             TCGMemOpIdx oi, uintptr_t retaddr);
1142 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1143                             TCGMemOpIdx oi, uintptr_t retaddr);
1144 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1145                             TCGMemOpIdx oi, uintptr_t retaddr);
1146 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1147                             TCGMemOpIdx oi, uintptr_t retaddr);
1148 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1149                             TCGMemOpIdx oi, uintptr_t retaddr);
1150
1151 /* Temporary aliases until backends are converted.  */
1152 #ifdef TARGET_WORDS_BIGENDIAN
1153 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1154 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1155 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1156 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1157 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1158 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1159 # define helper_ret_stw_mmu   helper_be_stw_mmu
1160 # define helper_ret_stl_mmu   helper_be_stl_mmu
1161 # define helper_ret_stq_mmu   helper_be_stq_mmu
1162 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1163 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1164 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1165 #else
1166 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1167 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1168 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1169 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1170 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1171 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1172 # define helper_ret_stw_mmu   helper_le_stw_mmu
1173 # define helper_ret_stl_mmu   helper_le_stl_mmu
1174 # define helper_ret_stq_mmu   helper_le_stq_mmu
1175 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1176 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1177 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1178 #endif
1179
1180 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1181                                     uint32_t cmpv, uint32_t newv,
1182                                     TCGMemOpIdx oi, uintptr_t retaddr);
1183 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1184                                        uint32_t cmpv, uint32_t newv,
1185                                        TCGMemOpIdx oi, uintptr_t retaddr);
1186 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1187                                        uint32_t cmpv, uint32_t newv,
1188                                        TCGMemOpIdx oi, uintptr_t retaddr);
1189 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1190                                        uint64_t cmpv, uint64_t newv,
1191                                        TCGMemOpIdx oi, uintptr_t retaddr);
1192 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1193                                        uint32_t cmpv, uint32_t newv,
1194                                        TCGMemOpIdx oi, uintptr_t retaddr);
1195 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1196                                        uint32_t cmpv, uint32_t newv,
1197                                        TCGMemOpIdx oi, uintptr_t retaddr);
1198 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1199                                        uint64_t cmpv, uint64_t newv,
1200                                        TCGMemOpIdx oi, uintptr_t retaddr);
1201
1202 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1203 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1204     (CPUArchState *env, target_ulong addr, TYPE val,  \
1205      TCGMemOpIdx oi, uintptr_t retaddr);
1206
1207 #ifdef CONFIG_ATOMIC64
1208 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1209     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1210     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1211     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1212     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1213     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1214     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1215     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1216 #else
1217 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1218     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1219     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1220     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1221     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1222     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1223 #endif
1224
1225 GEN_ATOMIC_HELPER_ALL(fetch_add)
1226 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1227 GEN_ATOMIC_HELPER_ALL(fetch_and)
1228 GEN_ATOMIC_HELPER_ALL(fetch_or)
1229 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1230
1231 GEN_ATOMIC_HELPER_ALL(add_fetch)
1232 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1233 GEN_ATOMIC_HELPER_ALL(and_fetch)
1234 GEN_ATOMIC_HELPER_ALL(or_fetch)
1235 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1236
1237 GEN_ATOMIC_HELPER_ALL(xchg)
1238
1239 #undef GEN_ATOMIC_HELPER_ALL
1240 #undef GEN_ATOMIC_HELPER
1241 #endif /* CONFIG_SOFTMMU */
1242
1243 #ifdef CONFIG_ATOMIC128
1244 #include "qemu/int128.h"
1245
1246 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1247    However, use the same format as the others, for use by the backends. */
1248 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1249                                      Int128 cmpv, Int128 newv,
1250                                      TCGMemOpIdx oi, uintptr_t retaddr);
1251 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1252                                      Int128 cmpv, Int128 newv,
1253                                      TCGMemOpIdx oi, uintptr_t retaddr);
1254
1255 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1256                                 TCGMemOpIdx oi, uintptr_t retaddr);
1257 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1258                                 TCGMemOpIdx oi, uintptr_t retaddr);
1259 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1260                               TCGMemOpIdx oi, uintptr_t retaddr);
1261 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1262                               TCGMemOpIdx oi, uintptr_t retaddr);
1263
1264 #endif /* CONFIG_ATOMIC128 */
1265
1266 #endif /* TCG_H */