4 * Altivec/VMX translation
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr
gen_avr_ptr(int reg
)
12 TCGv_ptr r
= tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
21 if (unlikely(!ctx->altivec_enabled)) { \
22 gen_exception(ctx, POWERPC_EXCP_VPU); \
25 gen_set_access_type(ctx, ACCESS_INT); \
26 EA = tcg_temp_new(); \
27 gen_addr_reg_index(ctx, EA); \
28 tcg_gen_andi_tl(EA, EA, ~0xf); \
29 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
30 necessary 64-bit byteswap already. */ \
32 gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
33 tcg_gen_addi_tl(EA, EA, 8); \
34 gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
36 gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
37 tcg_gen_addi_tl(EA, EA, 8); \
38 gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
43 #define GEN_VR_STX(name, opc2, opc3) \
44 static void gen_st##name(DisasContext *ctx) \
47 if (unlikely(!ctx->altivec_enabled)) { \
48 gen_exception(ctx, POWERPC_EXCP_VPU); \
51 gen_set_access_type(ctx, ACCESS_INT); \
52 EA = tcg_temp_new(); \
53 gen_addr_reg_index(ctx, EA); \
54 tcg_gen_andi_tl(EA, EA, ~0xf); \
55 /* We only need to swap high and low halves. gen_qemu_st64_i64 does \
56 necessary 64-bit byteswap already. */ \
58 gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
59 tcg_gen_addi_tl(EA, EA, 8); \
60 gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
62 gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
63 tcg_gen_addi_tl(EA, EA, 8); \
64 gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
69 #define GEN_VR_LVE(name, opc2, opc3, size) \
70 static void gen_lve##name(DisasContext *ctx) \
74 if (unlikely(!ctx->altivec_enabled)) { \
75 gen_exception(ctx, POWERPC_EXCP_VPU); \
78 gen_set_access_type(ctx, ACCESS_INT); \
79 EA = tcg_temp_new(); \
80 gen_addr_reg_index(ctx, EA); \
82 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
84 rs = gen_avr_ptr(rS(ctx->opcode)); \
85 gen_helper_lve##name(cpu_env, rs, EA); \
87 tcg_temp_free_ptr(rs); \
90 #define GEN_VR_STVE(name, opc2, opc3, size) \
91 static void gen_stve##name(DisasContext *ctx) \
95 if (unlikely(!ctx->altivec_enabled)) { \
96 gen_exception(ctx, POWERPC_EXCP_VPU); \
99 gen_set_access_type(ctx, ACCESS_INT); \
100 EA = tcg_temp_new(); \
101 gen_addr_reg_index(ctx, EA); \
103 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
105 rs = gen_avr_ptr(rS(ctx->opcode)); \
106 gen_helper_stve##name(cpu_env, rs, EA); \
108 tcg_temp_free_ptr(rs); \
111 GEN_VR_LDX(lvx
, 0x07, 0x03);
112 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
113 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
115 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
116 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
117 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
119 GEN_VR_STX(svx
, 0x07, 0x07);
120 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
121 GEN_VR_STX(svxl
, 0x07, 0x0F);
123 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
124 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
125 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
127 static void gen_lvsl(DisasContext
*ctx
)
131 if (unlikely(!ctx
->altivec_enabled
)) {
132 gen_exception(ctx
, POWERPC_EXCP_VPU
);
136 gen_addr_reg_index(ctx
, EA
);
137 rd
= gen_avr_ptr(rD(ctx
->opcode
));
138 gen_helper_lvsl(rd
, EA
);
140 tcg_temp_free_ptr(rd
);
143 static void gen_lvsr(DisasContext
*ctx
)
147 if (unlikely(!ctx
->altivec_enabled
)) {
148 gen_exception(ctx
, POWERPC_EXCP_VPU
);
152 gen_addr_reg_index(ctx
, EA
);
153 rd
= gen_avr_ptr(rD(ctx
->opcode
));
154 gen_helper_lvsr(rd
, EA
);
156 tcg_temp_free_ptr(rd
);
159 static void gen_mfvscr(DisasContext
*ctx
)
162 if (unlikely(!ctx
->altivec_enabled
)) {
163 gen_exception(ctx
, POWERPC_EXCP_VPU
);
166 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
167 t
= tcg_temp_new_i32();
168 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
169 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
170 tcg_temp_free_i32(t
);
173 static void gen_mtvscr(DisasContext
*ctx
)
176 if (unlikely(!ctx
->altivec_enabled
)) {
177 gen_exception(ctx
, POWERPC_EXCP_VPU
);
180 p
= gen_avr_ptr(rB(ctx
->opcode
));
181 gen_helper_mtvscr(cpu_env
, p
);
182 tcg_temp_free_ptr(p
);
185 /* Logical operations */
186 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
187 static void glue(gen_, name)(DisasContext *ctx) \
189 if (unlikely(!ctx->altivec_enabled)) { \
190 gen_exception(ctx, POWERPC_EXCP_VPU); \
193 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
194 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
197 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
198 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
199 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
200 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
201 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
202 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
203 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
204 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
206 #define GEN_VXFORM(name, opc2, opc3) \
207 static void glue(gen_, name)(DisasContext *ctx) \
209 TCGv_ptr ra, rb, rd; \
210 if (unlikely(!ctx->altivec_enabled)) { \
211 gen_exception(ctx, POWERPC_EXCP_VPU); \
214 ra = gen_avr_ptr(rA(ctx->opcode)); \
215 rb = gen_avr_ptr(rB(ctx->opcode)); \
216 rd = gen_avr_ptr(rD(ctx->opcode)); \
217 gen_helper_##name (rd, ra, rb); \
218 tcg_temp_free_ptr(ra); \
219 tcg_temp_free_ptr(rb); \
220 tcg_temp_free_ptr(rd); \
223 #define GEN_VXFORM_ENV(name, opc2, opc3) \
224 static void glue(gen_, name)(DisasContext *ctx) \
226 TCGv_ptr ra, rb, rd; \
227 if (unlikely(!ctx->altivec_enabled)) { \
228 gen_exception(ctx, POWERPC_EXCP_VPU); \
231 ra = gen_avr_ptr(rA(ctx->opcode)); \
232 rb = gen_avr_ptr(rB(ctx->opcode)); \
233 rd = gen_avr_ptr(rD(ctx->opcode)); \
234 gen_helper_##name(cpu_env, rd, ra, rb); \
235 tcg_temp_free_ptr(ra); \
236 tcg_temp_free_ptr(rb); \
237 tcg_temp_free_ptr(rd); \
240 #define GEN_VXFORM3(name, opc2, opc3) \
241 static void glue(gen_, name)(DisasContext *ctx) \
243 TCGv_ptr ra, rb, rc, rd; \
244 if (unlikely(!ctx->altivec_enabled)) { \
245 gen_exception(ctx, POWERPC_EXCP_VPU); \
248 ra = gen_avr_ptr(rA(ctx->opcode)); \
249 rb = gen_avr_ptr(rB(ctx->opcode)); \
250 rc = gen_avr_ptr(rC(ctx->opcode)); \
251 rd = gen_avr_ptr(rD(ctx->opcode)); \
252 gen_helper_##name(rd, ra, rb, rc); \
253 tcg_temp_free_ptr(ra); \
254 tcg_temp_free_ptr(rb); \
255 tcg_temp_free_ptr(rc); \
256 tcg_temp_free_ptr(rd); \
260 * Support for Altivec instruction pairs that use bit 31 (Rc) as
261 * an opcode bit. In general, these pairs come from different
262 * versions of the ISA, so we must also support a pair of flags for
265 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
266 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
268 if ((Rc(ctx->opcode) == 0) && \
269 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
271 } else if ((Rc(ctx->opcode) == 1) && \
272 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
279 GEN_VXFORM(vaddubm
, 0, 0);
280 GEN_VXFORM(vadduhm
, 0, 1);
281 GEN_VXFORM(vadduwm
, 0, 2);
282 GEN_VXFORM(vaddudm
, 0, 3);
283 GEN_VXFORM(vsububm
, 0, 16);
284 GEN_VXFORM(vsubuhm
, 0, 17);
285 GEN_VXFORM(vsubuwm
, 0, 18);
286 GEN_VXFORM(vsubudm
, 0, 19);
287 GEN_VXFORM(vmaxub
, 1, 0);
288 GEN_VXFORM(vmaxuh
, 1, 1);
289 GEN_VXFORM(vmaxuw
, 1, 2);
290 GEN_VXFORM(vmaxud
, 1, 3);
291 GEN_VXFORM(vmaxsb
, 1, 4);
292 GEN_VXFORM(vmaxsh
, 1, 5);
293 GEN_VXFORM(vmaxsw
, 1, 6);
294 GEN_VXFORM(vmaxsd
, 1, 7);
295 GEN_VXFORM(vminub
, 1, 8);
296 GEN_VXFORM(vminuh
, 1, 9);
297 GEN_VXFORM(vminuw
, 1, 10);
298 GEN_VXFORM(vminud
, 1, 11);
299 GEN_VXFORM(vminsb
, 1, 12);
300 GEN_VXFORM(vminsh
, 1, 13);
301 GEN_VXFORM(vminsw
, 1, 14);
302 GEN_VXFORM(vminsd
, 1, 15);
303 GEN_VXFORM(vavgub
, 1, 16);
304 GEN_VXFORM(vabsdub
, 1, 16);
305 GEN_VXFORM_DUAL(vavgub
, PPC_ALTIVEC
, PPC_NONE
, \
306 vabsdub
, PPC_NONE
, PPC2_ISA300
)
307 GEN_VXFORM(vavguh
, 1, 17);
308 GEN_VXFORM(vabsduh
, 1, 17);
309 GEN_VXFORM_DUAL(vavguh
, PPC_ALTIVEC
, PPC_NONE
, \
310 vabsduh
, PPC_NONE
, PPC2_ISA300
)
311 GEN_VXFORM(vavguw
, 1, 18);
312 GEN_VXFORM(vabsduw
, 1, 18);
313 GEN_VXFORM_DUAL(vavguw
, PPC_ALTIVEC
, PPC_NONE
, \
314 vabsduw
, PPC_NONE
, PPC2_ISA300
)
315 GEN_VXFORM(vavgsb
, 1, 20);
316 GEN_VXFORM(vavgsh
, 1, 21);
317 GEN_VXFORM(vavgsw
, 1, 22);
318 GEN_VXFORM(vmrghb
, 6, 0);
319 GEN_VXFORM(vmrghh
, 6, 1);
320 GEN_VXFORM(vmrghw
, 6, 2);
321 GEN_VXFORM(vmrglb
, 6, 4);
322 GEN_VXFORM(vmrglh
, 6, 5);
323 GEN_VXFORM(vmrglw
, 6, 6);
325 static void gen_vmrgew(DisasContext
*ctx
)
329 if (unlikely(!ctx
->altivec_enabled
)) {
330 gen_exception(ctx
, POWERPC_EXCP_VPU
);
333 VT
= rD(ctx
->opcode
);
334 VA
= rA(ctx
->opcode
);
335 VB
= rB(ctx
->opcode
);
336 tmp
= tcg_temp_new_i64();
337 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
338 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
339 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
340 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
341 tcg_temp_free_i64(tmp
);
344 static void gen_vmrgow(DisasContext
*ctx
)
347 if (unlikely(!ctx
->altivec_enabled
)) {
348 gen_exception(ctx
, POWERPC_EXCP_VPU
);
351 VT
= rD(ctx
->opcode
);
352 VA
= rA(ctx
->opcode
);
353 VB
= rB(ctx
->opcode
);
355 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
356 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
359 GEN_VXFORM(vmuloub
, 4, 0);
360 GEN_VXFORM(vmulouh
, 4, 1);
361 GEN_VXFORM(vmulouw
, 4, 2);
362 GEN_VXFORM(vmuluwm
, 4, 2);
363 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
364 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
365 GEN_VXFORM(vmulosb
, 4, 4);
366 GEN_VXFORM(vmulosh
, 4, 5);
367 GEN_VXFORM(vmulosw
, 4, 6);
368 GEN_VXFORM(vmuleub
, 4, 8);
369 GEN_VXFORM(vmuleuh
, 4, 9);
370 GEN_VXFORM(vmuleuw
, 4, 10);
371 GEN_VXFORM(vmulesb
, 4, 12);
372 GEN_VXFORM(vmulesh
, 4, 13);
373 GEN_VXFORM(vmulesw
, 4, 14);
374 GEN_VXFORM(vslb
, 2, 4);
375 GEN_VXFORM(vslh
, 2, 5);
376 GEN_VXFORM(vslw
, 2, 6);
377 GEN_VXFORM(vsld
, 2, 23);
378 GEN_VXFORM(vsrb
, 2, 8);
379 GEN_VXFORM(vsrh
, 2, 9);
380 GEN_VXFORM(vsrw
, 2, 10);
381 GEN_VXFORM(vsrd
, 2, 27);
382 GEN_VXFORM(vsrab
, 2, 12);
383 GEN_VXFORM(vsrah
, 2, 13);
384 GEN_VXFORM(vsraw
, 2, 14);
385 GEN_VXFORM(vsrad
, 2, 15);
386 GEN_VXFORM(vsrv
, 2, 28);
387 GEN_VXFORM(vslv
, 2, 29);
388 GEN_VXFORM(vslo
, 6, 16);
389 GEN_VXFORM(vsro
, 6, 17);
390 GEN_VXFORM(vaddcuw
, 0, 6);
391 GEN_VXFORM(vsubcuw
, 0, 22);
392 GEN_VXFORM_ENV(vaddubs
, 0, 8);
393 GEN_VXFORM_ENV(vadduhs
, 0, 9);
394 GEN_VXFORM_ENV(vadduws
, 0, 10);
395 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
396 GEN_VXFORM_ENV(vaddshs
, 0, 13);
397 GEN_VXFORM_ENV(vaddsws
, 0, 14);
398 GEN_VXFORM_ENV(vsububs
, 0, 24);
399 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
400 GEN_VXFORM_ENV(vsubuws
, 0, 26);
401 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
402 GEN_VXFORM_ENV(vsubshs
, 0, 29);
403 GEN_VXFORM_ENV(vsubsws
, 0, 30);
404 GEN_VXFORM(vadduqm
, 0, 4);
405 GEN_VXFORM(vaddcuq
, 0, 5);
406 GEN_VXFORM3(vaddeuqm
, 30, 0);
407 GEN_VXFORM3(vaddecuq
, 30, 0);
408 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
409 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
410 GEN_VXFORM(vsubuqm
, 0, 20);
411 GEN_VXFORM(vsubcuq
, 0, 21);
412 GEN_VXFORM3(vsubeuqm
, 31, 0);
413 GEN_VXFORM3(vsubecuq
, 31, 0);
414 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
415 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
416 GEN_VXFORM(vrlb
, 2, 0);
417 GEN_VXFORM(vrlh
, 2, 1);
418 GEN_VXFORM(vrlw
, 2, 2);
419 GEN_VXFORM(vrld
, 2, 3);
420 GEN_VXFORM(vsl
, 2, 7);
421 GEN_VXFORM(vsr
, 2, 11);
422 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
423 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
424 GEN_VXFORM_ENV(vpkudum
, 7, 17);
425 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
426 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
427 GEN_VXFORM_ENV(vpkudus
, 7, 19);
428 GEN_VXFORM_ENV(vpkshus
, 7, 4);
429 GEN_VXFORM_ENV(vpkswus
, 7, 5);
430 GEN_VXFORM_ENV(vpksdus
, 7, 21);
431 GEN_VXFORM_ENV(vpkshss
, 7, 6);
432 GEN_VXFORM_ENV(vpkswss
, 7, 7);
433 GEN_VXFORM_ENV(vpksdss
, 7, 23);
434 GEN_VXFORM(vpkpx
, 7, 12);
435 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
436 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
437 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
438 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
439 GEN_VXFORM_ENV(vsumsws
, 4, 30);
440 GEN_VXFORM_ENV(vaddfp
, 5, 0);
441 GEN_VXFORM_ENV(vsubfp
, 5, 1);
442 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
443 GEN_VXFORM_ENV(vminfp
, 5, 17);
445 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
446 static void glue(gen_, name)(DisasContext *ctx) \
448 TCGv_ptr ra, rb, rd; \
449 if (unlikely(!ctx->altivec_enabled)) { \
450 gen_exception(ctx, POWERPC_EXCP_VPU); \
453 ra = gen_avr_ptr(rA(ctx->opcode)); \
454 rb = gen_avr_ptr(rB(ctx->opcode)); \
455 rd = gen_avr_ptr(rD(ctx->opcode)); \
456 gen_helper_##opname(cpu_env, rd, ra, rb); \
457 tcg_temp_free_ptr(ra); \
458 tcg_temp_free_ptr(rb); \
459 tcg_temp_free_ptr(rd); \
462 #define GEN_VXRFORM(name, opc2, opc3) \
463 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
464 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
467 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
468 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
469 * come from different versions of the ISA, so we must also support a
470 * pair of flags for each instruction.
472 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
473 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
475 if ((Rc(ctx->opcode) == 0) && \
476 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
477 if (Rc21(ctx->opcode) == 0) { \
480 gen_##name0##_(ctx); \
482 } else if ((Rc(ctx->opcode) == 1) && \
483 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
484 if (Rc21(ctx->opcode) == 0) { \
487 gen_##name1##_(ctx); \
490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
494 GEN_VXRFORM(vcmpequb
, 3, 0)
495 GEN_VXRFORM(vcmpequh
, 3, 1)
496 GEN_VXRFORM(vcmpequw
, 3, 2)
497 GEN_VXRFORM(vcmpequd
, 3, 3)
498 GEN_VXRFORM(vcmpnezb
, 3, 4)
499 GEN_VXRFORM(vcmpnezh
, 3, 5)
500 GEN_VXRFORM(vcmpnezw
, 3, 6)
501 GEN_VXRFORM(vcmpgtsb
, 3, 12)
502 GEN_VXRFORM(vcmpgtsh
, 3, 13)
503 GEN_VXRFORM(vcmpgtsw
, 3, 14)
504 GEN_VXRFORM(vcmpgtsd
, 3, 15)
505 GEN_VXRFORM(vcmpgtub
, 3, 8)
506 GEN_VXRFORM(vcmpgtuh
, 3, 9)
507 GEN_VXRFORM(vcmpgtuw
, 3, 10)
508 GEN_VXRFORM(vcmpgtud
, 3, 11)
509 GEN_VXRFORM(vcmpeqfp
, 3, 3)
510 GEN_VXRFORM(vcmpgefp
, 3, 7)
511 GEN_VXRFORM(vcmpgtfp
, 3, 11)
512 GEN_VXRFORM(vcmpbfp
, 3, 15)
513 GEN_VXRFORM(vcmpneb
, 3, 0)
514 GEN_VXRFORM(vcmpneh
, 3, 1)
515 GEN_VXRFORM(vcmpnew
, 3, 2)
517 GEN_VXRFORM_DUAL(vcmpequb
, PPC_ALTIVEC
, PPC_NONE
, \
518 vcmpneb
, PPC_NONE
, PPC2_ISA300
)
519 GEN_VXRFORM_DUAL(vcmpequh
, PPC_ALTIVEC
, PPC_NONE
, \
520 vcmpneh
, PPC_NONE
, PPC2_ISA300
)
521 GEN_VXRFORM_DUAL(vcmpequw
, PPC_ALTIVEC
, PPC_NONE
, \
522 vcmpnew
, PPC_NONE
, PPC2_ISA300
)
523 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
524 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
525 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
526 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
527 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
528 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
530 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
531 static void glue(gen_, name)(DisasContext *ctx) \
535 if (unlikely(!ctx->altivec_enabled)) { \
536 gen_exception(ctx, POWERPC_EXCP_VPU); \
539 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
540 rd = gen_avr_ptr(rD(ctx->opcode)); \
541 gen_helper_##name (rd, simm); \
542 tcg_temp_free_i32(simm); \
543 tcg_temp_free_ptr(rd); \
546 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
547 GEN_VXFORM_SIMM(vspltish
, 6, 13);
548 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
550 #define GEN_VXFORM_NOA(name, opc2, opc3) \
551 static void glue(gen_, name)(DisasContext *ctx) \
554 if (unlikely(!ctx->altivec_enabled)) { \
555 gen_exception(ctx, POWERPC_EXCP_VPU); \
558 rb = gen_avr_ptr(rB(ctx->opcode)); \
559 rd = gen_avr_ptr(rD(ctx->opcode)); \
560 gen_helper_##name (rd, rb); \
561 tcg_temp_free_ptr(rb); \
562 tcg_temp_free_ptr(rd); \
565 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
566 static void glue(gen_, name)(DisasContext *ctx) \
570 if (unlikely(!ctx->altivec_enabled)) { \
571 gen_exception(ctx, POWERPC_EXCP_VPU); \
574 rb = gen_avr_ptr(rB(ctx->opcode)); \
575 rd = gen_avr_ptr(rD(ctx->opcode)); \
576 gen_helper_##name(cpu_env, rd, rb); \
577 tcg_temp_free_ptr(rb); \
578 tcg_temp_free_ptr(rd); \
581 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
582 static void glue(gen_, name)(DisasContext *ctx) \
585 if (unlikely(!ctx->altivec_enabled)) { \
586 gen_exception(ctx, POWERPC_EXCP_VPU); \
589 rb = gen_avr_ptr(rB(ctx->opcode)); \
590 rd = gen_avr_ptr(rD(ctx->opcode)); \
591 gen_helper_##name(rd, rb); \
592 tcg_temp_free_ptr(rb); \
593 tcg_temp_free_ptr(rd); \
596 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
597 static void glue(gen_, name)(DisasContext *ctx) \
600 if (unlikely(!ctx->altivec_enabled)) { \
601 gen_exception(ctx, POWERPC_EXCP_VPU); \
604 rb = gen_avr_ptr(rB(ctx->opcode)); \
605 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
606 tcg_temp_free_ptr(rb); \
608 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
609 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
610 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
611 GEN_VXFORM_NOA(vupklsb
, 7, 10);
612 GEN_VXFORM_NOA(vupklsh
, 7, 11);
613 GEN_VXFORM_NOA(vupklsw
, 7, 27);
614 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
615 GEN_VXFORM_NOA(vupklpx
, 7, 15);
616 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
617 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
618 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
619 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
620 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
621 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
622 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
623 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
625 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
626 static void glue(gen_, name)(DisasContext *ctx) \
630 if (unlikely(!ctx->altivec_enabled)) { \
631 gen_exception(ctx, POWERPC_EXCP_VPU); \
634 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
635 rd = gen_avr_ptr(rD(ctx->opcode)); \
636 gen_helper_##name (rd, simm); \
637 tcg_temp_free_i32(simm); \
638 tcg_temp_free_ptr(rd); \
641 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
642 static void glue(gen_, name)(DisasContext *ctx) \
646 if (unlikely(!ctx->altivec_enabled)) { \
647 gen_exception(ctx, POWERPC_EXCP_VPU); \
650 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
651 rb = gen_avr_ptr(rB(ctx->opcode)); \
652 rd = gen_avr_ptr(rD(ctx->opcode)); \
653 gen_helper_##name (rd, rb, uimm); \
654 tcg_temp_free_i32(uimm); \
655 tcg_temp_free_ptr(rb); \
656 tcg_temp_free_ptr(rd); \
659 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
660 static void glue(gen_, name)(DisasContext *ctx) \
665 if (unlikely(!ctx->altivec_enabled)) { \
666 gen_exception(ctx, POWERPC_EXCP_VPU); \
669 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
670 rb = gen_avr_ptr(rB(ctx->opcode)); \
671 rd = gen_avr_ptr(rD(ctx->opcode)); \
672 gen_helper_##name(cpu_env, rd, rb, uimm); \
673 tcg_temp_free_i32(uimm); \
674 tcg_temp_free_ptr(rb); \
675 tcg_temp_free_ptr(rd); \
678 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
679 static void glue(gen_, name)(DisasContext *ctx) \
682 uint8_t uimm = UIMM4(ctx->opcode); \
683 TCGv_i32 t0 = tcg_temp_new_i32(); \
684 if (unlikely(!ctx->altivec_enabled)) { \
685 gen_exception(ctx, POWERPC_EXCP_VPU); \
688 if (uimm > splat_max) { \
691 tcg_gen_movi_i32(t0, uimm); \
692 rb = gen_avr_ptr(rB(ctx->opcode)); \
693 rd = gen_avr_ptr(rD(ctx->opcode)); \
694 gen_helper_##name(rd, rb, t0); \
695 tcg_temp_free_i32(t0); \
696 tcg_temp_free_ptr(rb); \
697 tcg_temp_free_ptr(rd); \
700 GEN_VXFORM_UIMM(vspltb
, 6, 8);
701 GEN_VXFORM_UIMM(vsplth
, 6, 9);
702 GEN_VXFORM_UIMM(vspltw
, 6, 10);
703 GEN_VXFORM_UIMM_SPLAT(vextractub
, 6, 8, 15);
704 GEN_VXFORM_UIMM_SPLAT(vextractuh
, 6, 9, 14);
705 GEN_VXFORM_UIMM_SPLAT(vextractuw
, 6, 10, 12);
706 GEN_VXFORM_UIMM_SPLAT(vextractd
, 6, 11, 8);
707 GEN_VXFORM_UIMM_SPLAT(vinsertb
, 6, 12, 15);
708 GEN_VXFORM_UIMM_SPLAT(vinserth
, 6, 13, 14);
709 GEN_VXFORM_UIMM_SPLAT(vinsertw
, 6, 14, 12);
710 GEN_VXFORM_UIMM_SPLAT(vinsertd
, 6, 15, 8);
711 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
712 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
713 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
714 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
715 GEN_VXFORM_DUAL(vspltb
, PPC_ALTIVEC
, PPC_NONE
,
716 vextractub
, PPC_NONE
, PPC2_ISA300
);
717 GEN_VXFORM_DUAL(vsplth
, PPC_ALTIVEC
, PPC_NONE
,
718 vextractuh
, PPC_NONE
, PPC2_ISA300
);
719 GEN_VXFORM_DUAL(vspltw
, PPC_ALTIVEC
, PPC_NONE
,
720 vextractuw
, PPC_NONE
, PPC2_ISA300
);
721 GEN_VXFORM_DUAL(vspltisb
, PPC_ALTIVEC
, PPC_NONE
,
722 vinsertb
, PPC_NONE
, PPC2_ISA300
);
723 GEN_VXFORM_DUAL(vspltish
, PPC_ALTIVEC
, PPC_NONE
,
724 vinserth
, PPC_NONE
, PPC2_ISA300
);
725 GEN_VXFORM_DUAL(vspltisw
, PPC_ALTIVEC
, PPC_NONE
,
726 vinsertw
, PPC_NONE
, PPC2_ISA300
);
728 static void gen_vsldoi(DisasContext
*ctx
)
732 if (unlikely(!ctx
->altivec_enabled
)) {
733 gen_exception(ctx
, POWERPC_EXCP_VPU
);
736 ra
= gen_avr_ptr(rA(ctx
->opcode
));
737 rb
= gen_avr_ptr(rB(ctx
->opcode
));
738 rd
= gen_avr_ptr(rD(ctx
->opcode
));
739 sh
= tcg_const_i32(VSH(ctx
->opcode
));
740 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
741 tcg_temp_free_ptr(ra
);
742 tcg_temp_free_ptr(rb
);
743 tcg_temp_free_ptr(rd
);
744 tcg_temp_free_i32(sh
);
747 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
748 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
750 TCGv_ptr ra, rb, rc, rd; \
751 if (unlikely(!ctx->altivec_enabled)) { \
752 gen_exception(ctx, POWERPC_EXCP_VPU); \
755 ra = gen_avr_ptr(rA(ctx->opcode)); \
756 rb = gen_avr_ptr(rB(ctx->opcode)); \
757 rc = gen_avr_ptr(rC(ctx->opcode)); \
758 rd = gen_avr_ptr(rD(ctx->opcode)); \
759 if (Rc(ctx->opcode)) { \
760 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
762 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
764 tcg_temp_free_ptr(ra); \
765 tcg_temp_free_ptr(rb); \
766 tcg_temp_free_ptr(rc); \
767 tcg_temp_free_ptr(rd); \
770 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
772 static void gen_vmladduhm(DisasContext
*ctx
)
774 TCGv_ptr ra
, rb
, rc
, rd
;
775 if (unlikely(!ctx
->altivec_enabled
)) {
776 gen_exception(ctx
, POWERPC_EXCP_VPU
);
779 ra
= gen_avr_ptr(rA(ctx
->opcode
));
780 rb
= gen_avr_ptr(rB(ctx
->opcode
));
781 rc
= gen_avr_ptr(rC(ctx
->opcode
));
782 rd
= gen_avr_ptr(rD(ctx
->opcode
));
783 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
784 tcg_temp_free_ptr(ra
);
785 tcg_temp_free_ptr(rb
);
786 tcg_temp_free_ptr(rc
);
787 tcg_temp_free_ptr(rd
);
790 static void gen_vpermr(DisasContext
*ctx
)
792 TCGv_ptr ra
, rb
, rc
, rd
;
793 if (unlikely(!ctx
->altivec_enabled
)) {
794 gen_exception(ctx
, POWERPC_EXCP_VPU
);
797 ra
= gen_avr_ptr(rA(ctx
->opcode
));
798 rb
= gen_avr_ptr(rB(ctx
->opcode
));
799 rc
= gen_avr_ptr(rC(ctx
->opcode
));
800 rd
= gen_avr_ptr(rD(ctx
->opcode
));
801 gen_helper_vpermr(cpu_env
, rd
, ra
, rb
, rc
);
802 tcg_temp_free_ptr(ra
);
803 tcg_temp_free_ptr(rb
);
804 tcg_temp_free_ptr(rc
);
805 tcg_temp_free_ptr(rd
);
808 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
809 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
810 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
811 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
812 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
814 GEN_VXFORM_NOA(vclzb
, 1, 28)
815 GEN_VXFORM_NOA(vclzh
, 1, 29)
816 GEN_VXFORM_NOA(vclzw
, 1, 30)
817 GEN_VXFORM_NOA(vclzd
, 1, 31)
818 GEN_VXFORM_NOA_2(vextsb2w
, 1, 24, 16)
819 GEN_VXFORM_NOA_2(vextsh2w
, 1, 24, 17)
820 GEN_VXFORM_NOA_2(vextsb2d
, 1, 24, 24)
821 GEN_VXFORM_NOA_2(vextsh2d
, 1, 24, 25)
822 GEN_VXFORM_NOA_2(vextsw2d
, 1, 24, 26)
823 GEN_VXFORM_NOA_2(vctzb
, 1, 24, 28)
824 GEN_VXFORM_NOA_2(vctzh
, 1, 24, 29)
825 GEN_VXFORM_NOA_2(vctzw
, 1, 24, 30)
826 GEN_VXFORM_NOA_2(vctzd
, 1, 24, 31)
827 GEN_VXFORM_NOA_3(vclzlsbb
, 1, 24, 0)
828 GEN_VXFORM_NOA_3(vctzlsbb
, 1, 24, 1)
829 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
830 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
831 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
832 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
833 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
834 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
835 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
836 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
837 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
838 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
839 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
840 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
841 GEN_VXFORM(vbpermd
, 6, 23);
842 GEN_VXFORM(vbpermq
, 6, 21);
843 GEN_VXFORM_NOA(vgbbd
, 6, 20);
844 GEN_VXFORM(vpmsumb
, 4, 16)
845 GEN_VXFORM(vpmsumh
, 4, 17)
846 GEN_VXFORM(vpmsumw
, 4, 18)
847 GEN_VXFORM(vpmsumd
, 4, 19)
849 #define GEN_BCD(op) \
850 static void gen_##op(DisasContext *ctx) \
852 TCGv_ptr ra, rb, rd; \
855 if (unlikely(!ctx->altivec_enabled)) { \
856 gen_exception(ctx, POWERPC_EXCP_VPU); \
860 ra = gen_avr_ptr(rA(ctx->opcode)); \
861 rb = gen_avr_ptr(rB(ctx->opcode)); \
862 rd = gen_avr_ptr(rD(ctx->opcode)); \
864 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
866 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
868 tcg_temp_free_ptr(ra); \
869 tcg_temp_free_ptr(rb); \
870 tcg_temp_free_ptr(rd); \
871 tcg_temp_free_i32(ps); \
877 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
878 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
879 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
880 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
881 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
882 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
883 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
884 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
886 static void gen_vsbox(DisasContext
*ctx
)
889 if (unlikely(!ctx
->altivec_enabled
)) {
890 gen_exception(ctx
, POWERPC_EXCP_VPU
);
893 ra
= gen_avr_ptr(rA(ctx
->opcode
));
894 rd
= gen_avr_ptr(rD(ctx
->opcode
));
895 gen_helper_vsbox(rd
, ra
);
896 tcg_temp_free_ptr(ra
);
897 tcg_temp_free_ptr(rd
);
900 GEN_VXFORM(vcipher
, 4, 20)
901 GEN_VXFORM(vcipherlast
, 4, 20)
902 GEN_VXFORM(vncipher
, 4, 21)
903 GEN_VXFORM(vncipherlast
, 4, 21)
905 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
906 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
907 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
908 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
910 #define VSHASIGMA(op) \
911 static void gen_##op(DisasContext *ctx) \
915 if (unlikely(!ctx->altivec_enabled)) { \
916 gen_exception(ctx, POWERPC_EXCP_VPU); \
919 ra = gen_avr_ptr(rA(ctx->opcode)); \
920 rd = gen_avr_ptr(rD(ctx->opcode)); \
921 st_six = tcg_const_i32(rB(ctx->opcode)); \
922 gen_helper_##op(rd, ra, st_six); \
923 tcg_temp_free_ptr(ra); \
924 tcg_temp_free_ptr(rd); \
925 tcg_temp_free_i32(st_six); \
928 VSHASIGMA(vshasigmaw
)
929 VSHASIGMA(vshasigmad
)
931 GEN_VXFORM3(vpermxor
, 22, 0xFF)
932 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
933 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
940 #undef GEN_VX_LOGICAL
941 #undef GEN_VX_LOGICAL_207
943 #undef GEN_VXFORM_207
944 #undef GEN_VXFORM_DUAL
945 #undef GEN_VXRFORM_DUAL
948 #undef GEN_VXFORM_SIMM
949 #undef GEN_VXFORM_NOA
950 #undef GEN_VXFORM_UIMM
951 #undef GEN_VAFORM_PAIRED