target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "qemu-common.h"
  26
  27 #define TARGET_LONG_BITS 64
  28
  29 #define ELF_MACHINE_UNAME "S390X"
  30
  31 #define CPUArchState struct CPUS390XState
  32
  33 #include "exec/cpu-defs.h"
  34 #define TARGET_PAGE_BITS 12
  35
  36 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  37 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  38
  39 #include "exec/cpu-all.h"
  40
  41 #include "fpu/softfloat.h"
  42
  43 #define NB_MMU_MODES 3
  44 #define TARGET_INSN_START_EXTRA_WORDS 1
  45
  46 #define MMU_MODE0_SUFFIX _primary
  47 #define MMU_MODE1_SUFFIX _secondary
  48 #define MMU_MODE2_SUFFIX _home
  49
  50 #define MMU_USER_IDX 0
  51
  52 #define MAX_EXT_QUEUE 16
  53 #define MAX_IO_QUEUE 16
  54 #define MAX_MCHK_QUEUE 16
  55
  56 #define PSW_MCHK_MASK 0x0004000000000000
  57 #define PSW_IO_MASK 0x0200000000000000
  58
  59 typedef struct PSW {
  60     uint64_t mask;
  61     uint64_t addr;
  62 } PSW;
  63
  64 typedef struct ExtQueue {
  65     uint32_t code;
  66     uint32_t param;
  67     uint32_t param64;
  68 } ExtQueue;
  69
  70 typedef struct IOIntQueue {
  71     uint16_t id;
  72     uint16_t nr;
  73     uint32_t parm;
  74     uint32_t word;
  75 } IOIntQueue;
  76
  77 typedef struct MchkQueue {
  78     uint16_t type;
  79 } MchkQueue;
  80
  81 typedef struct CPUS390XState {
  82     uint64_t regs[16];     /* GP registers */
  83     /*
  84      * The floating point registers are part of the vector registers.
  85      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  86      */
  87     CPU_DoubleU vregs[32][2];  /* vector registers */
  88     uint32_t aregs[16];    /* access registers */
  89
  90     uint32_t fpc;          /* floating-point control register */
  91     uint32_t cc_op;
  92
  93     float_status fpu_status; /* passed to softfloat lib */
  94
  95     /* The low part of a 128-bit return, or remainder of a divide.  */
  96     uint64_t retxl;
  97
  98     PSW psw;
  99
 100     uint64_t cc_src;
 101     uint64_t cc_dst;
 102     uint64_t cc_vr;
 103
 104     uint64_t __excp_addr;
 105     uint64_t psa;
 106
 107     uint32_t int_pgm_code;
 108     uint32_t int_pgm_ilen;
 109
 110     uint32_t int_svc_code;
 111     uint32_t int_svc_ilen;
 112
 113     uint64_t per_address;
 114     uint16_t per_perc_atmid;
 115
 116     uint64_t cregs[16]; /* control registers */
 117
 118     ExtQueue ext_queue[MAX_EXT_QUEUE];
 119     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 120     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 121
 122     int pending_int;
 123     int ext_index;
 124     int io_index[8];
 125     int mchk_index;
 126
 127     uint64_t ckc;
 128     uint64_t cputm;
 129     uint32_t todpr;
 130
 131     uint64_t pfault_token;
 132     uint64_t pfault_compare;
 133     uint64_t pfault_select;
 134
 135     uint64_t gbea;
 136     uint64_t pp;
 137
 138     uint8_t riccb[64];
 139
 140     CPU_COMMON
 141
 142     /* reset does memset(0) up to here */
 143
 144     uint32_t cpu_num;
 145     uint32_t machine_type;
 146
 147     uint64_t tod_offset;
 148     uint64_t tod_basetime;
 149     QEMUTimer *tod_timer;
 150
 151     QEMUTimer *cpu_timer;
 152
 153     /*
 154      * The cpu state represents the logical state of a cpu. In contrast to other
 155      * architectures, there is a difference between a halt and a stop on s390.
 156      * If all cpus are either stopped (including check stop) or in the disabled
 157      * wait state, the vm can be shut down.
 158      */
 159 #define CPU_STATE_UNINITIALIZED        0x00
 160 #define CPU_STATE_STOPPED              0x01
 161 #define CPU_STATE_CHECK_STOP           0x02
 162 #define CPU_STATE_OPERATING            0x03
 163 #define CPU_STATE_LOAD                 0x04
 164     uint8_t cpu_state;
 165
 166     /* currently processed sigp order */
 167     uint8_t sigp_order;
 168
 169 } CPUS390XState;
 170
 171 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 172 {
 173     return &cs->vregs[nr][0];
 174 }
 175
 176 #include "cpu-qom.h"
 177 #include <sysemu/kvm.h>
 178
 179 /* distinguish between 24 bit and 31 bit addressing */
 180 #define HIGH_ORDER_BIT 0x80000000
 181
 182 /* Interrupt Codes */
 183 /* Program Interrupts */
 184 #define PGM_OPERATION                   0x0001
 185 #define PGM_PRIVILEGED                  0x0002
 186 #define PGM_EXECUTE                     0x0003
 187 #define PGM_PROTECTION                  0x0004
 188 #define PGM_ADDRESSING                  0x0005
 189 #define PGM_SPECIFICATION               0x0006
 190 #define PGM_DATA                        0x0007
 191 #define PGM_FIXPT_OVERFLOW              0x0008
 192 #define PGM_FIXPT_DIVIDE                0x0009
 193 #define PGM_DEC_OVERFLOW                0x000a
 194 #define PGM_DEC_DIVIDE                  0x000b
 195 #define PGM_HFP_EXP_OVERFLOW            0x000c
 196 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 197 #define PGM_HFP_SIGNIFICANCE            0x000e
 198 #define PGM_HFP_DIVIDE                  0x000f
 199 #define PGM_SEGMENT_TRANS               0x0010
 200 #define PGM_PAGE_TRANS                  0x0011
 201 #define PGM_TRANS_SPEC                  0x0012
 202 #define PGM_SPECIAL_OP                  0x0013
 203 #define PGM_OPERAND                     0x0015
 204 #define PGM_TRACE_TABLE                 0x0016
 205 #define PGM_SPACE_SWITCH                0x001c
 206 #define PGM_HFP_SQRT                    0x001d
 207 #define PGM_PC_TRANS_SPEC               0x001f
 208 #define PGM_AFX_TRANS                   0x0020
 209 #define PGM_ASX_TRANS                   0x0021
 210 #define PGM_LX_TRANS                    0x0022
 211 #define PGM_EX_TRANS                    0x0023
 212 #define PGM_PRIM_AUTH                   0x0024
 213 #define PGM_SEC_AUTH                    0x0025
 214 #define PGM_ALET_SPEC                   0x0028
 215 #define PGM_ALEN_SPEC                   0x0029
 216 #define PGM_ALE_SEQ                     0x002a
 217 #define PGM_ASTE_VALID                  0x002b
 218 #define PGM_ASTE_SEQ                    0x002c
 219 #define PGM_EXT_AUTH                    0x002d
 220 #define PGM_STACK_FULL                  0x0030
 221 #define PGM_STACK_EMPTY                 0x0031
 222 #define PGM_STACK_SPEC                  0x0032
 223 #define PGM_STACK_TYPE                  0x0033
 224 #define PGM_STACK_OP                    0x0034
 225 #define PGM_ASCE_TYPE                   0x0038
 226 #define PGM_REG_FIRST_TRANS             0x0039
 227 #define PGM_REG_SEC_TRANS               0x003a
 228 #define PGM_REG_THIRD_TRANS             0x003b
 229 #define PGM_MONITOR                     0x0040
 230 #define PGM_PER                         0x0080
 231 #define PGM_CRYPTO                      0x0119
 232
 233 /* External Interrupts */
 234 #define EXT_INTERRUPT_KEY               0x0040
 235 #define EXT_CLOCK_COMP                  0x1004
 236 #define EXT_CPU_TIMER                   0x1005
 237 #define EXT_MALFUNCTION                 0x1200
 238 #define EXT_EMERGENCY                   0x1201
 239 #define EXT_EXTERNAL_CALL               0x1202
 240 #define EXT_ETR                         0x1406
 241 #define EXT_SERVICE                     0x2401
 242 #define EXT_VIRTIO                      0x2603
 243
 244 /* PSW defines */
 245 #undef PSW_MASK_PER
 246 #undef PSW_MASK_DAT
 247 #undef PSW_MASK_IO
 248 #undef PSW_MASK_EXT
 249 #undef PSW_MASK_KEY
 250 #undef PSW_SHIFT_KEY
 251 #undef PSW_MASK_MCHECK
 252 #undef PSW_MASK_WAIT
 253 #undef PSW_MASK_PSTATE
 254 #undef PSW_MASK_ASC
 255 #undef PSW_MASK_CC
 256 #undef PSW_MASK_PM
 257 #undef PSW_MASK_64
 258 #undef PSW_MASK_32
 259 #undef PSW_MASK_ESA_ADDR
 260
 261 #define PSW_MASK_PER            0x4000000000000000ULL
 262 #define PSW_MASK_DAT            0x0400000000000000ULL
 263 #define PSW_MASK_IO             0x0200000000000000ULL
 264 #define PSW_MASK_EXT            0x0100000000000000ULL
 265 #define PSW_MASK_KEY            0x00F0000000000000ULL
 266 #define PSW_SHIFT_KEY           56
 267 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 268 #define PSW_MASK_WAIT           0x0002000000000000ULL
 269 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 270 #define PSW_MASK_ASC            0x0000C00000000000ULL
 271 #define PSW_MASK_CC             0x0000300000000000ULL
 272 #define PSW_MASK_PM             0x00000F0000000000ULL
 273 #define PSW_MASK_64             0x0000000100000000ULL
 274 #define PSW_MASK_32             0x0000000080000000ULL
 275 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 276
 277 #undef PSW_ASC_PRIMARY
 278 #undef PSW_ASC_ACCREG
 279 #undef PSW_ASC_SECONDARY
 280 #undef PSW_ASC_HOME
 281
 282 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 283 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 284 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 285 #define PSW_ASC_HOME            0x0000C00000000000ULL
 286
 287 /* tb flags */
 288
 289 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 290 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 291 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 292 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 293 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 294 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 295 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 296 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 297 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 298 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 299 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 300 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 301 #define FLAG_MASK_32            0x00001000
 302
 303 /* Control register 0 bits */
 304 #define CR0_LOWPROT             0x0000000010000000ULL
 305 #define CR0_EDAT                0x0000000000800000ULL
 306
 307 /* MMU */
 308 #define MMU_PRIMARY_IDX         0
 309 #define MMU_SECONDARY_IDX       1
 310 #define MMU_HOME_IDX            2
 311
 312 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
 313 {
 314     switch (env->psw.mask & PSW_MASK_ASC) {
 315     case PSW_ASC_PRIMARY:
 316         return MMU_PRIMARY_IDX;
 317     case PSW_ASC_SECONDARY:
 318         return MMU_SECONDARY_IDX;
 319     case PSW_ASC_HOME:
 320         return MMU_HOME_IDX;
 321     case PSW_ASC_ACCREG:
 322         /* Fallthrough: access register mode is not yet supported */
 323     default:
 324         abort();
 325     }
 326 }
 327
 328 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
 329 {
 330     switch (mmu_idx) {
 331     case MMU_PRIMARY_IDX:
 332         return PSW_ASC_PRIMARY;
 333     case MMU_SECONDARY_IDX:
 334         return PSW_ASC_SECONDARY;
 335     case MMU_HOME_IDX:
 336         return PSW_ASC_HOME;
 337     default:
 338         abort();
 339     }
 340 }
 341
 342 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 343                                         target_ulong *cs_base, uint32_t *flags)
 344 {
 345     *pc = env->psw.addr;
 346     *cs_base = 0;
 347     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 348              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 349 }
 350
 351 /* While the PoO talks about ILC (a number between 1-3) what is actually
 352    stored in LowCore is shifted left one bit (an even between 2-6).  As
 353    this is the actual length of the insn and therefore more useful, that
 354    is what we want to pass around and manipulate.  To make sure that we
 355    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 356 static inline int get_ilen(uint8_t opc)
 357 {
 358     switch (opc >> 6) {
 359     case 0:
 360         return 2;
 361     case 1:
 362     case 2:
 363         return 4;
 364     default:
 365         return 6;
 366     }
 367 }
 368
 369 /* PER bits from control register 9 */
 370 #define PER_CR9_EVENT_BRANCH           0x80000000
 371 #define PER_CR9_EVENT_IFETCH           0x40000000
 372 #define PER_CR9_EVENT_STORE            0x20000000
 373 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 374 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 375 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 376 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 377
 378 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 379 #define PER_CODE_EVENT_BRANCH          0x8000
 380 #define PER_CODE_EVENT_IFETCH          0x4000
 381 #define PER_CODE_EVENT_STORE           0x2000
 382 #define PER_CODE_EVENT_STORE_REAL      0x0800
 383 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 384
 385 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
 386    entry when a PER exception is triggered.  */
 387 static inline uint8_t get_per_atmid(CPUS390XState *env)
 388 {
 389     return ((env->psw.mask & PSW_MASK_64) ?      (1 << 7) : 0) |
 390            (                                     (1 << 6)    ) |
 391            ((env->psw.mask & PSW_MASK_32) ?      (1 << 5) : 0) |
 392            ((env->psw.mask & PSW_MASK_DAT)?      (1 << 4) : 0) |
 393            ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
 394            ((env->psw.mask & PSW_ASC_ACCREG)?    (1 << 2) : 0);
 395 }
 396
 397 /* Check if an address is within the PER starting address and the PER
 398    ending address.  The address range might loop.  */
 399 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
 400 {
 401     if (env->cregs[10] <= env->cregs[11]) {
 402         return env->cregs[10] <= addr && addr <= env->cregs[11];
 403     } else {
 404         return env->cregs[10] <= addr || addr <= env->cregs[11];
 405     }
 406 }
 407
 408 #ifndef CONFIG_USER_ONLY
 409 /* In several cases of runtime exceptions, we havn't recorded the true
 410    instruction length.  Use these codes when raising exceptions in order
 411    to re-compute the length by examining the insn in memory.  */
 412 #define ILEN_LATER       0x20
 413 #define ILEN_LATER_INC   0x21
 414 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 415 #endif
 416
 417 S390CPU *cpu_s390x_init(const char *cpu_model);
 418 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
 419 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
 420 void s390x_translate_init(void);
 421 int cpu_s390x_exec(CPUState *cpu);
 422
 423 /* you can call this signal handler from your SIGBUS and SIGSEGV
 424    signal handlers to inform the virtual CPU of exceptions. non zero
 425    is returned if the signal was handled by the virtual CPU.  */
 426 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 427                            void *puc);
 428 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 429                               int mmu_idx);
 430
 431 #include "ioinst.h"
 432
 433
 434 #ifndef CONFIG_USER_ONLY
 435 void do_restart_interrupt(CPUS390XState *env);
 436
 437 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 438                                        uint8_t *ar)
 439 {
 440     hwaddr addr = 0;
 441     uint8_t reg;
 442
 443     reg = ipb >> 28;
 444     if (reg > 0) {
 445         addr = env->regs[reg];
 446     }
 447     addr += (ipb >> 16) & 0xfff;
 448     if (ar) {
 449         *ar = reg;
 450     }
 451
 452     return addr;
 453 }
 454
 455 /* Base/displacement are at the same locations. */
 456 #define decode_basedisp_rs decode_basedisp_s
 457
 458 /* helper functions for run_on_cpu() */
 459 static inline void s390_do_cpu_reset(void *arg)
 460 {
 461     CPUState *cs = arg;
 462     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 463
 464     scc->cpu_reset(cs);
 465 }
 466 static inline void s390_do_cpu_full_reset(void *arg)
 467 {
 468     CPUState *cs = arg;
 469
 470     cpu_reset(cs);
 471 }
 472
 473 void s390x_tod_timer(void *opaque);
 474 void s390x_cpu_timer(void *opaque);
 475
 476 int s390_virtio_hypercall(CPUS390XState *env);
 477
 478 #ifdef CONFIG_KVM
 479 void kvm_s390_service_interrupt(uint32_t parm);
 480 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 481 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 482 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 483 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 484 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 485                     int len, bool is_write);
 486 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 487 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 488 #else
 489 static inline void kvm_s390_service_interrupt(uint32_t parm)
 490 {
 491 }
 492 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 493 {
 494     return -ENOSYS;
 495 }
 496 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 497 {
 498     return -ENOSYS;
 499 }
 500 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 501                                   void *hostbuf, int len, bool is_write)
 502 {
 503     return -ENOSYS;
 504 }
 505 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 506                                              uint64_t te_code)
 507 {
 508 }
 509 #endif
 510
 511 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 512 {
 513     if (kvm_enabled()) {
 514         return kvm_s390_get_clock(tod_high, tod_low);
 515     }
 516     /* Fixme TCG */
 517     *tod_high = 0;
 518     *tod_low = 0;
 519     return 0;
 520 }
 521
 522 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 523 {
 524     if (kvm_enabled()) {
 525         return kvm_s390_set_clock(tod_high, tod_low);
 526     }
 527     /* Fixme TCG */
 528     return 0;
 529 }
 530
 531 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 532 unsigned int s390_cpu_halt(S390CPU *cpu);
 533 void s390_cpu_unhalt(S390CPU *cpu);
 534 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 535 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 536 {
 537     return cpu->env.cpu_state;
 538 }
 539
 540 void gtod_save(QEMUFile *f, void *opaque);
 541 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 542
 543 /* service interrupts are floating therefore we must not pass an cpustate */
 544 void s390_sclp_extint(uint32_t parm);
 545
 546 #else
 547 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 548 {
 549     return 0;
 550 }
 551
 552 static inline void s390_cpu_unhalt(S390CPU *cpu)
 553 {
 554 }
 555
 556 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 557 {
 558     return 0;
 559 }
 560 #endif
 561 void cpu_lock(void);
 562 void cpu_unlock(void);
 563
 564 typedef struct SubchDev SubchDev;
 565
 566 #ifndef CONFIG_USER_ONLY
 567 extern void subsystem_reset(void);
 568 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 569                          uint16_t schid);
 570 bool css_subch_visible(SubchDev *sch);
 571 void css_conditional_io_interrupt(SubchDev *sch);
 572 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 573 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 574 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 575 int css_do_xsch(SubchDev *sch);
 576 int css_do_csch(SubchDev *sch);
 577 int css_do_hsch(SubchDev *sch);
 578 int css_do_ssch(SubchDev *sch, ORB *orb);
 579 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 580 void css_do_tsch_update_subch(SubchDev *sch);
 581 int css_do_stcrw(CRW *crw);
 582 void css_undo_stcrw(CRW *crw);
 583 int css_do_tpi(IOIntCode *int_code, int lowcore);
 584 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 585                          int rfmt, void *buf);
 586 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 587 int css_enable_mcsse(void);
 588 int css_enable_mss(void);
 589 int css_do_rsch(SubchDev *sch);
 590 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 591 bool css_present(uint8_t cssid);
 592 #endif
 593
 594 #define cpu_init(model) CPU(cpu_s390x_init(model))
 595 #define cpu_exec cpu_s390x_exec
 596 #define cpu_signal_handler cpu_s390x_signal_handler
 597
 598 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 599 #define cpu_list s390_cpu_list
 600
 601 #include "exec/exec-all.h"
 602
 603 #define EXCP_EXT 1 /* external interrupt */
 604 #define EXCP_SVC 2 /* supervisor call (syscall) */
 605 #define EXCP_PGM 3 /* program interruption */
 606 #define EXCP_IO  7 /* I/O interrupt */
 607 #define EXCP_MCHK 8 /* machine check */
 608
 609 #define INTERRUPT_EXT        (1 << 0)
 610 #define INTERRUPT_TOD        (1 << 1)
 611 #define INTERRUPT_CPUTIMER   (1 << 2)
 612 #define INTERRUPT_IO         (1 << 3)
 613 #define INTERRUPT_MCHK       (1 << 4)
 614
 615 /* Program Status Word.  */
 616 #define S390_PSWM_REGNUM 0
 617 #define S390_PSWA_REGNUM 1
 618 /* General Purpose Registers.  */
 619 #define S390_R0_REGNUM 2
 620 #define S390_R1_REGNUM 3
 621 #define S390_R2_REGNUM 4
 622 #define S390_R3_REGNUM 5
 623 #define S390_R4_REGNUM 6
 624 #define S390_R5_REGNUM 7
 625 #define S390_R6_REGNUM 8
 626 #define S390_R7_REGNUM 9
 627 #define S390_R8_REGNUM 10
 628 #define S390_R9_REGNUM 11
 629 #define S390_R10_REGNUM 12
 630 #define S390_R11_REGNUM 13
 631 #define S390_R12_REGNUM 14
 632 #define S390_R13_REGNUM 15
 633 #define S390_R14_REGNUM 16
 634 #define S390_R15_REGNUM 17
 635 /* Total Core Registers. */
 636 #define S390_NUM_CORE_REGS 18
 637
 638 /* CC optimization */
 639
 640 enum cc_op {
 641     CC_OP_CONST0 = 0,           /* CC is 0 */
 642     CC_OP_CONST1,               /* CC is 1 */
 643     CC_OP_CONST2,               /* CC is 2 */
 644     CC_OP_CONST3,               /* CC is 3 */
 645
 646     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 647     CC_OP_STATIC,               /* CC value is env->cc_op */
 648
 649     CC_OP_NZ,                   /* env->cc_dst != 0 */
 650     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 651     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 652     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 653     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 654     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 655     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 656
 657     CC_OP_ADD_64,               /* overflow on add (64bit) */
 658     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 659     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 660     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 661     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 662     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 663     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 664     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 665
 666     CC_OP_ADD_32,               /* overflow on add (32bit) */
 667     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 668     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 669     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 670     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 671     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 672     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 673     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 674
 675     CC_OP_COMP_32,              /* complement */
 676     CC_OP_COMP_64,              /* complement */
 677
 678     CC_OP_TM_32,                /* test under mask (32bit) */
 679     CC_OP_TM_64,                /* test under mask (64bit) */
 680
 681     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 682     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 683     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 684
 685     CC_OP_ICM,                  /* insert characters under mask */
 686     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 687     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 688     CC_OP_FLOGR,                /* find leftmost one */
 689     CC_OP_MAX
 690 };
 691
 692 static const char *cc_names[] = {
 693     [CC_OP_CONST0]    = "CC_OP_CONST0",
 694     [CC_OP_CONST1]    = "CC_OP_CONST1",
 695     [CC_OP_CONST2]    = "CC_OP_CONST2",
 696     [CC_OP_CONST3]    = "CC_OP_CONST3",
 697     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 698     [CC_OP_STATIC]    = "CC_OP_STATIC",
 699     [CC_OP_NZ]        = "CC_OP_NZ",
 700     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 701     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 702     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 703     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 704     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 705     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 706     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 707     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 708     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 709     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 710     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 711     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 712     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 713     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 714     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 715     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 716     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 717     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 718     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 719     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 720     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 721     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 722     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 723     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 724     [CC_OP_TM_32]     = "CC_OP_TM_32",
 725     [CC_OP_TM_64]     = "CC_OP_TM_64",
 726     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 727     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 728     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 729     [CC_OP_ICM]       = "CC_OP_ICM",
 730     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 731     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 732     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 733 };
 734
 735 static inline const char *cc_name(int cc_op)
 736 {
 737     return cc_names[cc_op];
 738 }
 739
 740 static inline void setcc(S390CPU *cpu, uint64_t cc)
 741 {
 742     CPUS390XState *env = &cpu->env;
 743
 744     env->psw.mask &= ~(3ull << 44);
 745     env->psw.mask |= (cc & 3) << 44;
 746     env->cc_op = cc;
 747 }
 748
 749 typedef struct LowCore
 750 {
 751     /* prefix area: defined by architecture */
 752     uint32_t        ccw1[2];                  /* 0x000 */
 753     uint32_t        ccw2[4];                  /* 0x008 */
 754     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 755     uint32_t        ext_params;               /* 0x080 */
 756     uint16_t        cpu_addr;                 /* 0x084 */
 757     uint16_t        ext_int_code;             /* 0x086 */
 758     uint16_t        svc_ilen;                 /* 0x088 */
 759     uint16_t        svc_code;                 /* 0x08a */
 760     uint16_t        pgm_ilen;                 /* 0x08c */
 761     uint16_t        pgm_code;                 /* 0x08e */
 762     uint32_t        data_exc_code;            /* 0x090 */
 763     uint16_t        mon_class_num;            /* 0x094 */
 764     uint16_t        per_perc_atmid;           /* 0x096 */
 765     uint64_t        per_address;              /* 0x098 */
 766     uint8_t         exc_access_id;            /* 0x0a0 */
 767     uint8_t         per_access_id;            /* 0x0a1 */
 768     uint8_t         op_access_id;             /* 0x0a2 */
 769     uint8_t         ar_access_id;             /* 0x0a3 */
 770     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 771     uint64_t        trans_exc_code;           /* 0x0a8 */
 772     uint64_t        monitor_code;             /* 0x0b0 */
 773     uint16_t        subchannel_id;            /* 0x0b8 */
 774     uint16_t        subchannel_nr;            /* 0x0ba */
 775     uint32_t        io_int_parm;              /* 0x0bc */
 776     uint32_t        io_int_word;              /* 0x0c0 */
 777     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 778     uint32_t        stfl_fac_list;            /* 0x0c8 */
 779     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 780     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 781     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 782     uint32_t        external_damage_code;     /* 0x0f4 */
 783     uint64_t        failing_storage_address;  /* 0x0f8 */
 784     uint8_t         pad6[0x110-0x100];        /* 0x100 */
 785     uint64_t        per_breaking_event_addr;  /* 0x110 */
 786     uint8_t         pad7[0x120-0x118];        /* 0x118 */
 787     PSW             restart_old_psw;          /* 0x120 */
 788     PSW             external_old_psw;         /* 0x130 */
 789     PSW             svc_old_psw;              /* 0x140 */
 790     PSW             program_old_psw;          /* 0x150 */
 791     PSW             mcck_old_psw;             /* 0x160 */
 792     PSW             io_old_psw;               /* 0x170 */
 793     uint8_t         pad8[0x1a0-0x180];        /* 0x180 */
 794     PSW             restart_new_psw;          /* 0x1a0 */
 795     PSW             external_new_psw;         /* 0x1b0 */
 796     PSW             svc_new_psw;              /* 0x1c0 */
 797     PSW             program_new_psw;          /* 0x1d0 */
 798     PSW             mcck_new_psw;             /* 0x1e0 */
 799     PSW             io_new_psw;               /* 0x1f0 */
 800     PSW             return_psw;               /* 0x200 */
 801     uint8_t         irb[64];                  /* 0x210 */
 802     uint64_t        sync_enter_timer;         /* 0x250 */
 803     uint64_t        async_enter_timer;        /* 0x258 */
 804     uint64_t        exit_timer;               /* 0x260 */
 805     uint64_t        last_update_timer;        /* 0x268 */
 806     uint64_t        user_timer;               /* 0x270 */
 807     uint64_t        system_timer;             /* 0x278 */
 808     uint64_t        last_update_clock;        /* 0x280 */
 809     uint64_t        steal_clock;              /* 0x288 */
 810     PSW             return_mcck_psw;          /* 0x290 */
 811     uint8_t         pad9[0xc00-0x2a0];        /* 0x2a0 */
 812     /* System info area */
 813     uint64_t        save_area[16];            /* 0xc00 */
 814     uint8_t         pad10[0xd40-0xc80];       /* 0xc80 */
 815     uint64_t        kernel_stack;             /* 0xd40 */
 816     uint64_t        thread_info;              /* 0xd48 */
 817     uint64_t        async_stack;              /* 0xd50 */
 818     uint64_t        kernel_asce;              /* 0xd58 */
 819     uint64_t        user_asce;                /* 0xd60 */
 820     uint64_t        panic_stack;              /* 0xd68 */
 821     uint64_t        user_exec_asce;           /* 0xd70 */
 822     uint8_t         pad11[0xdc0-0xd78];       /* 0xd78 */
 823
 824     /* SMP info area: defined by DJB */
 825     uint64_t        clock_comparator;         /* 0xdc0 */
 826     uint64_t        ext_call_fast;            /* 0xdc8 */
 827     uint64_t        percpu_offset;            /* 0xdd0 */
 828     uint64_t        current_task;             /* 0xdd8 */
 829     uint32_t        softirq_pending;          /* 0xde0 */
 830     uint32_t        pad_0x0de4;               /* 0xde4 */
 831     uint64_t        int_clock;                /* 0xde8 */
 832     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 833
 834     /* 0xe00 is used as indicator for dump tools */
 835     /* whether the kernel died with panic() or not */
 836     uint32_t        panic_magic;              /* 0xe00 */
 837
 838     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 839
 840     /* 64 bit extparam used for pfault, diag 250 etc  */
 841     uint64_t        ext_params2;               /* 0x11B8 */
 842
 843     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 844
 845     /* System info area */
 846
 847     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 848     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 849     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 850     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 851     uint32_t        prefixreg_save_area;       /* 0x1318 */
 852     uint32_t        fpt_creg_save_area;        /* 0x131c */
 853     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 854     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 855     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 856     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 857     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 858     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 859     uint64_t        cregs_save_area[16];       /* 0x1380 */
 860
 861     /* align to the top of the prefix area */
 862
 863     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 864 } QEMU_PACKED LowCore;
 865
 866 /* STSI */
 867 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 868 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 869 #define STSI_LEVEL_1            0x0000000010000000ULL
 870 #define STSI_LEVEL_2            0x0000000020000000ULL
 871 #define STSI_LEVEL_3            0x0000000030000000ULL
 872 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 873 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 874 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 875 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 876
 877 /* Basic Machine Configuration */
 878 struct sysib_111 {
 879     uint32_t res1[8];
 880     uint8_t  manuf[16];
 881     uint8_t  type[4];
 882     uint8_t  res2[12];
 883     uint8_t  model[16];
 884     uint8_t  sequence[16];
 885     uint8_t  plant[4];
 886     uint8_t  res3[156];
 887 };
 888
 889 /* Basic Machine CPU */
 890 struct sysib_121 {
 891     uint32_t res1[80];
 892     uint8_t  sequence[16];
 893     uint8_t  plant[4];
 894     uint8_t  res2[2];
 895     uint16_t cpu_addr;
 896     uint8_t  res3[152];
 897 };
 898
 899 /* Basic Machine CPUs */
 900 struct sysib_122 {
 901     uint8_t res1[32];
 902     uint32_t capability;
 903     uint16_t total_cpus;
 904     uint16_t active_cpus;
 905     uint16_t standby_cpus;
 906     uint16_t reserved_cpus;
 907     uint16_t adjustments[2026];
 908 };
 909
 910 /* LPAR CPU */
 911 struct sysib_221 {
 912     uint32_t res1[80];
 913     uint8_t  sequence[16];
 914     uint8_t  plant[4];
 915     uint16_t cpu_id;
 916     uint16_t cpu_addr;
 917     uint8_t  res3[152];
 918 };
 919
 920 /* LPAR CPUs */
 921 struct sysib_222 {
 922     uint32_t res1[32];
 923     uint16_t lpar_num;
 924     uint8_t  res2;
 925     uint8_t  lcpuc;
 926     uint16_t total_cpus;
 927     uint16_t conf_cpus;
 928     uint16_t standby_cpus;
 929     uint16_t reserved_cpus;
 930     uint8_t  name[8];
 931     uint32_t caf;
 932     uint8_t  res3[16];
 933     uint16_t dedicated_cpus;
 934     uint16_t shared_cpus;
 935     uint8_t  res4[180];
 936 };
 937
 938 /* VM CPUs */
 939 struct sysib_322 {
 940     uint8_t  res1[31];
 941     uint8_t  count;
 942     struct {
 943         uint8_t  res2[4];
 944         uint16_t total_cpus;
 945         uint16_t conf_cpus;
 946         uint16_t standby_cpus;
 947         uint16_t reserved_cpus;
 948         uint8_t  name[8];
 949         uint32_t caf;
 950         uint8_t  cpi[16];
 951         uint8_t res5[3];
 952         uint8_t ext_name_encoding;
 953         uint32_t res3;
 954         uint8_t uuid[16];
 955     } vm[8];
 956     uint8_t res4[1504];
 957     uint8_t ext_names[8][256];
 958 };
 959
 960 /* MMU defines */
 961 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 962 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 963 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 964 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 965 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 966 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 967 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 968 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 969 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 970 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 971 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 972 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 973
 974 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 975 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 976 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 977 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 978 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 979 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 980 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 981 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 982 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 983
 984 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 985 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 986 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 987 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 988
 989 #define _PAGE_RO        0x200            /* HW read-only bit  */
 990 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 991 #define _PAGE_RES0      0x800            /* bit must be zero  */
 992
 993 #define SK_C                    (0x1 << 1)
 994 #define SK_R                    (0x1 << 2)
 995 #define SK_F                    (0x1 << 3)
 996 #define SK_ACC_MASK             (0xf << 4)
 997
 998 /* SIGP order codes */
 999 #define SIGP_SENSE             0x01
1000 #define SIGP_EXTERNAL_CALL     0x02
1001 #define SIGP_EMERGENCY         0x03
1002 #define SIGP_START             0x04
1003 #define SIGP_STOP              0x05
1004 #define SIGP_RESTART           0x06
1005 #define SIGP_STOP_STORE_STATUS 0x09
1006 #define SIGP_INITIAL_CPU_RESET 0x0b
1007 #define SIGP_CPU_RESET         0x0c
1008 #define SIGP_SET_PREFIX        0x0d
1009 #define SIGP_STORE_STATUS_ADDR 0x0e
1010 #define SIGP_SET_ARCH          0x12
1011 #define SIGP_STORE_ADTL_STATUS 0x17
1012
1013 /* SIGP condition codes */
1014 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1015 #define SIGP_CC_STATUS_STORED       1
1016 #define SIGP_CC_BUSY                2
1017 #define SIGP_CC_NOT_OPERATIONAL     3
1018
1019 /* SIGP status bits */
1020 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
1021 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
1022 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1023 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
1024 #define SIGP_STAT_STOPPED           0x00000040UL
1025 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
1026 #define SIGP_STAT_CHECK_STOP        0x00000010UL
1027 #define SIGP_STAT_INOPERATIVE       0x00000004UL
1028 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
1029 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
1030
1031 /* SIGP SET ARCHITECTURE modes */
1032 #define SIGP_MODE_ESA_S390 0
1033 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1034 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1035
1036 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1037 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1038                   target_ulong *raddr, int *flags, bool exc);
1039 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1040 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1041                  uint64_t vr);
1042 void s390_cpu_recompute_watchpoints(CPUState *cs);
1043
1044 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1045                          int len, bool is_write);
1046
1047 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
1048         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1049 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
1050         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1051 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
1052         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1053
1054 /* The value of the TOD clock for 1.1.1970. */
1055 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1056
1057 /* Converts ns to s390's clock format */
1058 static inline uint64_t time2tod(uint64_t ns) {
1059     return (ns << 9) / 125;
1060 }
1061
1062 /* Converts s390's clock format to ns */
1063 static inline uint64_t tod2time(uint64_t t) {
1064     return (t * 125) >> 9;
1065 }
1066
1067 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1068                                   uint64_t param64)
1069 {
1070     CPUS390XState *env = &cpu->env;
1071
1072     if (env->ext_index == MAX_EXT_QUEUE - 1) {
1073         /* ugh - can't queue anymore. Let's drop. */
1074         return;
1075     }
1076
1077     env->ext_index++;
1078     assert(env->ext_index < MAX_EXT_QUEUE);
1079
1080     env->ext_queue[env->ext_index].code = code;
1081     env->ext_queue[env->ext_index].param = param;
1082     env->ext_queue[env->ext_index].param64 = param64;
1083
1084     env->pending_int |= INTERRUPT_EXT;
1085     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1086 }
1087
1088 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1089                                  uint16_t subchannel_number,
1090                                  uint32_t io_int_parm, uint32_t io_int_word)
1091 {
1092     CPUS390XState *env = &cpu->env;
1093     int isc = IO_INT_WORD_ISC(io_int_word);
1094
1095     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1096         /* ugh - can't queue anymore. Let's drop. */
1097         return;
1098     }
1099
1100     env->io_index[isc]++;
1101     assert(env->io_index[isc] < MAX_IO_QUEUE);
1102
1103     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1104     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1105     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1106     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1107
1108     env->pending_int |= INTERRUPT_IO;
1109     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1110 }
1111
1112 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1113 {
1114     CPUS390XState *env = &cpu->env;
1115
1116     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1117         /* ugh - can't queue anymore. Let's drop. */
1118         return;
1119     }
1120
1121     env->mchk_index++;
1122     assert(env->mchk_index < MAX_MCHK_QUEUE);
1123
1124     env->mchk_queue[env->mchk_index].type = 1;
1125
1126     env->pending_int |= INTERRUPT_MCHK;
1127     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1128 }
1129
1130 /* from s390-virtio-ccw */
1131 #define MEM_SECTION_SIZE             0x10000000UL
1132 #define MAX_AVAIL_SLOTS              32
1133
1134 /* fpu_helper.c */
1135 uint32_t set_cc_nz_f32(float32 v);
1136 uint32_t set_cc_nz_f64(float64 v);
1137 uint32_t set_cc_nz_f128(float128 v);
1138
1139 /* misc_helper.c */
1140 #ifndef CONFIG_USER_ONLY
1141 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1142 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1143 #endif
1144 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1145 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1146                                      uintptr_t retaddr);
1147
1148 #ifdef CONFIG_KVM
1149 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1150                            uint16_t subchannel_nr, uint32_t io_int_parm,
1151                            uint32_t io_int_word);
1152 void kvm_s390_crw_mchk(void);
1153 void kvm_s390_enable_css_support(S390CPU *cpu);
1154 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1155                                     int vq, bool assign);
1156 int kvm_s390_cpu_restart(S390CPU *cpu);
1157 int kvm_s390_get_memslot_count(KVMState *s);
1158 void kvm_s390_cmma_reset(void);
1159 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1160 void kvm_s390_reset_vcpu(S390CPU *cpu);
1161 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1162 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1163 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1164 int kvm_s390_get_ri(void);
1165 void kvm_s390_crypto_reset(void);
1166 #else
1167 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1168                                         uint16_t subchannel_nr,
1169                                         uint32_t io_int_parm,
1170                                         uint32_t io_int_word)
1171 {
1172 }
1173 static inline void kvm_s390_crw_mchk(void)
1174 {
1175 }
1176 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1177 {
1178 }
1179 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1180                                                   uint32_t sch, int vq,
1181                                                   bool assign)
1182 {
1183     return -ENOSYS;
1184 }
1185 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1186 {
1187     return -ENOSYS;
1188 }
1189 static inline void kvm_s390_cmma_reset(void)
1190 {
1191 }
1192 static inline int kvm_s390_get_memslot_count(KVMState *s)
1193 {
1194   return MAX_AVAIL_SLOTS;
1195 }
1196 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1197 {
1198     return -ENOSYS;
1199 }
1200 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1201 {
1202 }
1203 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1204                                          uint64_t *hw_limit)
1205 {
1206     return 0;
1207 }
1208 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1209 {
1210 }
1211 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1212 {
1213     return 0;
1214 }
1215 static inline int kvm_s390_get_ri(void)
1216 {
1217     return 0;
1218 }
1219 static inline void kvm_s390_crypto_reset(void)
1220 {
1221 }
1222 #endif
1223
1224 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1225 {
1226     if (kvm_enabled()) {
1227         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1228     }
1229     return 0;
1230 }
1231
1232 static inline void s390_cmma_reset(void)
1233 {
1234     if (kvm_enabled()) {
1235         kvm_s390_cmma_reset();
1236     }
1237 }
1238
1239 static inline int s390_cpu_restart(S390CPU *cpu)
1240 {
1241     if (kvm_enabled()) {
1242         return kvm_s390_cpu_restart(cpu);
1243     }
1244     return -ENOSYS;
1245 }
1246
1247 static inline int s390_get_memslot_count(KVMState *s)
1248 {
1249     if (kvm_enabled()) {
1250         return kvm_s390_get_memslot_count(s);
1251     } else {
1252         return MAX_AVAIL_SLOTS;
1253     }
1254 }
1255
1256 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1257                        uint32_t io_int_parm, uint32_t io_int_word);
1258 void s390_crw_mchk(void);
1259
1260 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1261                                               uint32_t sch_id, int vq,
1262                                               bool assign)
1263 {
1264     return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1265 }
1266
1267 static inline void s390_crypto_reset(void)
1268 {
1269     if (kvm_enabled()) {
1270         kvm_s390_crypto_reset();
1271     }
1272 }
1273
1274 #ifdef CONFIG_KVM
1275 static inline bool vregs_needed(void *opaque)
1276 {
1277     if (kvm_enabled()) {
1278         return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1279     }
1280     return 0;
1281 }
1282 static inline bool riccb_needed(void *opaque)
1283 {
1284     if (kvm_enabled()) {
1285         return kvm_s390_get_ri();
1286     }
1287     return 0;
1288 }
1289 #else
1290 static inline bool vregs_needed(void *opaque)
1291 {
1292     return 0;
1293 }
1294 static inline bool riccb_needed(void *opaque)
1295 {
1296     return 0;
1297 }
1298 #endif
1299
1300 /* machine check interruption code */
1301
1302 /* subclasses */
1303 #define MCIC_SC_SD 0x8000000000000000ULL
1304 #define MCIC_SC_PD 0x4000000000000000ULL
1305 #define MCIC_SC_SR 0x2000000000000000ULL
1306 #define MCIC_SC_CD 0x0800000000000000ULL
1307 #define MCIC_SC_ED 0x0400000000000000ULL
1308 #define MCIC_SC_DG 0x0100000000000000ULL
1309 #define MCIC_SC_W  0x0080000000000000ULL
1310 #define MCIC_SC_CP 0x0040000000000000ULL
1311 #define MCIC_SC_SP 0x0020000000000000ULL
1312 #define MCIC_SC_CK 0x0010000000000000ULL
1313
1314 /* subclass modifiers */
1315 #define MCIC_SCM_B  0x0002000000000000ULL
1316 #define MCIC_SCM_DA 0x0000000020000000ULL
1317 #define MCIC_SCM_AP 0x0000000000080000ULL
1318
1319 /* storage errors */
1320 #define MCIC_SE_SE 0x0000800000000000ULL
1321 #define MCIC_SE_SC 0x0000400000000000ULL
1322 #define MCIC_SE_KE 0x0000200000000000ULL
1323 #define MCIC_SE_DS 0x0000100000000000ULL
1324 #define MCIC_SE_IE 0x0000000080000000ULL
1325
1326 /* validity bits */
1327 #define MCIC_VB_WP 0x0000080000000000ULL
1328 #define MCIC_VB_MS 0x0000040000000000ULL
1329 #define MCIC_VB_PM 0x0000020000000000ULL
1330 #define MCIC_VB_IA 0x0000010000000000ULL
1331 #define MCIC_VB_FA 0x0000008000000000ULL
1332 #define MCIC_VB_VR 0x0000004000000000ULL
1333 #define MCIC_VB_EC 0x0000002000000000ULL
1334 #define MCIC_VB_FP 0x0000001000000000ULL
1335 #define MCIC_VB_GR 0x0000000800000000ULL
1336 #define MCIC_VB_CR 0x0000000400000000ULL
1337 #define MCIC_VB_ST 0x0000000100000000ULL
1338 #define MCIC_VB_AR 0x0000000040000000ULL
1339 #define MCIC_VB_PR 0x0000000000200000ULL
1340 #define MCIC_VB_FC 0x0000000000100000ULL
1341 #define MCIC_VB_CT 0x0000000000020000ULL
1342 #define MCIC_VB_CC 0x0000000000010000ULL
1343
1344 #endif