include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  66
  67 #include "qemu/log.h"
  68
  69 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  70 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  71                           target_ulong *data);
  72
  73 void cpu_gen_init(void);
  74 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  75
  76 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  77 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  78 TranslationBlock *tb_gen_code(CPUState *cpu,
  79                               target_ulong pc, target_ulong cs_base,
  80                               uint32_t flags,
  81                               int cflags);
  82 void cpu_exec_init(CPUState *cpu, Error **errp);
  83 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  84 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  85
  86 #if !defined(CONFIG_USER_ONLY)
  87 void cpu_reloading_memory_map(void);
  88 /**
  89  * cpu_address_space_init:
  90  * @cpu: CPU to add this address space to
  91  * @as: address space to add
  92  * @asidx: integer index of this address space
  93  *
  94  * Add the specified address space to the CPU's cpu_ases list.
  95  * The address space added with @asidx 0 is the one used for the
  96  * convenience pointer cpu->as.
  97  * The target-specific code which registers ASes is responsible
  98  * for defining what semantics address space 0, 1, 2, etc have.
  99  *
 100  * Before the first call to this function, the caller must set
 101  * cpu->num_ases to the total number of address spaces it needs
 102  * to support.
 103  *
 104  * Note that with KVM only one address space is supported.
 105  */
 106 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx);
 107 /**
 108  * cpu_get_address_space:
 109  * @cpu: CPU to get address space from
 110  * @asidx: index identifying which address space to get
 111  *
 112  * Return the requested address space of this CPU. @asidx
 113  * specifies which address space to read.
 114  */
 115 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
 116 /* cputlb.c */
 117 /**
 118  * tlb_flush_page:
 119  * @cpu: CPU whose TLB should be flushed
 120  * @addr: virtual address of page to be flushed
 121  *
 122  * Flush one page from the TLB of the specified CPU, for all
 123  * MMU indexes.
 124  */
 125 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 126 /**
 127  * tlb_flush:
 128  * @cpu: CPU whose TLB should be flushed
 129  * @flush_global: ignored
 130  *
 131  * Flush the entire TLB for the specified CPU.
 132  * The flush_global flag is in theory an indicator of whether the whole
 133  * TLB should be flushed, or only those entries not marked global.
 134  * In practice QEMU does not implement any global/not global flag for
 135  * TLB entries, and the argument is ignored.
 136  */
 137 void tlb_flush(CPUState *cpu, int flush_global);
 138 /**
 139  * tlb_flush_page_by_mmuidx:
 140  * @cpu: CPU whose TLB should be flushed
 141  * @addr: virtual address of page to be flushed
 142  * @...: list of MMU indexes to flush, terminated by a negative value
 143  *
 144  * Flush one page from the TLB of the specified CPU, for the specified
 145  * MMU indexes.
 146  */
 147 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
 148 /**
 149  * tlb_flush_by_mmuidx:
 150  * @cpu: CPU whose TLB should be flushed
 151  * @...: list of MMU indexes to flush, terminated by a negative value
 152  *
 153  * Flush all entries from the TLB of the specified CPU, for the specified
 154  * MMU indexes.
 155  */
 156 void tlb_flush_by_mmuidx(CPUState *cpu, ...);
 157 /**
 158  * tlb_set_page_with_attrs:
 159  * @cpu: CPU to add this TLB entry for
 160  * @vaddr: virtual address of page to add entry for
 161  * @paddr: physical address of the page
 162  * @attrs: memory transaction attributes
 163  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 164  * @mmu_idx: MMU index to insert TLB entry for
 165  * @size: size of the page in bytes
 166  *
 167  * Add an entry to this CPU's TLB (a mapping from virtual address
 168  * @vaddr to physical address @paddr) with the specified memory
 169  * transaction attributes. This is generally called by the target CPU
 170  * specific code after it has been called through the tlb_fill()
 171  * entry point and performed a successful page table walk to find
 172  * the physical address and attributes for the virtual address
 173  * which provoked the TLB miss.
 174  *
 175  * At most one entry for a given virtual address is permitted. Only a
 176  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 177  * used by tlb_flush_page.
 178  */
 179 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 180                              hwaddr paddr, MemTxAttrs attrs,
 181                              int prot, int mmu_idx, target_ulong size);
 182 /* tlb_set_page:
 183  *
 184  * This function is equivalent to calling tlb_set_page_with_attrs()
 185  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 186  * as a convenience for CPUs which don't use memory transaction attributes.
 187  */
 188 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 189                   hwaddr paddr, int prot,
 190                   int mmu_idx, target_ulong size);
 191 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 192 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 193                  uintptr_t retaddr);
 194 #else
 195 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 196 {
 197 }
 198
 199 static inline void tlb_flush(CPUState *cpu, int flush_global)
 200 {
 201 }
 202
 203 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 204                                             target_ulong addr, ...)
 205 {
 206 }
 207
 208 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...)
 209 {
 210 }
 211 #endif
 212
 213 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 214
 215 #define CODE_GEN_PHYS_HASH_BITS     15
 216 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 217
 218 /* Estimated block size for TB allocation.  */
 219 /* ??? The following is based on a 2015 survey of x86_64 host output.
 220    Better would seem to be some sort of dynamically sized TB array,
 221    adapting to the block sizes actually being produced.  */
 222 #if defined(CONFIG_SOFTMMU)
 223 #define CODE_GEN_AVG_BLOCK_SIZE 400
 224 #else
 225 #define CODE_GEN_AVG_BLOCK_SIZE 150
 226 #endif
 227
 228 #if defined(__arm__) || defined(_ARCH_PPC) \
 229     || defined(__x86_64__) || defined(__i386__) \
 230     || defined(__sparc__) || defined(__aarch64__) \
 231     || defined(__s390x__) || defined(__mips__) \
 232     || defined(CONFIG_TCG_INTERPRETER)
 233 /* NOTE: Direct jump patching must be atomic to be thread-safe. */
 234 #define USE_DIRECT_JUMP
 235 #endif
 236
 237 struct TranslationBlock {
 238     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 239     target_ulong cs_base; /* CS base for this block */
 240     uint32_t flags; /* flags defining in which context the code was generated */
 241     uint16_t size;      /* size of target code for this block (1 <=
 242                            size <= TARGET_PAGE_SIZE) */
 243     uint16_t icount;
 244     uint32_t cflags;    /* compile flags */
 245 #define CF_COUNT_MASK  0x7fff
 246 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 247 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 248 #define CF_USE_ICOUNT  0x20000
 249 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
 250
 251     void *tc_ptr;    /* pointer to the translated code */
 252     uint8_t *tc_search;  /* pointer to search data */
 253     /* next matching tb for physical address. */
 254     struct TranslationBlock *phys_hash_next;
 255     /* original tb when cflags has CF_NOCACHE */
 256     struct TranslationBlock *orig_tb;
 257     /* first and second physical page containing code. The lower bit
 258        of the pointer tells the index in page_next[] */
 259     struct TranslationBlock *page_next[2];
 260     tb_page_addr_t page_addr[2];
 261
 262     /* The following data are used to directly call another TB from
 263      * the code of this one. This can be done either by emitting direct or
 264      * indirect native jump instructions. These jumps are reset so that the TB
 265      * just continue its execution. The TB can be linked to another one by
 266      * setting one of the jump targets (or patching the jump instruction). Only
 267      * two of such jumps are supported.
 268      */
 269     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 270 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
 271 #ifdef USE_DIRECT_JUMP
 272     uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */
 273 #else
 274     uintptr_t jmp_target_addr[2]; /* target address for indirect jump */
 275 #endif
 276     /* Each TB has an assosiated circular list of TBs jumping to this one.
 277      * jmp_list_first points to the first TB jumping to this one.
 278      * jmp_list_next is used to point to the next TB in a list.
 279      * Since each TB can have two jumps, it can participate in two lists.
 280      * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a
 281      * TranslationBlock structure, but the two least significant bits of
 282      * them are used to encode which data field of the pointed TB should
 283      * be used to traverse the list further from that TB:
 284      * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first.
 285      * In other words, 0/1 tells which jump is used in the pointed TB,
 286      * and 2 means that this is a pointer back to the target TB of this list.
 287      */
 288     uintptr_t jmp_list_next[2];
 289     uintptr_t jmp_list_first;
 290 };
 291
 292 #include "qemu/thread.h"
 293
 294 typedef struct TBContext TBContext;
 295
 296 struct TBContext {
 297
 298     TranslationBlock *tbs;
 299     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 300     int nb_tbs;
 301     /* any access to the tbs or the page table must use this lock */
 302     QemuMutex tb_lock;
 303
 304     /* statistics */
 305     int tb_flush_count;
 306     int tb_phys_invalidate_count;
 307 };
 308
 309 void tb_free(TranslationBlock *tb);
 310 void tb_flush(CPUState *cpu);
 311 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 312
 313 #if defined(USE_DIRECT_JUMP)
 314
 315 #if defined(CONFIG_TCG_INTERPRETER)
 316 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 317 {
 318     /* patch the branch destination */
 319     atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
 320     /* no need to flush icache explicitly */
 321 }
 322 #elif defined(_ARCH_PPC)
 323 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 324 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 325 #elif defined(__i386__) || defined(__x86_64__)
 326 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 327 {
 328     /* patch the branch destination */
 329     atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
 330     /* no need to flush icache explicitly */
 331 }
 332 #elif defined(__s390x__)
 333 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 334 {
 335     /* patch the branch destination */
 336     intptr_t disp = addr - (jmp_addr - 2);
 337     atomic_set((int32_t *)jmp_addr, disp / 2);
 338     /* no need to flush icache explicitly */
 339 }
 340 #elif defined(__aarch64__)
 341 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 342 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 343 #elif defined(__arm__)
 344 void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 345 #define tb_set_jmp_target1 arm_tb_set_jmp_target
 346 #elif defined(__sparc__) || defined(__mips__)
 347 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 348 #else
 349 #error tb_set_jmp_target1 is missing
 350 #endif
 351
 352 static inline void tb_set_jmp_target(TranslationBlock *tb,
 353                                      int n, uintptr_t addr)
 354 {
 355     uint16_t offset = tb->jmp_insn_offset[n];
 356     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 357 }
 358
 359 #else
 360
 361 /* set the jump target */
 362 static inline void tb_set_jmp_target(TranslationBlock *tb,
 363                                      int n, uintptr_t addr)
 364 {
 365     tb->jmp_target_addr[n] = addr;
 366 }
 367
 368 #endif
 369
 370 static inline void tb_add_jump(TranslationBlock *tb, int n,
 371                                TranslationBlock *tb_next)
 372 {
 373     if (tb->jmp_list_next[n]) {
 374         /* Another thread has already done this while we were
 375          * outside of the lock; nothing to do in this case */
 376         return;
 377     }
 378     qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
 379                            "Linking TBs %p [" TARGET_FMT_lx
 380                            "] index %d -> %p [" TARGET_FMT_lx "]\n",
 381                            tb->tc_ptr, tb->pc, n,
 382                            tb_next->tc_ptr, tb_next->pc);
 383
 384     /* patch the native jump address */
 385     tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 386
 387     /* add in TB jmp circular list */
 388     tb->jmp_list_next[n] = tb_next->jmp_list_first;
 389     tb_next->jmp_list_first = (uintptr_t)tb | n;
 390 }
 391
 392 /* GETRA is the true target of the return instruction that we'll execute,
 393    defined here for simplicity of defining the follow-up macros.  */
 394 #if defined(CONFIG_TCG_INTERPRETER)
 395 extern uintptr_t tci_tb_ptr;
 396 # define GETRA() tci_tb_ptr
 397 #else
 398 # define GETRA() \
 399     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 400 #endif
 401
 402 /* The true return address will often point to a host insn that is part of
 403    the next translated guest insn.  Adjust the address backward to point to
 404    the middle of the call insn.  Subtracting one would do the job except for
 405    several compressed mode architectures (arm, mips) which set the low bit
 406    to indicate the compressed mode; subtracting two works around that.  It
 407    is also the case that there are no host isas that contain a call insn
 408    smaller than 4 bytes, so we don't worry about special-casing this.  */
 409 #define GETPC_ADJ   2
 410
 411 #define GETPC()  (GETRA() - GETPC_ADJ)
 412
 413 #if !defined(CONFIG_USER_ONLY)
 414
 415 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 416                                      hwaddr index, MemTxAttrs attrs);
 417
 418 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 419               uintptr_t retaddr);
 420
 421 #endif
 422
 423 #if defined(CONFIG_USER_ONLY)
 424 void mmap_lock(void);
 425 void mmap_unlock(void);
 426
 427 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 428 {
 429     return addr;
 430 }
 431 #else
 432 static inline void mmap_lock(void) {}
 433 static inline void mmap_unlock(void) {}
 434
 435 /* cputlb.c */
 436 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 437
 438 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 439 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 440
 441 /* exec.c */
 442 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
 443
 444 MemoryRegionSection *
 445 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 446                                   hwaddr *xlat, hwaddr *plen);
 447 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 448                                        MemoryRegionSection *section,
 449                                        target_ulong vaddr,
 450                                        hwaddr paddr, hwaddr xlat,
 451                                        int prot,
 452                                        target_ulong *address);
 453 bool memory_region_is_unassigned(MemoryRegion *mr);
 454
 455 #endif
 456
 457 /* vl.c */
 458 extern int singlestep;
 459
 460 /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */
 461 extern CPUState *tcg_current_cpu;
 462 extern bool exit_request;
 463
 464 #endif