user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "translate-all.h"
  26
  27 #undef EAX
  28 #undef ECX
  29 #undef EDX
  30 #undef EBX
  31 #undef ESP
  32 #undef EBP
  33 #undef ESI
  34 #undef EDI
  35 #undef EIP
  36 #ifdef __linux__
  37 #include <sys/ucontext.h>
  38 #endif
  39
  40 //#define DEBUG_SIGNAL
  41
  42 static void exception_action(CPUState *cpu)
  43 {
  44 #if defined(TARGET_I386)
  45     X86CPU *x86_cpu = X86_CPU(cpu);
  46     CPUX86State *env1 = &x86_cpu->env;
  47
  48     raise_exception_err(env1, cpu->exception_index, env1->error_code);
  49 #else
  50     cpu_loop_exit(cpu);
  51 #endif
  52 }
  53
  54 /* exit the current TB from a signal handler. The host registers are
  55    restored in a state compatible with the CPU emulator
  56  */
  57 void cpu_resume_from_signal(CPUState *cpu, void *puc)
  58 {
  59 #ifdef __linux__
  60     struct ucontext *uc = puc;
  61 #elif defined(__OpenBSD__)
  62     struct sigcontext *uc = puc;
  63 #endif
  64
  65     if (puc) {
  66         /* XXX: use siglongjmp ? */
  67 #ifdef __linux__
  68 #ifdef __ia64
  69         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  70 #else
  71         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  72 #endif
  73 #elif defined(__OpenBSD__)
  74         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  75 #endif
  76     }
  77     cpu->exception_index = -1;
  78     siglongjmp(cpu->jmp_env, 1);
  79 }
  80
  81 /* 'pc' is the host PC at which the exception was raised. 'address' is
  82    the effective address of the memory exception. 'is_write' is 1 if a
  83    write caused the exception and otherwise 0'. 'old_set' is the
  84    signal set which should be restored */
  85 static inline int handle_cpu_signal(uintptr_t pc, void *ptr,
  86                                     int is_write, sigset_t *old_set,
  87                                     void *puc)
  88 {
  89     uintptr_t address = (uintptr_t)ptr;
  90     CPUState *cpu;
  91     CPUClass *cc;
  92     int ret;
  93
  94 #if defined(DEBUG_SIGNAL)
  95     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  96            pc, address, is_write, *(unsigned long *)old_set);
  97 #endif
  98     /* XXX: locking issue */
  99     if (is_write && h2g_valid(address)
 100         && page_unprotect(h2g(address), pc, puc)) {
 101         return 1;
 102     }
 103
 104     /* Convert forcefully to guest address space, invalid addresses
 105        are still valid segv ones */
 106     address = h2g_nocheck(address);
 107
 108     cpu = current_cpu;
 109     cc = CPU_GET_CLASS(cpu);
 110     /* see if it is an MMU fault */
 111     g_assert(cc->handle_mmu_fault);
 112     ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
 113     if (ret < 0) {
 114         return 0; /* not an MMU fault */
 115     }
 116     if (ret == 0) {
 117         return 1; /* the MMU fault was handled without causing real CPU fault */
 118     }
 119     /* now we have a real cpu fault */
 120     cpu_restore_state(cpu, pc);
 121
 122     /* we restore the process signal mask as the sigreturn should
 123        do it (XXX: use sigsetjmp) */
 124     sigprocmask(SIG_SETMASK, old_set, NULL);
 125     exception_action(cpu);
 126
 127     /* never comes here */
 128     return 1;
 129 }
 130
 131 #if defined(__i386__)
 132
 133 #if defined(__APPLE__)
 134 #include <sys/ucontext.h>
 135
 136 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 137 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 138 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 139 #define MASK_sig(context)    ((context)->uc_sigmask)
 140 #elif defined(__NetBSD__)
 141 #include <ucontext.h>
 142
 143 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 144 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 145 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 146 #define MASK_sig(context)    ((context)->uc_sigmask)
 147 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 148 #include <ucontext.h>
 149
 150 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 151 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 152 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 153 #define MASK_sig(context)    ((context)->uc_sigmask)
 154 #elif defined(__OpenBSD__)
 155 #define EIP_sig(context)     ((context)->sc_eip)
 156 #define TRAP_sig(context)    ((context)->sc_trapno)
 157 #define ERROR_sig(context)   ((context)->sc_err)
 158 #define MASK_sig(context)    ((context)->sc_mask)
 159 #else
 160 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 161 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 162 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 163 #define MASK_sig(context)    ((context)->uc_sigmask)
 164 #endif
 165
 166 int cpu_signal_handler(int host_signum, void *pinfo,
 167                        void *puc)
 168 {
 169     siginfo_t *info = pinfo;
 170 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 171     ucontext_t *uc = puc;
 172 #elif defined(__OpenBSD__)
 173     struct sigcontext *uc = puc;
 174 #else
 175     struct ucontext *uc = puc;
 176 #endif
 177     uintptr_t pc;
 178     int trapno;
 179
 180 #ifndef REG_EIP
 181 /* for glibc 2.1 */
 182 #define REG_EIP    EIP
 183 #define REG_ERR    ERR
 184 #define REG_TRAPNO TRAPNO
 185 #endif
 186     pc = EIP_sig(uc);
 187     trapno = TRAP_sig(uc);
 188     return handle_cpu_signal(pc, info->si_addr,
 189                              trapno == 0xe ?
 190                              (ERROR_sig(uc) >> 1) & 1 : 0,
 191                              &MASK_sig(uc), puc);
 192 }
 193
 194 #elif defined(__x86_64__)
 195
 196 #ifdef __NetBSD__
 197 #define PC_sig(context)       _UC_MACHINE_PC(context)
 198 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 199 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 200 #define MASK_sig(context)     ((context)->uc_sigmask)
 201 #elif defined(__OpenBSD__)
 202 #define PC_sig(context)       ((context)->sc_rip)
 203 #define TRAP_sig(context)     ((context)->sc_trapno)
 204 #define ERROR_sig(context)    ((context)->sc_err)
 205 #define MASK_sig(context)     ((context)->sc_mask)
 206 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 207 #include <ucontext.h>
 208
 209 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 210 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 211 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 212 #define MASK_sig(context)     ((context)->uc_sigmask)
 213 #else
 214 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 215 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 216 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 217 #define MASK_sig(context)     ((context)->uc_sigmask)
 218 #endif
 219
 220 int cpu_signal_handler(int host_signum, void *pinfo,
 221                        void *puc)
 222 {
 223     siginfo_t *info = pinfo;
 224     uintptr_t pc;
 225 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 226     ucontext_t *uc = puc;
 227 #elif defined(__OpenBSD__)
 228     struct sigcontext *uc = puc;
 229 #else
 230     struct ucontext *uc = puc;
 231 #endif
 232
 233     pc = PC_sig(uc);
 234     return handle_cpu_signal(pc, info->si_addr,
 235                              TRAP_sig(uc) == 0xe ?
 236                              (ERROR_sig(uc) >> 1) & 1 : 0,
 237                              &MASK_sig(uc), puc);
 238 }
 239
 240 #elif defined(_ARCH_PPC)
 241
 242 /***********************************************************************
 243  * signal context platform-specific definitions
 244  * From Wine
 245  */
 246 #ifdef linux
 247 /* All Registers access - only for local access */
 248 #define REG_sig(reg_name, context)              \
 249     ((context)->uc_mcontext.regs->reg_name)
 250 /* Gpr Registers access  */
 251 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 252 /* Program counter */
 253 #define IAR_sig(context)                       REG_sig(nip, context)
 254 /* Machine State Register (Supervisor) */
 255 #define MSR_sig(context)                       REG_sig(msr, context)
 256 /* Count register */
 257 #define CTR_sig(context)                       REG_sig(ctr, context)
 258 /* User's integer exception register */
 259 #define XER_sig(context)                       REG_sig(xer, context)
 260 /* Link register */
 261 #define LR_sig(context)                        REG_sig(link, context)
 262 /* Condition register */
 263 #define CR_sig(context)                        REG_sig(ccr, context)
 264
 265 /* Float Registers access  */
 266 #define FLOAT_sig(reg_num, context)                                     \
 267     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 268 #define FPSCR_sig(context) \
 269     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 270 /* Exception Registers access */
 271 #define DAR_sig(context)                       REG_sig(dar, context)
 272 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 273 #define TRAP_sig(context)                      REG_sig(trap, context)
 274 #endif /* linux */
 275
 276 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 277 #include <ucontext.h>
 278 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 279 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 280 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 281 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 282 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 283 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 284 /* Exception Registers access */
 285 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 286 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 287 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 288 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 289
 290 #ifdef __APPLE__
 291 #include <sys/ucontext.h>
 292 typedef struct ucontext SIGCONTEXT;
 293 /* All Registers access - only for local access */
 294 #define REG_sig(reg_name, context)              \
 295     ((context)->uc_mcontext->ss.reg_name)
 296 #define FLOATREG_sig(reg_name, context)         \
 297     ((context)->uc_mcontext->fs.reg_name)
 298 #define EXCEPREG_sig(reg_name, context)         \
 299     ((context)->uc_mcontext->es.reg_name)
 300 #define VECREG_sig(reg_name, context)           \
 301     ((context)->uc_mcontext->vs.reg_name)
 302 /* Gpr Registers access */
 303 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 304 /* Program counter */
 305 #define IAR_sig(context)                       REG_sig(srr0, context)
 306 /* Machine State Register (Supervisor) */
 307 #define MSR_sig(context)                       REG_sig(srr1, context)
 308 #define CTR_sig(context)                       REG_sig(ctr, context)
 309 /* Link register */
 310 #define XER_sig(context)                       REG_sig(xer, context)
 311 /* User's integer exception register */
 312 #define LR_sig(context)                        REG_sig(lr, context)
 313 /* Condition register */
 314 #define CR_sig(context)                        REG_sig(cr, context)
 315 /* Float Registers access */
 316 #define FLOAT_sig(reg_num, context)             \
 317     FLOATREG_sig(fpregs[reg_num], context)
 318 #define FPSCR_sig(context)                      \
 319     ((double)FLOATREG_sig(fpscr, context))
 320 /* Exception Registers access */
 321 /* Fault registers for coredump */
 322 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 323 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 324 /* number of powerpc exception taken */
 325 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 326 #endif /* __APPLE__ */
 327
 328 int cpu_signal_handler(int host_signum, void *pinfo,
 329                        void *puc)
 330 {
 331     siginfo_t *info = pinfo;
 332 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 333     ucontext_t *uc = puc;
 334 #else
 335     struct ucontext *uc = puc;
 336 #endif
 337     uintptr_t pc;
 338     int is_write;
 339
 340     pc = IAR_sig(uc);
 341     is_write = 0;
 342 #if 0
 343     /* ppc 4xx case */
 344     if (DSISR_sig(uc) & 0x00800000) {
 345         is_write = 1;
 346     }
 347 #else
 348     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 349         is_write = 1;
 350     }
 351 #endif
 352     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 353 }
 354
 355 #elif defined(__alpha__)
 356
 357 int cpu_signal_handler(int host_signum, void *pinfo,
 358                            void *puc)
 359 {
 360     siginfo_t *info = pinfo;
 361     struct ucontext *uc = puc;
 362     uint32_t *pc = uc->uc_mcontext.sc_pc;
 363     uint32_t insn = *pc;
 364     int is_write = 0;
 365
 366     /* XXX: need kernel patch to get write flag faster */
 367     switch (insn >> 26) {
 368     case 0x0d: /* stw */
 369     case 0x0e: /* stb */
 370     case 0x0f: /* stq_u */
 371     case 0x24: /* stf */
 372     case 0x25: /* stg */
 373     case 0x26: /* sts */
 374     case 0x27: /* stt */
 375     case 0x2c: /* stl */
 376     case 0x2d: /* stq */
 377     case 0x2e: /* stl_c */
 378     case 0x2f: /* stq_c */
 379         is_write = 1;
 380     }
 381
 382     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 383 }
 384 #elif defined(__sparc__)
 385
 386 int cpu_signal_handler(int host_signum, void *pinfo,
 387                        void *puc)
 388 {
 389     siginfo_t *info = pinfo;
 390     int is_write;
 391     uint32_t insn;
 392 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 393     uint32_t *regs = (uint32_t *)(info + 1);
 394     void *sigmask = (regs + 20);
 395     /* XXX: is there a standard glibc define ? */
 396     uintptr_t pc = regs[1];
 397 #else
 398 #ifdef __linux__
 399     struct sigcontext *sc = puc;
 400     uintptr_t pc = sc->sigc_regs.tpc;
 401     void *sigmask = (void *)sc->sigc_mask;
 402 #elif defined(__OpenBSD__)
 403     struct sigcontext *uc = puc;
 404     uintptr_t pc = uc->sc_pc;
 405     void *sigmask = (void *)(long)uc->sc_mask;
 406 #elif defined(__NetBSD__)
 407     ucontext_t *uc = puc;
 408     unsigned long pc = _UC_MACHINE_PC(uc);
 409     void *sigmask = (void *)&uc->uc_sigmask;
 410 #endif
 411 #endif
 412
 413     /* XXX: need kernel patch to get write flag faster */
 414     is_write = 0;
 415     insn = *(uint32_t *)pc;
 416     if ((insn >> 30) == 3) {
 417         switch ((insn >> 19) & 0x3f) {
 418         case 0x05: /* stb */
 419         case 0x15: /* stba */
 420         case 0x06: /* sth */
 421         case 0x16: /* stha */
 422         case 0x04: /* st */
 423         case 0x14: /* sta */
 424         case 0x07: /* std */
 425         case 0x17: /* stda */
 426         case 0x0e: /* stx */
 427         case 0x1e: /* stxa */
 428         case 0x24: /* stf */
 429         case 0x34: /* stfa */
 430         case 0x27: /* stdf */
 431         case 0x37: /* stdfa */
 432         case 0x26: /* stqf */
 433         case 0x36: /* stqfa */
 434         case 0x25: /* stfsr */
 435         case 0x3c: /* casa */
 436         case 0x3e: /* casxa */
 437             is_write = 1;
 438             break;
 439         }
 440     }
 441     return handle_cpu_signal(pc, info->si_addr, is_write, sigmask, NULL);
 442 }
 443
 444 #elif defined(__arm__)
 445
 446 #if defined(__NetBSD__)
 447 #include <ucontext.h>
 448 #endif
 449
 450 int cpu_signal_handler(int host_signum, void *pinfo,
 451                        void *puc)
 452 {
 453     siginfo_t *info = pinfo;
 454 #if defined(__NetBSD__)
 455     ucontext_t *uc = puc;
 456 #else
 457     struct ucontext *uc = puc;
 458 #endif
 459     uintptr_t pc;
 460     int is_write;
 461
 462 #if defined(__NetBSD__)
 463     pc = uc->uc_mcontext.__gregs[_REG_R15];
 464 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 465     pc = uc->uc_mcontext.gregs[R15];
 466 #else
 467     pc = uc->uc_mcontext.arm_pc;
 468 #endif
 469
 470     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 471      * later processor; on v5 we will always report this as a read).
 472      */
 473     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 474     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 475 }
 476
 477 #elif defined(__aarch64__)
 478
 479 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 480 {
 481     siginfo_t *info = pinfo;
 482     struct ucontext *uc = puc;
 483     uintptr_t pc = uc->uc_mcontext.pc;
 484     uint32_t insn = *(uint32_t *)pc;
 485     bool is_write;
 486
 487     /* XXX: need kernel patch to get write flag faster.  */
 488     is_write = (   (insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 489                 || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 490                 || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 491                 || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 492                 || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 493                 || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 494                 || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 495                 /* Ingore bits 10, 11 & 21, controlling indexing.  */
 496                 || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 497                 || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 498                 /* Ignore bits 23 & 24, controlling indexing.  */
 499                 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 500
 501     return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
 502                              is_write, &uc->uc_sigmask, puc);
 503 }
 504
 505 #elif defined(__mc68000)
 506
 507 int cpu_signal_handler(int host_signum, void *pinfo,
 508                        void *puc)
 509 {
 510     siginfo_t *info = pinfo;
 511     struct ucontext *uc = puc;
 512     uintptr_t pc;
 513     int is_write;
 514
 515     pc = uc->uc_mcontext.gregs[16];
 516     /* XXX: compute is_write */
 517     is_write = 0;
 518     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 519 }
 520
 521 #elif defined(__ia64)
 522
 523 #ifndef __ISR_VALID
 524   /* This ought to be in <bits/siginfo.h>... */
 525 # define __ISR_VALID    1
 526 #endif
 527
 528 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 529 {
 530     siginfo_t *info = pinfo;
 531     struct ucontext *uc = puc;
 532     unsigned long ip;
 533     int is_write = 0;
 534
 535     ip = uc->uc_mcontext.sc_ip;
 536     switch (host_signum) {
 537     case SIGILL:
 538     case SIGFPE:
 539     case SIGSEGV:
 540     case SIGBUS:
 541     case SIGTRAP:
 542         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 543             /* ISR.W (write-access) is bit 33:  */
 544             is_write = (info->si_isr >> 33) & 1;
 545         }
 546         break;
 547
 548     default:
 549         break;
 550     }
 551     return handle_cpu_signal(ip, info->si_addr, is_write,
 552                              (sigset_t *)&uc->uc_sigmask, puc);
 553 }
 554
 555 #elif defined(__s390__)
 556
 557 int cpu_signal_handler(int host_signum, void *pinfo,
 558                        void *puc)
 559 {
 560     siginfo_t *info = pinfo;
 561     struct ucontext *uc = puc;
 562     uintptr_t pc;
 563     uint16_t *pinsn;
 564     int is_write = 0;
 565
 566     pc = uc->uc_mcontext.psw.addr;
 567
 568     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 569        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 570        from the hardware which does in fact contain the is_write value.
 571        The rt signal handler, as far as I can tell, does not give this value
 572        at all.  Not that we could get to it from here even if it were.  */
 573     /* ??? This is not even close to complete, since it ignores all
 574        of the read-modify-write instructions.  */
 575     pinsn = (uint16_t *)pc;
 576     switch (pinsn[0] >> 8) {
 577     case 0x50: /* ST */
 578     case 0x42: /* STC */
 579     case 0x40: /* STH */
 580         is_write = 1;
 581         break;
 582     case 0xc4: /* RIL format insns */
 583         switch (pinsn[0] & 0xf) {
 584         case 0xf: /* STRL */
 585         case 0xb: /* STGRL */
 586         case 0x7: /* STHRL */
 587             is_write = 1;
 588         }
 589         break;
 590     case 0xe3: /* RXY format insns */
 591         switch (pinsn[2] & 0xff) {
 592         case 0x50: /* STY */
 593         case 0x24: /* STG */
 594         case 0x72: /* STCY */
 595         case 0x70: /* STHY */
 596         case 0x8e: /* STPQ */
 597         case 0x3f: /* STRVH */
 598         case 0x3e: /* STRV */
 599         case 0x2f: /* STRVG */
 600             is_write = 1;
 601         }
 602         break;
 603     }
 604     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 605 }
 606
 607 #elif defined(__mips__)
 608
 609 int cpu_signal_handler(int host_signum, void *pinfo,
 610                        void *puc)
 611 {
 612     siginfo_t *info = pinfo;
 613     struct ucontext *uc = puc;
 614     greg_t pc = uc->uc_mcontext.pc;
 615     int is_write;
 616
 617     /* XXX: compute is_write */
 618     is_write = 0;
 619     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 620 }
 621
 622 #elif defined(__hppa__)
 623
 624 int cpu_signal_handler(int host_signum, void *pinfo,
 625                        void *puc)
 626 {
 627     siginfo_t *info = pinfo;
 628     struct ucontext *uc = puc;
 629     uintptr_t pc = uc->uc_mcontext.sc_iaoq[0];
 630     uint32_t insn = *(uint32_t *)pc;
 631     int is_write = 0;
 632
 633     /* XXX: need kernel patch to get write flag faster.  */
 634     switch (insn >> 26) {
 635     case 0x1a: /* STW */
 636     case 0x19: /* STH */
 637     case 0x18: /* STB */
 638     case 0x1b: /* STWM */
 639         is_write = 1;
 640         break;
 641
 642     case 0x09: /* CSTWX, FSTWX, FSTWS */
 643     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 644         /* Distinguish from coprocessor load ... */
 645         is_write = (insn >> 9) & 1;
 646         break;
 647
 648     case 0x03:
 649         switch ((insn >> 6) & 15) {
 650         case 0xa: /* STWS */
 651         case 0x9: /* STHS */
 652         case 0x8: /* STBS */
 653         case 0xe: /* STWAS */
 654         case 0xc: /* STBYS */
 655             is_write = 1;
 656         }
 657         break;
 658     }
 659
 660     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 661 }
 662
 663 #else
 664
 665 #error host CPU specific signal handler needed
 666
 667 #endif