2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_TCG_OPTIMIZATIONS
28 #include "qemu/osdep.h"
30 /* Define to jump the ELF file used to communicate with GDB. */
33 #include "qemu/error-report.h"
34 #include "qemu/cutils.h"
35 #include "qemu/host-utils.h"
36 #include "qemu/qemu-print.h"
37 #include "qemu/cacheflush.h"
38 #include "qemu/cacheinfo.h"
39 #include "qemu/timer.h"
41 /* Note: the long term plan is to reduce the dependencies on the QEMU
42 CPU definitions. Currently they are used for qemu_ld/st
44 #define NO_CPU_IO_DEFS
46 #include "exec/exec-all.h"
47 #include "tcg/tcg-op.h"
49 #if UINTPTR_MAX == UINT32_MAX
50 # define ELF_CLASS ELFCLASS32
52 # define ELF_CLASS ELFCLASS64
55 # define ELF_DATA ELFDATA2MSB
57 # define ELF_DATA ELFDATA2LSB
62 #include "tcg/tcg-ldst.h"
63 #include "tcg/tcg-temp-internal.h"
64 #include "tcg-internal.h"
65 #include "accel/tcg/perf.h"
67 /* Forward declarations for functions declared in tcg-target.c.inc and
69 static void tcg_target_init(TCGContext
*s
);
70 static void tcg_target_qemu_prologue(TCGContext
*s
);
71 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
72 intptr_t value
, intptr_t addend
);
74 /* The CIE and FDE header definitions will be common to all hosts. */
76 uint32_t len
__attribute__((aligned((sizeof(void *)))));
82 uint8_t return_column
;
85 typedef struct QEMU_PACKED
{
86 uint32_t len
__attribute__((aligned((sizeof(void *)))));
90 } DebugFrameFDEHeader
;
92 typedef struct QEMU_PACKED
{
94 DebugFrameFDEHeader fde
;
97 typedef struct TCGLabelQemuLdst
{
98 bool is_ld
; /* qemu_ld: true, qemu_st: false */
100 TCGType type
; /* result type of a load */
101 TCGReg addrlo_reg
; /* reg index for low word of guest virtual addr */
102 TCGReg addrhi_reg
; /* reg index for high word of guest virtual addr */
103 TCGReg datalo_reg
; /* reg index for low word to be loaded or stored */
104 TCGReg datahi_reg
; /* reg index for high word to be loaded or stored */
105 const tcg_insn_unit
*raddr
; /* addr of the next IR of qemu_ld/st IR */
106 tcg_insn_unit
*label_ptr
[2]; /* label pointers to be updated */
107 QSIMPLEQ_ENTRY(TCGLabelQemuLdst
) next
;
110 static void tcg_register_jit_int(const void *buf
, size_t size
,
111 const void *debug_frame
,
112 size_t debug_frame_size
)
113 __attribute__((unused
));
115 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
116 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
118 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
119 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
120 TCGReg ret
, tcg_target_long arg
);
121 static void tcg_out_ext8s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
122 static void tcg_out_ext16s(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
123 static void tcg_out_ext8u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
124 static void tcg_out_ext16u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
125 static void tcg_out_ext32s(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
126 static void tcg_out_ext32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
127 static void tcg_out_exts_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
128 static void tcg_out_extu_i32_i64(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
129 static void tcg_out_extrl_i64_i32(TCGContext
*s
, TCGReg ret
, TCGReg arg
);
130 static void tcg_out_addi_ptr(TCGContext
*s
, TCGReg
, TCGReg
, tcg_target_long
);
131 static bool tcg_out_xchg(TCGContext
*s
, TCGType type
, TCGReg r1
, TCGReg r2
);
132 static void tcg_out_exit_tb(TCGContext
*s
, uintptr_t arg
);
133 static void tcg_out_goto_tb(TCGContext
*s
, int which
);
134 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
135 const TCGArg args
[TCG_MAX_OP_ARGS
],
136 const int const_args
[TCG_MAX_OP_ARGS
]);
137 #if TCG_TARGET_MAYBE_vec
138 static bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
139 TCGReg dst
, TCGReg src
);
140 static bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
141 TCGReg dst
, TCGReg base
, intptr_t offset
);
142 static void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
143 TCGReg dst
, int64_t arg
);
144 static void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
145 unsigned vecl
, unsigned vece
,
146 const TCGArg args
[TCG_MAX_OP_ARGS
],
147 const int const_args
[TCG_MAX_OP_ARGS
]);
149 static inline bool tcg_out_dup_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
150 TCGReg dst
, TCGReg src
)
152 g_assert_not_reached();
154 static inline bool tcg_out_dupm_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
155 TCGReg dst
, TCGReg base
, intptr_t offset
)
157 g_assert_not_reached();
159 static inline void tcg_out_dupi_vec(TCGContext
*s
, TCGType type
, unsigned vece
,
160 TCGReg dst
, int64_t arg
)
162 g_assert_not_reached();
164 static inline void tcg_out_vec_op(TCGContext
*s
, TCGOpcode opc
,
165 unsigned vecl
, unsigned vece
,
166 const TCGArg args
[TCG_MAX_OP_ARGS
],
167 const int const_args
[TCG_MAX_OP_ARGS
])
169 g_assert_not_reached();
172 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
174 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
175 TCGReg base
, intptr_t ofs
);
176 static void tcg_out_call(TCGContext
*s
, const tcg_insn_unit
*target
,
177 const TCGHelperInfo
*info
);
178 static TCGReg
tcg_target_call_oarg_reg(TCGCallReturnKind kind
, int slot
);
179 static bool tcg_target_const_match(int64_t val
, TCGType type
, int ct
);
180 #ifdef TCG_TARGET_NEED_LDST_LABELS
181 static int tcg_out_ldst_finalize(TCGContext
*s
);
184 typedef struct TCGLdstHelperParam
{
185 TCGReg (*ra_gen
)(TCGContext
*s
, const TCGLabelQemuLdst
*l
, int arg_reg
);
188 } TCGLdstHelperParam
;
190 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
191 const TCGLdstHelperParam
*p
)
192 __attribute__((unused
));
193 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
194 bool load_sign
, const TCGLdstHelperParam
*p
)
195 __attribute__((unused
));
196 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*l
,
197 const TCGLdstHelperParam
*p
)
198 __attribute__((unused
));
200 TCGContext tcg_init_ctx
;
201 __thread TCGContext
*tcg_ctx
;
203 TCGContext
**tcg_ctxs
;
204 unsigned int tcg_cur_ctxs
;
205 unsigned int tcg_max_ctxs
;
206 TCGv_env cpu_env
= 0;
207 const void *tcg_code_gen_epilogue
;
208 uintptr_t tcg_splitwx_diff
;
210 #ifndef CONFIG_TCG_INTERPRETER
211 tcg_prologue_fn
*tcg_qemu_tb_exec
;
214 static TCGRegSet tcg_target_available_regs
[TCG_TYPE_COUNT
];
215 static TCGRegSet tcg_target_call_clobber_regs
;
217 #if TCG_TARGET_INSN_UNIT_SIZE == 1
218 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
223 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
230 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
231 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
233 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
236 tcg_insn_unit
*p
= s
->code_ptr
;
237 memcpy(p
, &v
, sizeof(v
));
238 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
242 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
245 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
248 memcpy(p
, &v
, sizeof(v
));
253 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
254 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
256 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
259 tcg_insn_unit
*p
= s
->code_ptr
;
260 memcpy(p
, &v
, sizeof(v
));
261 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
265 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
268 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
271 memcpy(p
, &v
, sizeof(v
));
276 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
277 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
279 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
282 tcg_insn_unit
*p
= s
->code_ptr
;
283 memcpy(p
, &v
, sizeof(v
));
284 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
288 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
291 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
294 memcpy(p
, &v
, sizeof(v
));
299 /* label relocation processing */
301 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
302 TCGLabel
*l
, intptr_t addend
)
304 TCGRelocation
*r
= tcg_malloc(sizeof(TCGRelocation
));
309 QSIMPLEQ_INSERT_TAIL(&l
->relocs
, r
, next
);
312 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
)
314 tcg_debug_assert(!l
->has_value
);
316 l
->u
.value_ptr
= tcg_splitwx_to_rx(s
->code_ptr
);
319 TCGLabel
*gen_new_label(void)
321 TCGContext
*s
= tcg_ctx
;
322 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
324 memset(l
, 0, sizeof(TCGLabel
));
325 l
->id
= s
->nb_labels
++;
326 QSIMPLEQ_INIT(&l
->branches
);
327 QSIMPLEQ_INIT(&l
->relocs
);
329 QSIMPLEQ_INSERT_TAIL(&s
->labels
, l
, next
);
334 static bool tcg_resolve_relocs(TCGContext
*s
)
338 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
340 uintptr_t value
= l
->u
.value
;
342 QSIMPLEQ_FOREACH(r
, &l
->relocs
, next
) {
343 if (!patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
)) {
351 static void set_jmp_reset_offset(TCGContext
*s
, int which
)
354 * We will check for overflow at the end of the opcode loop in
355 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
357 s
->gen_tb
->jmp_reset_offset
[which
] = tcg_current_code_size(s
);
360 static void G_GNUC_UNUSED
set_jmp_insn_offset(TCGContext
*s
, int which
)
363 * We will check for overflow at the end of the opcode loop in
364 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
366 s
->gen_tb
->jmp_insn_offset
[which
] = tcg_current_code_size(s
);
369 static uintptr_t G_GNUC_UNUSED
get_jmp_target_addr(TCGContext
*s
, int which
)
372 * Return the read-execute version of the pointer, for the benefit
373 * of any pc-relative addressing mode.
375 return (uintptr_t)tcg_splitwx_to_rx(&s
->gen_tb
->jmp_target_addr
[which
]);
378 /* Signal overflow, starting over with fewer guest insns. */
380 void tcg_raise_tb_overflow(TCGContext
*s
)
382 siglongjmp(s
->jmp_trans
, -2);
386 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext.
387 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg.
389 * However, tcg_out_helper_load_slots reuses this field to hold an
390 * argument slot number (which may designate a argument register or an
391 * argument stack slot), converting to TCGReg once all arguments that
392 * are destined for the stack are processed.
394 typedef struct TCGMovExtend
{
403 * tcg_out_movext -- move and extend
405 * @dst_type: integral type for destination
406 * @dst: destination register
407 * @src_type: integral type for source
408 * @src_ext: extension to apply to source
409 * @src: source register
411 * Move or extend @src into @dst, depending on @src_ext and the types.
413 static void tcg_out_movext(TCGContext
*s
, TCGType dst_type
, TCGReg dst
,
414 TCGType src_type
, MemOp src_ext
, TCGReg src
)
418 tcg_out_ext8u(s
, dst
, src
);
421 tcg_out_ext8s(s
, dst_type
, dst
, src
);
424 tcg_out_ext16u(s
, dst
, src
);
427 tcg_out_ext16s(s
, dst_type
, dst
, src
);
431 if (dst_type
== TCG_TYPE_I32
) {
432 if (src_type
== TCG_TYPE_I32
) {
433 tcg_out_mov(s
, TCG_TYPE_I32
, dst
, src
);
435 tcg_out_extrl_i64_i32(s
, dst
, src
);
437 } else if (src_type
== TCG_TYPE_I32
) {
438 if (src_ext
& MO_SIGN
) {
439 tcg_out_exts_i32_i64(s
, dst
, src
);
441 tcg_out_extu_i32_i64(s
, dst
, src
);
444 if (src_ext
& MO_SIGN
) {
445 tcg_out_ext32s(s
, dst
, src
);
447 tcg_out_ext32u(s
, dst
, src
);
452 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
453 if (dst_type
== TCG_TYPE_I32
) {
454 tcg_out_extrl_i64_i32(s
, dst
, src
);
456 tcg_out_mov(s
, TCG_TYPE_I64
, dst
, src
);
460 g_assert_not_reached();
464 /* Minor variations on a theme, using a structure. */
465 static void tcg_out_movext1_new_src(TCGContext
*s
, const TCGMovExtend
*i
,
468 tcg_out_movext(s
, i
->dst_type
, i
->dst
, i
->src_type
, i
->src_ext
, src
);
471 static void tcg_out_movext1(TCGContext
*s
, const TCGMovExtend
*i
)
473 tcg_out_movext1_new_src(s
, i
, i
->src
);
477 * tcg_out_movext2 -- move and extend two pair
479 * @i1: first move description
480 * @i2: second move description
481 * @scratch: temporary register, or -1 for none
483 * As tcg_out_movext, for both @i1 and @i2, caring for overlap
484 * between the sources and destinations.
487 static void tcg_out_movext2(TCGContext
*s
, const TCGMovExtend
*i1
,
488 const TCGMovExtend
*i2
, int scratch
)
490 TCGReg src1
= i1
->src
;
491 TCGReg src2
= i2
->src
;
493 if (i1
->dst
!= src2
) {
494 tcg_out_movext1(s
, i1
);
495 tcg_out_movext1(s
, i2
);
498 if (i2
->dst
== src1
) {
499 TCGType src1_type
= i1
->src_type
;
500 TCGType src2_type
= i2
->src_type
;
502 if (tcg_out_xchg(s
, MAX(src1_type
, src2_type
), src1
, src2
)) {
503 /* The data is now in the correct registers, now extend. */
507 tcg_debug_assert(scratch
>= 0);
508 tcg_out_mov(s
, src1_type
, scratch
, src1
);
512 tcg_out_movext1_new_src(s
, i2
, src2
);
513 tcg_out_movext1_new_src(s
, i1
, src1
);
516 #define C_PFX1(P, A) P##A
517 #define C_PFX2(P, A, B) P##A##_##B
518 #define C_PFX3(P, A, B, C) P##A##_##B##_##C
519 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
520 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
521 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
523 /* Define an enumeration for the various combinations. */
525 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
526 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
527 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
528 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
530 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
531 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
532 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
533 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
535 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
537 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
538 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
539 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
540 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
543 #include "tcg-target-con-set.h"
544 } TCGConstraintSetIndex
;
546 static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode
);
562 /* Put all of the constraint sets into an array, indexed by the enum. */
564 #define C_O0_I1(I1) { .args_ct_str = { #I1 } },
565 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
566 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
567 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
569 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
570 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
571 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
572 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
574 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
576 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
577 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
578 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
579 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
581 static const TCGTargetOpDef constraint_sets
[] = {
582 #include "tcg-target-con-set.h"
600 /* Expand the enumerator to be returned from tcg_target_op_def(). */
602 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
603 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
604 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
605 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
607 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
608 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
609 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
610 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
612 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
614 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
615 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
616 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
617 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
619 #include "tcg-target.c.inc"
621 static void alloc_tcg_plugin_context(TCGContext
*s
)
624 s
->plugin_tb
= g_new0(struct qemu_plugin_tb
, 1);
625 s
->plugin_tb
->insns
=
626 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn
);
631 * All TCG threads except the parent (i.e. the one that called tcg_context_init
632 * and registered the target's TCG globals) must register with this function
633 * before initiating translation.
635 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
636 * of tcg_region_init() for the reasoning behind this.
638 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in
639 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context
640 * is not used anymore for translation once this function is called.
642 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates
643 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode.
645 #ifdef CONFIG_USER_ONLY
646 void tcg_register_thread(void)
648 tcg_ctx
= &tcg_init_ctx
;
651 void tcg_register_thread(void)
653 TCGContext
*s
= g_malloc(sizeof(*s
));
658 /* Relink mem_base. */
659 for (i
= 0, n
= tcg_init_ctx
.nb_globals
; i
< n
; ++i
) {
660 if (tcg_init_ctx
.temps
[i
].mem_base
) {
661 ptrdiff_t b
= tcg_init_ctx
.temps
[i
].mem_base
- tcg_init_ctx
.temps
;
662 tcg_debug_assert(b
>= 0 && b
< n
);
663 s
->temps
[i
].mem_base
= &s
->temps
[b
];
667 /* Claim an entry in tcg_ctxs */
668 n
= qatomic_fetch_inc(&tcg_cur_ctxs
);
669 g_assert(n
< tcg_max_ctxs
);
670 qatomic_set(&tcg_ctxs
[n
], s
);
673 alloc_tcg_plugin_context(s
);
674 tcg_region_initial_alloc(s
);
679 #endif /* !CONFIG_USER_ONLY */
681 /* pool based memory allocation */
682 void *tcg_malloc_internal(TCGContext
*s
, int size
)
687 if (size
> TCG_POOL_CHUNK_SIZE
) {
688 /* big malloc: insert a new pool (XXX: could optimize) */
689 p
= g_malloc(sizeof(TCGPool
) + size
);
691 p
->next
= s
->pool_first_large
;
692 s
->pool_first_large
= p
;
703 pool_size
= TCG_POOL_CHUNK_SIZE
;
704 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
707 if (s
->pool_current
) {
708 s
->pool_current
->next
= p
;
718 s
->pool_cur
= p
->data
+ size
;
719 s
->pool_end
= p
->data
+ p
->size
;
723 void tcg_pool_reset(TCGContext
*s
)
726 for (p
= s
->pool_first_large
; p
; p
= t
) {
730 s
->pool_first_large
= NULL
;
731 s
->pool_cur
= s
->pool_end
= NULL
;
732 s
->pool_current
= NULL
;
735 #include "exec/helper-proto.h"
737 static TCGHelperInfo all_helpers
[] = {
738 #include "exec/helper-tcg.h"
740 static GHashTable
*helper_table
;
743 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions,
744 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N.
745 * We only use these for layout in tcg_out_ld_helper_ret and
746 * tcg_out_st_helper_args, and share them between several of
747 * the helpers, with the end result that it's easier to build manually.
750 #if TCG_TARGET_REG_BITS == 32
751 # define dh_typecode_ttl dh_typecode_i32
753 # define dh_typecode_ttl dh_typecode_i64
756 static TCGHelperInfo info_helper_ld32_mmu
= {
757 .flags
= TCG_CALL_NO_WG
,
758 .typemask
= dh_typemask(ttl
, 0) /* return tcg_target_ulong */
759 | dh_typemask(env
, 1)
760 | dh_typemask(tl
, 2) /* target_ulong addr */
761 | dh_typemask(i32
, 3) /* unsigned oi */
762 | dh_typemask(ptr
, 4) /* uintptr_t ra */
765 static TCGHelperInfo info_helper_ld64_mmu
= {
766 .flags
= TCG_CALL_NO_WG
,
767 .typemask
= dh_typemask(i64
, 0) /* return uint64_t */
768 | dh_typemask(env
, 1)
769 | dh_typemask(tl
, 2) /* target_ulong addr */
770 | dh_typemask(i32
, 3) /* unsigned oi */
771 | dh_typemask(ptr
, 4) /* uintptr_t ra */
774 static TCGHelperInfo info_helper_st32_mmu
= {
775 .flags
= TCG_CALL_NO_WG
,
776 .typemask
= dh_typemask(void, 0)
777 | dh_typemask(env
, 1)
778 | dh_typemask(tl
, 2) /* target_ulong addr */
779 | dh_typemask(i32
, 3) /* uint32_t data */
780 | dh_typemask(i32
, 4) /* unsigned oi */
781 | dh_typemask(ptr
, 5) /* uintptr_t ra */
784 static TCGHelperInfo info_helper_st64_mmu
= {
785 .flags
= TCG_CALL_NO_WG
,
786 .typemask
= dh_typemask(void, 0)
787 | dh_typemask(env
, 1)
788 | dh_typemask(tl
, 2) /* target_ulong addr */
789 | dh_typemask(i64
, 3) /* uint64_t data */
790 | dh_typemask(i32
, 4) /* unsigned oi */
791 | dh_typemask(ptr
, 5) /* uintptr_t ra */
794 #ifdef CONFIG_TCG_INTERPRETER
795 static ffi_type
*typecode_to_ffi(int argmask
)
798 * libffi does not support __int128_t, so we have forced Int128
799 * to use the structure definition instead of the builtin type.
801 static ffi_type
*ffi_type_i128_elements
[3] = {
806 static ffi_type ffi_type_i128
= {
808 .alignment
= __alignof__(Int128
),
809 .type
= FFI_TYPE_STRUCT
,
810 .elements
= ffi_type_i128_elements
,
814 case dh_typecode_void
:
815 return &ffi_type_void
;
816 case dh_typecode_i32
:
817 return &ffi_type_uint32
;
818 case dh_typecode_s32
:
819 return &ffi_type_sint32
;
820 case dh_typecode_i64
:
821 return &ffi_type_uint64
;
822 case dh_typecode_s64
:
823 return &ffi_type_sint64
;
824 case dh_typecode_ptr
:
825 return &ffi_type_pointer
;
826 case dh_typecode_i128
:
827 return &ffi_type_i128
;
829 g_assert_not_reached();
832 static void init_ffi_layouts(void)
834 /* g_direct_hash/equal for direct comparisons on uint32_t. */
835 GHashTable
*ffi_table
= g_hash_table_new(NULL
, NULL
);
837 for (int i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
838 TCGHelperInfo
*info
= &all_helpers
[i
];
839 unsigned typemask
= info
->typemask
;
840 gpointer hash
= (gpointer
)(uintptr_t)typemask
;
849 cif
= g_hash_table_lookup(ffi_table
, hash
);
855 /* Ignoring the return type, find the last non-zero field. */
856 nargs
= 32 - clz32(typemask
>> 3);
857 nargs
= DIV_ROUND_UP(nargs
, 3);
858 assert(nargs
<= MAX_CALL_IARGS
);
860 ca
= g_malloc0(sizeof(*ca
) + nargs
* sizeof(ffi_type
*));
861 ca
->cif
.rtype
= typecode_to_ffi(typemask
& 7);
862 ca
->cif
.nargs
= nargs
;
865 ca
->cif
.arg_types
= ca
->args
;
866 for (int j
= 0; j
< nargs
; ++j
) {
867 int typecode
= extract32(typemask
, (j
+ 1) * 3, 3);
868 ca
->args
[j
] = typecode_to_ffi(typecode
);
872 status
= ffi_prep_cif(&ca
->cif
, FFI_DEFAULT_ABI
, nargs
,
873 ca
->cif
.rtype
, ca
->cif
.arg_types
);
874 assert(status
== FFI_OK
);
878 g_hash_table_insert(ffi_table
, hash
, (gpointer
)cif
);
881 g_hash_table_destroy(ffi_table
);
883 #endif /* CONFIG_TCG_INTERPRETER */
885 static inline bool arg_slot_reg_p(unsigned arg_slot
)
888 * Split the sizeof away from the comparison to avoid Werror from
889 * "unsigned < 0 is always false", when iarg_regs is empty.
891 unsigned nreg
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
892 return arg_slot
< nreg
;
895 static inline int arg_slot_stk_ofs(unsigned arg_slot
)
897 unsigned max
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
898 unsigned stk_slot
= arg_slot
- ARRAY_SIZE(tcg_target_call_iarg_regs
);
900 tcg_debug_assert(stk_slot
< max
);
901 return TCG_TARGET_CALL_STACK_OFFSET
+ stk_slot
* sizeof(tcg_target_long
);
904 typedef struct TCGCumulativeArgs
{
905 int arg_idx
; /* tcg_gen_callN args[] */
906 int info_in_idx
; /* TCGHelperInfo in[] */
907 int arg_slot
; /* regs+stack slot */
908 int ref_slot
; /* stack slots for references */
911 static void layout_arg_even(TCGCumulativeArgs
*cum
)
913 cum
->arg_slot
+= cum
->arg_slot
& 1;
916 static void layout_arg_1(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
,
917 TCGCallArgumentKind kind
)
919 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
921 *loc
= (TCGCallArgumentLoc
){
923 .arg_idx
= cum
->arg_idx
,
924 .arg_slot
= cum
->arg_slot
,
930 static void layout_arg_normal_n(TCGCumulativeArgs
*cum
,
931 TCGHelperInfo
*info
, int n
)
933 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
935 for (int i
= 0; i
< n
; ++i
) {
936 /* Layout all using the same arg_idx, adjusting the subindex. */
937 loc
[i
] = (TCGCallArgumentLoc
){
938 .kind
= TCG_CALL_ARG_NORMAL
,
939 .arg_idx
= cum
->arg_idx
,
941 .arg_slot
= cum
->arg_slot
+ i
,
944 cum
->info_in_idx
+= n
;
948 static void layout_arg_by_ref(TCGCumulativeArgs
*cum
, TCGHelperInfo
*info
)
950 TCGCallArgumentLoc
*loc
= &info
->in
[cum
->info_in_idx
];
951 int n
= 128 / TCG_TARGET_REG_BITS
;
953 /* The first subindex carries the pointer. */
954 layout_arg_1(cum
, info
, TCG_CALL_ARG_BY_REF
);
957 * The callee is allowed to clobber memory associated with
958 * structure pass by-reference. Therefore we must make copies.
959 * Allocate space from "ref_slot", which will be adjusted to
960 * follow the parameters on the stack.
962 loc
[0].ref_slot
= cum
->ref_slot
;
965 * Subsequent words also go into the reference slot, but
966 * do not accumulate into the regular arguments.
968 for (int i
= 1; i
< n
; ++i
) {
969 loc
[i
] = (TCGCallArgumentLoc
){
970 .kind
= TCG_CALL_ARG_BY_REF_N
,
971 .arg_idx
= cum
->arg_idx
,
973 .ref_slot
= cum
->ref_slot
+ i
,
976 cum
->info_in_idx
+= n
;
980 static void init_call_layout(TCGHelperInfo
*info
)
982 int max_reg_slots
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
983 int max_stk_slots
= TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(tcg_target_long
);
984 unsigned typemask
= info
->typemask
;
986 TCGCumulativeArgs cum
= { };
989 * Parse and place any function return value.
991 typecode
= typemask
& 7;
993 case dh_typecode_void
:
996 case dh_typecode_i32
:
997 case dh_typecode_s32
:
998 case dh_typecode_ptr
:
1000 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1002 case dh_typecode_i64
:
1003 case dh_typecode_s64
:
1004 info
->nr_out
= 64 / TCG_TARGET_REG_BITS
;
1005 info
->out_kind
= TCG_CALL_RET_NORMAL
;
1006 /* Query the last register now to trigger any assert early. */
1007 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1009 case dh_typecode_i128
:
1010 info
->nr_out
= 128 / TCG_TARGET_REG_BITS
;
1011 info
->out_kind
= TCG_TARGET_CALL_RET_I128
;
1012 switch (TCG_TARGET_CALL_RET_I128
) {
1013 case TCG_CALL_RET_NORMAL
:
1014 /* Query the last register now to trigger any assert early. */
1015 tcg_target_call_oarg_reg(info
->out_kind
, info
->nr_out
- 1);
1017 case TCG_CALL_RET_BY_VEC
:
1018 /* Query the single register now to trigger any assert early. */
1019 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0);
1021 case TCG_CALL_RET_BY_REF
:
1023 * Allocate the first argument to the output.
1024 * We don't need to store this anywhere, just make it
1025 * unavailable for use in the input loop below.
1030 qemu_build_not_reached();
1034 g_assert_not_reached();
1038 * Parse and place function arguments.
1040 for (typemask
>>= 3; typemask
; typemask
>>= 3, cum
.arg_idx
++) {
1041 TCGCallArgumentKind kind
;
1044 typecode
= typemask
& 7;
1046 case dh_typecode_i32
:
1047 case dh_typecode_s32
:
1048 type
= TCG_TYPE_I32
;
1050 case dh_typecode_i64
:
1051 case dh_typecode_s64
:
1052 type
= TCG_TYPE_I64
;
1054 case dh_typecode_ptr
:
1055 type
= TCG_TYPE_PTR
;
1057 case dh_typecode_i128
:
1058 type
= TCG_TYPE_I128
;
1061 g_assert_not_reached();
1066 switch (TCG_TARGET_CALL_ARG_I32
) {
1067 case TCG_CALL_ARG_EVEN
:
1068 layout_arg_even(&cum
);
1070 case TCG_CALL_ARG_NORMAL
:
1071 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1073 case TCG_CALL_ARG_EXTEND
:
1074 kind
= TCG_CALL_ARG_EXTEND_U
+ (typecode
& 1);
1075 layout_arg_1(&cum
, info
, kind
);
1078 qemu_build_not_reached();
1083 switch (TCG_TARGET_CALL_ARG_I64
) {
1084 case TCG_CALL_ARG_EVEN
:
1085 layout_arg_even(&cum
);
1087 case TCG_CALL_ARG_NORMAL
:
1088 if (TCG_TARGET_REG_BITS
== 32) {
1089 layout_arg_normal_n(&cum
, info
, 2);
1091 layout_arg_1(&cum
, info
, TCG_CALL_ARG_NORMAL
);
1095 qemu_build_not_reached();
1100 switch (TCG_TARGET_CALL_ARG_I128
) {
1101 case TCG_CALL_ARG_EVEN
:
1102 layout_arg_even(&cum
);
1104 case TCG_CALL_ARG_NORMAL
:
1105 layout_arg_normal_n(&cum
, info
, 128 / TCG_TARGET_REG_BITS
);
1107 case TCG_CALL_ARG_BY_REF
:
1108 layout_arg_by_ref(&cum
, info
);
1111 qemu_build_not_reached();
1116 g_assert_not_reached();
1119 info
->nr_in
= cum
.info_in_idx
;
1121 /* Validate that we didn't overrun the input array. */
1122 assert(cum
.info_in_idx
<= ARRAY_SIZE(info
->in
));
1123 /* Validate the backend has enough argument space. */
1124 assert(cum
.arg_slot
<= max_reg_slots
+ max_stk_slots
);
1127 * Relocate the "ref_slot" area to the end of the parameters.
1128 * Minimizing this stack offset helps code size for x86,
1129 * which has a signed 8-bit offset encoding.
1131 if (cum
.ref_slot
!= 0) {
1134 if (cum
.arg_slot
> max_reg_slots
) {
1135 int align
= __alignof(Int128
) / sizeof(tcg_target_long
);
1137 ref_base
= cum
.arg_slot
- max_reg_slots
;
1139 ref_base
= ROUND_UP(ref_base
, align
);
1142 assert(ref_base
+ cum
.ref_slot
<= max_stk_slots
);
1143 ref_base
+= max_reg_slots
;
1145 if (ref_base
!= 0) {
1146 for (int i
= cum
.info_in_idx
- 1; i
>= 0; --i
) {
1147 TCGCallArgumentLoc
*loc
= &info
->in
[i
];
1148 switch (loc
->kind
) {
1149 case TCG_CALL_ARG_BY_REF
:
1150 case TCG_CALL_ARG_BY_REF_N
:
1151 loc
->ref_slot
+= ref_base
;
1161 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
1162 static void process_op_defs(TCGContext
*s
);
1163 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1164 TCGReg reg
, const char *name
);
1166 static void tcg_context_init(unsigned max_cpus
)
1168 TCGContext
*s
= &tcg_init_ctx
;
1169 int op
, total_args
, n
, i
;
1171 TCGArgConstraint
*args_ct
;
1174 memset(s
, 0, sizeof(*s
));
1177 /* Count total number of arguments and allocate the corresponding
1180 for(op
= 0; op
< NB_OPS
; op
++) {
1181 def
= &tcg_op_defs
[op
];
1182 n
= def
->nb_iargs
+ def
->nb_oargs
;
1186 args_ct
= g_new0(TCGArgConstraint
, total_args
);
1188 for(op
= 0; op
< NB_OPS
; op
++) {
1189 def
= &tcg_op_defs
[op
];
1190 def
->args_ct
= args_ct
;
1191 n
= def
->nb_iargs
+ def
->nb_oargs
;
1195 /* Register helpers. */
1196 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
1197 helper_table
= g_hash_table_new(NULL
, NULL
);
1199 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
1200 init_call_layout(&all_helpers
[i
]);
1201 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
1202 (gpointer
)&all_helpers
[i
]);
1205 init_call_layout(&info_helper_ld32_mmu
);
1206 init_call_layout(&info_helper_ld64_mmu
);
1207 init_call_layout(&info_helper_st32_mmu
);
1208 init_call_layout(&info_helper_st64_mmu
);
1210 #ifdef CONFIG_TCG_INTERPRETER
1217 /* Reverse the order of the saved registers, assuming they're all at
1218 the start of tcg_target_reg_alloc_order. */
1219 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
1220 int r
= tcg_target_reg_alloc_order
[n
];
1221 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
1225 for (i
= 0; i
< n
; ++i
) {
1226 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
1228 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
1229 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
1232 alloc_tcg_plugin_context(s
);
1236 * In user-mode we simply share the init context among threads, since we
1237 * use a single region. See the documentation tcg_region_init() for the
1238 * reasoning behind this.
1239 * In softmmu we will have at most max_cpus TCG threads.
1241 #ifdef CONFIG_USER_ONLY
1242 tcg_ctxs
= &tcg_ctx
;
1246 tcg_max_ctxs
= max_cpus
;
1247 tcg_ctxs
= g_new0(TCGContext
*, max_cpus
);
1250 tcg_debug_assert(!tcg_regset_test_reg(s
->reserved_regs
, TCG_AREG0
));
1251 ts
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, TCG_AREG0
, "env");
1252 cpu_env
= temp_tcgv_ptr(ts
);
1255 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
)
1257 tcg_context_init(max_cpus
);
1258 tcg_region_init(tb_size
, splitwx
, max_cpus
);
1262 * Allocate TBs right before their corresponding translated code, making
1263 * sure that TBs and code are on different cache lines.
1265 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
1267 uintptr_t align
= qemu_icache_linesize
;
1268 TranslationBlock
*tb
;
1272 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
1273 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
1275 if (unlikely(next
> s
->code_gen_highwater
)) {
1276 if (tcg_region_alloc(s
)) {
1281 qatomic_set(&s
->code_gen_ptr
, next
);
1282 s
->data_gen_ptr
= NULL
;
1286 void tcg_prologue_init(TCGContext
*s
)
1288 size_t prologue_size
;
1290 s
->code_ptr
= s
->code_gen_ptr
;
1291 s
->code_buf
= s
->code_gen_ptr
;
1292 s
->data_gen_ptr
= NULL
;
1294 #ifndef CONFIG_TCG_INTERPRETER
1295 tcg_qemu_tb_exec
= (tcg_prologue_fn
*)tcg_splitwx_to_rx(s
->code_ptr
);
1298 #ifdef TCG_TARGET_NEED_POOL_LABELS
1299 s
->pool_labels
= NULL
;
1302 qemu_thread_jit_write();
1303 /* Generate the prologue. */
1304 tcg_target_qemu_prologue(s
);
1306 #ifdef TCG_TARGET_NEED_POOL_LABELS
1307 /* Allow the prologue to put e.g. guest_base into a pool entry. */
1309 int result
= tcg_out_pool_finalize(s
);
1310 tcg_debug_assert(result
== 0);
1314 prologue_size
= tcg_current_code_size(s
);
1315 perf_report_prologue(s
->code_gen_ptr
, prologue_size
);
1317 #ifndef CONFIG_TCG_INTERPRETER
1318 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
1319 (uintptr_t)s
->code_buf
, prologue_size
);
1323 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
1324 FILE *logfile
= qemu_log_trylock();
1326 fprintf(logfile
, "PROLOGUE: [size=%zu]\n", prologue_size
);
1327 if (s
->data_gen_ptr
) {
1328 size_t code_size
= s
->data_gen_ptr
- s
->code_gen_ptr
;
1329 size_t data_size
= prologue_size
- code_size
;
1332 disas(logfile
, s
->code_gen_ptr
, code_size
);
1334 for (i
= 0; i
< data_size
; i
+= sizeof(tcg_target_ulong
)) {
1335 if (sizeof(tcg_target_ulong
) == 8) {
1337 "0x%08" PRIxPTR
": .quad 0x%016" PRIx64
"\n",
1338 (uintptr_t)s
->data_gen_ptr
+ i
,
1339 *(uint64_t *)(s
->data_gen_ptr
+ i
));
1342 "0x%08" PRIxPTR
": .long 0x%08x\n",
1343 (uintptr_t)s
->data_gen_ptr
+ i
,
1344 *(uint32_t *)(s
->data_gen_ptr
+ i
));
1348 disas(logfile
, s
->code_gen_ptr
, prologue_size
);
1350 fprintf(logfile
, "\n");
1351 qemu_log_unlock(logfile
);
1356 #ifndef CONFIG_TCG_INTERPRETER
1358 * Assert that goto_ptr is implemented completely, setting an epilogue.
1359 * For tci, we use NULL as the signal to return from the interpreter,
1360 * so skip this check.
1362 tcg_debug_assert(tcg_code_gen_epilogue
!= NULL
);
1365 tcg_region_prologue_set(s
);
1368 void tcg_func_start(TCGContext
*s
)
1371 s
->nb_temps
= s
->nb_globals
;
1373 /* No temps have been previously allocated for size or locality. */
1374 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
1376 /* No constant temps have been previously allocated. */
1377 for (int i
= 0; i
< TCG_TYPE_COUNT
; ++i
) {
1378 if (s
->const_table
[i
]) {
1379 g_hash_table_remove_all(s
->const_table
[i
]);
1385 s
->current_frame_offset
= s
->frame_start
;
1387 #ifdef CONFIG_DEBUG_TCG
1388 s
->goto_tb_issue_mask
= 0;
1391 QTAILQ_INIT(&s
->ops
);
1392 QTAILQ_INIT(&s
->free_ops
);
1393 QSIMPLEQ_INIT(&s
->labels
);
1396 static TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
1398 int n
= s
->nb_temps
++;
1400 if (n
>= TCG_MAX_TEMPS
) {
1401 tcg_raise_tb_overflow(s
);
1403 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
1406 static TCGTemp
*tcg_global_alloc(TCGContext
*s
)
1410 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
1411 tcg_debug_assert(s
->nb_globals
< TCG_MAX_TEMPS
);
1413 ts
= tcg_temp_alloc(s
);
1414 ts
->kind
= TEMP_GLOBAL
;
1419 static TCGTemp
*tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
1420 TCGReg reg
, const char *name
)
1424 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1426 ts
= tcg_global_alloc(s
);
1427 ts
->base_type
= type
;
1429 ts
->kind
= TEMP_FIXED
;
1432 tcg_regset_set_reg(s
->reserved_regs
, reg
);
1437 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
1439 s
->frame_start
= start
;
1440 s
->frame_end
= start
+ size
;
1442 = tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
1445 TCGTemp
*tcg_global_mem_new_internal(TCGType type
, TCGv_ptr base
,
1446 intptr_t offset
, const char *name
)
1448 TCGContext
*s
= tcg_ctx
;
1449 TCGTemp
*base_ts
= tcgv_ptr_temp(base
);
1450 TCGTemp
*ts
= tcg_global_alloc(s
);
1451 int indirect_reg
= 0;
1453 switch (base_ts
->kind
) {
1457 /* We do not support double-indirect registers. */
1458 tcg_debug_assert(!base_ts
->indirect_reg
);
1459 base_ts
->indirect_base
= 1;
1460 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
1465 g_assert_not_reached();
1468 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1469 TCGTemp
*ts2
= tcg_global_alloc(s
);
1472 ts
->base_type
= TCG_TYPE_I64
;
1473 ts
->type
= TCG_TYPE_I32
;
1474 ts
->indirect_reg
= indirect_reg
;
1475 ts
->mem_allocated
= 1;
1476 ts
->mem_base
= base_ts
;
1477 ts
->mem_offset
= offset
;
1478 pstrcpy(buf
, sizeof(buf
), name
);
1479 pstrcat(buf
, sizeof(buf
), "_0");
1480 ts
->name
= strdup(buf
);
1482 tcg_debug_assert(ts2
== ts
+ 1);
1483 ts2
->base_type
= TCG_TYPE_I64
;
1484 ts2
->type
= TCG_TYPE_I32
;
1485 ts2
->indirect_reg
= indirect_reg
;
1486 ts2
->mem_allocated
= 1;
1487 ts2
->mem_base
= base_ts
;
1488 ts2
->mem_offset
= offset
+ 4;
1489 ts2
->temp_subindex
= 1;
1490 pstrcpy(buf
, sizeof(buf
), name
);
1491 pstrcat(buf
, sizeof(buf
), "_1");
1492 ts2
->name
= strdup(buf
);
1494 ts
->base_type
= type
;
1496 ts
->indirect_reg
= indirect_reg
;
1497 ts
->mem_allocated
= 1;
1498 ts
->mem_base
= base_ts
;
1499 ts
->mem_offset
= offset
;
1505 TCGTemp
*tcg_temp_new_internal(TCGType type
, TCGTempKind kind
)
1507 TCGContext
*s
= tcg_ctx
;
1511 if (kind
== TEMP_EBB
) {
1512 int idx
= find_first_bit(s
->free_temps
[type
].l
, TCG_MAX_TEMPS
);
1514 if (idx
< TCG_MAX_TEMPS
) {
1515 /* There is already an available temp with the right type. */
1516 clear_bit(idx
, s
->free_temps
[type
].l
);
1518 ts
= &s
->temps
[idx
];
1519 ts
->temp_allocated
= 1;
1520 tcg_debug_assert(ts
->base_type
== type
);
1521 tcg_debug_assert(ts
->kind
== kind
);
1525 tcg_debug_assert(kind
== TEMP_TB
);
1536 n
= 64 / TCG_TARGET_REG_BITS
;
1539 n
= 128 / TCG_TARGET_REG_BITS
;
1542 g_assert_not_reached();
1545 ts
= tcg_temp_alloc(s
);
1546 ts
->base_type
= type
;
1547 ts
->temp_allocated
= 1;
1553 ts
->type
= TCG_TYPE_REG
;
1555 for (int i
= 1; i
< n
; ++i
) {
1556 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1558 tcg_debug_assert(ts2
== ts
+ i
);
1559 ts2
->base_type
= type
;
1560 ts2
->type
= TCG_TYPE_REG
;
1561 ts2
->temp_allocated
= 1;
1562 ts2
->temp_subindex
= i
;
1569 TCGv_vec
tcg_temp_new_vec(TCGType type
)
1573 #ifdef CONFIG_DEBUG_TCG
1576 assert(TCG_TARGET_HAS_v64
);
1579 assert(TCG_TARGET_HAS_v128
);
1582 assert(TCG_TARGET_HAS_v256
);
1585 g_assert_not_reached();
1589 t
= tcg_temp_new_internal(type
, TEMP_EBB
);
1590 return temp_tcgv_vec(t
);
1593 /* Create a new temp of the same type as an existing temp. */
1594 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
)
1596 TCGTemp
*t
= tcgv_vec_temp(match
);
1598 tcg_debug_assert(t
->temp_allocated
!= 0);
1600 t
= tcg_temp_new_internal(t
->base_type
, TEMP_EBB
);
1601 return temp_tcgv_vec(t
);
1604 void tcg_temp_free_internal(TCGTemp
*ts
)
1606 TCGContext
*s
= tcg_ctx
;
1611 /* Silently ignore free. */
1614 tcg_debug_assert(ts
->temp_allocated
!= 0);
1615 ts
->temp_allocated
= 0;
1616 set_bit(temp_idx(ts
), s
->free_temps
[ts
->base_type
].l
);
1619 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */
1620 g_assert_not_reached();
1624 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
)
1626 TCGContext
*s
= tcg_ctx
;
1627 GHashTable
*h
= s
->const_table
[type
];
1631 h
= g_hash_table_new(g_int64_hash
, g_int64_equal
);
1632 s
->const_table
[type
] = h
;
1635 ts
= g_hash_table_lookup(h
, &val
);
1639 ts
= tcg_temp_alloc(s
);
1641 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
1642 TCGTemp
*ts2
= tcg_temp_alloc(s
);
1644 tcg_debug_assert(ts2
== ts
+ 1);
1646 ts
->base_type
= TCG_TYPE_I64
;
1647 ts
->type
= TCG_TYPE_I32
;
1648 ts
->kind
= TEMP_CONST
;
1649 ts
->temp_allocated
= 1;
1651 ts2
->base_type
= TCG_TYPE_I64
;
1652 ts2
->type
= TCG_TYPE_I32
;
1653 ts2
->kind
= TEMP_CONST
;
1654 ts2
->temp_allocated
= 1;
1655 ts2
->temp_subindex
= 1;
1658 * Retain the full value of the 64-bit constant in the low
1659 * part, so that the hash table works. Actual uses will
1660 * truncate the value to the low part.
1662 ts
[HOST_BIG_ENDIAN
].val
= val
;
1663 ts
[!HOST_BIG_ENDIAN
].val
= val
>> 32;
1664 val_ptr
= &ts
[HOST_BIG_ENDIAN
].val
;
1666 ts
->base_type
= type
;
1668 ts
->kind
= TEMP_CONST
;
1669 ts
->temp_allocated
= 1;
1673 g_hash_table_insert(h
, val_ptr
, ts
);
1679 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
)
1681 val
= dup_const(vece
, val
);
1682 return temp_tcgv_vec(tcg_constant_internal(type
, val
));
1685 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
)
1687 TCGTemp
*t
= tcgv_vec_temp(match
);
1689 tcg_debug_assert(t
->temp_allocated
!= 0);
1690 return tcg_constant_vec(t
->base_type
, vece
, val
);
1693 /* Return true if OP may appear in the opcode stream.
1694 Test the runtime variable that controls each opcode. */
1695 bool tcg_op_supported(TCGOpcode op
)
1698 = TCG_TARGET_HAS_v64
| TCG_TARGET_HAS_v128
| TCG_TARGET_HAS_v256
;
1701 case INDEX_op_discard
:
1702 case INDEX_op_set_label
:
1706 case INDEX_op_insn_start
:
1707 case INDEX_op_exit_tb
:
1708 case INDEX_op_goto_tb
:
1709 case INDEX_op_goto_ptr
:
1710 case INDEX_op_qemu_ld_i32
:
1711 case INDEX_op_qemu_st_i32
:
1712 case INDEX_op_qemu_ld_i64
:
1713 case INDEX_op_qemu_st_i64
:
1716 case INDEX_op_qemu_st8_i32
:
1717 return TCG_TARGET_HAS_qemu_st8_i32
;
1719 case INDEX_op_mov_i32
:
1720 case INDEX_op_setcond_i32
:
1721 case INDEX_op_brcond_i32
:
1722 case INDEX_op_ld8u_i32
:
1723 case INDEX_op_ld8s_i32
:
1724 case INDEX_op_ld16u_i32
:
1725 case INDEX_op_ld16s_i32
:
1726 case INDEX_op_ld_i32
:
1727 case INDEX_op_st8_i32
:
1728 case INDEX_op_st16_i32
:
1729 case INDEX_op_st_i32
:
1730 case INDEX_op_add_i32
:
1731 case INDEX_op_sub_i32
:
1732 case INDEX_op_mul_i32
:
1733 case INDEX_op_and_i32
:
1734 case INDEX_op_or_i32
:
1735 case INDEX_op_xor_i32
:
1736 case INDEX_op_shl_i32
:
1737 case INDEX_op_shr_i32
:
1738 case INDEX_op_sar_i32
:
1741 case INDEX_op_movcond_i32
:
1742 return TCG_TARGET_HAS_movcond_i32
;
1743 case INDEX_op_div_i32
:
1744 case INDEX_op_divu_i32
:
1745 return TCG_TARGET_HAS_div_i32
;
1746 case INDEX_op_rem_i32
:
1747 case INDEX_op_remu_i32
:
1748 return TCG_TARGET_HAS_rem_i32
;
1749 case INDEX_op_div2_i32
:
1750 case INDEX_op_divu2_i32
:
1751 return TCG_TARGET_HAS_div2_i32
;
1752 case INDEX_op_rotl_i32
:
1753 case INDEX_op_rotr_i32
:
1754 return TCG_TARGET_HAS_rot_i32
;
1755 case INDEX_op_deposit_i32
:
1756 return TCG_TARGET_HAS_deposit_i32
;
1757 case INDEX_op_extract_i32
:
1758 return TCG_TARGET_HAS_extract_i32
;
1759 case INDEX_op_sextract_i32
:
1760 return TCG_TARGET_HAS_sextract_i32
;
1761 case INDEX_op_extract2_i32
:
1762 return TCG_TARGET_HAS_extract2_i32
;
1763 case INDEX_op_add2_i32
:
1764 return TCG_TARGET_HAS_add2_i32
;
1765 case INDEX_op_sub2_i32
:
1766 return TCG_TARGET_HAS_sub2_i32
;
1767 case INDEX_op_mulu2_i32
:
1768 return TCG_TARGET_HAS_mulu2_i32
;
1769 case INDEX_op_muls2_i32
:
1770 return TCG_TARGET_HAS_muls2_i32
;
1771 case INDEX_op_muluh_i32
:
1772 return TCG_TARGET_HAS_muluh_i32
;
1773 case INDEX_op_mulsh_i32
:
1774 return TCG_TARGET_HAS_mulsh_i32
;
1775 case INDEX_op_ext8s_i32
:
1776 return TCG_TARGET_HAS_ext8s_i32
;
1777 case INDEX_op_ext16s_i32
:
1778 return TCG_TARGET_HAS_ext16s_i32
;
1779 case INDEX_op_ext8u_i32
:
1780 return TCG_TARGET_HAS_ext8u_i32
;
1781 case INDEX_op_ext16u_i32
:
1782 return TCG_TARGET_HAS_ext16u_i32
;
1783 case INDEX_op_bswap16_i32
:
1784 return TCG_TARGET_HAS_bswap16_i32
;
1785 case INDEX_op_bswap32_i32
:
1786 return TCG_TARGET_HAS_bswap32_i32
;
1787 case INDEX_op_not_i32
:
1788 return TCG_TARGET_HAS_not_i32
;
1789 case INDEX_op_neg_i32
:
1790 return TCG_TARGET_HAS_neg_i32
;
1791 case INDEX_op_andc_i32
:
1792 return TCG_TARGET_HAS_andc_i32
;
1793 case INDEX_op_orc_i32
:
1794 return TCG_TARGET_HAS_orc_i32
;
1795 case INDEX_op_eqv_i32
:
1796 return TCG_TARGET_HAS_eqv_i32
;
1797 case INDEX_op_nand_i32
:
1798 return TCG_TARGET_HAS_nand_i32
;
1799 case INDEX_op_nor_i32
:
1800 return TCG_TARGET_HAS_nor_i32
;
1801 case INDEX_op_clz_i32
:
1802 return TCG_TARGET_HAS_clz_i32
;
1803 case INDEX_op_ctz_i32
:
1804 return TCG_TARGET_HAS_ctz_i32
;
1805 case INDEX_op_ctpop_i32
:
1806 return TCG_TARGET_HAS_ctpop_i32
;
1808 case INDEX_op_brcond2_i32
:
1809 case INDEX_op_setcond2_i32
:
1810 return TCG_TARGET_REG_BITS
== 32;
1812 case INDEX_op_mov_i64
:
1813 case INDEX_op_setcond_i64
:
1814 case INDEX_op_brcond_i64
:
1815 case INDEX_op_ld8u_i64
:
1816 case INDEX_op_ld8s_i64
:
1817 case INDEX_op_ld16u_i64
:
1818 case INDEX_op_ld16s_i64
:
1819 case INDEX_op_ld32u_i64
:
1820 case INDEX_op_ld32s_i64
:
1821 case INDEX_op_ld_i64
:
1822 case INDEX_op_st8_i64
:
1823 case INDEX_op_st16_i64
:
1824 case INDEX_op_st32_i64
:
1825 case INDEX_op_st_i64
:
1826 case INDEX_op_add_i64
:
1827 case INDEX_op_sub_i64
:
1828 case INDEX_op_mul_i64
:
1829 case INDEX_op_and_i64
:
1830 case INDEX_op_or_i64
:
1831 case INDEX_op_xor_i64
:
1832 case INDEX_op_shl_i64
:
1833 case INDEX_op_shr_i64
:
1834 case INDEX_op_sar_i64
:
1835 case INDEX_op_ext_i32_i64
:
1836 case INDEX_op_extu_i32_i64
:
1837 return TCG_TARGET_REG_BITS
== 64;
1839 case INDEX_op_movcond_i64
:
1840 return TCG_TARGET_HAS_movcond_i64
;
1841 case INDEX_op_div_i64
:
1842 case INDEX_op_divu_i64
:
1843 return TCG_TARGET_HAS_div_i64
;
1844 case INDEX_op_rem_i64
:
1845 case INDEX_op_remu_i64
:
1846 return TCG_TARGET_HAS_rem_i64
;
1847 case INDEX_op_div2_i64
:
1848 case INDEX_op_divu2_i64
:
1849 return TCG_TARGET_HAS_div2_i64
;
1850 case INDEX_op_rotl_i64
:
1851 case INDEX_op_rotr_i64
:
1852 return TCG_TARGET_HAS_rot_i64
;
1853 case INDEX_op_deposit_i64
:
1854 return TCG_TARGET_HAS_deposit_i64
;
1855 case INDEX_op_extract_i64
:
1856 return TCG_TARGET_HAS_extract_i64
;
1857 case INDEX_op_sextract_i64
:
1858 return TCG_TARGET_HAS_sextract_i64
;
1859 case INDEX_op_extract2_i64
:
1860 return TCG_TARGET_HAS_extract2_i64
;
1861 case INDEX_op_extrl_i64_i32
:
1862 return TCG_TARGET_HAS_extrl_i64_i32
;
1863 case INDEX_op_extrh_i64_i32
:
1864 return TCG_TARGET_HAS_extrh_i64_i32
;
1865 case INDEX_op_ext8s_i64
:
1866 return TCG_TARGET_HAS_ext8s_i64
;
1867 case INDEX_op_ext16s_i64
:
1868 return TCG_TARGET_HAS_ext16s_i64
;
1869 case INDEX_op_ext32s_i64
:
1870 return TCG_TARGET_HAS_ext32s_i64
;
1871 case INDEX_op_ext8u_i64
:
1872 return TCG_TARGET_HAS_ext8u_i64
;
1873 case INDEX_op_ext16u_i64
:
1874 return TCG_TARGET_HAS_ext16u_i64
;
1875 case INDEX_op_ext32u_i64
:
1876 return TCG_TARGET_HAS_ext32u_i64
;
1877 case INDEX_op_bswap16_i64
:
1878 return TCG_TARGET_HAS_bswap16_i64
;
1879 case INDEX_op_bswap32_i64
:
1880 return TCG_TARGET_HAS_bswap32_i64
;
1881 case INDEX_op_bswap64_i64
:
1882 return TCG_TARGET_HAS_bswap64_i64
;
1883 case INDEX_op_not_i64
:
1884 return TCG_TARGET_HAS_not_i64
;
1885 case INDEX_op_neg_i64
:
1886 return TCG_TARGET_HAS_neg_i64
;
1887 case INDEX_op_andc_i64
:
1888 return TCG_TARGET_HAS_andc_i64
;
1889 case INDEX_op_orc_i64
:
1890 return TCG_TARGET_HAS_orc_i64
;
1891 case INDEX_op_eqv_i64
:
1892 return TCG_TARGET_HAS_eqv_i64
;
1893 case INDEX_op_nand_i64
:
1894 return TCG_TARGET_HAS_nand_i64
;
1895 case INDEX_op_nor_i64
:
1896 return TCG_TARGET_HAS_nor_i64
;
1897 case INDEX_op_clz_i64
:
1898 return TCG_TARGET_HAS_clz_i64
;
1899 case INDEX_op_ctz_i64
:
1900 return TCG_TARGET_HAS_ctz_i64
;
1901 case INDEX_op_ctpop_i64
:
1902 return TCG_TARGET_HAS_ctpop_i64
;
1903 case INDEX_op_add2_i64
:
1904 return TCG_TARGET_HAS_add2_i64
;
1905 case INDEX_op_sub2_i64
:
1906 return TCG_TARGET_HAS_sub2_i64
;
1907 case INDEX_op_mulu2_i64
:
1908 return TCG_TARGET_HAS_mulu2_i64
;
1909 case INDEX_op_muls2_i64
:
1910 return TCG_TARGET_HAS_muls2_i64
;
1911 case INDEX_op_muluh_i64
:
1912 return TCG_TARGET_HAS_muluh_i64
;
1913 case INDEX_op_mulsh_i64
:
1914 return TCG_TARGET_HAS_mulsh_i64
;
1916 case INDEX_op_mov_vec
:
1917 case INDEX_op_dup_vec
:
1918 case INDEX_op_dupm_vec
:
1919 case INDEX_op_ld_vec
:
1920 case INDEX_op_st_vec
:
1921 case INDEX_op_add_vec
:
1922 case INDEX_op_sub_vec
:
1923 case INDEX_op_and_vec
:
1924 case INDEX_op_or_vec
:
1925 case INDEX_op_xor_vec
:
1926 case INDEX_op_cmp_vec
:
1928 case INDEX_op_dup2_vec
:
1929 return have_vec
&& TCG_TARGET_REG_BITS
== 32;
1930 case INDEX_op_not_vec
:
1931 return have_vec
&& TCG_TARGET_HAS_not_vec
;
1932 case INDEX_op_neg_vec
:
1933 return have_vec
&& TCG_TARGET_HAS_neg_vec
;
1934 case INDEX_op_abs_vec
:
1935 return have_vec
&& TCG_TARGET_HAS_abs_vec
;
1936 case INDEX_op_andc_vec
:
1937 return have_vec
&& TCG_TARGET_HAS_andc_vec
;
1938 case INDEX_op_orc_vec
:
1939 return have_vec
&& TCG_TARGET_HAS_orc_vec
;
1940 case INDEX_op_nand_vec
:
1941 return have_vec
&& TCG_TARGET_HAS_nand_vec
;
1942 case INDEX_op_nor_vec
:
1943 return have_vec
&& TCG_TARGET_HAS_nor_vec
;
1944 case INDEX_op_eqv_vec
:
1945 return have_vec
&& TCG_TARGET_HAS_eqv_vec
;
1946 case INDEX_op_mul_vec
:
1947 return have_vec
&& TCG_TARGET_HAS_mul_vec
;
1948 case INDEX_op_shli_vec
:
1949 case INDEX_op_shri_vec
:
1950 case INDEX_op_sari_vec
:
1951 return have_vec
&& TCG_TARGET_HAS_shi_vec
;
1952 case INDEX_op_shls_vec
:
1953 case INDEX_op_shrs_vec
:
1954 case INDEX_op_sars_vec
:
1955 return have_vec
&& TCG_TARGET_HAS_shs_vec
;
1956 case INDEX_op_shlv_vec
:
1957 case INDEX_op_shrv_vec
:
1958 case INDEX_op_sarv_vec
:
1959 return have_vec
&& TCG_TARGET_HAS_shv_vec
;
1960 case INDEX_op_rotli_vec
:
1961 return have_vec
&& TCG_TARGET_HAS_roti_vec
;
1962 case INDEX_op_rotls_vec
:
1963 return have_vec
&& TCG_TARGET_HAS_rots_vec
;
1964 case INDEX_op_rotlv_vec
:
1965 case INDEX_op_rotrv_vec
:
1966 return have_vec
&& TCG_TARGET_HAS_rotv_vec
;
1967 case INDEX_op_ssadd_vec
:
1968 case INDEX_op_usadd_vec
:
1969 case INDEX_op_sssub_vec
:
1970 case INDEX_op_ussub_vec
:
1971 return have_vec
&& TCG_TARGET_HAS_sat_vec
;
1972 case INDEX_op_smin_vec
:
1973 case INDEX_op_umin_vec
:
1974 case INDEX_op_smax_vec
:
1975 case INDEX_op_umax_vec
:
1976 return have_vec
&& TCG_TARGET_HAS_minmax_vec
;
1977 case INDEX_op_bitsel_vec
:
1978 return have_vec
&& TCG_TARGET_HAS_bitsel_vec
;
1979 case INDEX_op_cmpsel_vec
:
1980 return have_vec
&& TCG_TARGET_HAS_cmpsel_vec
;
1983 tcg_debug_assert(op
> INDEX_op_last_generic
&& op
< NB_OPS
);
1988 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
);
1990 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
)
1992 const TCGHelperInfo
*info
;
1993 TCGv_i64 extend_free
[MAX_CALL_IARGS
];
1996 int i
, n
, pi
= 0, total_args
;
1998 info
= g_hash_table_lookup(helper_table
, (gpointer
)func
);
1999 total_args
= info
->nr_out
+ info
->nr_in
+ 2;
2000 op
= tcg_op_alloc(INDEX_op_call
, total_args
);
2002 #ifdef CONFIG_PLUGIN
2003 /* Flag helpers that may affect guest state */
2004 if (tcg_ctx
->plugin_insn
&&
2005 !(info
->flags
& TCG_CALL_PLUGIN
) &&
2006 !(info
->flags
& TCG_CALL_NO_SIDE_EFFECTS
)) {
2007 tcg_ctx
->plugin_insn
->calls_helpers
= true;
2011 TCGOP_CALLO(op
) = n
= info
->nr_out
;
2014 tcg_debug_assert(ret
== NULL
);
2017 tcg_debug_assert(ret
!= NULL
);
2018 op
->args
[pi
++] = temp_arg(ret
);
2022 tcg_debug_assert(ret
!= NULL
);
2023 tcg_debug_assert(ret
->base_type
== ret
->type
+ ctz32(n
));
2024 tcg_debug_assert(ret
->temp_subindex
== 0);
2025 for (i
= 0; i
< n
; ++i
) {
2026 op
->args
[pi
++] = temp_arg(ret
+ i
);
2030 g_assert_not_reached();
2033 TCGOP_CALLI(op
) = n
= info
->nr_in
;
2034 for (i
= 0; i
< n
; i
++) {
2035 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
2036 TCGTemp
*ts
= args
[loc
->arg_idx
] + loc
->tmp_subindex
;
2038 switch (loc
->kind
) {
2039 case TCG_CALL_ARG_NORMAL
:
2040 case TCG_CALL_ARG_BY_REF
:
2041 case TCG_CALL_ARG_BY_REF_N
:
2042 op
->args
[pi
++] = temp_arg(ts
);
2045 case TCG_CALL_ARG_EXTEND_U
:
2046 case TCG_CALL_ARG_EXTEND_S
:
2048 TCGv_i64 temp
= tcg_temp_ebb_new_i64();
2049 TCGv_i32 orig
= temp_tcgv_i32(ts
);
2051 if (loc
->kind
== TCG_CALL_ARG_EXTEND_S
) {
2052 tcg_gen_ext_i32_i64(temp
, orig
);
2054 tcg_gen_extu_i32_i64(temp
, orig
);
2056 op
->args
[pi
++] = tcgv_i64_arg(temp
);
2057 extend_free
[n_extend
++] = temp
;
2062 g_assert_not_reached();
2065 op
->args
[pi
++] = (uintptr_t)func
;
2066 op
->args
[pi
++] = (uintptr_t)info
;
2067 tcg_debug_assert(pi
== total_args
);
2069 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2071 tcg_debug_assert(n_extend
< ARRAY_SIZE(extend_free
));
2072 for (i
= 0; i
< n_extend
; ++i
) {
2073 tcg_temp_free_i64(extend_free
[i
]);
2077 static void tcg_reg_alloc_start(TCGContext
*s
)
2081 for (i
= 0, n
= s
->nb_temps
; i
< n
; i
++) {
2082 TCGTemp
*ts
= &s
->temps
[i
];
2083 TCGTempVal val
= TEMP_VAL_MEM
;
2087 val
= TEMP_VAL_CONST
;
2095 val
= TEMP_VAL_DEAD
;
2098 ts
->mem_allocated
= 0;
2101 g_assert_not_reached();
2106 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
2109 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
2112 int idx
= temp_idx(ts
);
2117 pstrcpy(buf
, buf_size
, ts
->name
);
2120 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
2123 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
2128 snprintf(buf
, buf_size
, "$0x%x", (int32_t)ts
->val
);
2130 #if TCG_TARGET_REG_BITS > 32
2132 snprintf(buf
, buf_size
, "$0x%" PRIx64
, ts
->val
);
2138 snprintf(buf
, buf_size
, "v%d$0x%" PRIx64
,
2139 64 << (ts
->type
- TCG_TYPE_V64
), ts
->val
);
2142 g_assert_not_reached();
2149 static char *tcg_get_arg_str(TCGContext
*s
, char *buf
,
2150 int buf_size
, TCGArg arg
)
2152 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, arg_temp(arg
));
2155 static const char * const cond_name
[] =
2157 [TCG_COND_NEVER
] = "never",
2158 [TCG_COND_ALWAYS
] = "always",
2159 [TCG_COND_EQ
] = "eq",
2160 [TCG_COND_NE
] = "ne",
2161 [TCG_COND_LT
] = "lt",
2162 [TCG_COND_GE
] = "ge",
2163 [TCG_COND_LE
] = "le",
2164 [TCG_COND_GT
] = "gt",
2165 [TCG_COND_LTU
] = "ltu",
2166 [TCG_COND_GEU
] = "geu",
2167 [TCG_COND_LEU
] = "leu",
2168 [TCG_COND_GTU
] = "gtu"
2171 static const char * const ldst_name
[] =
2187 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
2188 #ifdef TARGET_ALIGNED_ONLY
2189 [MO_UNALN
>> MO_ASHIFT
] = "un+",
2190 [MO_ALIGN
>> MO_ASHIFT
] = "",
2192 [MO_UNALN
>> MO_ASHIFT
] = "",
2193 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
2195 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
2196 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
2197 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
2198 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
2199 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
2200 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
2203 static const char bswap_flag_name
[][6] = {
2204 [TCG_BSWAP_IZ
] = "iz",
2205 [TCG_BSWAP_OZ
] = "oz",
2206 [TCG_BSWAP_OS
] = "os",
2207 [TCG_BSWAP_IZ
| TCG_BSWAP_OZ
] = "iz,oz",
2208 [TCG_BSWAP_IZ
| TCG_BSWAP_OS
] = "iz,os",
2211 static inline bool tcg_regset_single(TCGRegSet d
)
2213 return (d
& (d
- 1)) == 0;
2216 static inline TCGReg
tcg_regset_first(TCGRegSet d
)
2218 if (TCG_TARGET_NB_REGS
<= 32) {
2225 /* Return only the number of characters output -- no error return. */
2226 #define ne_fprintf(...) \
2227 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; })
2229 static void tcg_dump_ops(TCGContext
*s
, FILE *f
, bool have_prefs
)
2234 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
2235 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
2236 const TCGOpDef
*def
;
2241 def
= &tcg_op_defs
[c
];
2243 if (c
== INDEX_op_insn_start
) {
2245 col
+= ne_fprintf(f
, "\n ----");
2247 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2249 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2250 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
2254 col
+= ne_fprintf(f
, " " TARGET_FMT_lx
, a
);
2256 } else if (c
== INDEX_op_call
) {
2257 const TCGHelperInfo
*info
= tcg_call_info(op
);
2258 void *func
= tcg_call_func(op
);
2260 /* variable number of arguments */
2261 nb_oargs
= TCGOP_CALLO(op
);
2262 nb_iargs
= TCGOP_CALLI(op
);
2263 nb_cargs
= def
->nb_cargs
;
2265 col
+= ne_fprintf(f
, " %s ", def
->name
);
2268 * Print the function name from TCGHelperInfo, if available.
2269 * Note that plugins have a template function for the info,
2270 * but the actual function pointer comes from the plugin.
2272 if (func
== info
->func
) {
2273 col
+= ne_fprintf(f
, "%s", info
->name
);
2275 col
+= ne_fprintf(f
, "plugin(%p)", func
);
2278 col
+= ne_fprintf(f
, ",$0x%x,$%d", info
->flags
, nb_oargs
);
2279 for (i
= 0; i
< nb_oargs
; i
++) {
2280 col
+= ne_fprintf(f
, ",%s", tcg_get_arg_str(s
, buf
, sizeof(buf
),
2283 for (i
= 0; i
< nb_iargs
; i
++) {
2284 TCGArg arg
= op
->args
[nb_oargs
+ i
];
2285 const char *t
= tcg_get_arg_str(s
, buf
, sizeof(buf
), arg
);
2286 col
+= ne_fprintf(f
, ",%s", t
);
2289 col
+= ne_fprintf(f
, " %s ", def
->name
);
2291 nb_oargs
= def
->nb_oargs
;
2292 nb_iargs
= def
->nb_iargs
;
2293 nb_cargs
= def
->nb_cargs
;
2295 if (def
->flags
& TCG_OPF_VECTOR
) {
2296 col
+= ne_fprintf(f
, "v%d,e%d,", 64 << TCGOP_VECL(op
),
2297 8 << TCGOP_VECE(op
));
2301 for (i
= 0; i
< nb_oargs
; i
++) {
2302 const char *sep
= k
? "," : "";
2303 col
+= ne_fprintf(f
, "%s%s", sep
,
2304 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2307 for (i
= 0; i
< nb_iargs
; i
++) {
2308 const char *sep
= k
? "," : "";
2309 col
+= ne_fprintf(f
, "%s%s", sep
,
2310 tcg_get_arg_str(s
, buf
, sizeof(buf
),
2314 case INDEX_op_brcond_i32
:
2315 case INDEX_op_setcond_i32
:
2316 case INDEX_op_movcond_i32
:
2317 case INDEX_op_brcond2_i32
:
2318 case INDEX_op_setcond2_i32
:
2319 case INDEX_op_brcond_i64
:
2320 case INDEX_op_setcond_i64
:
2321 case INDEX_op_movcond_i64
:
2322 case INDEX_op_cmp_vec
:
2323 case INDEX_op_cmpsel_vec
:
2324 if (op
->args
[k
] < ARRAY_SIZE(cond_name
)
2325 && cond_name
[op
->args
[k
]]) {
2326 col
+= ne_fprintf(f
, ",%s", cond_name
[op
->args
[k
++]]);
2328 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, op
->args
[k
++]);
2332 case INDEX_op_qemu_ld_i32
:
2333 case INDEX_op_qemu_st_i32
:
2334 case INDEX_op_qemu_st8_i32
:
2335 case INDEX_op_qemu_ld_i64
:
2336 case INDEX_op_qemu_st_i64
:
2338 MemOpIdx oi
= op
->args
[k
++];
2339 MemOp op
= get_memop(oi
);
2340 unsigned ix
= get_mmuidx(oi
);
2342 if (op
& ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
)) {
2343 col
+= ne_fprintf(f
, ",$0x%x,%u", op
, ix
);
2345 const char *s_al
, *s_op
;
2346 s_al
= alignment_name
[(op
& MO_AMASK
) >> MO_ASHIFT
];
2347 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
2348 col
+= ne_fprintf(f
, ",%s%s,%u", s_al
, s_op
, ix
);
2353 case INDEX_op_bswap16_i32
:
2354 case INDEX_op_bswap16_i64
:
2355 case INDEX_op_bswap32_i32
:
2356 case INDEX_op_bswap32_i64
:
2357 case INDEX_op_bswap64_i64
:
2359 TCGArg flags
= op
->args
[k
];
2360 const char *name
= NULL
;
2362 if (flags
< ARRAY_SIZE(bswap_flag_name
)) {
2363 name
= bswap_flag_name
[flags
];
2366 col
+= ne_fprintf(f
, ",%s", name
);
2368 col
+= ne_fprintf(f
, ",$0x%" TCG_PRIlx
, flags
);
2378 case INDEX_op_set_label
:
2380 case INDEX_op_brcond_i32
:
2381 case INDEX_op_brcond_i64
:
2382 case INDEX_op_brcond2_i32
:
2383 col
+= ne_fprintf(f
, "%s$L%d", k
? "," : "",
2384 arg_label(op
->args
[k
])->id
);
2389 TCGBar membar
= op
->args
[k
];
2390 const char *b_op
, *m_op
;
2392 switch (membar
& TCG_BAR_SC
) {
2406 g_assert_not_reached();
2409 switch (membar
& TCG_MO_ALL
) {
2425 case TCG_MO_LD_LD
| TCG_MO_LD_ST
:
2428 case TCG_MO_LD_LD
| TCG_MO_ST_LD
:
2431 case TCG_MO_LD_LD
| TCG_MO_ST_ST
:
2434 case TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2437 case TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2440 case TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2443 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_LD
:
2446 case TCG_MO_LD_LD
| TCG_MO_LD_ST
| TCG_MO_ST_ST
:
2449 case TCG_MO_LD_LD
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2452 case TCG_MO_LD_ST
| TCG_MO_ST_LD
| TCG_MO_ST_ST
:
2459 g_assert_not_reached();
2462 col
+= ne_fprintf(f
, "%s%s:%s", (k
? "," : ""), b_op
, m_op
);
2469 for (; i
< nb_cargs
; i
++, k
++) {
2470 col
+= ne_fprintf(f
, "%s$0x%" TCG_PRIlx
, k
? "," : "",
2475 if (have_prefs
|| op
->life
) {
2476 for (; col
< 40; ++col
) {
2482 unsigned life
= op
->life
;
2484 if (life
& (SYNC_ARG
* 3)) {
2485 ne_fprintf(f
, " sync:");
2486 for (i
= 0; i
< 2; ++i
) {
2487 if (life
& (SYNC_ARG
<< i
)) {
2488 ne_fprintf(f
, " %d", i
);
2494 ne_fprintf(f
, " dead:");
2495 for (i
= 0; life
; ++i
, life
>>= 1) {
2497 ne_fprintf(f
, " %d", i
);
2504 for (i
= 0; i
< nb_oargs
; ++i
) {
2505 TCGRegSet set
= output_pref(op
, i
);
2508 ne_fprintf(f
, " pref=");
2513 ne_fprintf(f
, "none");
2514 } else if (set
== MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS
)) {
2515 ne_fprintf(f
, "all");
2516 #ifdef CONFIG_DEBUG_TCG
2517 } else if (tcg_regset_single(set
)) {
2518 TCGReg reg
= tcg_regset_first(set
);
2519 ne_fprintf(f
, "%s", tcg_target_reg_names
[reg
]);
2521 } else if (TCG_TARGET_NB_REGS
<= 32) {
2522 ne_fprintf(f
, "0x%x", (uint32_t)set
);
2524 ne_fprintf(f
, "0x%" PRIx64
, (uint64_t)set
);
2533 /* we give more priority to constraints with less registers */
2534 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
2536 const TCGArgConstraint
*arg_ct
= &def
->args_ct
[k
];
2537 int n
= ctpop64(arg_ct
->regs
);
2540 * Sort constraints of a single register first, which includes output
2541 * aliases (which must exactly match the input already allocated).
2543 if (n
== 1 || arg_ct
->oalias
) {
2548 * Sort register pairs next, first then second immediately after.
2549 * Arbitrarily sort multiple pairs by the index of the first reg;
2550 * there shouldn't be many pairs.
2552 switch (arg_ct
->pair
) {
2557 return (arg_ct
->pair_index
+ 1) * 2 - 1;
2560 /* Finally, sort by decreasing register count. */
2565 /* sort from highest priority to lowest */
2566 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
2569 TCGArgConstraint
*a
= def
->args_ct
;
2571 for (i
= 0; i
< n
; i
++) {
2572 a
[start
+ i
].sort_index
= start
+ i
;
2577 for (i
= 0; i
< n
- 1; i
++) {
2578 for (j
= i
+ 1; j
< n
; j
++) {
2579 int p1
= get_constraint_priority(def
, a
[start
+ i
].sort_index
);
2580 int p2
= get_constraint_priority(def
, a
[start
+ j
].sort_index
);
2582 int tmp
= a
[start
+ i
].sort_index
;
2583 a
[start
+ i
].sort_index
= a
[start
+ j
].sort_index
;
2584 a
[start
+ j
].sort_index
= tmp
;
2590 static void process_op_defs(TCGContext
*s
)
2594 for (op
= 0; op
< NB_OPS
; op
++) {
2595 TCGOpDef
*def
= &tcg_op_defs
[op
];
2596 const TCGTargetOpDef
*tdefs
;
2597 bool saw_alias_pair
= false;
2598 int i
, o
, i2
, o2
, nb_args
;
2600 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2604 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
2610 * Macro magic should make it impossible, but double-check that
2611 * the array index is in range. Since the signness of an enum
2612 * is implementation defined, force the result to unsigned.
2614 unsigned con_set
= tcg_target_op_def(op
);
2615 tcg_debug_assert(con_set
< ARRAY_SIZE(constraint_sets
));
2616 tdefs
= &constraint_sets
[con_set
];
2618 for (i
= 0; i
< nb_args
; i
++) {
2619 const char *ct_str
= tdefs
->args_ct_str
[i
];
2620 bool input_p
= i
>= def
->nb_oargs
;
2622 /* Incomplete TCGTargetOpDef entry. */
2623 tcg_debug_assert(ct_str
!= NULL
);
2628 tcg_debug_assert(input_p
);
2629 tcg_debug_assert(o
< def
->nb_oargs
);
2630 tcg_debug_assert(def
->args_ct
[o
].regs
!= 0);
2631 tcg_debug_assert(!def
->args_ct
[o
].oalias
);
2632 def
->args_ct
[i
] = def
->args_ct
[o
];
2633 /* The output sets oalias. */
2634 def
->args_ct
[o
].oalias
= 1;
2635 def
->args_ct
[o
].alias_index
= i
;
2636 /* The input sets ialias. */
2637 def
->args_ct
[i
].ialias
= 1;
2638 def
->args_ct
[i
].alias_index
= o
;
2639 if (def
->args_ct
[i
].pair
) {
2640 saw_alias_pair
= true;
2642 tcg_debug_assert(ct_str
[1] == '\0');
2646 tcg_debug_assert(!input_p
);
2647 def
->args_ct
[i
].newreg
= true;
2651 case 'p': /* plus */
2652 /* Allocate to the register after the previous. */
2653 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2655 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2656 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2657 def
->args_ct
[i
] = (TCGArgConstraint
){
2660 .regs
= def
->args_ct
[o
].regs
<< 1,
2662 def
->args_ct
[o
].pair
= 1;
2663 def
->args_ct
[o
].pair_index
= i
;
2664 tcg_debug_assert(ct_str
[1] == '\0');
2667 case 'm': /* minus */
2668 /* Allocate to the register before the previous. */
2669 tcg_debug_assert(i
> (input_p
? def
->nb_oargs
: 0));
2671 tcg_debug_assert(!def
->args_ct
[o
].pair
);
2672 tcg_debug_assert(!def
->args_ct
[o
].ct
);
2673 def
->args_ct
[i
] = (TCGArgConstraint
){
2676 .regs
= def
->args_ct
[o
].regs
>> 1,
2678 def
->args_ct
[o
].pair
= 2;
2679 def
->args_ct
[o
].pair_index
= i
;
2680 tcg_debug_assert(ct_str
[1] == '\0');
2687 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
2690 /* Include all of the target-specific constraints. */
2693 #define CONST(CASE, MASK) \
2694 case CASE: def->args_ct[i].ct |= MASK; break;
2695 #define REGS(CASE, MASK) \
2696 case CASE: def->args_ct[i].regs |= MASK; break;
2698 #include "tcg-target-con-str.h"
2707 /* Typo in TCGTargetOpDef constraint. */
2708 g_assert_not_reached();
2710 } while (*++ct_str
!= '\0');
2713 /* TCGTargetOpDef entry with too much information? */
2714 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
2717 * Fix up output pairs that are aliased with inputs.
2718 * When we created the alias, we copied pair from the output.
2719 * There are three cases:
2720 * (1a) Pairs of inputs alias pairs of outputs.
2721 * (1b) One input aliases the first of a pair of outputs.
2722 * (2) One input aliases the second of a pair of outputs.
2724 * Case 1a is handled by making sure that the pair_index'es are
2725 * properly updated so that they appear the same as a pair of inputs.
2727 * Case 1b is handled by setting the pair_index of the input to
2728 * itself, simply so it doesn't point to an unrelated argument.
2729 * Since we don't encounter the "second" during the input allocation
2730 * phase, nothing happens with the second half of the input pair.
2732 * Case 2 is handled by setting the second input to pair=3, the
2733 * first output to pair=3, and the pair_index'es to match.
2735 if (saw_alias_pair
) {
2736 for (i
= def
->nb_oargs
; i
< nb_args
; i
++) {
2738 * Since [0-9pm] must be alone in the constraint string,
2739 * the only way they can both be set is if the pair comes
2740 * from the output alias.
2742 if (!def
->args_ct
[i
].ialias
) {
2745 switch (def
->args_ct
[i
].pair
) {
2749 o
= def
->args_ct
[i
].alias_index
;
2750 o2
= def
->args_ct
[o
].pair_index
;
2751 tcg_debug_assert(def
->args_ct
[o
].pair
== 1);
2752 tcg_debug_assert(def
->args_ct
[o2
].pair
== 2);
2753 if (def
->args_ct
[o2
].oalias
) {
2755 i2
= def
->args_ct
[o2
].alias_index
;
2756 tcg_debug_assert(def
->args_ct
[i2
].pair
== 2);
2757 def
->args_ct
[i2
].pair_index
= i
;
2758 def
->args_ct
[i
].pair_index
= i2
;
2761 def
->args_ct
[i
].pair_index
= i
;
2765 o
= def
->args_ct
[i
].alias_index
;
2766 o2
= def
->args_ct
[o
].pair_index
;
2767 tcg_debug_assert(def
->args_ct
[o
].pair
== 2);
2768 tcg_debug_assert(def
->args_ct
[o2
].pair
== 1);
2769 if (def
->args_ct
[o2
].oalias
) {
2771 i2
= def
->args_ct
[o2
].alias_index
;
2772 tcg_debug_assert(def
->args_ct
[i2
].pair
== 1);
2773 def
->args_ct
[i2
].pair_index
= i
;
2774 def
->args_ct
[i
].pair_index
= i2
;
2777 def
->args_ct
[i
].pair
= 3;
2778 def
->args_ct
[o2
].pair
= 3;
2779 def
->args_ct
[i
].pair_index
= o2
;
2780 def
->args_ct
[o2
].pair_index
= i
;
2784 g_assert_not_reached();
2789 /* sort the constraints (XXX: this is just an heuristic) */
2790 sort_constraints(def
, 0, def
->nb_oargs
);
2791 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
2795 static void remove_label_use(TCGOp
*op
, int idx
)
2797 TCGLabel
*label
= arg_label(op
->args
[idx
]);
2800 QSIMPLEQ_FOREACH(use
, &label
->branches
, next
) {
2801 if (use
->op
== op
) {
2802 QSIMPLEQ_REMOVE(&label
->branches
, use
, TCGLabelUse
, next
);
2806 g_assert_not_reached();
2809 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
2813 remove_label_use(op
, 0);
2815 case INDEX_op_brcond_i32
:
2816 case INDEX_op_brcond_i64
:
2817 remove_label_use(op
, 3);
2819 case INDEX_op_brcond2_i32
:
2820 remove_label_use(op
, 5);
2826 QTAILQ_REMOVE(&s
->ops
, op
, link
);
2827 QTAILQ_INSERT_TAIL(&s
->free_ops
, op
, link
);
2830 #ifdef CONFIG_PROFILER
2831 qatomic_set(&s
->prof
.del_op_count
, s
->prof
.del_op_count
+ 1);
2835 void tcg_remove_ops_after(TCGOp
*op
)
2837 TCGContext
*s
= tcg_ctx
;
2840 TCGOp
*last
= tcg_last_op();
2844 tcg_op_remove(s
, last
);
2848 static TCGOp
*tcg_op_alloc(TCGOpcode opc
, unsigned nargs
)
2850 TCGContext
*s
= tcg_ctx
;
2853 if (unlikely(!QTAILQ_EMPTY(&s
->free_ops
))) {
2854 QTAILQ_FOREACH(op
, &s
->free_ops
, link
) {
2855 if (nargs
<= op
->nargs
) {
2856 QTAILQ_REMOVE(&s
->free_ops
, op
, link
);
2863 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */
2864 nargs
= MAX(4, nargs
);
2865 op
= tcg_malloc(sizeof(TCGOp
) + sizeof(TCGArg
) * nargs
);
2868 memset(op
, 0, offsetof(TCGOp
, link
));
2872 /* Check for bitfield overflow. */
2873 tcg_debug_assert(op
->nargs
== nargs
);
2879 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
)
2881 TCGOp
*op
= tcg_op_alloc(opc
, nargs
);
2882 QTAILQ_INSERT_TAIL(&tcg_ctx
->ops
, op
, link
);
2886 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
2887 TCGOpcode opc
, unsigned nargs
)
2889 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
2890 QTAILQ_INSERT_BEFORE(old_op
, new_op
, link
);
2894 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
2895 TCGOpcode opc
, unsigned nargs
)
2897 TCGOp
*new_op
= tcg_op_alloc(opc
, nargs
);
2898 QTAILQ_INSERT_AFTER(&s
->ops
, old_op
, new_op
, link
);
2902 static void move_label_uses(TCGLabel
*to
, TCGLabel
*from
)
2906 QSIMPLEQ_FOREACH(u
, &from
->branches
, next
) {
2910 op
->args
[0] = label_arg(to
);
2912 case INDEX_op_brcond_i32
:
2913 case INDEX_op_brcond_i64
:
2914 op
->args
[3] = label_arg(to
);
2916 case INDEX_op_brcond2_i32
:
2917 op
->args
[5] = label_arg(to
);
2920 g_assert_not_reached();
2924 QSIMPLEQ_CONCAT(&to
->branches
, &from
->branches
);
2927 /* Reachable analysis : remove unreachable code. */
2928 static void __attribute__((noinline
))
2929 reachable_code_pass(TCGContext
*s
)
2931 TCGOp
*op
, *op_next
, *op_prev
;
2934 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
2939 case INDEX_op_set_label
:
2940 label
= arg_label(op
->args
[0]);
2943 * Note that the first op in the TB is always a load,
2944 * so there is always something before a label.
2946 op_prev
= QTAILQ_PREV(op
, link
);
2949 * If we find two sequential labels, move all branches to
2950 * reference the second label and remove the first label.
2951 * Do this before branch to next optimization, so that the
2952 * middle label is out of the way.
2954 if (op_prev
->opc
== INDEX_op_set_label
) {
2955 move_label_uses(label
, arg_label(op_prev
->args
[0]));
2956 tcg_op_remove(s
, op_prev
);
2957 op_prev
= QTAILQ_PREV(op
, link
);
2961 * Optimization can fold conditional branches to unconditional.
2962 * If we find a label which is preceded by an unconditional
2963 * branch to next, remove the branch. We couldn't do this when
2964 * processing the branch because any dead code between the branch
2965 * and label had not yet been removed.
2967 if (op_prev
->opc
== INDEX_op_br
&&
2968 label
== arg_label(op_prev
->args
[0])) {
2969 tcg_op_remove(s
, op_prev
);
2970 /* Fall through means insns become live again. */
2974 if (QSIMPLEQ_EMPTY(&label
->branches
)) {
2976 * While there is an occasional backward branch, virtually
2977 * all branches generated by the translators are forward.
2978 * Which means that generally we will have already removed
2979 * all references to the label that will be, and there is
2980 * little to be gained by iterating.
2984 /* Once we see a label, insns become live again. */
2991 case INDEX_op_exit_tb
:
2992 case INDEX_op_goto_ptr
:
2993 /* Unconditional branches; everything following is dead. */
2998 /* Notice noreturn helper calls, raising exceptions. */
2999 if (tcg_call_flags(op
) & TCG_CALL_NO_RETURN
) {
3004 case INDEX_op_insn_start
:
3005 /* Never remove -- we need to keep these for unwind. */
3014 tcg_op_remove(s
, op
);
3022 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
3023 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
3025 /* For liveness_pass_1, the register preferences for a given temp. */
3026 static inline TCGRegSet
*la_temp_pref(TCGTemp
*ts
)
3028 return ts
->state_ptr
;
3031 /* For liveness_pass_1, reset the preferences for a given temp to the
3032 * maximal regset for its type.
3034 static inline void la_reset_pref(TCGTemp
*ts
)
3037 = (ts
->state
== TS_DEAD
? 0 : tcg_target_available_regs
[ts
->type
]);
3040 /* liveness analysis: end of function: all temps are dead, and globals
3041 should be in memory. */
3042 static void la_func_end(TCGContext
*s
, int ng
, int nt
)
3046 for (i
= 0; i
< ng
; ++i
) {
3047 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3048 la_reset_pref(&s
->temps
[i
]);
3050 for (i
= ng
; i
< nt
; ++i
) {
3051 s
->temps
[i
].state
= TS_DEAD
;
3052 la_reset_pref(&s
->temps
[i
]);
3056 /* liveness analysis: end of basic block: all temps are dead, globals
3057 and local temps should be in memory. */
3058 static void la_bb_end(TCGContext
*s
, int ng
, int nt
)
3062 for (i
= 0; i
< nt
; ++i
) {
3063 TCGTemp
*ts
= &s
->temps
[i
];
3070 state
= TS_DEAD
| TS_MEM
;
3077 g_assert_not_reached();
3084 /* liveness analysis: sync globals back to memory. */
3085 static void la_global_sync(TCGContext
*s
, int ng
)
3089 for (i
= 0; i
< ng
; ++i
) {
3090 int state
= s
->temps
[i
].state
;
3091 s
->temps
[i
].state
= state
| TS_MEM
;
3092 if (state
== TS_DEAD
) {
3093 /* If the global was previously dead, reset prefs. */
3094 la_reset_pref(&s
->temps
[i
]);
3100 * liveness analysis: conditional branch: all temps are dead unless
3101 * explicitly live-across-conditional-branch, globals and local temps
3104 static void la_bb_sync(TCGContext
*s
, int ng
, int nt
)
3106 la_global_sync(s
, ng
);
3108 for (int i
= ng
; i
< nt
; ++i
) {
3109 TCGTemp
*ts
= &s
->temps
[i
];
3115 ts
->state
= state
| TS_MEM
;
3116 if (state
!= TS_DEAD
) {
3124 g_assert_not_reached();
3126 la_reset_pref(&s
->temps
[i
]);
3130 /* liveness analysis: sync globals back to memory and kill. */
3131 static void la_global_kill(TCGContext
*s
, int ng
)
3135 for (i
= 0; i
< ng
; i
++) {
3136 s
->temps
[i
].state
= TS_DEAD
| TS_MEM
;
3137 la_reset_pref(&s
->temps
[i
]);
3141 /* liveness analysis: note live globals crossing calls. */
3142 static void la_cross_call(TCGContext
*s
, int nt
)
3144 TCGRegSet mask
= ~tcg_target_call_clobber_regs
;
3147 for (i
= 0; i
< nt
; i
++) {
3148 TCGTemp
*ts
= &s
->temps
[i
];
3149 if (!(ts
->state
& TS_DEAD
)) {
3150 TCGRegSet
*pset
= la_temp_pref(ts
);
3151 TCGRegSet set
= *pset
;
3154 /* If the combination is not possible, restart. */
3156 set
= tcg_target_available_regs
[ts
->type
] & mask
;
3164 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce
3165 * to TEMP_EBB, if possible.
3167 static void __attribute__((noinline
))
3168 liveness_pass_0(TCGContext
*s
)
3170 void * const multiple_ebb
= (void *)(uintptr_t)-1;
3171 int nb_temps
= s
->nb_temps
;
3174 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3175 s
->temps
[i
].state_ptr
= NULL
;
3179 * Represent each EBB by the op at which it begins. In the case of
3180 * the first EBB, this is the first op, otherwise it is a label.
3181 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use
3182 * within a single EBB, else MULTIPLE_EBB.
3184 ebb
= QTAILQ_FIRST(&s
->ops
);
3185 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
3186 const TCGOpDef
*def
;
3187 int nb_oargs
, nb_iargs
;
3190 case INDEX_op_set_label
:
3193 case INDEX_op_discard
:
3196 nb_oargs
= TCGOP_CALLO(op
);
3197 nb_iargs
= TCGOP_CALLI(op
);
3200 def
= &tcg_op_defs
[op
->opc
];
3201 nb_oargs
= def
->nb_oargs
;
3202 nb_iargs
= def
->nb_iargs
;
3206 for (int i
= 0; i
< nb_oargs
+ nb_iargs
; ++i
) {
3207 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
3209 if (ts
->kind
!= TEMP_TB
) {
3212 if (ts
->state_ptr
== NULL
) {
3213 ts
->state_ptr
= ebb
;
3214 } else if (ts
->state_ptr
!= ebb
) {
3215 ts
->state_ptr
= multiple_ebb
;
3221 * For TEMP_TB that turned out not to be used beyond one EBB,
3222 * reduce the liveness to TEMP_EBB.
3224 for (int i
= s
->nb_globals
; i
< nb_temps
; ++i
) {
3225 TCGTemp
*ts
= &s
->temps
[i
];
3226 if (ts
->kind
== TEMP_TB
&& ts
->state_ptr
!= multiple_ebb
) {
3227 ts
->kind
= TEMP_EBB
;
3232 /* Liveness analysis : update the opc_arg_life array to tell if a
3233 given input arguments is dead. Instructions updating dead
3234 temporaries are removed. */
3235 static void __attribute__((noinline
))
3236 liveness_pass_1(TCGContext
*s
)
3238 int nb_globals
= s
->nb_globals
;
3239 int nb_temps
= s
->nb_temps
;
3240 TCGOp
*op
, *op_prev
;
3244 prefs
= tcg_malloc(sizeof(TCGRegSet
) * nb_temps
);
3245 for (i
= 0; i
< nb_temps
; ++i
) {
3246 s
->temps
[i
].state_ptr
= prefs
+ i
;
3249 /* ??? Should be redundant with the exit_tb that ends the TB. */
3250 la_func_end(s
, nb_globals
, nb_temps
);
3252 QTAILQ_FOREACH_REVERSE_SAFE(op
, &s
->ops
, link
, op_prev
) {
3253 int nb_iargs
, nb_oargs
;
3254 TCGOpcode opc_new
, opc_new2
;
3256 TCGLifeData arg_life
= 0;
3258 TCGOpcode opc
= op
->opc
;
3259 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3264 const TCGHelperInfo
*info
= tcg_call_info(op
);
3265 int call_flags
= tcg_call_flags(op
);
3267 nb_oargs
= TCGOP_CALLO(op
);
3268 nb_iargs
= TCGOP_CALLI(op
);
3270 /* pure functions can be removed if their result is unused */
3271 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
3272 for (i
= 0; i
< nb_oargs
; i
++) {
3273 ts
= arg_temp(op
->args
[i
]);
3274 if (ts
->state
!= TS_DEAD
) {
3275 goto do_not_remove_call
;
3282 /* Output args are dead. */
3283 for (i
= 0; i
< nb_oargs
; i
++) {
3284 ts
= arg_temp(op
->args
[i
]);
3285 if (ts
->state
& TS_DEAD
) {
3286 arg_life
|= DEAD_ARG
<< i
;
3288 if (ts
->state
& TS_MEM
) {
3289 arg_life
|= SYNC_ARG
<< i
;
3291 ts
->state
= TS_DEAD
;
3295 /* Not used -- it will be tcg_target_call_oarg_reg(). */
3296 memset(op
->output_pref
, 0, sizeof(op
->output_pref
));
3298 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
3299 TCG_CALL_NO_READ_GLOBALS
))) {
3300 la_global_kill(s
, nb_globals
);
3301 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
3302 la_global_sync(s
, nb_globals
);
3305 /* Record arguments that die in this helper. */
3306 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3307 ts
= arg_temp(op
->args
[i
]);
3308 if (ts
->state
& TS_DEAD
) {
3309 arg_life
|= DEAD_ARG
<< i
;
3313 /* For all live registers, remove call-clobbered prefs. */
3314 la_cross_call(s
, nb_temps
);
3317 * Input arguments are live for preceding opcodes.
3319 * For those arguments that die, and will be allocated in
3320 * registers, clear the register set for that arg, to be
3321 * filled in below. For args that will be on the stack,
3322 * reset to any available reg. Process arguments in reverse
3323 * order so that if a temp is used more than once, the stack
3324 * reset to max happens before the register reset to 0.
3326 for (i
= nb_iargs
- 1; i
>= 0; i
--) {
3327 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3328 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3330 if (ts
->state
& TS_DEAD
) {
3331 switch (loc
->kind
) {
3332 case TCG_CALL_ARG_NORMAL
:
3333 case TCG_CALL_ARG_EXTEND_U
:
3334 case TCG_CALL_ARG_EXTEND_S
:
3335 if (arg_slot_reg_p(loc
->arg_slot
)) {
3336 *la_temp_pref(ts
) = 0;
3342 tcg_target_available_regs
[ts
->type
];
3345 ts
->state
&= ~TS_DEAD
;
3350 * For each input argument, add its input register to prefs.
3351 * If a temp is used once, this produces a single set bit;
3352 * if a temp is used multiple times, this produces a set.
3354 for (i
= 0; i
< nb_iargs
; i
++) {
3355 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
3356 ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
3358 switch (loc
->kind
) {
3359 case TCG_CALL_ARG_NORMAL
:
3360 case TCG_CALL_ARG_EXTEND_U
:
3361 case TCG_CALL_ARG_EXTEND_S
:
3362 if (arg_slot_reg_p(loc
->arg_slot
)) {
3363 tcg_regset_set_reg(*la_temp_pref(ts
),
3364 tcg_target_call_iarg_regs
[loc
->arg_slot
]);
3373 case INDEX_op_insn_start
:
3375 case INDEX_op_discard
:
3376 /* mark the temporary as dead */
3377 ts
= arg_temp(op
->args
[0]);
3378 ts
->state
= TS_DEAD
;
3382 case INDEX_op_add2_i32
:
3383 opc_new
= INDEX_op_add_i32
;
3385 case INDEX_op_sub2_i32
:
3386 opc_new
= INDEX_op_sub_i32
;
3388 case INDEX_op_add2_i64
:
3389 opc_new
= INDEX_op_add_i64
;
3391 case INDEX_op_sub2_i64
:
3392 opc_new
= INDEX_op_sub_i64
;
3396 /* Test if the high part of the operation is dead, but not
3397 the low part. The result can be optimized to a simple
3398 add or sub. This happens often for x86_64 guest when the
3399 cpu mode is set to 32 bit. */
3400 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3401 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3404 /* Replace the opcode and adjust the args in place,
3405 leaving 3 unused args at the end. */
3406 op
->opc
= opc
= opc_new
;
3407 op
->args
[1] = op
->args
[2];
3408 op
->args
[2] = op
->args
[4];
3409 /* Fall through and mark the single-word operation live. */
3415 case INDEX_op_mulu2_i32
:
3416 opc_new
= INDEX_op_mul_i32
;
3417 opc_new2
= INDEX_op_muluh_i32
;
3418 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
3420 case INDEX_op_muls2_i32
:
3421 opc_new
= INDEX_op_mul_i32
;
3422 opc_new2
= INDEX_op_mulsh_i32
;
3423 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
3425 case INDEX_op_mulu2_i64
:
3426 opc_new
= INDEX_op_mul_i64
;
3427 opc_new2
= INDEX_op_muluh_i64
;
3428 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
3430 case INDEX_op_muls2_i64
:
3431 opc_new
= INDEX_op_mul_i64
;
3432 opc_new2
= INDEX_op_mulsh_i64
;
3433 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
3438 if (arg_temp(op
->args
[1])->state
== TS_DEAD
) {
3439 if (arg_temp(op
->args
[0])->state
== TS_DEAD
) {
3440 /* Both parts of the operation are dead. */
3443 /* The high part of the operation is dead; generate the low. */
3444 op
->opc
= opc
= opc_new
;
3445 op
->args
[1] = op
->args
[2];
3446 op
->args
[2] = op
->args
[3];
3447 } else if (arg_temp(op
->args
[0])->state
== TS_DEAD
&& have_opc_new2
) {
3448 /* The low part of the operation is dead; generate the high. */
3449 op
->opc
= opc
= opc_new2
;
3450 op
->args
[0] = op
->args
[1];
3451 op
->args
[1] = op
->args
[2];
3452 op
->args
[2] = op
->args
[3];
3456 /* Mark the single-word operation live. */
3461 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
3462 nb_iargs
= def
->nb_iargs
;
3463 nb_oargs
= def
->nb_oargs
;
3465 /* Test if the operation can be removed because all
3466 its outputs are dead. We assume that nb_oargs == 0
3467 implies side effects */
3468 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
3469 for (i
= 0; i
< nb_oargs
; i
++) {
3470 if (arg_temp(op
->args
[i
])->state
!= TS_DEAD
) {
3479 tcg_op_remove(s
, op
);
3483 for (i
= 0; i
< nb_oargs
; i
++) {
3484 ts
= arg_temp(op
->args
[i
]);
3486 /* Remember the preference of the uses that followed. */
3487 if (i
< ARRAY_SIZE(op
->output_pref
)) {
3488 op
->output_pref
[i
] = *la_temp_pref(ts
);
3491 /* Output args are dead. */
3492 if (ts
->state
& TS_DEAD
) {
3493 arg_life
|= DEAD_ARG
<< i
;
3495 if (ts
->state
& TS_MEM
) {
3496 arg_life
|= SYNC_ARG
<< i
;
3498 ts
->state
= TS_DEAD
;
3502 /* If end of basic block, update. */
3503 if (def
->flags
& TCG_OPF_BB_EXIT
) {
3504 la_func_end(s
, nb_globals
, nb_temps
);
3505 } else if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3506 la_bb_sync(s
, nb_globals
, nb_temps
);
3507 } else if (def
->flags
& TCG_OPF_BB_END
) {
3508 la_bb_end(s
, nb_globals
, nb_temps
);
3509 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3510 la_global_sync(s
, nb_globals
);
3511 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
3512 la_cross_call(s
, nb_temps
);
3516 /* Record arguments that die in this opcode. */
3517 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3518 ts
= arg_temp(op
->args
[i
]);
3519 if (ts
->state
& TS_DEAD
) {
3520 arg_life
|= DEAD_ARG
<< i
;
3524 /* Input arguments are live for preceding opcodes. */
3525 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3526 ts
= arg_temp(op
->args
[i
]);
3527 if (ts
->state
& TS_DEAD
) {
3528 /* For operands that were dead, initially allow
3529 all regs for the type. */
3530 *la_temp_pref(ts
) = tcg_target_available_regs
[ts
->type
];
3531 ts
->state
&= ~TS_DEAD
;
3535 /* Incorporate constraints for this operand. */
3537 case INDEX_op_mov_i32
:
3538 case INDEX_op_mov_i64
:
3539 /* Note that these are TCG_OPF_NOT_PRESENT and do not
3540 have proper constraints. That said, special case
3541 moves to propagate preferences backward. */
3542 if (IS_DEAD_ARG(1)) {
3543 *la_temp_pref(arg_temp(op
->args
[0]))
3544 = *la_temp_pref(arg_temp(op
->args
[1]));
3549 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
3550 const TCGArgConstraint
*ct
= &def
->args_ct
[i
];
3551 TCGRegSet set
, *pset
;
3553 ts
= arg_temp(op
->args
[i
]);
3554 pset
= la_temp_pref(ts
);
3559 set
&= output_pref(op
, ct
->alias_index
);
3561 /* If the combination is not possible, restart. */
3571 op
->life
= arg_life
;
3575 /* Liveness analysis: Convert indirect regs to direct temporaries. */
3576 static bool __attribute__((noinline
))
3577 liveness_pass_2(TCGContext
*s
)
3579 int nb_globals
= s
->nb_globals
;
3581 bool changes
= false;
3582 TCGOp
*op
, *op_next
;
3584 /* Create a temporary for each indirect global. */
3585 for (i
= 0; i
< nb_globals
; ++i
) {
3586 TCGTemp
*its
= &s
->temps
[i
];
3587 if (its
->indirect_reg
) {
3588 TCGTemp
*dts
= tcg_temp_alloc(s
);
3589 dts
->type
= its
->type
;
3590 dts
->base_type
= its
->base_type
;
3591 dts
->temp_subindex
= its
->temp_subindex
;
3592 dts
->kind
= TEMP_EBB
;
3593 its
->state_ptr
= dts
;
3595 its
->state_ptr
= NULL
;
3597 /* All globals begin dead. */
3598 its
->state
= TS_DEAD
;
3600 for (nb_temps
= s
->nb_temps
; i
< nb_temps
; ++i
) {
3601 TCGTemp
*its
= &s
->temps
[i
];
3602 its
->state_ptr
= NULL
;
3603 its
->state
= TS_DEAD
;
3606 QTAILQ_FOREACH_SAFE(op
, &s
->ops
, link
, op_next
) {
3607 TCGOpcode opc
= op
->opc
;
3608 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
3609 TCGLifeData arg_life
= op
->life
;
3610 int nb_iargs
, nb_oargs
, call_flags
;
3611 TCGTemp
*arg_ts
, *dir_ts
;
3613 if (opc
== INDEX_op_call
) {
3614 nb_oargs
= TCGOP_CALLO(op
);
3615 nb_iargs
= TCGOP_CALLI(op
);
3616 call_flags
= tcg_call_flags(op
);
3618 nb_iargs
= def
->nb_iargs
;
3619 nb_oargs
= def
->nb_oargs
;
3621 /* Set flags similar to how calls require. */
3622 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
3623 /* Like reading globals: sync_globals */
3624 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3625 } else if (def
->flags
& TCG_OPF_BB_END
) {
3626 /* Like writing globals: save_globals */
3628 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
3629 /* Like reading globals: sync_globals */
3630 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
3632 /* No effect on globals. */
3633 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
3634 TCG_CALL_NO_WRITE_GLOBALS
);
3638 /* Make sure that input arguments are available. */
3639 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3640 arg_ts
= arg_temp(op
->args
[i
]);
3641 dir_ts
= arg_ts
->state_ptr
;
3642 if (dir_ts
&& arg_ts
->state
== TS_DEAD
) {
3643 TCGOpcode lopc
= (arg_ts
->type
== TCG_TYPE_I32
3646 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
3648 lop
->args
[0] = temp_arg(dir_ts
);
3649 lop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3650 lop
->args
[2] = arg_ts
->mem_offset
;
3652 /* Loaded, but synced with memory. */
3653 arg_ts
->state
= TS_MEM
;
3657 /* Perform input replacement, and mark inputs that became dead.
3658 No action is required except keeping temp_state up to date
3659 so that we reload when needed. */
3660 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
3661 arg_ts
= arg_temp(op
->args
[i
]);
3662 dir_ts
= arg_ts
->state_ptr
;
3664 op
->args
[i
] = temp_arg(dir_ts
);
3666 if (IS_DEAD_ARG(i
)) {
3667 arg_ts
->state
= TS_DEAD
;
3672 /* Liveness analysis should ensure that the following are
3673 all correct, for call sites and basic block end points. */
3674 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
3676 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
3677 for (i
= 0; i
< nb_globals
; ++i
) {
3678 /* Liveness should see that globals are synced back,
3679 that is, either TS_DEAD or TS_MEM. */
3680 arg_ts
= &s
->temps
[i
];
3681 tcg_debug_assert(arg_ts
->state_ptr
== 0
3682 || arg_ts
->state
!= 0);
3685 for (i
= 0; i
< nb_globals
; ++i
) {
3686 /* Liveness should see that globals are saved back,
3687 that is, TS_DEAD, waiting to be reloaded. */
3688 arg_ts
= &s
->temps
[i
];
3689 tcg_debug_assert(arg_ts
->state_ptr
== 0
3690 || arg_ts
->state
== TS_DEAD
);
3694 /* Outputs become available. */
3695 if (opc
== INDEX_op_mov_i32
|| opc
== INDEX_op_mov_i64
) {
3696 arg_ts
= arg_temp(op
->args
[0]);
3697 dir_ts
= arg_ts
->state_ptr
;
3699 op
->args
[0] = temp_arg(dir_ts
);
3702 /* The output is now live and modified. */
3705 if (NEED_SYNC_ARG(0)) {
3706 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3709 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3710 TCGTemp
*out_ts
= dir_ts
;
3712 if (IS_DEAD_ARG(0)) {
3713 out_ts
= arg_temp(op
->args
[1]);
3714 arg_ts
->state
= TS_DEAD
;
3715 tcg_op_remove(s
, op
);
3717 arg_ts
->state
= TS_MEM
;
3720 sop
->args
[0] = temp_arg(out_ts
);
3721 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3722 sop
->args
[2] = arg_ts
->mem_offset
;
3724 tcg_debug_assert(!IS_DEAD_ARG(0));
3728 for (i
= 0; i
< nb_oargs
; i
++) {
3729 arg_ts
= arg_temp(op
->args
[i
]);
3730 dir_ts
= arg_ts
->state_ptr
;
3734 op
->args
[i
] = temp_arg(dir_ts
);
3737 /* The output is now live and modified. */
3740 /* Sync outputs upon their last write. */
3741 if (NEED_SYNC_ARG(i
)) {
3742 TCGOpcode sopc
= (arg_ts
->type
== TCG_TYPE_I32
3745 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
3747 sop
->args
[0] = temp_arg(dir_ts
);
3748 sop
->args
[1] = temp_arg(arg_ts
->mem_base
);
3749 sop
->args
[2] = arg_ts
->mem_offset
;
3751 arg_ts
->state
= TS_MEM
;
3753 /* Drop outputs that are dead. */
3754 if (IS_DEAD_ARG(i
)) {
3755 arg_ts
->state
= TS_DEAD
;
3764 static void temp_allocate_frame(TCGContext
*s
, TCGTemp
*ts
)
3769 /* When allocating an object, look at the full type. */
3770 size
= tcg_type_size(ts
->base_type
);
3771 switch (ts
->base_type
) {
3783 * Note that we do not require aligned storage for V256,
3784 * and that we provide alignment for I128 to match V128,
3785 * even if that's above what the host ABI requires.
3790 g_assert_not_reached();
3794 * Assume the stack is sufficiently aligned.
3795 * This affects e.g. ARM NEON, where we have 8 byte stack alignment
3796 * and do not require 16 byte vector alignment. This seems slightly
3797 * easier than fully parameterizing the above switch statement.
3799 align
= MIN(TCG_TARGET_STACK_ALIGN
, align
);
3800 off
= ROUND_UP(s
->current_frame_offset
, align
);
3802 /* If we've exhausted the stack frame, restart with a smaller TB. */
3803 if (off
+ size
> s
->frame_end
) {
3804 tcg_raise_tb_overflow(s
);
3806 s
->current_frame_offset
= off
+ size
;
3807 #if defined(__sparc__)
3808 off
+= TCG_TARGET_STACK_BIAS
;
3811 /* If the object was subdivided, assign memory to all the parts. */
3812 if (ts
->base_type
!= ts
->type
) {
3813 int part_size
= tcg_type_size(ts
->type
);
3814 int part_count
= size
/ part_size
;
3817 * Each part is allocated sequentially in tcg_temp_new_internal.
3818 * Jump back to the first part by subtracting the current index.
3820 ts
-= ts
->temp_subindex
;
3821 for (int i
= 0; i
< part_count
; ++i
) {
3822 ts
[i
].mem_offset
= off
+ i
* part_size
;
3823 ts
[i
].mem_base
= s
->frame_temp
;
3824 ts
[i
].mem_allocated
= 1;
3827 ts
->mem_offset
= off
;
3828 ts
->mem_base
= s
->frame_temp
;
3829 ts
->mem_allocated
= 1;
3833 /* Assign @reg to @ts, and update reg_to_temp[]. */
3834 static void set_temp_val_reg(TCGContext
*s
, TCGTemp
*ts
, TCGReg reg
)
3836 if (ts
->val_type
== TEMP_VAL_REG
) {
3837 TCGReg old
= ts
->reg
;
3838 tcg_debug_assert(s
->reg_to_temp
[old
] == ts
);
3842 s
->reg_to_temp
[old
] = NULL
;
3844 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
3845 s
->reg_to_temp
[reg
] = ts
;
3846 ts
->val_type
= TEMP_VAL_REG
;
3850 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */
3851 static void set_temp_val_nonreg(TCGContext
*s
, TCGTemp
*ts
, TCGTempVal type
)
3853 tcg_debug_assert(type
!= TEMP_VAL_REG
);
3854 if (ts
->val_type
== TEMP_VAL_REG
) {
3855 TCGReg reg
= ts
->reg
;
3856 tcg_debug_assert(s
->reg_to_temp
[reg
] == ts
);
3857 s
->reg_to_temp
[reg
] = NULL
;
3859 ts
->val_type
= type
;
3862 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
, TCGRegSet
);
3864 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
3865 mark it free; otherwise mark it dead. */
3866 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
3868 TCGTempVal new_type
;
3875 new_type
= TEMP_VAL_MEM
;
3878 new_type
= free_or_dead
< 0 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
;
3881 new_type
= TEMP_VAL_CONST
;
3884 g_assert_not_reached();
3886 set_temp_val_nonreg(s
, ts
, new_type
);
3889 /* Mark a temporary as dead. */
3890 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
3892 temp_free_or_dead(s
, ts
, 1);
3895 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
3896 registers needs to be allocated to store a constant. If 'free_or_dead'
3897 is non-zero, subsequently release the temporary; if it is positive, the
3898 temp is dead; if it is negative, the temp is free. */
3899 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
,
3900 TCGRegSet preferred_regs
, int free_or_dead
)
3902 if (!temp_readonly(ts
) && !ts
->mem_coherent
) {
3903 if (!ts
->mem_allocated
) {
3904 temp_allocate_frame(s
, ts
);
3906 switch (ts
->val_type
) {
3907 case TEMP_VAL_CONST
:
3908 /* If we're going to free the temp immediately, then we won't
3909 require it later in a register, so attempt to store the
3910 constant to memory directly. */
3912 && tcg_out_sti(s
, ts
->type
, ts
->val
,
3913 ts
->mem_base
->reg
, ts
->mem_offset
)) {
3916 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
3917 allocated_regs
, preferred_regs
);
3921 tcg_out_st(s
, ts
->type
, ts
->reg
,
3922 ts
->mem_base
->reg
, ts
->mem_offset
);
3930 g_assert_not_reached();
3932 ts
->mem_coherent
= 1;
3935 temp_free_or_dead(s
, ts
, free_or_dead
);
3939 /* free register 'reg' by spilling the corresponding temporary if necessary */
3940 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
3942 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
3944 temp_sync(s
, ts
, allocated_regs
, 0, -1);
3950 * @required_regs: Set of registers in which we must allocate.
3951 * @allocated_regs: Set of registers which must be avoided.
3952 * @preferred_regs: Set of registers we should prefer.
3953 * @rev: True if we search the registers in "indirect" order.
3955 * The allocated register must be in @required_regs & ~@allocated_regs,
3956 * but if we can put it in @preferred_regs we may save a move later.
3958 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet required_regs
,
3959 TCGRegSet allocated_regs
,
3960 TCGRegSet preferred_regs
, bool rev
)
3962 int i
, j
, f
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
3963 TCGRegSet reg_ct
[2];
3966 reg_ct
[1] = required_regs
& ~allocated_regs
;
3967 tcg_debug_assert(reg_ct
[1] != 0);
3968 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
3970 /* Skip the preferred_regs option if it cannot be satisfied,
3971 or if the preference made no difference. */
3972 f
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
3974 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
3976 /* Try free registers, preferences first. */
3977 for (j
= f
; j
< 2; j
++) {
3978 TCGRegSet set
= reg_ct
[j
];
3980 if (tcg_regset_single(set
)) {
3981 /* One register in the set. */
3982 TCGReg reg
= tcg_regset_first(set
);
3983 if (s
->reg_to_temp
[reg
] == NULL
) {
3987 for (i
= 0; i
< n
; i
++) {
3988 TCGReg reg
= order
[i
];
3989 if (s
->reg_to_temp
[reg
] == NULL
&&
3990 tcg_regset_test_reg(set
, reg
)) {
3997 /* We must spill something. */
3998 for (j
= f
; j
< 2; j
++) {
3999 TCGRegSet set
= reg_ct
[j
];
4001 if (tcg_regset_single(set
)) {
4002 /* One register in the set. */
4003 TCGReg reg
= tcg_regset_first(set
);
4004 tcg_reg_free(s
, reg
, allocated_regs
);
4007 for (i
= 0; i
< n
; i
++) {
4008 TCGReg reg
= order
[i
];
4009 if (tcg_regset_test_reg(set
, reg
)) {
4010 tcg_reg_free(s
, reg
, allocated_regs
);
4017 g_assert_not_reached();
4020 static TCGReg
tcg_reg_alloc_pair(TCGContext
*s
, TCGRegSet required_regs
,
4021 TCGRegSet allocated_regs
,
4022 TCGRegSet preferred_regs
, bool rev
)
4024 int i
, j
, k
, fmin
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
4025 TCGRegSet reg_ct
[2];
4028 /* Ensure that if I is not in allocated_regs, I+1 is not either. */
4029 reg_ct
[1] = required_regs
& ~(allocated_regs
| (allocated_regs
>> 1));
4030 tcg_debug_assert(reg_ct
[1] != 0);
4031 reg_ct
[0] = reg_ct
[1] & preferred_regs
;
4033 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
4036 * Skip the preferred_regs option if it cannot be satisfied,
4037 * or if the preference made no difference.
4039 k
= reg_ct
[0] == 0 || reg_ct
[0] == reg_ct
[1];
4042 * Minimize the number of flushes by looking for 2 free registers first,
4043 * then a single flush, then two flushes.
4045 for (fmin
= 2; fmin
>= 0; fmin
--) {
4046 for (j
= k
; j
< 2; j
++) {
4047 TCGRegSet set
= reg_ct
[j
];
4049 for (i
= 0; i
< n
; i
++) {
4050 TCGReg reg
= order
[i
];
4052 if (tcg_regset_test_reg(set
, reg
)) {
4053 int f
= !s
->reg_to_temp
[reg
] + !s
->reg_to_temp
[reg
+ 1];
4055 tcg_reg_free(s
, reg
, allocated_regs
);
4056 tcg_reg_free(s
, reg
+ 1, allocated_regs
);
4063 g_assert_not_reached();
4066 /* Make sure the temporary is in a register. If needed, allocate the register
4067 from DESIRED while avoiding ALLOCATED. */
4068 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
4069 TCGRegSet allocated_regs
, TCGRegSet preferred_regs
)
4073 switch (ts
->val_type
) {
4076 case TEMP_VAL_CONST
:
4077 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4078 preferred_regs
, ts
->indirect_base
);
4079 if (ts
->type
<= TCG_TYPE_I64
) {
4080 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
4082 uint64_t val
= ts
->val
;
4086 * Find the minimal vector element that matches the constant.
4087 * The targets will, in general, have to do this search anyway,
4088 * do this generically.
4090 if (val
== dup_const(MO_8
, val
)) {
4092 } else if (val
== dup_const(MO_16
, val
)) {
4094 } else if (val
== dup_const(MO_32
, val
)) {
4098 tcg_out_dupi_vec(s
, ts
->type
, vece
, reg
, ts
->val
);
4100 ts
->mem_coherent
= 0;
4103 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
,
4104 preferred_regs
, ts
->indirect_base
);
4105 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
4106 ts
->mem_coherent
= 1;
4110 g_assert_not_reached();
4112 set_temp_val_reg(s
, ts
, reg
);
4115 /* Save a temporary to memory. 'allocated_regs' is used in case a
4116 temporary registers needs to be allocated to store a constant. */
4117 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
4119 /* The liveness analysis already ensures that globals are back
4120 in memory. Keep an tcg_debug_assert for safety. */
4121 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| temp_readonly(ts
));
4124 /* save globals to their canonical location and assume they can be
4125 modified be the following code. 'allocated_regs' is used in case a
4126 temporary registers needs to be allocated to store a constant. */
4127 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4131 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4132 temp_save(s
, &s
->temps
[i
], allocated_regs
);
4136 /* sync globals to their canonical location and assume they can be
4137 read by the following code. 'allocated_regs' is used in case a
4138 temporary registers needs to be allocated to store a constant. */
4139 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
4143 for (i
= 0, n
= s
->nb_globals
; i
< n
; i
++) {
4144 TCGTemp
*ts
= &s
->temps
[i
];
4145 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
4146 || ts
->kind
== TEMP_FIXED
4147 || ts
->mem_coherent
);
4151 /* at the end of a basic block, we assume all temporaries are dead and
4152 all globals are stored at their canonical location. */
4153 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
4157 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4158 TCGTemp
*ts
= &s
->temps
[i
];
4162 temp_save(s
, ts
, allocated_regs
);
4165 /* The liveness analysis already ensures that temps are dead.
4166 Keep an tcg_debug_assert for safety. */
4167 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
4170 /* Similarly, we should have freed any allocated register. */
4171 tcg_debug_assert(ts
->val_type
== TEMP_VAL_CONST
);
4174 g_assert_not_reached();
4178 save_globals(s
, allocated_regs
);
4182 * At a conditional branch, we assume all temporaries are dead unless
4183 * explicitly live-across-conditional-branch; all globals and local
4184 * temps are synced to their location.
4186 static void tcg_reg_alloc_cbranch(TCGContext
*s
, TCGRegSet allocated_regs
)
4188 sync_globals(s
, allocated_regs
);
4190 for (int i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
4191 TCGTemp
*ts
= &s
->temps
[i
];
4193 * The liveness analysis already ensures that temps are dead.
4194 * Keep tcg_debug_asserts for safety.
4198 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
|| ts
->mem_coherent
);
4204 g_assert_not_reached();
4210 * Specialized code generation for INDEX_op_mov_* with a constant.
4212 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
4213 tcg_target_ulong val
, TCGLifeData arg_life
,
4214 TCGRegSet preferred_regs
)
4216 /* ENV should not be modified. */
4217 tcg_debug_assert(!temp_readonly(ots
));
4219 /* The movi is not explicitly generated here. */
4220 set_temp_val_nonreg(s
, ots
, TEMP_VAL_CONST
);
4222 ots
->mem_coherent
= 0;
4223 if (NEED_SYNC_ARG(0)) {
4224 temp_sync(s
, ots
, s
->reserved_regs
, preferred_regs
, IS_DEAD_ARG(0));
4225 } else if (IS_DEAD_ARG(0)) {
4231 * Specialized code generation for INDEX_op_mov_*.
4233 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOp
*op
)
4235 const TCGLifeData arg_life
= op
->life
;
4236 TCGRegSet allocated_regs
, preferred_regs
;
4238 TCGType otype
, itype
;
4241 allocated_regs
= s
->reserved_regs
;
4242 preferred_regs
= output_pref(op
, 0);
4243 ots
= arg_temp(op
->args
[0]);
4244 ts
= arg_temp(op
->args
[1]);
4246 /* ENV should not be modified. */
4247 tcg_debug_assert(!temp_readonly(ots
));
4249 /* Note that otype != itype for no-op truncation. */
4253 if (ts
->val_type
== TEMP_VAL_CONST
) {
4254 /* propagate constant or generate sti */
4255 tcg_target_ulong val
= ts
->val
;
4256 if (IS_DEAD_ARG(1)) {
4259 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, preferred_regs
);
4263 /* If the source value is in memory we're going to be forced
4264 to have it in a register in order to perform the copy. Copy
4265 the SOURCE value into its own register first, that way we
4266 don't have to reload SOURCE the next time it is used. */
4267 if (ts
->val_type
== TEMP_VAL_MEM
) {
4268 temp_load(s
, ts
, tcg_target_available_regs
[itype
],
4269 allocated_regs
, preferred_regs
);
4271 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
4274 if (IS_DEAD_ARG(0)) {
4275 /* mov to a non-saved dead register makes no sense (even with
4276 liveness analysis disabled). */
4277 tcg_debug_assert(NEED_SYNC_ARG(0));
4278 if (!ots
->mem_allocated
) {
4279 temp_allocate_frame(s
, ots
);
4281 tcg_out_st(s
, otype
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4282 if (IS_DEAD_ARG(1)) {
4289 if (IS_DEAD_ARG(1) && ts
->kind
!= TEMP_FIXED
) {
4291 * The mov can be suppressed. Kill input first, so that it
4292 * is unlinked from reg_to_temp, then set the output to the
4293 * reg that we saved from the input.
4298 if (ots
->val_type
== TEMP_VAL_REG
) {
4301 /* Make sure to not spill the input register during allocation. */
4302 oreg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
4303 allocated_regs
| ((TCGRegSet
)1 << ireg
),
4304 preferred_regs
, ots
->indirect_base
);
4306 if (!tcg_out_mov(s
, otype
, oreg
, ireg
)) {
4308 * Cross register class move not supported.
4309 * Store the source register into the destination slot
4310 * and leave the destination temp as TEMP_VAL_MEM.
4312 assert(!temp_readonly(ots
));
4313 if (!ts
->mem_allocated
) {
4314 temp_allocate_frame(s
, ots
);
4316 tcg_out_st(s
, ts
->type
, ireg
, ots
->mem_base
->reg
, ots
->mem_offset
);
4317 set_temp_val_nonreg(s
, ts
, TEMP_VAL_MEM
);
4318 ots
->mem_coherent
= 1;
4322 set_temp_val_reg(s
, ots
, oreg
);
4323 ots
->mem_coherent
= 0;
4325 if (NEED_SYNC_ARG(0)) {
4326 temp_sync(s
, ots
, allocated_regs
, 0, 0);
4331 * Specialized code generation for INDEX_op_dup_vec.
4333 static void tcg_reg_alloc_dup(TCGContext
*s
, const TCGOp
*op
)
4335 const TCGLifeData arg_life
= op
->life
;
4336 TCGRegSet dup_out_regs
, dup_in_regs
;
4338 TCGType itype
, vtype
;
4343 ots
= arg_temp(op
->args
[0]);
4344 its
= arg_temp(op
->args
[1]);
4346 /* ENV should not be modified. */
4347 tcg_debug_assert(!temp_readonly(ots
));
4350 vece
= TCGOP_VECE(op
);
4351 vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4353 if (its
->val_type
== TEMP_VAL_CONST
) {
4354 /* Propagate constant via movi -> dupi. */
4355 tcg_target_ulong val
= its
->val
;
4356 if (IS_DEAD_ARG(1)) {
4359 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
, output_pref(op
, 0));
4363 dup_out_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4364 dup_in_regs
= tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[1].regs
;
4366 /* Allocate the output register now. */
4367 if (ots
->val_type
!= TEMP_VAL_REG
) {
4368 TCGRegSet allocated_regs
= s
->reserved_regs
;
4371 if (!IS_DEAD_ARG(1) && its
->val_type
== TEMP_VAL_REG
) {
4372 /* Make sure to not spill the input register. */
4373 tcg_regset_set_reg(allocated_regs
, its
->reg
);
4375 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4376 output_pref(op
, 0), ots
->indirect_base
);
4377 set_temp_val_reg(s
, ots
, oreg
);
4380 switch (its
->val_type
) {
4383 * The dup constriaints must be broad, covering all possible VECE.
4384 * However, tcg_op_dup_vec() gets to see the VECE and we allow it
4385 * to fail, indicating that extra moves are required for that case.
4387 if (tcg_regset_test_reg(dup_in_regs
, its
->reg
)) {
4388 if (tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, its
->reg
)) {
4391 /* Try again from memory or a vector input register. */
4393 if (!its
->mem_coherent
) {
4395 * The input register is not synced, and so an extra store
4396 * would be required to use memory. Attempt an integer-vector
4397 * register move first. We do not have a TCGRegSet for this.
4399 if (tcg_out_mov(s
, itype
, ots
->reg
, its
->reg
)) {
4402 /* Sync the temp back to its slot and load from there. */
4403 temp_sync(s
, its
, s
->reserved_regs
, 0, 0);
4409 if (HOST_BIG_ENDIAN
) {
4410 lowpart_ofs
= tcg_type_size(itype
) - (1 << vece
);
4412 if (tcg_out_dupm_vec(s
, vtype
, vece
, ots
->reg
, its
->mem_base
->reg
,
4413 its
->mem_offset
+ lowpart_ofs
)) {
4416 /* Load the input into the destination vector register. */
4417 tcg_out_ld(s
, itype
, ots
->reg
, its
->mem_base
->reg
, its
->mem_offset
);
4421 g_assert_not_reached();
4424 /* We now have a vector input register, so dup must succeed. */
4425 ok
= tcg_out_dup_vec(s
, vtype
, vece
, ots
->reg
, ots
->reg
);
4426 tcg_debug_assert(ok
);
4429 ots
->mem_coherent
= 0;
4430 if (IS_DEAD_ARG(1)) {
4433 if (NEED_SYNC_ARG(0)) {
4434 temp_sync(s
, ots
, s
->reserved_regs
, 0, 0);
4436 if (IS_DEAD_ARG(0)) {
4441 static void tcg_reg_alloc_op(TCGContext
*s
, const TCGOp
*op
)
4443 const TCGLifeData arg_life
= op
->life
;
4444 const TCGOpDef
* const def
= &tcg_op_defs
[op
->opc
];
4445 TCGRegSet i_allocated_regs
;
4446 TCGRegSet o_allocated_regs
;
4447 int i
, k
, nb_iargs
, nb_oargs
;
4450 const TCGArgConstraint
*arg_ct
;
4452 TCGArg new_args
[TCG_MAX_OP_ARGS
];
4453 int const_args
[TCG_MAX_OP_ARGS
];
4455 nb_oargs
= def
->nb_oargs
;
4456 nb_iargs
= def
->nb_iargs
;
4458 /* copy constants */
4459 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
4460 op
->args
+ nb_oargs
+ nb_iargs
,
4461 sizeof(TCGArg
) * def
->nb_cargs
);
4463 i_allocated_regs
= s
->reserved_regs
;
4464 o_allocated_regs
= s
->reserved_regs
;
4466 /* satisfy input constraints */
4467 for (k
= 0; k
< nb_iargs
; k
++) {
4468 TCGRegSet i_preferred_regs
, i_required_regs
;
4469 bool allocate_new_reg
, copyto_new_reg
;
4473 i
= def
->args_ct
[nb_oargs
+ k
].sort_index
;
4475 arg_ct
= &def
->args_ct
[i
];
4478 if (ts
->val_type
== TEMP_VAL_CONST
4479 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
->ct
)) {
4480 /* constant is OK for instruction */
4482 new_args
[i
] = ts
->val
;
4487 i_preferred_regs
= 0;
4488 i_required_regs
= arg_ct
->regs
;
4489 allocate_new_reg
= false;
4490 copyto_new_reg
= false;
4492 switch (arg_ct
->pair
) {
4493 case 0: /* not paired */
4494 if (arg_ct
->ialias
) {
4495 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4498 * If the input is readonly, then it cannot also be an
4499 * output and aliased to itself. If the input is not
4500 * dead after the instruction, we must allocate a new
4501 * register and move it.
4503 if (temp_readonly(ts
) || !IS_DEAD_ARG(i
)) {
4504 allocate_new_reg
= true;
4505 } else if (ts
->val_type
== TEMP_VAL_REG
) {
4507 * Check if the current register has already been
4508 * allocated for another input.
4511 tcg_regset_test_reg(i_allocated_regs
, reg
);
4514 if (!allocate_new_reg
) {
4515 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4518 allocate_new_reg
= !tcg_regset_test_reg(i_required_regs
, reg
);
4520 if (allocate_new_reg
) {
4522 * Allocate a new register matching the constraint
4523 * and move the temporary register into it.
4525 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4526 i_allocated_regs
, 0);
4527 reg
= tcg_reg_alloc(s
, i_required_regs
, i_allocated_regs
,
4528 i_preferred_regs
, ts
->indirect_base
);
4529 copyto_new_reg
= true;
4534 /* First of an input pair; if i1 == i2, the second is an output. */
4536 i2
= arg_ct
->pair_index
;
4537 ts2
= i1
!= i2
? arg_temp(op
->args
[i2
]) : NULL
;
4540 * It is easier to default to allocating a new pair
4541 * and to identify a few cases where it's not required.
4543 if (arg_ct
->ialias
) {
4544 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4545 if (IS_DEAD_ARG(i1
) &&
4547 !temp_readonly(ts
) &&
4548 ts
->val_type
== TEMP_VAL_REG
&&
4549 ts
->reg
< TCG_TARGET_NB_REGS
- 1 &&
4550 tcg_regset_test_reg(i_required_regs
, reg
) &&
4551 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4552 !tcg_regset_test_reg(i_allocated_regs
, reg
+ 1) &&
4554 ? ts2
->val_type
== TEMP_VAL_REG
&&
4555 ts2
->reg
== reg
+ 1 &&
4557 : s
->reg_to_temp
[reg
+ 1] == NULL
)) {
4561 /* Without aliasing, the pair must also be an input. */
4562 tcg_debug_assert(ts2
);
4563 if (ts
->val_type
== TEMP_VAL_REG
&&
4564 ts2
->val_type
== TEMP_VAL_REG
&&
4565 ts2
->reg
== reg
+ 1 &&
4566 tcg_regset_test_reg(i_required_regs
, reg
)) {
4570 reg
= tcg_reg_alloc_pair(s
, i_required_regs
, i_allocated_regs
,
4571 0, ts
->indirect_base
);
4574 case 2: /* pair second */
4575 reg
= new_args
[arg_ct
->pair_index
] + 1;
4578 case 3: /* ialias with second output, no first input */
4579 tcg_debug_assert(arg_ct
->ialias
);
4580 i_preferred_regs
= output_pref(op
, arg_ct
->alias_index
);
4582 if (IS_DEAD_ARG(i
) &&
4583 !temp_readonly(ts
) &&
4584 ts
->val_type
== TEMP_VAL_REG
&&
4586 s
->reg_to_temp
[reg
- 1] == NULL
&&
4587 tcg_regset_test_reg(i_required_regs
, reg
) &&
4588 !tcg_regset_test_reg(i_allocated_regs
, reg
) &&
4589 !tcg_regset_test_reg(i_allocated_regs
, reg
- 1)) {
4590 tcg_regset_set_reg(i_allocated_regs
, reg
- 1);
4593 reg
= tcg_reg_alloc_pair(s
, i_required_regs
>> 1,
4594 i_allocated_regs
, 0,
4596 tcg_regset_set_reg(i_allocated_regs
, reg
);
4602 * If an aliased input is not dead after the instruction,
4603 * we must allocate a new register and move it.
4605 if (arg_ct
->ialias
&& (!IS_DEAD_ARG(i
) || temp_readonly(ts
))) {
4606 TCGRegSet t_allocated_regs
= i_allocated_regs
;
4609 * Because of the alias, and the continued life, make sure
4610 * that the temp is somewhere *other* than the reg pair,
4611 * and we get a copy in reg.
4613 tcg_regset_set_reg(t_allocated_regs
, reg
);
4614 tcg_regset_set_reg(t_allocated_regs
, reg
+ 1);
4615 if (ts
->val_type
== TEMP_VAL_REG
&& ts
->reg
== reg
) {
4616 /* If ts was already in reg, copy it somewhere else. */
4620 tcg_debug_assert(ts
->kind
!= TEMP_FIXED
);
4621 nr
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
4622 t_allocated_regs
, 0, ts
->indirect_base
);
4623 ok
= tcg_out_mov(s
, ts
->type
, nr
, reg
);
4624 tcg_debug_assert(ok
);
4626 set_temp_val_reg(s
, ts
, nr
);
4628 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
4629 t_allocated_regs
, 0);
4630 copyto_new_reg
= true;
4633 /* Preferably allocate to reg, otherwise copy. */
4634 i_required_regs
= (TCGRegSet
)1 << reg
;
4635 temp_load(s
, ts
, i_required_regs
, i_allocated_regs
,
4637 copyto_new_reg
= ts
->reg
!= reg
;
4642 g_assert_not_reached();
4645 if (copyto_new_reg
) {
4646 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4648 * Cross register class move not supported. Sync the
4649 * temp back to its slot and load from there.
4651 temp_sync(s
, ts
, i_allocated_regs
, 0, 0);
4652 tcg_out_ld(s
, ts
->type
, reg
,
4653 ts
->mem_base
->reg
, ts
->mem_offset
);
4658 tcg_regset_set_reg(i_allocated_regs
, reg
);
4661 /* mark dead temporaries and free the associated registers */
4662 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
4663 if (IS_DEAD_ARG(i
)) {
4664 temp_dead(s
, arg_temp(op
->args
[i
]));
4668 if (def
->flags
& TCG_OPF_COND_BRANCH
) {
4669 tcg_reg_alloc_cbranch(s
, i_allocated_regs
);
4670 } else if (def
->flags
& TCG_OPF_BB_END
) {
4671 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
4673 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
4674 /* XXX: permit generic clobber register list ? */
4675 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
4676 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
4677 tcg_reg_free(s
, i
, i_allocated_regs
);
4681 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
4682 /* sync globals if the op has side effects and might trigger
4684 sync_globals(s
, i_allocated_regs
);
4687 /* satisfy the output constraints */
4688 for(k
= 0; k
< nb_oargs
; k
++) {
4689 i
= def
->args_ct
[k
].sort_index
;
4691 arg_ct
= &def
->args_ct
[i
];
4694 /* ENV should not be modified. */
4695 tcg_debug_assert(!temp_readonly(ts
));
4697 switch (arg_ct
->pair
) {
4698 case 0: /* not paired */
4699 if (arg_ct
->oalias
&& !const_args
[arg_ct
->alias_index
]) {
4700 reg
= new_args
[arg_ct
->alias_index
];
4701 } else if (arg_ct
->newreg
) {
4702 reg
= tcg_reg_alloc(s
, arg_ct
->regs
,
4703 i_allocated_regs
| o_allocated_regs
,
4704 output_pref(op
, k
), ts
->indirect_base
);
4706 reg
= tcg_reg_alloc(s
, arg_ct
->regs
, o_allocated_regs
,
4707 output_pref(op
, k
), ts
->indirect_base
);
4711 case 1: /* first of pair */
4712 tcg_debug_assert(!arg_ct
->newreg
);
4713 if (arg_ct
->oalias
) {
4714 reg
= new_args
[arg_ct
->alias_index
];
4717 reg
= tcg_reg_alloc_pair(s
, arg_ct
->regs
, o_allocated_regs
,
4718 output_pref(op
, k
), ts
->indirect_base
);
4721 case 2: /* second of pair */
4722 tcg_debug_assert(!arg_ct
->newreg
);
4723 if (arg_ct
->oalias
) {
4724 reg
= new_args
[arg_ct
->alias_index
];
4726 reg
= new_args
[arg_ct
->pair_index
] + 1;
4730 case 3: /* first of pair, aliasing with a second input */
4731 tcg_debug_assert(!arg_ct
->newreg
);
4732 reg
= new_args
[arg_ct
->pair_index
] - 1;
4736 g_assert_not_reached();
4738 tcg_regset_set_reg(o_allocated_regs
, reg
);
4739 set_temp_val_reg(s
, ts
, reg
);
4740 ts
->mem_coherent
= 0;
4745 /* emit instruction */
4747 case INDEX_op_ext8s_i32
:
4748 tcg_out_ext8s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4750 case INDEX_op_ext8s_i64
:
4751 tcg_out_ext8s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4753 case INDEX_op_ext8u_i32
:
4754 case INDEX_op_ext8u_i64
:
4755 tcg_out_ext8u(s
, new_args
[0], new_args
[1]);
4757 case INDEX_op_ext16s_i32
:
4758 tcg_out_ext16s(s
, TCG_TYPE_I32
, new_args
[0], new_args
[1]);
4760 case INDEX_op_ext16s_i64
:
4761 tcg_out_ext16s(s
, TCG_TYPE_I64
, new_args
[0], new_args
[1]);
4763 case INDEX_op_ext16u_i32
:
4764 case INDEX_op_ext16u_i64
:
4765 tcg_out_ext16u(s
, new_args
[0], new_args
[1]);
4767 case INDEX_op_ext32s_i64
:
4768 tcg_out_ext32s(s
, new_args
[0], new_args
[1]);
4770 case INDEX_op_ext32u_i64
:
4771 tcg_out_ext32u(s
, new_args
[0], new_args
[1]);
4773 case INDEX_op_ext_i32_i64
:
4774 tcg_out_exts_i32_i64(s
, new_args
[0], new_args
[1]);
4776 case INDEX_op_extu_i32_i64
:
4777 tcg_out_extu_i32_i64(s
, new_args
[0], new_args
[1]);
4779 case INDEX_op_extrl_i64_i32
:
4780 tcg_out_extrl_i64_i32(s
, new_args
[0], new_args
[1]);
4783 if (def
->flags
& TCG_OPF_VECTOR
) {
4784 tcg_out_vec_op(s
, op
->opc
, TCGOP_VECL(op
), TCGOP_VECE(op
),
4785 new_args
, const_args
);
4787 tcg_out_op(s
, op
->opc
, new_args
, const_args
);
4792 /* move the outputs in the correct register if needed */
4793 for(i
= 0; i
< nb_oargs
; i
++) {
4794 ts
= arg_temp(op
->args
[i
]);
4796 /* ENV should not be modified. */
4797 tcg_debug_assert(!temp_readonly(ts
));
4799 if (NEED_SYNC_ARG(i
)) {
4800 temp_sync(s
, ts
, o_allocated_regs
, 0, IS_DEAD_ARG(i
));
4801 } else if (IS_DEAD_ARG(i
)) {
4807 static bool tcg_reg_alloc_dup2(TCGContext
*s
, const TCGOp
*op
)
4809 const TCGLifeData arg_life
= op
->life
;
4810 TCGTemp
*ots
, *itsl
, *itsh
;
4811 TCGType vtype
= TCGOP_VECL(op
) + TCG_TYPE_V64
;
4813 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
4814 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
4815 tcg_debug_assert(TCGOP_VECE(op
) == MO_64
);
4817 ots
= arg_temp(op
->args
[0]);
4818 itsl
= arg_temp(op
->args
[1]);
4819 itsh
= arg_temp(op
->args
[2]);
4821 /* ENV should not be modified. */
4822 tcg_debug_assert(!temp_readonly(ots
));
4824 /* Allocate the output register now. */
4825 if (ots
->val_type
!= TEMP_VAL_REG
) {
4826 TCGRegSet allocated_regs
= s
->reserved_regs
;
4827 TCGRegSet dup_out_regs
=
4828 tcg_op_defs
[INDEX_op_dup_vec
].args_ct
[0].regs
;
4831 /* Make sure to not spill the input registers. */
4832 if (!IS_DEAD_ARG(1) && itsl
->val_type
== TEMP_VAL_REG
) {
4833 tcg_regset_set_reg(allocated_regs
, itsl
->reg
);
4835 if (!IS_DEAD_ARG(2) && itsh
->val_type
== TEMP_VAL_REG
) {
4836 tcg_regset_set_reg(allocated_regs
, itsh
->reg
);
4839 oreg
= tcg_reg_alloc(s
, dup_out_regs
, allocated_regs
,
4840 output_pref(op
, 0), ots
->indirect_base
);
4841 set_temp_val_reg(s
, ots
, oreg
);
4844 /* Promote dup2 of immediates to dupi_vec. */
4845 if (itsl
->val_type
== TEMP_VAL_CONST
&& itsh
->val_type
== TEMP_VAL_CONST
) {
4846 uint64_t val
= deposit64(itsl
->val
, 32, 32, itsh
->val
);
4849 if (val
== dup_const(MO_8
, val
)) {
4851 } else if (val
== dup_const(MO_16
, val
)) {
4853 } else if (val
== dup_const(MO_32
, val
)) {
4857 tcg_out_dupi_vec(s
, vtype
, vece
, ots
->reg
, val
);
4861 /* If the two inputs form one 64-bit value, try dupm_vec. */
4862 if (itsl
->temp_subindex
== HOST_BIG_ENDIAN
&&
4863 itsh
->temp_subindex
== !HOST_BIG_ENDIAN
&&
4864 itsl
== itsh
+ (HOST_BIG_ENDIAN
? 1 : -1)) {
4865 TCGTemp
*its
= itsl
- HOST_BIG_ENDIAN
;
4867 temp_sync(s
, its
+ 0, s
->reserved_regs
, 0, 0);
4868 temp_sync(s
, its
+ 1, s
->reserved_regs
, 0, 0);
4870 if (tcg_out_dupm_vec(s
, vtype
, MO_64
, ots
->reg
,
4871 its
->mem_base
->reg
, its
->mem_offset
)) {
4876 /* Fall back to generic expansion. */
4880 ots
->mem_coherent
= 0;
4881 if (IS_DEAD_ARG(1)) {
4884 if (IS_DEAD_ARG(2)) {
4887 if (NEED_SYNC_ARG(0)) {
4888 temp_sync(s
, ots
, s
->reserved_regs
, 0, IS_DEAD_ARG(0));
4889 } else if (IS_DEAD_ARG(0)) {
4895 static void load_arg_reg(TCGContext
*s
, TCGReg reg
, TCGTemp
*ts
,
4896 TCGRegSet allocated_regs
)
4898 if (ts
->val_type
== TEMP_VAL_REG
) {
4899 if (ts
->reg
!= reg
) {
4900 tcg_reg_free(s
, reg
, allocated_regs
);
4901 if (!tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
)) {
4903 * Cross register class move not supported. Sync the
4904 * temp back to its slot and load from there.
4906 temp_sync(s
, ts
, allocated_regs
, 0, 0);
4907 tcg_out_ld(s
, ts
->type
, reg
,
4908 ts
->mem_base
->reg
, ts
->mem_offset
);
4912 TCGRegSet arg_set
= 0;
4914 tcg_reg_free(s
, reg
, allocated_regs
);
4915 tcg_regset_set_reg(arg_set
, reg
);
4916 temp_load(s
, ts
, arg_set
, allocated_regs
, 0);
4920 static void load_arg_stk(TCGContext
*s
, unsigned arg_slot
, TCGTemp
*ts
,
4921 TCGRegSet allocated_regs
)
4924 * When the destination is on the stack, load up the temp and store.
4925 * If there are many call-saved registers, the temp might live to
4926 * see another use; otherwise it'll be discarded.
4928 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
], allocated_regs
, 0);
4929 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
,
4930 arg_slot_stk_ofs(arg_slot
));
4933 static void load_arg_normal(TCGContext
*s
, const TCGCallArgumentLoc
*l
,
4934 TCGTemp
*ts
, TCGRegSet
*allocated_regs
)
4936 if (arg_slot_reg_p(l
->arg_slot
)) {
4937 TCGReg reg
= tcg_target_call_iarg_regs
[l
->arg_slot
];
4938 load_arg_reg(s
, reg
, ts
, *allocated_regs
);
4939 tcg_regset_set_reg(*allocated_regs
, reg
);
4941 load_arg_stk(s
, l
->arg_slot
, ts
, *allocated_regs
);
4945 static void load_arg_ref(TCGContext
*s
, unsigned arg_slot
, TCGReg ref_base
,
4946 intptr_t ref_off
, TCGRegSet
*allocated_regs
)
4950 if (arg_slot_reg_p(arg_slot
)) {
4951 reg
= tcg_target_call_iarg_regs
[arg_slot
];
4952 tcg_reg_free(s
, reg
, *allocated_regs
);
4953 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
4954 tcg_regset_set_reg(*allocated_regs
, reg
);
4956 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[TCG_TYPE_PTR
],
4957 *allocated_regs
, 0, false);
4958 tcg_out_addi_ptr(s
, reg
, ref_base
, ref_off
);
4959 tcg_out_st(s
, TCG_TYPE_PTR
, reg
, TCG_REG_CALL_STACK
,
4960 arg_slot_stk_ofs(arg_slot
));
4964 static void tcg_reg_alloc_call(TCGContext
*s
, TCGOp
*op
)
4966 const int nb_oargs
= TCGOP_CALLO(op
);
4967 const int nb_iargs
= TCGOP_CALLI(op
);
4968 const TCGLifeData arg_life
= op
->life
;
4969 const TCGHelperInfo
*info
= tcg_call_info(op
);
4970 TCGRegSet allocated_regs
= s
->reserved_regs
;
4974 * Move inputs into place in reverse order,
4975 * so that we place stacked arguments first.
4977 for (i
= nb_iargs
- 1; i
>= 0; --i
) {
4978 const TCGCallArgumentLoc
*loc
= &info
->in
[i
];
4979 TCGTemp
*ts
= arg_temp(op
->args
[nb_oargs
+ i
]);
4981 switch (loc
->kind
) {
4982 case TCG_CALL_ARG_NORMAL
:
4983 case TCG_CALL_ARG_EXTEND_U
:
4984 case TCG_CALL_ARG_EXTEND_S
:
4985 load_arg_normal(s
, loc
, ts
, &allocated_regs
);
4987 case TCG_CALL_ARG_BY_REF
:
4988 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
4989 load_arg_ref(s
, loc
->arg_slot
, TCG_REG_CALL_STACK
,
4990 arg_slot_stk_ofs(loc
->ref_slot
),
4993 case TCG_CALL_ARG_BY_REF_N
:
4994 load_arg_stk(s
, loc
->ref_slot
, ts
, allocated_regs
);
4997 g_assert_not_reached();
5001 /* Mark dead temporaries and free the associated registers. */
5002 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
5003 if (IS_DEAD_ARG(i
)) {
5004 temp_dead(s
, arg_temp(op
->args
[i
]));
5008 /* Clobber call registers. */
5009 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
5010 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
5011 tcg_reg_free(s
, i
, allocated_regs
);
5016 * Save globals if they might be written by the helper,
5017 * sync them if they might be read.
5019 if (info
->flags
& TCG_CALL_NO_READ_GLOBALS
) {
5021 } else if (info
->flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
5022 sync_globals(s
, allocated_regs
);
5024 save_globals(s
, allocated_regs
);
5028 * If the ABI passes a pointer to the returned struct as the first
5029 * argument, load that now. Pass a pointer to the output home slot.
5031 if (info
->out_kind
== TCG_CALL_RET_BY_REF
) {
5032 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5034 if (!ts
->mem_allocated
) {
5035 temp_allocate_frame(s
, ts
);
5037 load_arg_ref(s
, 0, ts
->mem_base
->reg
, ts
->mem_offset
, &allocated_regs
);
5040 tcg_out_call(s
, tcg_call_func(op
), info
);
5042 /* Assign output registers and emit moves if needed. */
5043 switch (info
->out_kind
) {
5044 case TCG_CALL_RET_NORMAL
:
5045 for (i
= 0; i
< nb_oargs
; i
++) {
5046 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5047 TCGReg reg
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, i
);
5049 /* ENV should not be modified. */
5050 tcg_debug_assert(!temp_readonly(ts
));
5052 set_temp_val_reg(s
, ts
, reg
);
5053 ts
->mem_coherent
= 0;
5057 case TCG_CALL_RET_BY_VEC
:
5059 TCGTemp
*ts
= arg_temp(op
->args
[0]);
5061 tcg_debug_assert(ts
->base_type
== TCG_TYPE_I128
);
5062 tcg_debug_assert(ts
->temp_subindex
== 0);
5063 if (!ts
->mem_allocated
) {
5064 temp_allocate_frame(s
, ts
);
5066 tcg_out_st(s
, TCG_TYPE_V128
,
5067 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC
, 0),
5068 ts
->mem_base
->reg
, ts
->mem_offset
);
5070 /* fall through to mark all parts in memory */
5072 case TCG_CALL_RET_BY_REF
:
5073 /* The callee has performed a write through the reference. */
5074 for (i
= 0; i
< nb_oargs
; i
++) {
5075 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5076 ts
->val_type
= TEMP_VAL_MEM
;
5081 g_assert_not_reached();
5084 /* Flush or discard output registers as needed. */
5085 for (i
= 0; i
< nb_oargs
; i
++) {
5086 TCGTemp
*ts
= arg_temp(op
->args
[i
]);
5087 if (NEED_SYNC_ARG(i
)) {
5088 temp_sync(s
, ts
, s
->reserved_regs
, 0, IS_DEAD_ARG(i
));
5089 } else if (IS_DEAD_ARG(i
)) {
5096 * Similarly for qemu_ld/st slow path helpers.
5097 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously,
5098 * using only the provided backend tcg_out_* functions.
5101 static int tcg_out_helper_stk_ofs(TCGType type
, unsigned slot
)
5103 int ofs
= arg_slot_stk_ofs(slot
);
5106 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not
5107 * require extension to uint64_t, adjust the address for uint32_t.
5109 if (HOST_BIG_ENDIAN
&&
5110 TCG_TARGET_REG_BITS
== 64 &&
5111 type
== TCG_TYPE_I32
) {
5117 static void tcg_out_helper_load_regs(TCGContext
*s
,
5118 unsigned nmov
, TCGMovExtend
*mov
,
5119 unsigned ntmp
, const int *tmp
)
5123 /* The backend must have provided enough temps for the worst case. */
5124 tcg_debug_assert(ntmp
+ 1 >= nmov
);
5126 for (unsigned i
= nmov
- 1; i
>= 2; --i
) {
5127 TCGReg dst
= mov
[i
].dst
;
5129 for (unsigned j
= 0; j
< i
; ++j
) {
5130 if (dst
== mov
[j
].src
) {
5133 * Copy the source to a temporary, recurse for the
5134 * remaining moves, perform the extension from our
5135 * scratch on the way out.
5137 TCGReg scratch
= tmp
[--ntmp
];
5138 tcg_out_mov(s
, mov
[i
].src_type
, scratch
, mov
[i
].src
);
5139 mov
[i
].src
= scratch
;
5141 tcg_out_helper_load_regs(s
, i
, mov
, ntmp
, tmp
);
5142 tcg_out_movext1(s
, &mov
[i
]);
5147 /* No conflicts: perform this move and continue. */
5148 tcg_out_movext1(s
, &mov
[i
]);
5150 /* fall through for the final two moves */
5153 tcg_out_movext2(s
, mov
, mov
+ 1, ntmp
? tmp
[0] : -1);
5156 tcg_out_movext1(s
, mov
);
5159 g_assert_not_reached();
5163 static void tcg_out_helper_load_slots(TCGContext
*s
,
5164 unsigned nmov
, TCGMovExtend
*mov
,
5165 const TCGLdstHelperParam
*parm
)
5170 * Start from the end, storing to the stack first.
5171 * This frees those registers, so we need not consider overlap.
5173 for (i
= nmov
; i
-- > 0; ) {
5174 unsigned slot
= mov
[i
].dst
;
5176 if (arg_slot_reg_p(slot
)) {
5180 TCGReg src
= mov
[i
].src
;
5181 TCGType dst_type
= mov
[i
].dst_type
;
5182 MemOp dst_mo
= dst_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5184 /* The argument is going onto the stack; extend into scratch. */
5185 if ((mov
[i
].src_ext
& MO_SIZE
) != dst_mo
) {
5186 tcg_debug_assert(parm
->ntmp
!= 0);
5187 mov
[i
].dst
= src
= parm
->tmp
[0];
5188 tcg_out_movext1(s
, &mov
[i
]);
5191 tcg_out_st(s
, dst_type
, src
, TCG_REG_CALL_STACK
,
5192 tcg_out_helper_stk_ofs(dst_type
, slot
));
5198 * The remaining arguments are in registers.
5199 * Convert slot numbers to argument registers.
5202 for (i
= 0; i
< nmov
; ++i
) {
5203 mov
[i
].dst
= tcg_target_call_iarg_regs
[mov
[i
].dst
];
5205 tcg_out_helper_load_regs(s
, nmov
, mov
, parm
->ntmp
, parm
->tmp
);
5208 static void tcg_out_helper_load_imm(TCGContext
*s
, unsigned slot
,
5209 TCGType type
, tcg_target_long imm
,
5210 const TCGLdstHelperParam
*parm
)
5212 if (arg_slot_reg_p(slot
)) {
5213 tcg_out_movi(s
, type
, tcg_target_call_iarg_regs
[slot
], imm
);
5215 int ofs
= tcg_out_helper_stk_ofs(type
, slot
);
5216 if (!tcg_out_sti(s
, type
, imm
, TCG_REG_CALL_STACK
, ofs
)) {
5217 tcg_debug_assert(parm
->ntmp
!= 0);
5218 tcg_out_movi(s
, type
, parm
->tmp
[0], imm
);
5219 tcg_out_st(s
, type
, parm
->tmp
[0], TCG_REG_CALL_STACK
, ofs
);
5224 static void tcg_out_helper_load_common_args(TCGContext
*s
,
5225 const TCGLabelQemuLdst
*ldst
,
5226 const TCGLdstHelperParam
*parm
,
5227 const TCGHelperInfo
*info
,
5230 TCGMovExtend ptr_mov
= {
5231 .dst_type
= TCG_TYPE_PTR
,
5232 .src_type
= TCG_TYPE_PTR
,
5233 .src_ext
= sizeof(void *) == 4 ? MO_32
: MO_64
5235 const TCGCallArgumentLoc
*loc
= &info
->in
[0];
5238 tcg_target_ulong imm
;
5241 * Handle env, which is always first.
5243 ptr_mov
.dst
= loc
->arg_slot
;
5244 ptr_mov
.src
= TCG_AREG0
;
5245 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5251 loc
= &info
->in
[next_arg
];
5252 type
= TCG_TYPE_I32
;
5253 switch (loc
->kind
) {
5254 case TCG_CALL_ARG_NORMAL
:
5256 case TCG_CALL_ARG_EXTEND_U
:
5257 case TCG_CALL_ARG_EXTEND_S
:
5258 /* No extension required for MemOpIdx. */
5259 tcg_debug_assert(imm
<= INT32_MAX
);
5260 type
= TCG_TYPE_REG
;
5263 g_assert_not_reached();
5265 tcg_out_helper_load_imm(s
, loc
->arg_slot
, type
, imm
, parm
);
5271 loc
= &info
->in
[next_arg
];
5272 slot
= loc
->arg_slot
;
5277 if (arg_slot_reg_p(slot
)) {
5278 arg_reg
= tcg_target_call_iarg_regs
[slot
];
5280 ra_reg
= parm
->ra_gen(s
, ldst
, arg_reg
);
5283 ptr_mov
.src
= ra_reg
;
5284 tcg_out_helper_load_slots(s
, 1, &ptr_mov
, parm
);
5286 imm
= (uintptr_t)ldst
->raddr
;
5287 tcg_out_helper_load_imm(s
, slot
, TCG_TYPE_PTR
, imm
, parm
);
5291 static unsigned tcg_out_helper_add_mov(TCGMovExtend
*mov
,
5292 const TCGCallArgumentLoc
*loc
,
5293 TCGType dst_type
, TCGType src_type
,
5294 TCGReg lo
, TCGReg hi
)
5296 if (dst_type
<= TCG_TYPE_REG
) {
5299 switch (loc
->kind
) {
5300 case TCG_CALL_ARG_NORMAL
:
5301 src_ext
= src_type
== TCG_TYPE_I32
? MO_32
: MO_64
;
5303 case TCG_CALL_ARG_EXTEND_U
:
5304 dst_type
= TCG_TYPE_REG
;
5307 case TCG_CALL_ARG_EXTEND_S
:
5308 dst_type
= TCG_TYPE_REG
;
5312 g_assert_not_reached();
5315 mov
[0].dst
= loc
->arg_slot
;
5316 mov
[0].dst_type
= dst_type
;
5318 mov
[0].src_type
= src_type
;
5319 mov
[0].src_ext
= src_ext
;
5323 assert(TCG_TARGET_REG_BITS
== 32);
5325 mov
[0].dst
= loc
[HOST_BIG_ENDIAN
].arg_slot
;
5327 mov
[0].dst_type
= TCG_TYPE_I32
;
5328 mov
[0].src_type
= TCG_TYPE_I32
;
5329 mov
[0].src_ext
= MO_32
;
5331 mov
[1].dst
= loc
[!HOST_BIG_ENDIAN
].arg_slot
;
5333 mov
[1].dst_type
= TCG_TYPE_I32
;
5334 mov
[1].src_type
= TCG_TYPE_I32
;
5335 mov
[1].src_ext
= MO_32
;
5340 static void tcg_out_ld_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5341 const TCGLdstHelperParam
*parm
)
5343 const TCGHelperInfo
*info
;
5344 const TCGCallArgumentLoc
*loc
;
5345 TCGMovExtend mov
[2];
5346 unsigned next_arg
, nmov
;
5347 MemOp mop
= get_memop(ldst
->oi
);
5349 switch (mop
& MO_SIZE
) {
5353 info
= &info_helper_ld32_mmu
;
5356 info
= &info_helper_ld64_mmu
;
5359 g_assert_not_reached();
5362 /* Defer env argument. */
5365 loc
= &info
->in
[next_arg
];
5366 nmov
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_TL
, TCG_TYPE_TL
,
5367 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5370 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5372 /* No special attention for 32 and 64-bit return values. */
5373 tcg_debug_assert(info
->out_kind
== TCG_CALL_RET_NORMAL
);
5375 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5378 static void tcg_out_ld_helper_ret(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5380 const TCGLdstHelperParam
*parm
)
5382 TCGMovExtend mov
[2];
5384 if (ldst
->type
<= TCG_TYPE_REG
) {
5385 MemOp mop
= get_memop(ldst
->oi
);
5387 mov
[0].dst
= ldst
->datalo_reg
;
5388 mov
[0].src
= tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, 0);
5389 mov
[0].dst_type
= ldst
->type
;
5390 mov
[0].src_type
= TCG_TYPE_REG
;
5393 * If load_sign, then we allowed the helper to perform the
5394 * appropriate sign extension to tcg_target_ulong, and all
5395 * we need now is a plain move.
5397 * If they do not, then we expect the relevant extension
5398 * instruction to be no more expensive than a move, and
5399 * we thus save the icache etc by only using one of two
5402 if (load_sign
|| !(mop
& MO_SIGN
)) {
5403 if (TCG_TARGET_REG_BITS
== 32 || ldst
->type
== TCG_TYPE_I32
) {
5404 mov
[0].src_ext
= MO_32
;
5406 mov
[0].src_ext
= MO_64
;
5409 mov
[0].src_ext
= mop
& MO_SSIZE
;
5411 tcg_out_movext1(s
, mov
);
5413 assert(TCG_TARGET_REG_BITS
== 32);
5415 mov
[0].dst
= ldst
->datalo_reg
;
5417 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, HOST_BIG_ENDIAN
);
5418 mov
[0].dst_type
= TCG_TYPE_I32
;
5419 mov
[0].src_type
= TCG_TYPE_I32
;
5420 mov
[0].src_ext
= MO_32
;
5422 mov
[1].dst
= ldst
->datahi_reg
;
5424 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL
, !HOST_BIG_ENDIAN
);
5425 mov
[1].dst_type
= TCG_TYPE_REG
;
5426 mov
[1].src_type
= TCG_TYPE_REG
;
5427 mov
[1].src_ext
= MO_32
;
5429 tcg_out_movext2(s
, mov
, mov
+ 1, parm
->ntmp
? parm
->tmp
[0] : -1);
5433 static void tcg_out_st_helper_args(TCGContext
*s
, const TCGLabelQemuLdst
*ldst
,
5434 const TCGLdstHelperParam
*parm
)
5436 const TCGHelperInfo
*info
;
5437 const TCGCallArgumentLoc
*loc
;
5438 TCGMovExtend mov
[4];
5440 unsigned next_arg
, nmov
, n
;
5441 MemOp mop
= get_memop(ldst
->oi
);
5443 switch (mop
& MO_SIZE
) {
5447 info
= &info_helper_st32_mmu
;
5448 data_type
= TCG_TYPE_I32
;
5451 info
= &info_helper_st64_mmu
;
5452 data_type
= TCG_TYPE_I64
;
5455 g_assert_not_reached();
5458 /* Defer env argument. */
5462 /* Handle addr argument. */
5463 loc
= &info
->in
[next_arg
];
5464 n
= tcg_out_helper_add_mov(mov
, loc
, TCG_TYPE_TL
, TCG_TYPE_TL
,
5465 ldst
->addrlo_reg
, ldst
->addrhi_reg
);
5469 /* Handle data argument. */
5470 loc
= &info
->in
[next_arg
];
5471 n
= tcg_out_helper_add_mov(mov
+ nmov
, loc
, data_type
, ldst
->type
,
5472 ldst
->datalo_reg
, ldst
->datahi_reg
);
5475 tcg_debug_assert(nmov
<= ARRAY_SIZE(mov
));
5477 tcg_out_helper_load_slots(s
, nmov
, mov
, parm
);
5478 tcg_out_helper_load_common_args(s
, ldst
, parm
, info
, next_arg
);
5481 #ifdef CONFIG_PROFILER
5483 /* avoid copy/paste errors */
5484 #define PROF_ADD(to, from, field) \
5486 (to)->field += qatomic_read(&((from)->field)); \
5489 #define PROF_MAX(to, from, field) \
5491 typeof((from)->field) val__ = qatomic_read(&((from)->field)); \
5492 if (val__ > (to)->field) { \
5493 (to)->field = val__; \
5497 /* Pass in a zero'ed @prof */
5499 void tcg_profile_snapshot(TCGProfile
*prof
, bool counters
, bool table
)
5501 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5504 for (i
= 0; i
< n_ctxs
; i
++) {
5505 TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5506 const TCGProfile
*orig
= &s
->prof
;
5509 PROF_ADD(prof
, orig
, cpu_exec_time
);
5510 PROF_ADD(prof
, orig
, tb_count1
);
5511 PROF_ADD(prof
, orig
, tb_count
);
5512 PROF_ADD(prof
, orig
, op_count
);
5513 PROF_MAX(prof
, orig
, op_count_max
);
5514 PROF_ADD(prof
, orig
, temp_count
);
5515 PROF_MAX(prof
, orig
, temp_count_max
);
5516 PROF_ADD(prof
, orig
, del_op_count
);
5517 PROF_ADD(prof
, orig
, code_in_len
);
5518 PROF_ADD(prof
, orig
, code_out_len
);
5519 PROF_ADD(prof
, orig
, search_out_len
);
5520 PROF_ADD(prof
, orig
, interm_time
);
5521 PROF_ADD(prof
, orig
, code_time
);
5522 PROF_ADD(prof
, orig
, la_time
);
5523 PROF_ADD(prof
, orig
, opt_time
);
5524 PROF_ADD(prof
, orig
, restore_count
);
5525 PROF_ADD(prof
, orig
, restore_time
);
5530 for (i
= 0; i
< NB_OPS
; i
++) {
5531 PROF_ADD(prof
, orig
, table_op_count
[i
]);
5540 static void tcg_profile_snapshot_counters(TCGProfile
*prof
)
5542 tcg_profile_snapshot(prof
, true, false);
5545 static void tcg_profile_snapshot_table(TCGProfile
*prof
)
5547 tcg_profile_snapshot(prof
, false, true);
5550 void tcg_dump_op_count(GString
*buf
)
5552 TCGProfile prof
= {};
5555 tcg_profile_snapshot_table(&prof
);
5556 for (i
= 0; i
< NB_OPS
; i
++) {
5557 g_string_append_printf(buf
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
5558 prof
.table_op_count
[i
]);
5562 int64_t tcg_cpu_exec_time(void)
5564 unsigned int n_ctxs
= qatomic_read(&tcg_cur_ctxs
);
5568 for (i
= 0; i
< n_ctxs
; i
++) {
5569 const TCGContext
*s
= qatomic_read(&tcg_ctxs
[i
]);
5570 const TCGProfile
*prof
= &s
->prof
;
5572 ret
+= qatomic_read(&prof
->cpu_exec_time
);
5577 void tcg_dump_op_count(GString
*buf
)
5579 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
5582 int64_t tcg_cpu_exec_time(void)
5584 error_report("%s: TCG profiler not compiled", __func__
);
5590 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, target_ulong pc_start
)
5592 #ifdef CONFIG_PROFILER
5593 TCGProfile
*prof
= &s
->prof
;
5598 #ifdef CONFIG_PROFILER
5602 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5605 qatomic_set(&prof
->op_count
, prof
->op_count
+ n
);
5606 if (n
> prof
->op_count_max
) {
5607 qatomic_set(&prof
->op_count_max
, n
);
5611 qatomic_set(&prof
->temp_count
, prof
->temp_count
+ n
);
5612 if (n
> prof
->temp_count_max
) {
5613 qatomic_set(&prof
->temp_count_max
, n
);
5619 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
5620 && qemu_log_in_addr_range(pc_start
))) {
5621 FILE *logfile
= qemu_log_trylock();
5623 fprintf(logfile
, "OP:\n");
5624 tcg_dump_ops(s
, logfile
, false);
5625 fprintf(logfile
, "\n");
5626 qemu_log_unlock(logfile
);
5631 #ifdef CONFIG_DEBUG_TCG
5632 /* Ensure all labels referenced have been emitted. */
5637 QSIMPLEQ_FOREACH(l
, &s
->labels
, next
) {
5638 if (unlikely(!l
->present
) && !QSIMPLEQ_EMPTY(&l
->branches
)) {
5639 qemu_log_mask(CPU_LOG_TB_OP
,
5640 "$L%d referenced but not present.\n", l
->id
);
5648 #ifdef CONFIG_PROFILER
5649 qatomic_set(&prof
->opt_time
, prof
->opt_time
- profile_getclock());
5652 #ifdef USE_TCG_OPTIMIZATIONS
5656 #ifdef CONFIG_PROFILER
5657 qatomic_set(&prof
->opt_time
, prof
->opt_time
+ profile_getclock());
5658 qatomic_set(&prof
->la_time
, prof
->la_time
- profile_getclock());
5661 reachable_code_pass(s
);
5665 if (s
->nb_indirects
> 0) {
5667 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
5668 && qemu_log_in_addr_range(pc_start
))) {
5669 FILE *logfile
= qemu_log_trylock();
5671 fprintf(logfile
, "OP before indirect lowering:\n");
5672 tcg_dump_ops(s
, logfile
, false);
5673 fprintf(logfile
, "\n");
5674 qemu_log_unlock(logfile
);
5678 /* Replace indirect temps with direct temps. */
5679 if (liveness_pass_2(s
)) {
5680 /* If changes were made, re-run liveness. */
5685 #ifdef CONFIG_PROFILER
5686 qatomic_set(&prof
->la_time
, prof
->la_time
+ profile_getclock());
5690 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
5691 && qemu_log_in_addr_range(pc_start
))) {
5692 FILE *logfile
= qemu_log_trylock();
5694 fprintf(logfile
, "OP after optimization and liveness analysis:\n");
5695 tcg_dump_ops(s
, logfile
, true);
5696 fprintf(logfile
, "\n");
5697 qemu_log_unlock(logfile
);
5702 /* Initialize goto_tb jump offsets. */
5703 tb
->jmp_reset_offset
[0] = TB_JMP_OFFSET_INVALID
;
5704 tb
->jmp_reset_offset
[1] = TB_JMP_OFFSET_INVALID
;
5705 tb
->jmp_insn_offset
[0] = TB_JMP_OFFSET_INVALID
;
5706 tb
->jmp_insn_offset
[1] = TB_JMP_OFFSET_INVALID
;
5708 tcg_reg_alloc_start(s
);
5711 * Reset the buffer pointers when restarting after overflow.
5712 * TODO: Move this into translate-all.c with the rest of the
5713 * buffer management. Having only this done here is confusing.
5715 s
->code_buf
= tcg_splitwx_to_rw(tb
->tc
.ptr
);
5716 s
->code_ptr
= s
->code_buf
;
5718 #ifdef TCG_TARGET_NEED_LDST_LABELS
5719 QSIMPLEQ_INIT(&s
->ldst_labels
);
5721 #ifdef TCG_TARGET_NEED_POOL_LABELS
5722 s
->pool_labels
= NULL
;
5726 QTAILQ_FOREACH(op
, &s
->ops
, link
) {
5727 TCGOpcode opc
= op
->opc
;
5729 #ifdef CONFIG_PROFILER
5730 qatomic_set(&prof
->table_op_count
[opc
], prof
->table_op_count
[opc
] + 1);
5734 case INDEX_op_mov_i32
:
5735 case INDEX_op_mov_i64
:
5736 case INDEX_op_mov_vec
:
5737 tcg_reg_alloc_mov(s
, op
);
5739 case INDEX_op_dup_vec
:
5740 tcg_reg_alloc_dup(s
, op
);
5742 case INDEX_op_insn_start
:
5743 if (num_insns
>= 0) {
5744 size_t off
= tcg_current_code_size(s
);
5745 s
->gen_insn_end_off
[num_insns
] = off
;
5746 /* Assert that we do not overflow our stored offset. */
5747 assert(s
->gen_insn_end_off
[num_insns
] == off
);
5750 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
5752 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
5753 a
= deposit64(op
->args
[i
* 2], 32, 32, op
->args
[i
* 2 + 1]);
5757 s
->gen_insn_data
[num_insns
][i
] = a
;
5760 case INDEX_op_discard
:
5761 temp_dead(s
, arg_temp(op
->args
[0]));
5763 case INDEX_op_set_label
:
5764 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
5765 tcg_out_label(s
, arg_label(op
->args
[0]));
5768 tcg_reg_alloc_call(s
, op
);
5770 case INDEX_op_exit_tb
:
5771 tcg_out_exit_tb(s
, op
->args
[0]);
5773 case INDEX_op_goto_tb
:
5774 tcg_out_goto_tb(s
, op
->args
[0]);
5776 case INDEX_op_dup2_vec
:
5777 if (tcg_reg_alloc_dup2(s
, op
)) {
5782 /* Sanity check that we've not introduced any unhandled opcodes. */
5783 tcg_debug_assert(tcg_op_supported(opc
));
5784 /* Note: in order to speed up the code, it would be much
5785 faster to have specialized register allocator functions for
5786 some common argument patterns */
5787 tcg_reg_alloc_op(s
, op
);
5790 /* Test for (pending) buffer overflow. The assumption is that any
5791 one operation beginning below the high water mark cannot overrun
5792 the buffer completely. Thus we can test for overflow after
5793 generating code without having to check during generation. */
5794 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
5797 /* Test for TB overflow, as seen by gen_insn_end_off. */
5798 if (unlikely(tcg_current_code_size(s
) > UINT16_MAX
)) {
5802 tcg_debug_assert(num_insns
>= 0);
5803 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
5805 /* Generate TB finalization at the end of block */
5806 #ifdef TCG_TARGET_NEED_LDST_LABELS
5807 i
= tcg_out_ldst_finalize(s
);
5812 #ifdef TCG_TARGET_NEED_POOL_LABELS
5813 i
= tcg_out_pool_finalize(s
);
5818 if (!tcg_resolve_relocs(s
)) {
5822 #ifndef CONFIG_TCG_INTERPRETER
5823 /* flush instruction cache */
5824 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s
->code_buf
),
5825 (uintptr_t)s
->code_buf
,
5826 tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
));
5829 return tcg_current_code_size(s
);
5832 #ifdef CONFIG_PROFILER
5833 void tcg_dump_info(GString
*buf
)
5835 TCGProfile prof
= {};
5836 const TCGProfile
*s
;
5838 int64_t tb_div_count
;
5841 tcg_profile_snapshot_counters(&prof
);
5843 tb_count
= s
->tb_count
;
5844 tb_div_count
= tb_count
? tb_count
: 1;
5845 tot
= s
->interm_time
+ s
->code_time
;
5847 g_string_append_printf(buf
, "JIT cycles %" PRId64
5848 " (%0.3f s at 2.4 GHz)\n",
5850 g_string_append_printf(buf
, "translated TBs %" PRId64
5851 " (aborted=%" PRId64
" %0.1f%%)\n",
5852 tb_count
, s
->tb_count1
- tb_count
,
5853 (double)(s
->tb_count1
- s
->tb_count
)
5854 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
5855 g_string_append_printf(buf
, "avg ops/TB %0.1f max=%d\n",
5856 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
5857 g_string_append_printf(buf
, "deleted ops/TB %0.2f\n",
5858 (double)s
->del_op_count
/ tb_div_count
);
5859 g_string_append_printf(buf
, "avg temps/TB %0.2f max=%d\n",
5860 (double)s
->temp_count
/ tb_div_count
,
5862 g_string_append_printf(buf
, "avg host code/TB %0.1f\n",
5863 (double)s
->code_out_len
/ tb_div_count
);
5864 g_string_append_printf(buf
, "avg search data/TB %0.1f\n",
5865 (double)s
->search_out_len
/ tb_div_count
);
5867 g_string_append_printf(buf
, "cycles/op %0.1f\n",
5868 s
->op_count
? (double)tot
/ s
->op_count
: 0);
5869 g_string_append_printf(buf
, "cycles/in byte %0.1f\n",
5870 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
5871 g_string_append_printf(buf
, "cycles/out byte %0.1f\n",
5872 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
5873 g_string_append_printf(buf
, "cycles/search byte %0.1f\n",
5875 (double)tot
/ s
->search_out_len
: 0);
5879 g_string_append_printf(buf
, " gen_interm time %0.1f%%\n",
5880 (double)s
->interm_time
/ tot
* 100.0);
5881 g_string_append_printf(buf
, " gen_code time %0.1f%%\n",
5882 (double)s
->code_time
/ tot
* 100.0);
5883 g_string_append_printf(buf
, "optim./code time %0.1f%%\n",
5884 (double)s
->opt_time
/ (s
->code_time
?
5887 g_string_append_printf(buf
, "liveness/code time %0.1f%%\n",
5888 (double)s
->la_time
/ (s
->code_time
?
5889 s
->code_time
: 1) * 100.0);
5890 g_string_append_printf(buf
, "cpu_restore count %" PRId64
"\n",
5892 g_string_append_printf(buf
, " avg cycles %0.1f\n",
5894 (double)s
->restore_time
/ s
->restore_count
: 0);
5897 void tcg_dump_info(GString
*buf
)
5899 g_string_append_printf(buf
, "[TCG profiler not compiled]\n");
5903 #ifdef ELF_HOST_MACHINE
5904 /* In order to use this feature, the backend needs to do three things:
5906 (1) Define ELF_HOST_MACHINE to indicate both what value to
5907 put into the ELF image and to indicate support for the feature.
5909 (2) Define tcg_register_jit. This should create a buffer containing
5910 the contents of a .debug_frame section that describes the post-
5911 prologue unwind info for the tcg machine.
5913 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
5916 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
5923 struct jit_code_entry
{
5924 struct jit_code_entry
*next_entry
;
5925 struct jit_code_entry
*prev_entry
;
5926 const void *symfile_addr
;
5927 uint64_t symfile_size
;
5930 struct jit_descriptor
{
5932 uint32_t action_flag
;
5933 struct jit_code_entry
*relevant_entry
;
5934 struct jit_code_entry
*first_entry
;
5937 void __jit_debug_register_code(void) __attribute__((noinline
));
5938 void __jit_debug_register_code(void)
5943 /* Must statically initialize the version, because GDB may check
5944 the version before we can set it. */
5945 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
5947 /* End GDB interface. */
5949 static int find_string(const char *strtab
, const char *str
)
5951 const char *p
= strtab
+ 1;
5954 if (strcmp(p
, str
) == 0) {
5961 static void tcg_register_jit_int(const void *buf_ptr
, size_t buf_size
,
5962 const void *debug_frame
,
5963 size_t debug_frame_size
)
5965 struct __attribute__((packed
)) DebugInfo
{
5972 uintptr_t cu_low_pc
;
5973 uintptr_t cu_high_pc
;
5976 uintptr_t fn_low_pc
;
5977 uintptr_t fn_high_pc
;
5986 struct DebugInfo di
;
5991 struct ElfImage
*img
;
5993 static const struct ElfImage img_template
= {
5995 .e_ident
[EI_MAG0
] = ELFMAG0
,
5996 .e_ident
[EI_MAG1
] = ELFMAG1
,
5997 .e_ident
[EI_MAG2
] = ELFMAG2
,
5998 .e_ident
[EI_MAG3
] = ELFMAG3
,
5999 .e_ident
[EI_CLASS
] = ELF_CLASS
,
6000 .e_ident
[EI_DATA
] = ELF_DATA
,
6001 .e_ident
[EI_VERSION
] = EV_CURRENT
,
6003 .e_machine
= ELF_HOST_MACHINE
,
6004 .e_version
= EV_CURRENT
,
6005 .e_phoff
= offsetof(struct ElfImage
, phdr
),
6006 .e_shoff
= offsetof(struct ElfImage
, shdr
),
6007 .e_ehsize
= sizeof(ElfW(Shdr
)),
6008 .e_phentsize
= sizeof(ElfW(Phdr
)),
6010 .e_shentsize
= sizeof(ElfW(Shdr
)),
6011 .e_shnum
= ARRAY_SIZE(img
->shdr
),
6012 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
6013 #ifdef ELF_HOST_FLAGS
6014 .e_flags
= ELF_HOST_FLAGS
,
6017 .e_ident
[EI_OSABI
] = ELF_OSABI
,
6025 [0] = { .sh_type
= SHT_NULL
},
6026 /* Trick: The contents of code_gen_buffer are not present in
6027 this fake ELF file; that got allocated elsewhere. Therefore
6028 we mark .text as SHT_NOBITS (similar to .bss) so that readers
6029 will not look for contents. We can record any address. */
6031 .sh_type
= SHT_NOBITS
,
6032 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
6034 [2] = { /* .debug_info */
6035 .sh_type
= SHT_PROGBITS
,
6036 .sh_offset
= offsetof(struct ElfImage
, di
),
6037 .sh_size
= sizeof(struct DebugInfo
),
6039 [3] = { /* .debug_abbrev */
6040 .sh_type
= SHT_PROGBITS
,
6041 .sh_offset
= offsetof(struct ElfImage
, da
),
6042 .sh_size
= sizeof(img
->da
),
6044 [4] = { /* .debug_frame */
6045 .sh_type
= SHT_PROGBITS
,
6046 .sh_offset
= sizeof(struct ElfImage
),
6048 [5] = { /* .symtab */
6049 .sh_type
= SHT_SYMTAB
,
6050 .sh_offset
= offsetof(struct ElfImage
, sym
),
6051 .sh_size
= sizeof(img
->sym
),
6053 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
6054 .sh_entsize
= sizeof(ElfW(Sym
)),
6056 [6] = { /* .strtab */
6057 .sh_type
= SHT_STRTAB
,
6058 .sh_offset
= offsetof(struct ElfImage
, str
),
6059 .sh_size
= sizeof(img
->str
),
6063 [1] = { /* code_gen_buffer */
6064 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
6069 .len
= sizeof(struct DebugInfo
) - 4,
6071 .ptr_size
= sizeof(void *),
6073 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
6075 .fn_name
= "code_gen_buffer"
6078 1, /* abbrev number (the cu) */
6079 0x11, 1, /* DW_TAG_compile_unit, has children */
6080 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
6081 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6082 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6083 0, 0, /* end of abbrev */
6084 2, /* abbrev number (the fn) */
6085 0x2e, 0, /* DW_TAG_subprogram, no children */
6086 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
6087 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
6088 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
6089 0, 0, /* end of abbrev */
6090 0 /* no more abbrev */
6092 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
6093 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
6096 /* We only need a single jit entry; statically allocate it. */
6097 static struct jit_code_entry one_entry
;
6099 uintptr_t buf
= (uintptr_t)buf_ptr
;
6100 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
6101 DebugFrameHeader
*dfh
;
6103 img
= g_malloc(img_size
);
6104 *img
= img_template
;
6106 img
->phdr
.p_vaddr
= buf
;
6107 img
->phdr
.p_paddr
= buf
;
6108 img
->phdr
.p_memsz
= buf_size
;
6110 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
6111 img
->shdr
[1].sh_addr
= buf
;
6112 img
->shdr
[1].sh_size
= buf_size
;
6114 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
6115 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
6117 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
6118 img
->shdr
[4].sh_size
= debug_frame_size
;
6120 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
6121 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
6123 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
6124 img
->sym
[1].st_value
= buf
;
6125 img
->sym
[1].st_size
= buf_size
;
6127 img
->di
.cu_low_pc
= buf
;
6128 img
->di
.cu_high_pc
= buf
+ buf_size
;
6129 img
->di
.fn_low_pc
= buf
;
6130 img
->di
.fn_high_pc
= buf
+ buf_size
;
6132 dfh
= (DebugFrameHeader
*)(img
+ 1);
6133 memcpy(dfh
, debug_frame
, debug_frame_size
);
6134 dfh
->fde
.func_start
= buf
;
6135 dfh
->fde
.func_len
= buf_size
;
6138 /* Enable this block to be able to debug the ELF image file creation.
6139 One can use readelf, objdump, or other inspection utilities. */
6141 g_autofree
char *jit
= g_strdup_printf("%s/qemu.jit", g_get_tmp_dir());
6142 FILE *f
= fopen(jit
, "w+b");
6144 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
6145 /* Avoid stupid unused return value warning for fwrite. */
6152 one_entry
.symfile_addr
= img
;
6153 one_entry
.symfile_size
= img_size
;
6155 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
6156 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
6157 __jit_debug_descriptor
.first_entry
= &one_entry
;
6158 __jit_debug_register_code();
6161 /* No support for the feature. Provide the entry point expected by exec.c,
6162 and implement the internal function we declared earlier. */
6164 static void tcg_register_jit_int(const void *buf
, size_t size
,
6165 const void *debug_frame
,
6166 size_t debug_frame_size
)
6170 void tcg_register_jit(const void *buf
, size_t buf_size
)
6173 #endif /* ELF_HOST_MACHINE */
6175 #if !TCG_TARGET_MAYBE_vec
6176 void tcg_expand_vec_op(TCGOpcode o
, TCGType t
, unsigned e
, TCGArg a0
, ...)
6178 g_assert_not_reached();