2 * MicroBlaze virtual CPU header
4 * Copyright (c) 2009 Edgar E. Iglesias
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef MICROBLAZE_CPU_H
21 #define MICROBLAZE_CPU_H
23 #include "qemu-common.h"
26 #define TARGET_LONG_BITS 32
28 #define CPUArchState struct CPUMBState
30 #include "exec/cpu-defs.h"
31 #include "fpu/softfloat.h"
33 typedef struct CPUMBState CPUMBState
;
34 #if !defined(CONFIG_USER_ONLY)
41 #define EXCP_HW_BREAK 4
42 #define EXCP_HW_EXCP 5
44 /* MicroBlaze-specific interrupt pending bits. */
45 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
47 /* Meanings of the MBCPU object's two inbound GPIO lines */
51 /* Register aliases. R0 - R15 */
62 #define MSR_BE (1<<0) /* 0x001 */
63 #define MSR_IE (1<<1) /* 0x002 */
64 #define MSR_C (1<<2) /* 0x004 */
65 #define MSR_BIP (1<<3) /* 0x008 */
66 #define MSR_FSL (1<<4) /* 0x010 */
67 #define MSR_ICE (1<<5) /* 0x020 */
68 #define MSR_DZ (1<<6) /* 0x040 */
69 #define MSR_DCE (1<<7) /* 0x080 */
70 #define MSR_EE (1<<8) /* 0x100 */
71 #define MSR_EIP (1<<9) /* 0x200 */
72 #define MSR_PVR (1<<10) /* 0x400 */
73 #define MSR_CC (1<<31)
75 /* Machine State Register (MSR) Fields */
76 #define MSR_UM (1<<11) /* User Mode */
77 #define MSR_UMS (1<<12) /* User Mode Save */
78 #define MSR_VM (1<<13) /* Virtual Mode */
79 #define MSR_VMS (1<<14) /* Virtual Mode Save */
81 #define MSR_KERNEL MSR_EE|MSR_VM
82 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
83 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
84 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
86 /* Exception State Register (ESR) Fields */
87 #define ESR_DIZ (1<<11) /* Zone Protection */
88 #define ESR_S (1<<10) /* Store instruction */
90 #define ESR_ESS_FSL_OFFSET 5
93 #define ESR_EC_UNALIGNED_DATA 1
94 #define ESR_EC_ILLEGAL_OP 2
95 #define ESR_EC_INSN_BUS 3
96 #define ESR_EC_DATA_BUS 4
97 #define ESR_EC_DIVZERO 5
99 #define ESR_EC_PRIVINSN 7
100 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
101 #define ESR_EC_DATA_STORAGE 8
102 #define ESR_EC_INSN_STORAGE 9
103 #define ESR_EC_DATA_TLB 10
104 #define ESR_EC_INSN_TLB 11
105 #define ESR_EC_MASK 31
107 /* Floating Point Status Register (FSR) Bits */
108 #define FSR_IO (1<<4) /* Invalid operation */
109 #define FSR_DZ (1<<3) /* Divide-by-zero */
110 #define FSR_OF (1<<2) /* Overflow */
111 #define FSR_UF (1<<1) /* Underflow */
112 #define FSR_DO (1<<0) /* Denormalized operand error */
116 #define PVR0_PVR_FULL_MASK 0x80000000
117 #define PVR0_USE_BARREL_MASK 0x40000000
118 #define PVR0_USE_DIV_MASK 0x20000000
119 #define PVR0_USE_HW_MUL_MASK 0x10000000
120 #define PVR0_USE_FPU_MASK 0x08000000
121 #define PVR0_USE_EXC_MASK 0x04000000
122 #define PVR0_USE_ICACHE_MASK 0x02000000
123 #define PVR0_USE_DCACHE_MASK 0x01000000
124 #define PVR0_USE_MMU_MASK 0x00800000
125 #define PVR0_USE_BTC 0x00400000
126 #define PVR0_ENDI_MASK 0x00200000
127 #define PVR0_FAULT 0x00100000
128 #define PVR0_VERSION_MASK 0x0000FF00
129 #define PVR0_USER1_MASK 0x000000FF
130 #define PVR0_SPROT_MASK 0x00000001
132 #define PVR0_VERSION_SHIFT 8
134 /* User 2 PVR mask */
135 #define PVR1_USER2_MASK 0xFFFFFFFF
137 /* Configuration PVR masks */
138 #define PVR2_D_OPB_MASK 0x80000000
139 #define PVR2_D_LMB_MASK 0x40000000
140 #define PVR2_I_OPB_MASK 0x20000000
141 #define PVR2_I_LMB_MASK 0x10000000
142 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
143 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
144 #define PVR2_D_PLB_MASK 0x02000000 /* new */
145 #define PVR2_I_PLB_MASK 0x01000000 /* new */
146 #define PVR2_INTERCONNECT 0x00800000 /* new */
147 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
148 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
149 #define PVR2_USE_MSR_INSTR 0x00020000
150 #define PVR2_USE_PCMP_INSTR 0x00010000
151 #define PVR2_AREA_OPTIMISED 0x00008000
152 #define PVR2_USE_BARREL_MASK 0x00004000
153 #define PVR2_USE_DIV_MASK 0x00002000
154 #define PVR2_USE_HW_MUL_MASK 0x00001000
155 #define PVR2_USE_FPU_MASK 0x00000800
156 #define PVR2_USE_MUL64_MASK 0x00000400
157 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
158 #define PVR2_USE_IPLBEXC 0x00000100
159 #define PVR2_USE_DPLBEXC 0x00000080
160 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
161 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
162 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
163 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
164 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
165 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
166 #define PVR2_FPU_EXC_MASK 0x00000001
168 /* Debug and exception PVR masks */
169 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
170 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
171 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
172 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
173 #define PVR3_FSL_LINKS_MASK 0x00000380
175 /* ICache config PVR masks */
176 #define PVR4_USE_ICACHE_MASK 0x80000000
177 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
178 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
179 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
180 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
181 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
183 /* DCache config PVR masks */
184 #define PVR5_USE_DCACHE_MASK 0x80000000
185 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
186 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
187 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
188 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
189 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
190 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
192 /* ICache base address PVR mask */
193 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
195 /* ICache high address PVR mask */
196 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
198 /* DCache base address PVR mask */
199 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
201 /* DCache high address PVR mask */
202 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
204 /* Target family PVR mask */
205 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
207 /* MMU descrtiption */
208 #define PVR11_USE_MMU 0xC0000000
209 #define PVR11_MMU_ITLB_SIZE 0x38000000
210 #define PVR11_MMU_DTLB_SIZE 0x07000000
211 #define PVR11_MMU_TLB_ACCESS 0x00C00000
212 #define PVR11_MMU_ZONES 0x003E0000
213 /* MSR Reset value PVR mask */
214 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
217 #define C_PVR_BASIC 1
222 /* Condition codes. */
230 #define NB_MMU_MODES 3
232 #define STREAM_EXCEPTION (1 << 0)
233 #define STREAM_ATOMIC (1 << 1)
234 #define STREAM_TEST (1 << 2)
235 #define STREAM_CONTROL (1 << 3)
236 #define STREAM_NONBLOCK (1 << 4)
247 float_status fp_status
;
248 /* Stack protectors. Yes, it's a hw feature. */
251 /* lwx/swx reserved address */
252 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
256 /* Internal flags. */
258 #define MSR_EE_FLAG (1 << 8)
259 #define DRTI_FLAG (1 << 16)
260 #define DRTE_FLAG (1 << 17)
261 #define DRTB_FLAG (1 << 18)
262 #define D_FLAG (1 << 19) /* Bit in ESR. */
263 /* TB dependent CPUMBState. */
264 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
267 #if !defined(CONFIG_USER_ONLY)
269 struct microblaze_mmu mmu
;
272 /* Fields up to this point are cleared by a CPU reset */
273 struct {} end_reset_fields
;
277 /* These fields are preserved on reset. */
290 struct MicroBlazeCPU
{
296 /* Microblaze Configuration Settings */
299 uint32_t base_vectors
;
307 bool dcache_writeback
;
316 static inline MicroBlazeCPU
*mb_env_get_cpu(CPUMBState
*env
)
318 return container_of(env
, MicroBlazeCPU
, env
);
321 #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
323 #define ENV_OFFSET offsetof(MicroBlazeCPU, env)
325 void mb_cpu_do_interrupt(CPUState
*cs
);
326 bool mb_cpu_exec_interrupt(CPUState
*cs
, int int_req
);
327 void mb_cpu_dump_state(CPUState
*cpu
, FILE *f
, fprintf_function cpu_fprintf
,
329 hwaddr
mb_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
330 int mb_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
331 int mb_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
333 void mb_tcg_init(void);
334 MicroBlazeCPU
*cpu_mb_init(const char *cpu_model
);
335 /* you can call this signal handler from your SIGBUS and SIGSEGV
336 signal handlers to inform the virtual CPU of exceptions. non zero
337 is returned if the signal was handled by the virtual CPU. */
338 int cpu_mb_signal_handler(int host_signum
, void *pinfo
,
341 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
342 #define TARGET_PAGE_BITS 12
344 #define TARGET_PHYS_ADDR_SPACE_BITS 32
345 #define TARGET_VIRT_ADDR_SPACE_BITS 32
347 #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
349 #define cpu_signal_handler cpu_mb_signal_handler
351 /* MMU modes definitions */
352 #define MMU_MODE0_SUFFIX _nommu
353 #define MMU_MODE1_SUFFIX _kernel
354 #define MMU_MODE2_SUFFIX _user
355 #define MMU_NOMMU_IDX 0
356 #define MMU_KERNEL_IDX 1
357 #define MMU_USER_IDX 2
358 /* See NB_MMU_MODES further up the file. */
360 static inline int cpu_mmu_index (CPUMBState
*env
, bool ifetch
)
362 /* Are we in nommu mode?. */
363 if (!(env
->sregs
[SR_MSR
] & MSR_VM
))
364 return MMU_NOMMU_IDX
;
366 if (env
->sregs
[SR_MSR
] & MSR_UM
)
368 return MMU_KERNEL_IDX
;
371 int mb_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
374 #include "exec/cpu-all.h"
376 static inline void cpu_get_tb_cpu_state(CPUMBState
*env
, target_ulong
*pc
,
377 target_ulong
*cs_base
, uint32_t *flags
)
379 *pc
= env
->sregs
[SR_PC
];
381 *flags
= (env
->iflags
& IFLAGS_TB_MASK
) |
382 (env
->sregs
[SR_MSR
] & (MSR_UM
| MSR_VM
| MSR_EE
));
385 #if !defined(CONFIG_USER_ONLY)
386 void mb_cpu_unassigned_access(CPUState
*cpu
, hwaddr addr
,
387 bool is_write
, bool is_exec
, int is_asi
,