target-ppc/mem_helper.c

   1 /*
   2  *  PowerPC memory access emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "qemu/host-utils.h"
  21 #include "exec/helper-proto.h"
  22
  23 #include "helper_regs.h"
  24 #include "exec/cpu_ldst.h"
  25
  26 //#define DEBUG_OP
  27
  28 /*****************************************************************************/
  29 /* Memory load and stores */
  30
  31 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
  32                                     target_long arg)
  33 {
  34 #if defined(TARGET_PPC64)
  35     if (!msr_is_64bit(env, env->msr)) {
  36         return (uint32_t)(addr + arg);
  37     } else
  38 #endif
  39     {
  40         return addr + arg;
  41     }
  42 }
  43
  44 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  45 {
  46     for (; reg < 32; reg++) {
  47         if (msr_le) {
  48             env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
  49         } else {
  50             env->gpr[reg] = cpu_ldl_data(env, addr);
  51         }
  52         addr = addr_add(env, addr, 4);
  53     }
  54 }
  55
  56 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  57 {
  58     for (; reg < 32; reg++) {
  59         if (msr_le) {
  60             cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
  61         } else {
  62             cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
  63         }
  64         addr = addr_add(env, addr, 4);
  65     }
  66 }
  67
  68 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
  69 {
  70     int sh;
  71
  72     for (; nb > 3; nb -= 4) {
  73         env->gpr[reg] = cpu_ldl_data(env, addr);
  74         reg = (reg + 1) % 32;
  75         addr = addr_add(env, addr, 4);
  76     }
  77     if (unlikely(nb > 0)) {
  78         env->gpr[reg] = 0;
  79         for (sh = 24; nb > 0; nb--, sh -= 8) {
  80             env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
  81             addr = addr_add(env, addr, 1);
  82         }
  83     }
  84 }
  85 /* PPC32 specification says we must generate an exception if
  86  * rA is in the range of registers to be loaded.
  87  * In an other hand, IBM says this is valid, but rA won't be loaded.
  88  * For now, I'll follow the spec...
  89  */
  90 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
  91                  uint32_t ra, uint32_t rb)
  92 {
  93     if (likely(xer_bc != 0)) {
  94         if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
  95                      (reg < rb && (reg + xer_bc) > rb))) {
  96             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
  97                                        POWERPC_EXCP_INVAL |
  98                                        POWERPC_EXCP_INVAL_LSWX);
  99         } else {
 100             helper_lsw(env, addr, xer_bc, reg);
 101         }
 102     }
 103 }
 104
 105 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 106                  uint32_t reg)
 107 {
 108     int sh;
 109
 110     for (; nb > 3; nb -= 4) {
 111         cpu_stl_data(env, addr, env->gpr[reg]);
 112         reg = (reg + 1) % 32;
 113         addr = addr_add(env, addr, 4);
 114     }
 115     if (unlikely(nb > 0)) {
 116         for (sh = 24; nb > 0; nb--, sh -= 8) {
 117             cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
 118             addr = addr_add(env, addr, 1);
 119         }
 120     }
 121 }
 122
 123 static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
 124 {
 125     int i;
 126
 127     addr &= ~(dcache_line_size - 1);
 128     for (i = 0; i < dcache_line_size; i += 4) {
 129         cpu_stl_data(env, addr + i, 0);
 130     }
 131     if (env->reserve_addr == addr) {
 132         env->reserve_addr = (target_ulong)-1ULL;
 133     }
 134 }
 135
 136 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
 137 {
 138     int dcbz_size = env->dcache_line_size;
 139
 140 #if defined(TARGET_PPC64)
 141     if (!is_dcbzl &&
 142         (env->excp_model == POWERPC_EXCP_970) &&
 143         ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
 144         dcbz_size = 32;
 145     }
 146 #endif
 147
 148     /* XXX add e500mc support */
 149
 150     do_dcbz(env, addr, dcbz_size);
 151 }
 152
 153 void helper_icbi(CPUPPCState *env, target_ulong addr)
 154 {
 155     addr &= ~(env->dcache_line_size - 1);
 156     /* Invalidate one cache line :
 157      * PowerPC specification says this is to be treated like a load
 158      * (not a fetch) by the MMU. To be sure it will be so,
 159      * do the load "by hand".
 160      */
 161     cpu_ldl_data(env, addr);
 162 }
 163
 164 /* XXX: to be tested */
 165 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 166                           uint32_t ra, uint32_t rb)
 167 {
 168     int i, c, d;
 169
 170     d = 24;
 171     for (i = 0; i < xer_bc; i++) {
 172         c = cpu_ldub_data(env, addr);
 173         addr = addr_add(env, addr, 1);
 174         /* ra (if not 0) and rb are never modified */
 175         if (likely(reg != rb && (ra == 0 || reg != ra))) {
 176             env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
 177         }
 178         if (unlikely(c == xer_cmp)) {
 179             break;
 180         }
 181         if (likely(d != 0)) {
 182             d -= 8;
 183         } else {
 184             d = 24;
 185             reg++;
 186             reg = reg & 0x1F;
 187         }
 188     }
 189     return i;
 190 }
 191
 192 /*****************************************************************************/
 193 /* Altivec extension helpers */
 194 #if defined(HOST_WORDS_BIGENDIAN)
 195 #define HI_IDX 0
 196 #define LO_IDX 1
 197 #else
 198 #define HI_IDX 1
 199 #define LO_IDX 0
 200 #endif
 201
 202 #define LVE(name, access, swap, element)                        \
 203     void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
 204                        target_ulong addr)                       \
 205     {                                                           \
 206         size_t n_elems = ARRAY_SIZE(r->element);                \
 207         int adjust = HI_IDX*(n_elems - 1);                      \
 208         int sh = sizeof(r->element[0]) >> 1;                    \
 209         int index = (addr & 0xf) >> sh;                         \
 210                                                                 \
 211         if (msr_le) {                                           \
 212             index = n_elems - index - 1;                        \
 213             r->element[LO_IDX ? index : (adjust - index)] =     \
 214                 swap(access(env, addr));                        \
 215         } else {                                                \
 216             r->element[LO_IDX ? index : (adjust - index)] =     \
 217                 access(env, addr);                              \
 218         }                                                       \
 219     }
 220 #define I(x) (x)
 221 LVE(lvebx, cpu_ldub_data, I, u8)
 222 LVE(lvehx, cpu_lduw_data, bswap16, u16)
 223 LVE(lvewx, cpu_ldl_data, bswap32, u32)
 224 #undef I
 225 #undef LVE
 226
 227 #define STVE(name, access, swap, element)                               \
 228     void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
 229                        target_ulong addr)                               \
 230     {                                                                   \
 231         size_t n_elems = ARRAY_SIZE(r->element);                        \
 232         int adjust = HI_IDX * (n_elems - 1);                            \
 233         int sh = sizeof(r->element[0]) >> 1;                            \
 234         int index = (addr & 0xf) >> sh;                                 \
 235                                                                         \
 236         if (msr_le) {                                                   \
 237             index = n_elems - index - 1;                                \
 238             access(env, addr, swap(r->element[LO_IDX ? index :          \
 239                                               (adjust - index)]));      \
 240         } else {                                                        \
 241             access(env, addr, r->element[LO_IDX ? index :               \
 242                                          (adjust - index)]);            \
 243         }                                                               \
 244     }
 245 #define I(x) (x)
 246 STVE(stvebx, cpu_stb_data, I, u8)
 247 STVE(stvehx, cpu_stw_data, bswap16, u16)
 248 STVE(stvewx, cpu_stl_data, bswap32, u32)
 249 #undef I
 250 #undef LVE
 251
 252 #undef HI_IDX
 253 #undef LO_IDX