hw/ide/microdrive.c

   1 /*
   2  * QEMU IDE Emulation: microdrive (CF / PCMCIA)
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pcmcia.h>
  28 #include "block/block.h"
  29 #include "sysemu/dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /***********************************************************/
  34 /* CF-ATA Microdrive */
  35
  36 #define METADATA_SIZE   0x20
  37
  38 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */
  39 typedef struct {
  40     IDEBus bus;
  41     PCMCIACardState card;
  42     uint32_t attr_base;
  43     uint32_t io_base;
  44
  45     /* Card state */
  46     uint8_t opt;
  47     uint8_t stat;
  48     uint8_t pins;
  49
  50     uint8_t ctrl;
  51     uint16_t io;
  52     uint8_t cycle;
  53 } MicroDriveState;
  54
  55 /* Register bitfields */
  56 enum md_opt {
  57     OPT_MODE_MMAP       = 0,
  58     OPT_MODE_IOMAP16    = 1,
  59     OPT_MODE_IOMAP1     = 2,
  60     OPT_MODE_IOMAP2     = 3,
  61     OPT_MODE            = 0x3f,
  62     OPT_LEVIREQ         = 0x40,
  63     OPT_SRESET          = 0x80,
  64 };
  65 enum md_cstat {
  66     STAT_INT            = 0x02,
  67     STAT_PWRDWN         = 0x04,
  68     STAT_XE             = 0x10,
  69     STAT_IOIS8          = 0x20,
  70     STAT_SIGCHG         = 0x40,
  71     STAT_CHANGED        = 0x80,
  72 };
  73 enum md_pins {
  74     PINS_MRDY           = 0x02,
  75     PINS_CRDY           = 0x20,
  76 };
  77 enum md_ctrl {
  78     CTRL_IEN            = 0x02,
  79     CTRL_SRST           = 0x04,
  80 };
  81
  82 static inline void md_interrupt_update(MicroDriveState *s)
  83 {
  84     if (!s->card.slot)
  85         return;
  86
  87     qemu_set_irq(s->card.slot->irq,
  88                     !(s->stat & STAT_INT) &&    /* Inverted */
  89                     !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
  90                     !(s->opt & OPT_SRESET));
  91 }
  92
  93 static void md_set_irq(void *opaque, int irq, int level)
  94 {
  95     MicroDriveState *s = opaque;
  96     if (level)
  97         s->stat |= STAT_INT;
  98     else
  99         s->stat &= ~STAT_INT;
 100
 101     md_interrupt_update(s);
 102 }
 103
 104 static void md_reset(MicroDriveState *s)
 105 {
 106     s->opt = OPT_MODE_MMAP;
 107     s->stat = 0;
 108     s->pins = 0;
 109     s->cycle = 0;
 110     s->ctrl = 0;
 111     ide_bus_reset(&s->bus);
 112 }
 113
 114 static uint8_t md_attr_read(void *opaque, uint32_t at)
 115 {
 116     MicroDriveState *s = opaque;
 117     if (at < s->attr_base) {
 118         if (at < s->card.cis_len)
 119             return s->card.cis[at];
 120         else
 121             return 0x00;
 122     }
 123
 124     at -= s->attr_base;
 125
 126     switch (at) {
 127     case 0x00:  /* Configuration Option Register */
 128         return s->opt;
 129     case 0x02:  /* Card Configuration Status Register */
 130         if (s->ctrl & CTRL_IEN)
 131             return s->stat & ~STAT_INT;
 132         else
 133             return s->stat;
 134     case 0x04:  /* Pin Replacement Register */
 135         return (s->pins & PINS_CRDY) | 0x0c;
 136     case 0x06:  /* Socket and Copy Register */
 137         return 0x00;
 138 #ifdef VERBOSE
 139     default:
 140         printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
 141 #endif
 142     }
 143
 144     return 0;
 145 }
 146
 147 static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
 148 {
 149     MicroDriveState *s = opaque;
 150     at -= s->attr_base;
 151
 152     switch (at) {
 153     case 0x00:  /* Configuration Option Register */
 154         s->opt = value & 0xcf;
 155         if (value & OPT_SRESET)
 156             md_reset(s);
 157         md_interrupt_update(s);
 158         break;
 159     case 0x02:  /* Card Configuration Status Register */
 160         if ((s->stat ^ value) & STAT_PWRDWN)
 161             s->pins |= PINS_CRDY;
 162         s->stat &= 0x82;
 163         s->stat |= value & 0x74;
 164         md_interrupt_update(s);
 165         /* Word 170 in Identify Device must be equal to STAT_XE */
 166         break;
 167     case 0x04:  /* Pin Replacement Register */
 168         s->pins &= PINS_CRDY;
 169         s->pins |= value & PINS_MRDY;
 170         break;
 171     case 0x06:  /* Socket and Copy Register */
 172         break;
 173     default:
 174         printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
 175     }
 176 }
 177
 178 static uint16_t md_common_read(void *opaque, uint32_t at)
 179 {
 180     MicroDriveState *s = opaque;
 181     IDEState *ifs;
 182     uint16_t ret;
 183     at -= s->io_base;
 184
 185     switch (s->opt & OPT_MODE) {
 186     case OPT_MODE_MMAP:
 187         if ((at & ~0x3ff) == 0x400)
 188             at = 0;
 189         break;
 190     case OPT_MODE_IOMAP16:
 191         at &= 0xf;
 192         break;
 193     case OPT_MODE_IOMAP1:
 194         if ((at & ~0xf) == 0x3f0)
 195             at -= 0x3e8;
 196         else if ((at & ~0xf) == 0x1f0)
 197             at -= 0x1f0;
 198         break;
 199     case OPT_MODE_IOMAP2:
 200         if ((at & ~0xf) == 0x370)
 201             at -= 0x368;
 202         else if ((at & ~0xf) == 0x170)
 203             at -= 0x170;
 204     }
 205
 206     switch (at) {
 207     case 0x0:   /* Even RD Data */
 208     case 0x8:
 209         return ide_data_readw(&s->bus, 0);
 210
 211         /* TODO: 8-bit accesses */
 212         if (s->cycle)
 213             ret = s->io >> 8;
 214         else {
 215             s->io = ide_data_readw(&s->bus, 0);
 216             ret = s->io & 0xff;
 217         }
 218         s->cycle = !s->cycle;
 219         return ret;
 220     case 0x9:   /* Odd RD Data */
 221         return s->io >> 8;
 222     case 0xd:   /* Error */
 223         return ide_ioport_read(&s->bus, 0x1);
 224     case 0xe:   /* Alternate Status */
 225         ifs = idebus_active_if(&s->bus);
 226         if (ifs->bs)
 227             return ifs->status;
 228         else
 229             return 0;
 230     case 0xf:   /* Device Address */
 231         ifs = idebus_active_if(&s->bus);
 232         return 0xc2 | ((~ifs->select << 2) & 0x3c);
 233     default:
 234         return ide_ioport_read(&s->bus, at);
 235     }
 236
 237     return 0;
 238 }
 239
 240 static void md_common_write(void *opaque, uint32_t at, uint16_t value)
 241 {
 242     MicroDriveState *s = opaque;
 243     at -= s->io_base;
 244
 245     switch (s->opt & OPT_MODE) {
 246     case OPT_MODE_MMAP:
 247         if ((at & ~0x3ff) == 0x400)
 248             at = 0;
 249         break;
 250     case OPT_MODE_IOMAP16:
 251         at &= 0xf;
 252         break;
 253     case OPT_MODE_IOMAP1:
 254         if ((at & ~0xf) == 0x3f0)
 255             at -= 0x3e8;
 256         else if ((at & ~0xf) == 0x1f0)
 257             at -= 0x1f0;
 258         break;
 259     case OPT_MODE_IOMAP2:
 260         if ((at & ~0xf) == 0x370)
 261             at -= 0x368;
 262         else if ((at & ~0xf) == 0x170)
 263             at -= 0x170;
 264     }
 265
 266     switch (at) {
 267     case 0x0:   /* Even WR Data */
 268     case 0x8:
 269         ide_data_writew(&s->bus, 0, value);
 270         break;
 271
 272         /* TODO: 8-bit accesses */
 273         if (s->cycle)
 274             ide_data_writew(&s->bus, 0, s->io | (value << 8));
 275         else
 276             s->io = value & 0xff;
 277         s->cycle = !s->cycle;
 278         break;
 279     case 0x9:
 280         s->io = value & 0xff;
 281         s->cycle = !s->cycle;
 282         break;
 283     case 0xd:   /* Features */
 284         ide_ioport_write(&s->bus, 0x1, value);
 285         break;
 286     case 0xe:   /* Device Control */
 287         s->ctrl = value;
 288         if (value & CTRL_SRST)
 289             md_reset(s);
 290         md_interrupt_update(s);
 291         break;
 292     default:
 293         if (s->stat & STAT_PWRDWN) {
 294             s->pins |= PINS_CRDY;
 295             s->stat &= ~STAT_PWRDWN;
 296         }
 297         ide_ioport_write(&s->bus, at, value);
 298     }
 299 }
 300
 301 static const VMStateDescription vmstate_microdrive = {
 302     .name = "microdrive",
 303     .version_id = 3,
 304     .minimum_version_id = 0,
 305     .minimum_version_id_old = 0,
 306     .fields      = (VMStateField []) {
 307         VMSTATE_UINT8(opt, MicroDriveState),
 308         VMSTATE_UINT8(stat, MicroDriveState),
 309         VMSTATE_UINT8(pins, MicroDriveState),
 310         VMSTATE_UINT8(ctrl, MicroDriveState),
 311         VMSTATE_UINT16(io, MicroDriveState),
 312         VMSTATE_UINT8(cycle, MicroDriveState),
 313         VMSTATE_IDE_BUS(bus, MicroDriveState),
 314         VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 static const uint8_t dscm1xxxx_cis[0x14a] = {
 320     [0x000] = CISTPL_DEVICE,    /* 5V Device Information */
 321     [0x002] = 0x03,             /* Tuple length = 4 bytes */
 322     [0x004] = 0xdb,             /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
 323     [0x006] = 0x01,             /* Size = 2K bytes */
 324     [0x008] = CISTPL_ENDMARK,
 325
 326     [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
 327     [0x00c] = 0x04,             /* Tuple length = 4 byest */
 328     [0x00e] = 0x03,             /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
 329     [0x010] = 0xdb,             /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
 330     [0x012] = 0x01,             /* Size = 2K bytes */
 331     [0x014] = CISTPL_ENDMARK,
 332
 333     [0x016] = CISTPL_JEDEC_C,   /* JEDEC ID */
 334     [0x018] = 0x02,             /* Tuple length = 2 bytes */
 335     [0x01a] = 0xdf,             /* PC Card ATA with no Vpp required */
 336     [0x01c] = 0x01,
 337
 338     [0x01e] = CISTPL_MANFID,    /* Manufacture ID */
 339     [0x020] = 0x04,             /* Tuple length = 4 bytes */
 340     [0x022] = 0xa4,             /* TPLMID_MANF = 00a4 (IBM) */
 341     [0x024] = 0x00,
 342     [0x026] = 0x00,             /* PLMID_CARD = 0000 */
 343     [0x028] = 0x00,
 344
 345     [0x02a] = CISTPL_VERS_1,    /* Level 1 Version */
 346     [0x02c] = 0x12,             /* Tuple length = 23 bytes */
 347     [0x02e] = 0x04,             /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
 348     [0x030] = 0x01,             /* Minor Version = 1 */
 349     [0x032] = 'I',
 350     [0x034] = 'B',
 351     [0x036] = 'M',
 352     [0x038] = 0x00,
 353     [0x03a] = 'm',
 354     [0x03c] = 'i',
 355     [0x03e] = 'c',
 356     [0x040] = 'r',
 357     [0x042] = 'o',
 358     [0x044] = 'd',
 359     [0x046] = 'r',
 360     [0x048] = 'i',
 361     [0x04a] = 'v',
 362     [0x04c] = 'e',
 363     [0x04e] = 0x00,
 364     [0x050] = CISTPL_ENDMARK,
 365
 366     [0x052] = CISTPL_FUNCID,    /* Function ID */
 367     [0x054] = 0x02,             /* Tuple length = 2 bytes */
 368     [0x056] = 0x04,             /* TPLFID_FUNCTION = Fixed Disk */
 369     [0x058] = 0x01,             /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
 370
 371     [0x05a] = CISTPL_FUNCE,     /* Function Extension */
 372     [0x05c] = 0x02,             /* Tuple length = 2 bytes */
 373     [0x05e] = 0x01,             /* TPLFE_TYPE = Disk Device Interface */
 374     [0x060] = 0x01,             /* TPLFE_DATA = PC Card ATA Interface */
 375
 376     [0x062] = CISTPL_FUNCE,     /* Function Extension */
 377     [0x064] = 0x03,             /* Tuple length = 3 bytes */
 378     [0x066] = 0x02,             /* TPLFE_TYPE = Basic PC Card ATA Interface */
 379     [0x068] = 0x08,             /* TPLFE_DATA: Rotating, Unique, Single */
 380     [0x06a] = 0x0f,             /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
 381
 382     [0x06c] = CISTPL_CONFIG,    /* Configuration */
 383     [0x06e] = 0x05,             /* Tuple length = 5 bytes */
 384     [0x070] = 0x01,             /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
 385     [0x072] = 0x07,             /* TPCC_LAST = 7 */
 386     [0x074] = 0x00,             /* TPCC_RADR = 0200 */
 387     [0x076] = 0x02,
 388     [0x078] = 0x0f,             /* TPCC_RMSK = 200, 202, 204, 206 */
 389
 390     [0x07a] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 391     [0x07c] = 0x0b,             /* Tuple length = 11 bytes */
 392     [0x07e] = 0xc0,             /* TPCE_INDX = Memory Mode, Default, Iface */
 393     [0x080] = 0xc0,             /* TPCE_IF = Memory, no BVDs, no WP, READY */
 394     [0x082] = 0xa1,             /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
 395     [0x084] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 396     [0x086] = 0x55,             /* NomV: 5.0 V */
 397     [0x088] = 0x4d,             /* MinV: 4.5 V */
 398     [0x08a] = 0x5d,             /* MaxV: 5.5 V */
 399     [0x08c] = 0x4e,             /* Peakl: 450 mA */
 400     [0x08e] = 0x08,             /* TPCE_MS = 1 window, 1 byte, Host address */
 401     [0x090] = 0x00,             /* Window descriptor: Window length = 0 */
 402     [0x092] = 0x20,             /* TPCE_MI: support power down mode, RW */
 403
 404     [0x094] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 405     [0x096] = 0x06,             /* Tuple length = 6 bytes */
 406     [0x098] = 0x00,             /* TPCE_INDX = Memory Mode, no Default */
 407     [0x09a] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 408     [0x09c] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 409     [0x09e] = 0xb5,             /* NomV: 3.3 V */
 410     [0x0a0] = 0x1e,
 411     [0x0a2] = 0x3e,             /* Peakl: 350 mA */
 412
 413     [0x0a4] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 414     [0x0a6] = 0x0d,             /* Tuple length = 13 bytes */
 415     [0x0a8] = 0xc1,             /* TPCE_INDX = I/O and Memory Mode, Default */
 416     [0x0aa] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 417     [0x0ac] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 418     [0x0ae] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 419     [0x0b0] = 0x55,             /* NomV: 5.0 V */
 420     [0x0b2] = 0x4d,             /* MinV: 4.5 V */
 421     [0x0b4] = 0x5d,             /* MaxV: 5.5 V */
 422     [0x0b6] = 0x4e,             /* Peakl: 450 mA */
 423     [0x0b8] = 0x64,             /* TPCE_IO = 16-byte boundary, 16/8 accesses */
 424     [0x0ba] = 0xf0,             /* TPCE_IR =  MASK, Level, Pulse, Share */
 425     [0x0bc] = 0xff,             /* IRQ0..IRQ7 supported */
 426     [0x0be] = 0xff,             /* IRQ8..IRQ15 supported */
 427     [0x0c0] = 0x20,             /* TPCE_MI = support power down mode */
 428
 429     [0x0c2] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 430     [0x0c4] = 0x06,             /* Tuple length = 6 bytes */
 431     [0x0c6] = 0x01,             /* TPCE_INDX = I/O and Memory Mode */
 432     [0x0c8] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 433     [0x0ca] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 434     [0x0cc] = 0xb5,             /* NomV: 3.3 V */
 435     [0x0ce] = 0x1e,
 436     [0x0d0] = 0x3e,             /* Peakl: 350 mA */
 437
 438     [0x0d2] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 439     [0x0d4] = 0x12,             /* Tuple length = 18 bytes */
 440     [0x0d6] = 0xc2,             /* TPCE_INDX = I/O Primary Mode */
 441     [0x0d8] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 442     [0x0da] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 443     [0x0dc] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 444     [0x0de] = 0x55,             /* NomV: 5.0 V */
 445     [0x0e0] = 0x4d,             /* MinV: 4.5 V */
 446     [0x0e2] = 0x5d,             /* MaxV: 5.5 V */
 447     [0x0e4] = 0x4e,             /* Peakl: 450 mA */
 448     [0x0e6] = 0xea,             /* TPCE_IO = 1K boundary, 16/8 access, Range */
 449     [0x0e8] = 0x61,             /* Range: 2 fields, 2 bytes addr, 1 byte len */
 450     [0x0ea] = 0xf0,             /* Field 1 address = 0x01f0 */
 451     [0x0ec] = 0x01,
 452     [0x0ee] = 0x07,             /* Address block length = 8 */
 453     [0x0f0] = 0xf6,             /* Field 2 address = 0x03f6 */
 454     [0x0f2] = 0x03,
 455     [0x0f4] = 0x01,             /* Address block length = 2 */
 456     [0x0f6] = 0xee,             /* TPCE_IR = IRQ E, Level, Pulse, Share */
 457     [0x0f8] = 0x20,             /* TPCE_MI = support power down mode */
 458
 459     [0x0fa] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 460     [0x0fc] = 0x06,             /* Tuple length = 6 bytes */
 461     [0x0fe] = 0x02,             /* TPCE_INDX = I/O Primary Mode, no Default */
 462     [0x100] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 463     [0x102] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 464     [0x104] = 0xb5,             /* NomV: 3.3 V */
 465     [0x106] = 0x1e,
 466     [0x108] = 0x3e,             /* Peakl: 350 mA */
 467
 468     [0x10a] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 469     [0x10c] = 0x12,             /* Tuple length = 18 bytes */
 470     [0x10e] = 0xc3,             /* TPCE_INDX = I/O Secondary Mode, Default */
 471     [0x110] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 472     [0x112] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 473     [0x114] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 474     [0x116] = 0x55,             /* NomV: 5.0 V */
 475     [0x118] = 0x4d,             /* MinV: 4.5 V */
 476     [0x11a] = 0x5d,             /* MaxV: 5.5 V */
 477     [0x11c] = 0x4e,             /* Peakl: 450 mA */
 478     [0x11e] = 0xea,             /* TPCE_IO = 1K boundary, 16/8 access, Range */
 479     [0x120] = 0x61,             /* Range: 2 fields, 2 byte addr, 1 byte len */
 480     [0x122] = 0x70,             /* Field 1 address = 0x0170 */
 481     [0x124] = 0x01,
 482     [0x126] = 0x07,             /* Address block length = 8 */
 483     [0x128] = 0x76,             /* Field 2 address = 0x0376 */
 484     [0x12a] = 0x03,
 485     [0x12c] = 0x01,             /* Address block length = 2 */
 486     [0x12e] = 0xee,             /* TPCE_IR = IRQ E, Level, Pulse, Share */
 487     [0x130] = 0x20,             /* TPCE_MI = support power down mode */
 488
 489     [0x132] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 490     [0x134] = 0x06,             /* Tuple length = 6 bytes */
 491     [0x136] = 0x03,             /* TPCE_INDX = I/O Secondary Mode */
 492     [0x138] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 493     [0x13a] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 494     [0x13c] = 0xb5,             /* NomV: 3.3 V */
 495     [0x13e] = 0x1e,
 496     [0x140] = 0x3e,             /* Peakl: 350 mA */
 497
 498     [0x142] = CISTPL_NO_LINK,   /* No Link */
 499     [0x144] = 0x00,             /* Tuple length = 0 bytes */
 500
 501     [0x146] = CISTPL_END,       /* Tuple End */
 502 };
 503
 504 static int dscm1xxxx_attach(void *opaque)
 505 {
 506     MicroDriveState *md = opaque;
 507     md->card.attr_read = md_attr_read;
 508     md->card.attr_write = md_attr_write;
 509     md->card.common_read = md_common_read;
 510     md->card.common_write = md_common_write;
 511     md->card.io_read = md_common_read;
 512     md->card.io_write = md_common_write;
 513
 514     md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
 515     md->io_base = 0x0;
 516
 517     md_reset(md);
 518     md_interrupt_update(md);
 519
 520     md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
 521     return 0;
 522 }
 523
 524 static int dscm1xxxx_detach(void *opaque)
 525 {
 526     MicroDriveState *md = opaque;
 527     md_reset(md);
 528     return 0;
 529 }
 530
 531 PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv)
 532 {
 533     MicroDriveState *md = (MicroDriveState *) g_malloc0(sizeof(MicroDriveState));
 534     md->card.state = md;
 535     md->card.attach = dscm1xxxx_attach;
 536     md->card.detach = dscm1xxxx_detach;
 537     md->card.cis = dscm1xxxx_cis;
 538     md->card.cis_len = sizeof(dscm1xxxx_cis);
 539
 540     ide_init2_with_non_qdev_drives(&md->bus, bdrv, NULL,
 541                                    qemu_allocate_irqs(md_set_irq, md, 1)[0]);
 542     md->bus.ifs[0].drive_kind = IDE_CFATA;
 543     md->bus.ifs[0].mdata_size = METADATA_SIZE;
 544     md->bus.ifs[0].mdata_storage = (uint8_t *) g_malloc0(METADATA_SIZE);
 545
 546     vmstate_register(NULL, -1, &vmstate_microdrive, md);
 547
 548     return &md->card;
 549 }