?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
qapi: convert to use python print function instead of statement
[qemu/ar7.git] / memory.c
blob449a1429b946c57034a286d0f50cc43f321069ff
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "exec/ioport.h"
23 #include "qapi/visitor.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/misc/mmio_interface.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36
37 //#define DEBUG_UNASSIGNED
38
39 static unsigned memory_region_transaction_depth;
40 static bool memory_region_update_pending;
41 static bool ioeventfd_update_pending;
42 static bool global_dirty_log = false;
43
44 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
46
47 static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
50 static GHashTable *flat_views;
51
52 typedef struct AddrRange AddrRange;
53
54 /*
55 * Note that signed integers are needed for negative offsetting in aliases
56 * (large MemoryRegion::alias_offset).
57 */
58 struct AddrRange {
59 Int128 start;
60 Int128 size;
61 };
62
63 static AddrRange addrrange_make(Int128 start, Int128 size)
64 {
65 return (AddrRange) { start, size };
66 }
67
68 static bool addrrange_equal(AddrRange r1, AddrRange r2)
69 {
70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
71 }
72
73 static Int128 addrrange_end(AddrRange r)
74 {
75 return int128_add(r.start, r.size);
76 }
77
78 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
79 {
80 int128_addto(&range.start, delta);
81 return range;
82 }
83
84 static bool addrrange_contains(AddrRange range, Int128 addr)
85 {
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88 }
89
90 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91 {
92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
94 }
95
96 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97 {
98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
101 }
102
103 enum ListenerDirection { Forward, Reverse };
104
105 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 struct memory_listeners_as *list = &(_as)->listeners; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
156 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
157 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
158 do { \
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
162 } while(0)
163
164 struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167 };
168
169 struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
173 EventNotifier *e;
174 };
175
176 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178 {
179 if (int128_lt(a.addr.start, b.addr.start)) {
180 return true;
181 } else if (int128_gt(a.addr.start, b.addr.start)) {
182 return false;
183 } else if (int128_lt(a.addr.size, b.addr.size)) {
184 return true;
185 } else if (int128_gt(a.addr.size, b.addr.size)) {
186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
198 if (a.e < b.e) {
199 return true;
200 } else if (a.e > b.e) {
201 return false;
202 }
203 return false;
204 }
205
206 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208 {
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211 }
212
213 typedef struct FlatRange FlatRange;
214
215 /* Range of memory in the global map. Addresses are absolute. */
216 struct FlatRange {
217 MemoryRegion *mr;
218 hwaddr offset_in_region;
219 AddrRange addr;
220 uint8_t dirty_log_mask;
221 bool romd_mode;
222 bool readonly;
223 };
224
225 /* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228 struct FlatView {
229 struct rcu_head rcu;
230 unsigned ref;
231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
234 struct AddressSpaceDispatch *dispatch;
235 MemoryRegion *root;
236 };
237
238 typedef struct AddressSpaceOps AddressSpaceOps;
239
240 #define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
243 static inline MemoryRegionSection
244 section_from_flat_range(FlatRange *fr, FlatView *fv)
245 {
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
248 .fv = fv,
249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254 }
255
256 static bool flatrange_equal(FlatRange *a, FlatRange *b)
257 {
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
260 && a->offset_in_region == b->offset_in_region
261 && a->romd_mode == b->romd_mode
262 && a->readonly == b->readonly;
263 }
264
265 static FlatView *flatview_new(MemoryRegion *mr_root)
266 {
267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
270 view->ref = 1;
271 view->root = mr_root;
272 memory_region_ref(mr_root);
273 trace_flatview_new(view, mr_root);
274
275 return view;
276 }
277
278 /* Insert a range into a given position. Caller is responsible for maintaining
279 * sorting order.
280 */
281 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
282 {
283 if (view->nr == view->nr_allocated) {
284 view->nr_allocated = MAX(2 * view->nr, 10);
285 view->ranges = g_realloc(view->ranges,
286 view->nr_allocated * sizeof(*view->ranges));
287 }
288 memmove(view->ranges + pos + 1, view->ranges + pos,
289 (view->nr - pos) * sizeof(FlatRange));
290 view->ranges[pos] = *range;
291 memory_region_ref(range->mr);
292 ++view->nr;
293 }
294
295 static void flatview_destroy(FlatView *view)
296 {
297 int i;
298
299 trace_flatview_destroy(view, view->root);
300 if (view->dispatch) {
301 address_space_dispatch_free(view->dispatch);
302 }
303 for (i = 0; i < view->nr; i++) {
304 memory_region_unref(view->ranges[i].mr);
305 }
306 g_free(view->ranges);
307 memory_region_unref(view->root);
308 g_free(view);
309 }
310
311 static bool flatview_ref(FlatView *view)
312 {
313 return atomic_fetch_inc_nonzero(&view->ref) > 0;
314 }
315
316 static void flatview_unref(FlatView *view)
317 {
318 if (atomic_fetch_dec(&view->ref) == 1) {
319 trace_flatview_destroy_rcu(view, view->root);
320 assert(view->root);
321 call_rcu(view, flatview_destroy, rcu);
322 }
323 }
324
325 FlatView *address_space_to_flatview(AddressSpace *as)
326 {
327 return atomic_rcu_read(&as->current_map);
328 }
329
330 AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
331 {
332 return fv->dispatch;
333 }
334
335 AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
336 {
337 return flatview_to_dispatch(address_space_to_flatview(as));
338 }
339
340 static bool can_merge(FlatRange *r1, FlatRange *r2)
341 {
342 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
343 && r1->mr == r2->mr
344 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
345 r1->addr.size),
346 int128_make64(r2->offset_in_region))
347 && r1->dirty_log_mask == r2->dirty_log_mask
348 && r1->romd_mode == r2->romd_mode
349 && r1->readonly == r2->readonly;
350 }
351
352 /* Attempt to simplify a view by merging adjacent ranges */
353 static void flatview_simplify(FlatView *view)
354 {
355 unsigned i, j;
356
357 i = 0;
358 while (i < view->nr) {
359 j = i + 1;
360 while (j < view->nr
361 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
362 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
363 ++j;
364 }
365 ++i;
366 memmove(&view->ranges[i], &view->ranges[j],
367 (view->nr - j) * sizeof(view->ranges[j]));
368 view->nr -= j - i;
369 }
370 }
371
372 static bool memory_region_big_endian(MemoryRegion *mr)
373 {
374 #ifdef TARGET_WORDS_BIGENDIAN
375 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
376 #else
377 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
378 #endif
379 }
380
381 static bool memory_region_wrong_endianness(MemoryRegion *mr)
382 {
383 #ifdef TARGET_WORDS_BIGENDIAN
384 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
385 #else
386 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
387 #endif
388 }
389
390 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
391 {
392 if (memory_region_wrong_endianness(mr)) {
393 switch (size) {
394 case 1:
395 break;
396 case 2:
397 *data = bswap16(*data);
398 break;
399 case 4:
400 *data = bswap32(*data);
401 break;
402 case 8:
403 *data = bswap64(*data);
404 break;
405 default:
406 abort();
407 }
408 }
409 }
410
411 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
412 {
413 MemoryRegion *root;
414 hwaddr abs_addr = offset;
415
416 abs_addr += mr->addr;
417 for (root = mr; root->container; ) {
418 root = root->container;
419 abs_addr += root->addr;
420 }
421
422 return abs_addr;
423 }
424
425 static int get_cpu_index(void)
426 {
427 if (current_cpu) {
428 return current_cpu->cpu_index;
429 }
430 return -1;
431 }
432
433 static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
434 hwaddr addr,
435 uint64_t *value,
436 unsigned size,
437 unsigned shift,
438 uint64_t mask,
439 MemTxAttrs attrs)
440 {
441 uint64_t tmp;
442
443 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
444 if (mr->subpage) {
445 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
446 } else if (mr == &io_mem_notdirty) {
447 /* Accesses to code which has previously been translated into a TB show
448 * up in the MMIO path, as accesses to the io_mem_notdirty
449 * MemoryRegion. */
450 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
451 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
452 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
453 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
454 }
455 *value |= (tmp & mask) << shift;
456 return MEMTX_OK;
457 }
458
459 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
460 hwaddr addr,
461 uint64_t *value,
462 unsigned size,
463 unsigned shift,
464 uint64_t mask,
465 MemTxAttrs attrs)
466 {
467 uint64_t tmp;
468
469 tmp = mr->ops->read(mr->opaque, addr, size);
470 if (mr->subpage) {
471 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
472 } else if (mr == &io_mem_notdirty) {
473 /* Accesses to code which has previously been translated into a TB show
474 * up in the MMIO path, as accesses to the io_mem_notdirty
475 * MemoryRegion. */
476 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
477 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
478 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
479 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
480 }
481 *value |= (tmp & mask) << shift;
482 return MEMTX_OK;
483 }
484
485 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
486 hwaddr addr,
487 uint64_t *value,
488 unsigned size,
489 unsigned shift,
490 uint64_t mask,
491 MemTxAttrs attrs)
492 {
493 uint64_t tmp = 0;
494 MemTxResult r;
495
496 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
497 if (mr->subpage) {
498 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
499 } else if (mr == &io_mem_notdirty) {
500 /* Accesses to code which has previously been translated into a TB show
501 * up in the MMIO path, as accesses to the io_mem_notdirty
502 * MemoryRegion. */
503 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
504 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
505 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
506 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
507 }
508 *value |= (tmp & mask) << shift;
509 return r;
510 }
511
512 static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
516 unsigned shift,
517 uint64_t mask,
518 MemTxAttrs attrs)
519 {
520 uint64_t tmp;
521
522 tmp = (*value >> shift) & mask;
523 if (mr->subpage) {
524 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
525 } else if (mr == &io_mem_notdirty) {
526 /* Accesses to code which has previously been translated into a TB show
527 * up in the MMIO path, as accesses to the io_mem_notdirty
528 * MemoryRegion. */
529 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
530 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
531 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
532 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
533 }
534 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
535 return MEMTX_OK;
536 }
537
538 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
539 hwaddr addr,
540 uint64_t *value,
541 unsigned size,
542 unsigned shift,
543 uint64_t mask,
544 MemTxAttrs attrs)
545 {
546 uint64_t tmp;
547
548 tmp = (*value >> shift) & mask;
549 if (mr->subpage) {
550 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
551 } else if (mr == &io_mem_notdirty) {
552 /* Accesses to code which has previously been translated into a TB show
553 * up in the MMIO path, as accesses to the io_mem_notdirty
554 * MemoryRegion. */
555 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
556 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
557 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
558 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
559 }
560 mr->ops->write(mr->opaque, addr, tmp, size);
561 return MEMTX_OK;
562 }
563
564 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
565 hwaddr addr,
566 uint64_t *value,
567 unsigned size,
568 unsigned shift,
569 uint64_t mask,
570 MemTxAttrs attrs)
571 {
572 uint64_t tmp;
573
574 tmp = (*value >> shift) & mask;
575 if (mr->subpage) {
576 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
577 } else if (mr == &io_mem_notdirty) {
578 /* Accesses to code which has previously been translated into a TB show
579 * up in the MMIO path, as accesses to the io_mem_notdirty
580 * MemoryRegion. */
581 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
582 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
583 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
584 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
585 }
586 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
587 }
588
589 static MemTxResult access_with_adjusted_size(hwaddr addr,
590 uint64_t *value,
591 unsigned size,
592 unsigned access_size_min,
593 unsigned access_size_max,
594 MemTxResult (*access_fn)
595 (MemoryRegion *mr,
596 hwaddr addr,
597 uint64_t *value,
598 unsigned size,
599 unsigned shift,
600 uint64_t mask,
601 MemTxAttrs attrs),
602 MemoryRegion *mr,
603 MemTxAttrs attrs)
604 {
605 uint64_t access_mask;
606 unsigned access_size;
607 unsigned i;
608 MemTxResult r = MEMTX_OK;
609
610 if (!access_size_min) {
611 access_size_min = 1;
612 }
613 if (!access_size_max) {
614 access_size_max = 4;
615 }
616
617 /* FIXME: support unaligned access? */
618 access_size = MAX(MIN(size, access_size_max), access_size_min);
619 access_mask = -1ULL >> (64 - access_size * 8);
620 if (memory_region_big_endian(mr)) {
621 for (i = 0; i < size; i += access_size) {
622 r |= access_fn(mr, addr + i, value, access_size,
623 (size - access_size - i) * 8, access_mask, attrs);
624 }
625 } else {
626 for (i = 0; i < size; i += access_size) {
627 r |= access_fn(mr, addr + i, value, access_size, i * 8,
628 access_mask, attrs);
629 }
630 }
631 return r;
632 }
633
634 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
635 {
636 AddressSpace *as;
637
638 while (mr->container) {
639 mr = mr->container;
640 }
641 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
642 if (mr == as->root) {
643 return as;
644 }
645 }
646 return NULL;
647 }
648
649 /* Render a memory region into the global view. Ranges in @view obscure
650 * ranges in @mr.
651 */
652 static void render_memory_region(FlatView *view,
653 MemoryRegion *mr,
654 Int128 base,
655 AddrRange clip,
656 bool readonly)
657 {
658 MemoryRegion *subregion;
659 unsigned i;
660 hwaddr offset_in_region;
661 Int128 remain;
662 Int128 now;
663 FlatRange fr;
664 AddrRange tmp;
665
666 if (!mr->enabled) {
667 return;
668 }
669
670 int128_addto(&base, int128_make64(mr->addr));
671 readonly |= mr->readonly;
672
673 tmp = addrrange_make(base, mr->size);
674
675 if (!addrrange_intersects(tmp, clip)) {
676 return;
677 }
678
679 clip = addrrange_intersection(tmp, clip);
680
681 if (mr->alias) {
682 int128_subfrom(&base, int128_make64(mr->alias->addr));
683 int128_subfrom(&base, int128_make64(mr->alias_offset));
684 render_memory_region(view, mr->alias, base, clip, readonly);
685 return;
686 }
687
688 /* Render subregions in priority order. */
689 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
690 render_memory_region(view, subregion, base, clip, readonly);
691 }
692
693 if (!mr->terminates) {
694 return;
695 }
696
697 offset_in_region = int128_get64(int128_sub(clip.start, base));
698 base = clip.start;
699 remain = clip.size;
700
701 fr.mr = mr;
702 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
703 fr.romd_mode = mr->romd_mode;
704 fr.readonly = readonly;
705
706 /* Render the region itself into any gaps left by the current view. */
707 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
708 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
709 continue;
710 }
711 if (int128_lt(base, view->ranges[i].addr.start)) {
712 now = int128_min(remain,
713 int128_sub(view->ranges[i].addr.start, base));
714 fr.offset_in_region = offset_in_region;
715 fr.addr = addrrange_make(base, now);
716 flatview_insert(view, i, &fr);
717 ++i;
718 int128_addto(&base, now);
719 offset_in_region += int128_get64(now);
720 int128_subfrom(&remain, now);
721 }
722 now = int128_sub(int128_min(int128_add(base, remain),
723 addrrange_end(view->ranges[i].addr)),
724 base);
725 int128_addto(&base, now);
726 offset_in_region += int128_get64(now);
727 int128_subfrom(&remain, now);
728 }
729 if (int128_nz(remain)) {
730 fr.offset_in_region = offset_in_region;
731 fr.addr = addrrange_make(base, remain);
732 flatview_insert(view, i, &fr);
733 }
734 }
735
736 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
737 {
738 while (mr->enabled) {
739 if (mr->alias) {
740 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
741 /* The alias is included in its entirety. Use it as
742 * the "real" root, so that we can share more FlatViews.
743 */
744 mr = mr->alias;
745 continue;
746 }
747 } else if (!mr->terminates) {
748 unsigned int found = 0;
749 MemoryRegion *child, *next = NULL;
750 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
751 if (child->enabled) {
752 if (++found > 1) {
753 next = NULL;
754 break;
755 }
756 if (!child->addr && int128_ge(mr->size, child->size)) {
757 /* A child is included in its entirety. If it's the only
758 * enabled one, use it in the hope of finding an alias down the
759 * way. This will also let us share FlatViews.
760 */
761 next = child;
762 }
763 }
764 }
765 if (found == 0) {
766 return NULL;
767 }
768 if (next) {
769 mr = next;
770 continue;
771 }
772 }
773
774 return mr;
775 }
776
777 return NULL;
778 }
779
780 /* Render a memory topology into a list of disjoint absolute ranges. */
781 static FlatView *generate_memory_topology(MemoryRegion *mr)
782 {
783 int i;
784 FlatView *view;
785
786 view = flatview_new(mr);
787
788 if (mr) {
789 render_memory_region(view, mr, int128_zero(),
790 addrrange_make(int128_zero(), int128_2_64()), false);
791 }
792 flatview_simplify(view);
793
794 view->dispatch = address_space_dispatch_new(view);
795 for (i = 0; i < view->nr; i++) {
796 MemoryRegionSection mrs =
797 section_from_flat_range(&view->ranges[i], view);
798 flatview_add_to_dispatch(view, &mrs);
799 }
800 address_space_dispatch_compact(view->dispatch);
801 g_hash_table_replace(flat_views, mr, view);
802
803 return view;
804 }
805
806 static void address_space_add_del_ioeventfds(AddressSpace *as,
807 MemoryRegionIoeventfd *fds_new,
808 unsigned fds_new_nb,
809 MemoryRegionIoeventfd *fds_old,
810 unsigned fds_old_nb)
811 {
812 unsigned iold, inew;
813 MemoryRegionIoeventfd *fd;
814 MemoryRegionSection section;
815
816 /* Generate a symmetric difference of the old and new fd sets, adding
817 * and deleting as necessary.
818 */
819
820 iold = inew = 0;
821 while (iold < fds_old_nb || inew < fds_new_nb) {
822 if (iold < fds_old_nb
823 && (inew == fds_new_nb
824 || memory_region_ioeventfd_before(fds_old[iold],
825 fds_new[inew]))) {
826 fd = &fds_old[iold];
827 section = (MemoryRegionSection) {
828 .fv = address_space_to_flatview(as),
829 .offset_within_address_space = int128_get64(fd->addr.start),
830 .size = fd->addr.size,
831 };
832 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
833 fd->match_data, fd->data, fd->e);
834 ++iold;
835 } else if (inew < fds_new_nb
836 && (iold == fds_old_nb
837 || memory_region_ioeventfd_before(fds_new[inew],
838 fds_old[iold]))) {
839 fd = &fds_new[inew];
840 section = (MemoryRegionSection) {
841 .fv = address_space_to_flatview(as),
842 .offset_within_address_space = int128_get64(fd->addr.start),
843 .size = fd->addr.size,
844 };
845 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
846 fd->match_data, fd->data, fd->e);
847 ++inew;
848 } else {
849 ++iold;
850 ++inew;
851 }
852 }
853 }
854
855 static FlatView *address_space_get_flatview(AddressSpace *as)
856 {
857 FlatView *view;
858
859 rcu_read_lock();
860 do {
861 view = address_space_to_flatview(as);
862 /* If somebody has replaced as->current_map concurrently,
863 * flatview_ref returns false.
864 */
865 } while (!flatview_ref(view));
866 rcu_read_unlock();
867 return view;
868 }
869
870 static void address_space_update_ioeventfds(AddressSpace *as)
871 {
872 FlatView *view;
873 FlatRange *fr;
874 unsigned ioeventfd_nb = 0;
875 MemoryRegionIoeventfd *ioeventfds = NULL;
876 AddrRange tmp;
877 unsigned i;
878
879 view = address_space_get_flatview(as);
880 FOR_EACH_FLAT_RANGE(fr, view) {
881 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
882 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
883 int128_sub(fr->addr.start,
884 int128_make64(fr->offset_in_region)));
885 if (addrrange_intersects(fr->addr, tmp)) {
886 ++ioeventfd_nb;
887 ioeventfds = g_realloc(ioeventfds,
888 ioeventfd_nb * sizeof(*ioeventfds));
889 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
890 ioeventfds[ioeventfd_nb-1].addr = tmp;
891 }
892 }
893 }
894
895 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
896 as->ioeventfds, as->ioeventfd_nb);
897
898 g_free(as->ioeventfds);
899 as->ioeventfds = ioeventfds;
900 as->ioeventfd_nb = ioeventfd_nb;
901 flatview_unref(view);
902 }
903
904 static void address_space_update_topology_pass(AddressSpace *as,
905 const FlatView *old_view,
906 const FlatView *new_view,
907 bool adding)
908 {
909 unsigned iold, inew;
910 FlatRange *frold, *frnew;
911
912 /* Generate a symmetric difference of the old and new memory maps.
913 * Kill ranges in the old map, and instantiate ranges in the new map.
914 */
915 iold = inew = 0;
916 while (iold < old_view->nr || inew < new_view->nr) {
917 if (iold < old_view->nr) {
918 frold = &old_view->ranges[iold];
919 } else {
920 frold = NULL;
921 }
922 if (inew < new_view->nr) {
923 frnew = &new_view->ranges[inew];
924 } else {
925 frnew = NULL;
926 }
927
928 if (frold
929 && (!frnew
930 || int128_lt(frold->addr.start, frnew->addr.start)
931 || (int128_eq(frold->addr.start, frnew->addr.start)
932 && !flatrange_equal(frold, frnew)))) {
933 /* In old but not in new, or in both but attributes changed. */
934
935 if (!adding) {
936 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
937 }
938
939 ++iold;
940 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
941 /* In both and unchanged (except logging may have changed) */
942
943 if (adding) {
944 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
945 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
946 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
947 frold->dirty_log_mask,
948 frnew->dirty_log_mask);
949 }
950 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
951 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
952 frold->dirty_log_mask,
953 frnew->dirty_log_mask);
954 }
955 }
956
957 ++iold;
958 ++inew;
959 } else {
960 /* In new */
961
962 if (adding) {
963 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
964 }
965
966 ++inew;
967 }
968 }
969 }
970
971 static void flatviews_init(void)
972 {
973 static FlatView *empty_view;
974
975 if (flat_views) {
976 return;
977 }
978
979 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
980 (GDestroyNotify) flatview_unref);
981 if (!empty_view) {
982 empty_view = generate_memory_topology(NULL);
983 /* We keep it alive forever in the global variable. */
984 flatview_ref(empty_view);
985 } else {
986 g_hash_table_replace(flat_views, NULL, empty_view);
987 flatview_ref(empty_view);
988 }
989 }
990
991 static void flatviews_reset(void)
992 {
993 AddressSpace *as;
994
995 if (flat_views) {
996 g_hash_table_unref(flat_views);
997 flat_views = NULL;
998 }
999 flatviews_init();
1000
1001 /* Render unique FVs */
1002 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1003 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1004
1005 if (g_hash_table_lookup(flat_views, physmr)) {
1006 continue;
1007 }
1008
1009 generate_memory_topology(physmr);
1010 }
1011 }
1012
1013 static void address_space_set_flatview(AddressSpace *as)
1014 {
1015 FlatView *old_view = address_space_to_flatview(as);
1016 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1017 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1018
1019 assert(new_view);
1020
1021 if (old_view == new_view) {
1022 return;
1023 }
1024
1025 if (old_view) {
1026 flatview_ref(old_view);
1027 }
1028
1029 flatview_ref(new_view);
1030
1031 if (!QTAILQ_EMPTY(&as->listeners)) {
1032 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1033
1034 if (!old_view2) {
1035 old_view2 = &tmpview;
1036 }
1037 address_space_update_topology_pass(as, old_view2, new_view, false);
1038 address_space_update_topology_pass(as, old_view2, new_view, true);
1039 }
1040
1041 /* Writes are protected by the BQL. */
1042 atomic_rcu_set(&as->current_map, new_view);
1043 if (old_view) {
1044 flatview_unref(old_view);
1045 }
1046
1047 /* Note that all the old MemoryRegions are still alive up to this
1048 * point. This relieves most MemoryListeners from the need to
1049 * ref/unref the MemoryRegions they get---unless they use them
1050 * outside the iothread mutex, in which case precise reference
1051 * counting is necessary.
1052 */
1053 if (old_view) {
1054 flatview_unref(old_view);
1055 }
1056 }
1057
1058 static void address_space_update_topology(AddressSpace *as)
1059 {
1060 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1061
1062 flatviews_init();
1063 if (!g_hash_table_lookup(flat_views, physmr)) {
1064 generate_memory_topology(physmr);
1065 }
1066 address_space_set_flatview(as);
1067 }
1068
1069 void memory_region_transaction_begin(void)
1070 {
1071 qemu_flush_coalesced_mmio_buffer();
1072 ++memory_region_transaction_depth;
1073 }
1074
1075 void memory_region_transaction_commit(void)
1076 {
1077 AddressSpace *as;
1078
1079 assert(memory_region_transaction_depth);
1080 assert(qemu_mutex_iothread_locked());
1081
1082 --memory_region_transaction_depth;
1083 if (!memory_region_transaction_depth) {
1084 if (memory_region_update_pending) {
1085 flatviews_reset();
1086
1087 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1088
1089 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1090 address_space_set_flatview(as);
1091 address_space_update_ioeventfds(as);
1092 }
1093 memory_region_update_pending = false;
1094 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1095 } else if (ioeventfd_update_pending) {
1096 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1097 address_space_update_ioeventfds(as);
1098 }
1099 ioeventfd_update_pending = false;
1100 }
1101 }
1102 }
1103
1104 static void memory_region_destructor_none(MemoryRegion *mr)
1105 {
1106 }
1107
1108 static void memory_region_destructor_ram(MemoryRegion *mr)
1109 {
1110 qemu_ram_free(mr->ram_block);
1111 }
1112
1113 static bool memory_region_need_escape(char c)
1114 {
1115 return c == '/' || c == '[' || c == '\\' || c == ']';
1116 }
1117
1118 static char *memory_region_escape_name(const char *name)
1119 {
1120 const char *p;
1121 char *escaped, *q;
1122 uint8_t c;
1123 size_t bytes = 0;
1124
1125 for (p = name; *p; p++) {
1126 bytes += memory_region_need_escape(*p) ? 4 : 1;
1127 }
1128 if (bytes == p - name) {
1129 return g_memdup(name, bytes + 1);
1130 }
1131
1132 escaped = g_malloc(bytes + 1);
1133 for (p = name, q = escaped; *p; p++) {
1134 c = *p;
1135 if (unlikely(memory_region_need_escape(c))) {
1136 *q++ = '\\';
1137 *q++ = 'x';
1138 *q++ = "0123456789abcdef"[c >> 4];
1139 c = "0123456789abcdef"[c & 15];
1140 }
1141 *q++ = c;
1142 }
1143 *q = 0;
1144 return escaped;
1145 }
1146
1147 static void memory_region_do_init(MemoryRegion *mr,
1148 Object *owner,
1149 const char *name,
1150 uint64_t size)
1151 {
1152 mr->size = int128_make64(size);
1153 if (size == UINT64_MAX) {
1154 mr->size = int128_2_64();
1155 }
1156 mr->name = g_strdup(name);
1157 mr->owner = owner;
1158 mr->ram_block = NULL;
1159
1160 if (name) {
1161 char *escaped_name = memory_region_escape_name(name);
1162 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1163
1164 if (!owner) {
1165 owner = container_get(qdev_get_machine(), "/unattached");
1166 }
1167
1168 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1169 object_unref(OBJECT(mr));
1170 g_free(name_array);
1171 g_free(escaped_name);
1172 }
1173 }
1174
1175 void memory_region_init(MemoryRegion *mr,
1176 Object *owner,
1177 const char *name,
1178 uint64_t size)
1179 {
1180 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1181 memory_region_do_init(mr, owner, name, size);
1182 }
1183
1184 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1185 void *opaque, Error **errp)
1186 {
1187 MemoryRegion *mr = MEMORY_REGION(obj);
1188 uint64_t value = mr->addr;
1189
1190 visit_type_uint64(v, name, &value, errp);
1191 }
1192
1193 static void memory_region_get_container(Object *obj, Visitor *v,
1194 const char *name, void *opaque,
1195 Error **errp)
1196 {
1197 MemoryRegion *mr = MEMORY_REGION(obj);
1198 gchar *path = (gchar *)"";
1199
1200 if (mr->container) {
1201 path = object_get_canonical_path(OBJECT(mr->container));
1202 }
1203 visit_type_str(v, name, &path, errp);
1204 if (mr->container) {
1205 g_free(path);
1206 }
1207 }
1208
1209 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1210 const char *part)
1211 {
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213
1214 return OBJECT(mr->container);
1215 }
1216
1217 static void memory_region_get_priority(Object *obj, Visitor *v,
1218 const char *name, void *opaque,
1219 Error **errp)
1220 {
1221 MemoryRegion *mr = MEMORY_REGION(obj);
1222 int32_t value = mr->priority;
1223
1224 visit_type_int32(v, name, &value, errp);
1225 }
1226
1227 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1228 void *opaque, Error **errp)
1229 {
1230 MemoryRegion *mr = MEMORY_REGION(obj);
1231 uint64_t value = memory_region_size(mr);
1232
1233 visit_type_uint64(v, name, &value, errp);
1234 }
1235
1236 static void memory_region_initfn(Object *obj)
1237 {
1238 MemoryRegion *mr = MEMORY_REGION(obj);
1239 ObjectProperty *op;
1240
1241 mr->ops = &unassigned_mem_ops;
1242 mr->enabled = true;
1243 mr->romd_mode = true;
1244 mr->global_locking = true;
1245 mr->destructor = memory_region_destructor_none;
1246 QTAILQ_INIT(&mr->subregions);
1247 QTAILQ_INIT(&mr->coalesced);
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL, &error_abort);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add(OBJECT(mr), "addr", "uint64",
1257 memory_region_get_addr,
1258 NULL, /* memory_region_set_addr */
1259 NULL, NULL, &error_abort);
1260 object_property_add(OBJECT(mr), "priority", "uint32",
1261 memory_region_get_priority,
1262 NULL, /* memory_region_set_priority */
1263 NULL, NULL, &error_abort);
1264 object_property_add(OBJECT(mr), "size", "uint64",
1265 memory_region_get_size,
1266 NULL, /* memory_region_set_size, */
1267 NULL, NULL, &error_abort);
1268 }
1269
1270 static void iommu_memory_region_initfn(Object *obj)
1271 {
1272 MemoryRegion *mr = MEMORY_REGION(obj);
1273
1274 mr->is_iommu = true;
1275 }
1276
1277 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1278 unsigned size)
1279 {
1280 #ifdef DEBUG_UNASSIGNED
1281 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1282 #endif
1283 if (current_cpu != NULL) {
1284 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
1285 }
1286 return 0;
1287 }
1288
1289 static void unassigned_mem_write(void *opaque, hwaddr addr,
1290 uint64_t val, unsigned size)
1291 {
1292 #ifdef DEBUG_UNASSIGNED
1293 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1294 #endif
1295 if (current_cpu != NULL) {
1296 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1297 }
1298 }
1299
1300 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1301 unsigned size, bool is_write)
1302 {
1303 return false;
1304 }
1305
1306 const MemoryRegionOps unassigned_mem_ops = {
1307 .valid.accepts = unassigned_mem_accepts,
1308 .endianness = DEVICE_NATIVE_ENDIAN,
1309 };
1310
1311 static uint64_t memory_region_ram_device_read(void *opaque,
1312 hwaddr addr, unsigned size)
1313 {
1314 MemoryRegion *mr = opaque;
1315 uint64_t data = (uint64_t)~0;
1316
1317 switch (size) {
1318 case 1:
1319 data = *(uint8_t *)(mr->ram_block->host + addr);
1320 break;
1321 case 2:
1322 data = *(uint16_t *)(mr->ram_block->host + addr);
1323 break;
1324 case 4:
1325 data = *(uint32_t *)(mr->ram_block->host + addr);
1326 break;
1327 case 8:
1328 data = *(uint64_t *)(mr->ram_block->host + addr);
1329 break;
1330 }
1331
1332 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1333
1334 return data;
1335 }
1336
1337 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1338 uint64_t data, unsigned size)
1339 {
1340 MemoryRegion *mr = opaque;
1341
1342 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1343
1344 switch (size) {
1345 case 1:
1346 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1347 break;
1348 case 2:
1349 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1350 break;
1351 case 4:
1352 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1353 break;
1354 case 8:
1355 *(uint64_t *)(mr->ram_block->host + addr) = data;
1356 break;
1357 }
1358 }
1359
1360 static const MemoryRegionOps ram_device_mem_ops = {
1361 .read = memory_region_ram_device_read,
1362 .write = memory_region_ram_device_write,
1363 .endianness = DEVICE_HOST_ENDIAN,
1364 .valid = {
1365 .min_access_size = 1,
1366 .max_access_size = 8,
1367 .unaligned = true,
1368 },
1369 .impl = {
1370 .min_access_size = 1,
1371 .max_access_size = 8,
1372 .unaligned = true,
1373 },
1374 };
1375
1376 bool memory_region_access_valid(MemoryRegion *mr,
1377 hwaddr addr,
1378 unsigned size,
1379 bool is_write)
1380 {
1381 int access_size_min, access_size_max;
1382 int access_size, i;
1383
1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 return false;
1386 }
1387
1388 if (!mr->ops->valid.accepts) {
1389 return true;
1390 }
1391
1392 access_size_min = mr->ops->valid.min_access_size;
1393 if (!mr->ops->valid.min_access_size) {
1394 access_size_min = 1;
1395 }
1396
1397 access_size_max = mr->ops->valid.max_access_size;
1398 if (!mr->ops->valid.max_access_size) {
1399 access_size_max = 4;
1400 }
1401
1402 access_size = MAX(MIN(size, access_size_max), access_size_min);
1403 for (i = 0; i < size; i += access_size) {
1404 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1405 is_write)) {
1406 return false;
1407 }
1408 }
1409
1410 return true;
1411 }
1412
1413 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1414 hwaddr addr,
1415 uint64_t *pval,
1416 unsigned size,
1417 MemTxAttrs attrs)
1418 {
1419 *pval = 0;
1420
1421 if (mr->ops->read) {
1422 return access_with_adjusted_size(addr, pval, size,
1423 mr->ops->impl.min_access_size,
1424 mr->ops->impl.max_access_size,
1425 memory_region_read_accessor,
1426 mr, attrs);
1427 } else if (mr->ops->read_with_attrs) {
1428 return access_with_adjusted_size(addr, pval, size,
1429 mr->ops->impl.min_access_size,
1430 mr->ops->impl.max_access_size,
1431 memory_region_read_with_attrs_accessor,
1432 mr, attrs);
1433 } else {
1434 return access_with_adjusted_size(addr, pval, size, 1, 4,
1435 memory_region_oldmmio_read_accessor,
1436 mr, attrs);
1437 }
1438 }
1439
1440 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1441 hwaddr addr,
1442 uint64_t *pval,
1443 unsigned size,
1444 MemTxAttrs attrs)
1445 {
1446 MemTxResult r;
1447
1448 if (!memory_region_access_valid(mr, addr, size, false)) {
1449 *pval = unassigned_mem_read(mr, addr, size);
1450 return MEMTX_DECODE_ERROR;
1451 }
1452
1453 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1454 adjust_endianness(mr, pval, size);
1455 return r;
1456 }
1457
1458 /* Return true if an eventfd was signalled */
1459 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1460 hwaddr addr,
1461 uint64_t data,
1462 unsigned size,
1463 MemTxAttrs attrs)
1464 {
1465 MemoryRegionIoeventfd ioeventfd = {
1466 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1467 .data = data,
1468 };
1469 unsigned i;
1470
1471 for (i = 0; i < mr->ioeventfd_nb; i++) {
1472 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1473 ioeventfd.e = mr->ioeventfds[i].e;
1474
1475 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1476 event_notifier_set(ioeventfd.e);
1477 return true;
1478 }
1479 }
1480
1481 return false;
1482 }
1483
1484 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1485 hwaddr addr,
1486 uint64_t data,
1487 unsigned size,
1488 MemTxAttrs attrs)
1489 {
1490 if (!memory_region_access_valid(mr, addr, size, true)) {
1491 unassigned_mem_write(mr, addr, data, size);
1492 return MEMTX_DECODE_ERROR;
1493 }
1494
1495 adjust_endianness(mr, &data, size);
1496
1497 if ((!kvm_eventfds_enabled()) &&
1498 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1499 return MEMTX_OK;
1500 }
1501
1502 if (mr->ops->write) {
1503 return access_with_adjusted_size(addr, &data, size,
1504 mr->ops->impl.min_access_size,
1505 mr->ops->impl.max_access_size,
1506 memory_region_write_accessor, mr,
1507 attrs);
1508 } else if (mr->ops->write_with_attrs) {
1509 return
1510 access_with_adjusted_size(addr, &data, size,
1511 mr->ops->impl.min_access_size,
1512 mr->ops->impl.max_access_size,
1513 memory_region_write_with_attrs_accessor,
1514 mr, attrs);
1515 } else {
1516 return access_with_adjusted_size(addr, &data, size, 1, 4,
1517 memory_region_oldmmio_write_accessor,
1518 mr, attrs);
1519 }
1520 }
1521
1522 void memory_region_init_io(MemoryRegion *mr,
1523 Object *owner,
1524 const MemoryRegionOps *ops,
1525 void *opaque,
1526 const char *name,
1527 uint64_t size)
1528 {
1529 memory_region_init(mr, owner, name, size);
1530 mr->ops = ops ? ops : &unassigned_mem_ops;
1531 mr->opaque = opaque;
1532 mr->terminates = true;
1533 }
1534
1535 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1536 Object *owner,
1537 const char *name,
1538 uint64_t size,
1539 Error **errp)
1540 {
1541 memory_region_init(mr, owner, name, size);
1542 mr->ram = true;
1543 mr->terminates = true;
1544 mr->destructor = memory_region_destructor_ram;
1545 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1546 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1547 }
1548
1549 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1550 Object *owner,
1551 const char *name,
1552 uint64_t size,
1553 uint64_t max_size,
1554 void (*resized)(const char*,
1555 uint64_t length,
1556 void *host),
1557 Error **errp)
1558 {
1559 memory_region_init(mr, owner, name, size);
1560 mr->ram = true;
1561 mr->terminates = true;
1562 mr->destructor = memory_region_destructor_ram;
1563 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1564 mr, errp);
1565 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1566 }
1567
1568 #ifdef __linux__
1569 void memory_region_init_ram_from_file(MemoryRegion *mr,
1570 struct Object *owner,
1571 const char *name,
1572 uint64_t size,
1573 uint64_t align,
1574 bool share,
1575 const char *path,
1576 Error **errp)
1577 {
1578 memory_region_init(mr, owner, name, size);
1579 mr->ram = true;
1580 mr->terminates = true;
1581 mr->destructor = memory_region_destructor_ram;
1582 mr->align = align;
1583 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
1584 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1585 }
1586
1587 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1588 struct Object *owner,
1589 const char *name,
1590 uint64_t size,
1591 bool share,
1592 int fd,
1593 Error **errp)
1594 {
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1600 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1601 }
1602 #endif
1603
1604 void memory_region_init_ram_ptr(MemoryRegion *mr,
1605 Object *owner,
1606 const char *name,
1607 uint64_t size,
1608 void *ptr)
1609 {
1610 memory_region_init(mr, owner, name, size);
1611 mr->ram = true;
1612 mr->terminates = true;
1613 mr->destructor = memory_region_destructor_ram;
1614 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1615
1616 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1617 assert(ptr != NULL);
1618 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1619 }
1620
1621 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1622 Object *owner,
1623 const char *name,
1624 uint64_t size,
1625 void *ptr)
1626 {
1627 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1628 mr->ram_device = true;
1629 mr->ops = &ram_device_mem_ops;
1630 mr->opaque = mr;
1631 }
1632
1633 void memory_region_init_alias(MemoryRegion *mr,
1634 Object *owner,
1635 const char *name,
1636 MemoryRegion *orig,
1637 hwaddr offset,
1638 uint64_t size)
1639 {
1640 memory_region_init(mr, owner, name, size);
1641 mr->alias = orig;
1642 mr->alias_offset = offset;
1643 }
1644
1645 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1646 struct Object *owner,
1647 const char *name,
1648 uint64_t size,
1649 Error **errp)
1650 {
1651 memory_region_init(mr, owner, name, size);
1652 mr->ram = true;
1653 mr->readonly = true;
1654 mr->terminates = true;
1655 mr->destructor = memory_region_destructor_ram;
1656 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1657 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1658 }
1659
1660 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1661 Object *owner,
1662 const MemoryRegionOps *ops,
1663 void *opaque,
1664 const char *name,
1665 uint64_t size,
1666 Error **errp)
1667 {
1668 assert(ops);
1669 memory_region_init(mr, owner, name, size);
1670 mr->ops = ops;
1671 mr->opaque = opaque;
1672 mr->terminates = true;
1673 mr->rom_device = true;
1674 mr->destructor = memory_region_destructor_ram;
1675 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1676 }
1677
1678 void memory_region_init_iommu(void *_iommu_mr,
1679 size_t instance_size,
1680 const char *mrtypename,
1681 Object *owner,
1682 const char *name,
1683 uint64_t size)
1684 {
1685 struct IOMMUMemoryRegion *iommu_mr;
1686 struct MemoryRegion *mr;
1687
1688 object_initialize(_iommu_mr, instance_size, mrtypename);
1689 mr = MEMORY_REGION(_iommu_mr);
1690 memory_region_do_init(mr, owner, name, size);
1691 iommu_mr = IOMMU_MEMORY_REGION(mr);
1692 mr->terminates = true; /* then re-forwards */
1693 QLIST_INIT(&iommu_mr->iommu_notify);
1694 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1695 }
1696
1697 static void memory_region_finalize(Object *obj)
1698 {
1699 MemoryRegion *mr = MEMORY_REGION(obj);
1700
1701 assert(!mr->container);
1702
1703 /* We know the region is not visible in any address space (it
1704 * does not have a container and cannot be a root either because
1705 * it has no references, so we can blindly clear mr->enabled.
1706 * memory_region_set_enabled instead could trigger a transaction
1707 * and cause an infinite loop.
1708 */
1709 mr->enabled = false;
1710 memory_region_transaction_begin();
1711 while (!QTAILQ_EMPTY(&mr->subregions)) {
1712 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1713 memory_region_del_subregion(mr, subregion);
1714 }
1715 memory_region_transaction_commit();
1716
1717 mr->destructor(mr);
1718 memory_region_clear_coalescing(mr);
1719 g_free((char *)mr->name);
1720 g_free(mr->ioeventfds);
1721 }
1722
1723 Object *memory_region_owner(MemoryRegion *mr)
1724 {
1725 Object *obj = OBJECT(mr);
1726 return obj->parent;
1727 }
1728
1729 void memory_region_ref(MemoryRegion *mr)
1730 {
1731 /* MMIO callbacks most likely will access data that belongs
1732 * to the owner, hence the need to ref/unref the owner whenever
1733 * the memory region is in use.
1734 *
1735 * The memory region is a child of its owner. As long as the
1736 * owner doesn't call unparent itself on the memory region,
1737 * ref-ing the owner will also keep the memory region alive.
1738 * Memory regions without an owner are supposed to never go away;
1739 * we do not ref/unref them because it slows down DMA sensibly.
1740 */
1741 if (mr && mr->owner) {
1742 object_ref(mr->owner);
1743 }
1744 }
1745
1746 void memory_region_unref(MemoryRegion *mr)
1747 {
1748 if (mr && mr->owner) {
1749 object_unref(mr->owner);
1750 }
1751 }
1752
1753 uint64_t memory_region_size(MemoryRegion *mr)
1754 {
1755 if (int128_eq(mr->size, int128_2_64())) {
1756 return UINT64_MAX;
1757 }
1758 return int128_get64(mr->size);
1759 }
1760
1761 const char *memory_region_name(const MemoryRegion *mr)
1762 {
1763 if (!mr->name) {
1764 ((MemoryRegion *)mr)->name =
1765 object_get_canonical_path_component(OBJECT(mr));
1766 }
1767 return mr->name;
1768 }
1769
1770 bool memory_region_is_ram_device(MemoryRegion *mr)
1771 {
1772 return mr->ram_device;
1773 }
1774
1775 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1776 {
1777 uint8_t mask = mr->dirty_log_mask;
1778 if (global_dirty_log && mr->ram_block) {
1779 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1780 }
1781 return mask;
1782 }
1783
1784 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1785 {
1786 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1787 }
1788
1789 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1790 {
1791 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1792 IOMMUNotifier *iommu_notifier;
1793 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1794
1795 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1796 flags |= iommu_notifier->notifier_flags;
1797 }
1798
1799 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1800 imrc->notify_flag_changed(iommu_mr,
1801 iommu_mr->iommu_notify_flags,
1802 flags);
1803 }
1804
1805 iommu_mr->iommu_notify_flags = flags;
1806 }
1807
1808 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1809 IOMMUNotifier *n)
1810 {
1811 IOMMUMemoryRegion *iommu_mr;
1812
1813 if (mr->alias) {
1814 memory_region_register_iommu_notifier(mr->alias, n);
1815 return;
1816 }
1817
1818 /* We need to register for at least one bitfield */
1819 iommu_mr = IOMMU_MEMORY_REGION(mr);
1820 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1821 assert(n->start <= n->end);
1822 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1823 memory_region_update_iommu_notify_flags(iommu_mr);
1824 }
1825
1826 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1827 {
1828 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1829
1830 if (imrc->get_min_page_size) {
1831 return imrc->get_min_page_size(iommu_mr);
1832 }
1833 return TARGET_PAGE_SIZE;
1834 }
1835
1836 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1837 {
1838 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1839 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1840 hwaddr addr, granularity;
1841 IOMMUTLBEntry iotlb;
1842
1843 /* If the IOMMU has its own replay callback, override */
1844 if (imrc->replay) {
1845 imrc->replay(iommu_mr, n);
1846 return;
1847 }
1848
1849 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1850
1851 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1852 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
1853 if (iotlb.perm != IOMMU_NONE) {
1854 n->notify(n, &iotlb);
1855 }
1856
1857 /* if (2^64 - MR size) < granularity, it's possible to get an
1858 * infinite loop here. This should catch such a wraparound */
1859 if ((addr + granularity) < addr) {
1860 break;
1861 }
1862 }
1863 }
1864
1865 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1866 {
1867 IOMMUNotifier *notifier;
1868
1869 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1870 memory_region_iommu_replay(iommu_mr, notifier);
1871 }
1872 }
1873
1874 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1875 IOMMUNotifier *n)
1876 {
1877 IOMMUMemoryRegion *iommu_mr;
1878
1879 if (mr->alias) {
1880 memory_region_unregister_iommu_notifier(mr->alias, n);
1881 return;
1882 }
1883 QLIST_REMOVE(n, node);
1884 iommu_mr = IOMMU_MEMORY_REGION(mr);
1885 memory_region_update_iommu_notify_flags(iommu_mr);
1886 }
1887
1888 void memory_region_notify_one(IOMMUNotifier *notifier,
1889 IOMMUTLBEntry *entry)
1890 {
1891 IOMMUNotifierFlag request_flags;
1892
1893 /*
1894 * Skip the notification if the notification does not overlap
1895 * with registered range.
1896 */
1897 if (notifier->start > entry->iova + entry->addr_mask ||
1898 notifier->end < entry->iova) {
1899 return;
1900 }
1901
1902 if (entry->perm & IOMMU_RW) {
1903 request_flags = IOMMU_NOTIFIER_MAP;
1904 } else {
1905 request_flags = IOMMU_NOTIFIER_UNMAP;
1906 }
1907
1908 if (notifier->notifier_flags & request_flags) {
1909 notifier->notify(notifier, entry);
1910 }
1911 }
1912
1913 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1914 IOMMUTLBEntry entry)
1915 {
1916 IOMMUNotifier *iommu_notifier;
1917
1918 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1919
1920 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1921 memory_region_notify_one(iommu_notifier, &entry);
1922 }
1923 }
1924
1925 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1926 {
1927 uint8_t mask = 1 << client;
1928 uint8_t old_logging;
1929
1930 assert(client == DIRTY_MEMORY_VGA);
1931 old_logging = mr->vga_logging_count;
1932 mr->vga_logging_count += log ? 1 : -1;
1933 if (!!old_logging == !!mr->vga_logging_count) {
1934 return;
1935 }
1936
1937 memory_region_transaction_begin();
1938 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1939 memory_region_update_pending |= mr->enabled;
1940 memory_region_transaction_commit();
1941 }
1942
1943 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1944 hwaddr size, unsigned client)
1945 {
1946 assert(mr->ram_block);
1947 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1948 size, client);
1949 }
1950
1951 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1952 hwaddr size)
1953 {
1954 assert(mr->ram_block);
1955 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1956 size,
1957 memory_region_get_dirty_log_mask(mr));
1958 }
1959
1960 bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1961 hwaddr size, unsigned client)
1962 {
1963 assert(mr->ram_block);
1964 return cpu_physical_memory_test_and_clear_dirty(
1965 memory_region_get_ram_addr(mr) + addr, size, client);
1966 }
1967
1968 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1969 hwaddr addr,
1970 hwaddr size,
1971 unsigned client)
1972 {
1973 assert(mr->ram_block);
1974 return cpu_physical_memory_snapshot_and_clear_dirty(
1975 memory_region_get_ram_addr(mr) + addr, size, client);
1976 }
1977
1978 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1979 hwaddr addr, hwaddr size)
1980 {
1981 assert(mr->ram_block);
1982 return cpu_physical_memory_snapshot_get_dirty(snap,
1983 memory_region_get_ram_addr(mr) + addr, size);
1984 }
1985
1986 void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1987 {
1988 MemoryListener *listener;
1989 AddressSpace *as;
1990 FlatView *view;
1991 FlatRange *fr;
1992
1993 /* If the same address space has multiple log_sync listeners, we
1994 * visit that address space's FlatView multiple times. But because
1995 * log_sync listeners are rare, it's still cheaper than walking each
1996 * address space once.
1997 */
1998 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1999 if (!listener->log_sync) {
2000 continue;
2001 }
2002 as = listener->address_space;
2003 view = address_space_get_flatview(as);
2004 FOR_EACH_FLAT_RANGE(fr, view) {
2005 if (fr->mr == mr) {
2006 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2007 listener->log_sync(listener, &mrs);
2008 }
2009 }
2010 flatview_unref(view);
2011 }
2012 }
2013
2014 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2015 {
2016 if (mr->readonly != readonly) {
2017 memory_region_transaction_begin();
2018 mr->readonly = readonly;
2019 memory_region_update_pending |= mr->enabled;
2020 memory_region_transaction_commit();
2021 }
2022 }
2023
2024 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2025 {
2026 if (mr->romd_mode != romd_mode) {
2027 memory_region_transaction_begin();
2028 mr->romd_mode = romd_mode;
2029 memory_region_update_pending |= mr->enabled;
2030 memory_region_transaction_commit();
2031 }
2032 }
2033
2034 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2035 hwaddr size, unsigned client)
2036 {
2037 assert(mr->ram_block);
2038 cpu_physical_memory_test_and_clear_dirty(
2039 memory_region_get_ram_addr(mr) + addr, size, client);
2040 }
2041
2042 int memory_region_get_fd(MemoryRegion *mr)
2043 {
2044 int fd;
2045
2046 rcu_read_lock();
2047 while (mr->alias) {
2048 mr = mr->alias;
2049 }
2050 fd = mr->ram_block->fd;
2051 rcu_read_unlock();
2052
2053 return fd;
2054 }
2055
2056 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2057 {
2058 void *ptr;
2059 uint64_t offset = 0;
2060
2061 rcu_read_lock();
2062 while (mr->alias) {
2063 offset += mr->alias_offset;
2064 mr = mr->alias;
2065 }
2066 assert(mr->ram_block);
2067 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2068 rcu_read_unlock();
2069
2070 return ptr;
2071 }
2072
2073 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2074 {
2075 RAMBlock *block;
2076
2077 block = qemu_ram_block_from_host(ptr, false, offset);
2078 if (!block) {
2079 return NULL;
2080 }
2081
2082 return block->mr;
2083 }
2084
2085 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2086 {
2087 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2088 }
2089
2090 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2091 {
2092 assert(mr->ram_block);
2093
2094 qemu_ram_resize(mr->ram_block, newsize, errp);
2095 }
2096
2097 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2098 {
2099 FlatView *view;
2100 FlatRange *fr;
2101 CoalescedMemoryRange *cmr;
2102 AddrRange tmp;
2103 MemoryRegionSection section;
2104
2105 view = address_space_get_flatview(as);
2106 FOR_EACH_FLAT_RANGE(fr, view) {
2107 if (fr->mr == mr) {
2108 section = (MemoryRegionSection) {
2109 .fv = view,
2110 .offset_within_address_space = int128_get64(fr->addr.start),
2111 .size = fr->addr.size,
2112 };
2113
2114 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2115 int128_get64(fr->addr.start),
2116 int128_get64(fr->addr.size));
2117 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2118 tmp = addrrange_shift(cmr->addr,
2119 int128_sub(fr->addr.start,
2120 int128_make64(fr->offset_in_region)));
2121 if (!addrrange_intersects(tmp, fr->addr)) {
2122 continue;
2123 }
2124 tmp = addrrange_intersection(tmp, fr->addr);
2125 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2126 int128_get64(tmp.start),
2127 int128_get64(tmp.size));
2128 }
2129 }
2130 }
2131 flatview_unref(view);
2132 }
2133
2134 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2135 {
2136 AddressSpace *as;
2137
2138 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2139 memory_region_update_coalesced_range_as(mr, as);
2140 }
2141 }
2142
2143 void memory_region_set_coalescing(MemoryRegion *mr)
2144 {
2145 memory_region_clear_coalescing(mr);
2146 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2147 }
2148
2149 void memory_region_add_coalescing(MemoryRegion *mr,
2150 hwaddr offset,
2151 uint64_t size)
2152 {
2153 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2154
2155 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2156 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2157 memory_region_update_coalesced_range(mr);
2158 memory_region_set_flush_coalesced(mr);
2159 }
2160
2161 void memory_region_clear_coalescing(MemoryRegion *mr)
2162 {
2163 CoalescedMemoryRange *cmr;
2164 bool updated = false;
2165
2166 qemu_flush_coalesced_mmio_buffer();
2167 mr->flush_coalesced_mmio = false;
2168
2169 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2170 cmr = QTAILQ_FIRST(&mr->coalesced);
2171 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2172 g_free(cmr);
2173 updated = true;
2174 }
2175
2176 if (updated) {
2177 memory_region_update_coalesced_range(mr);
2178 }
2179 }
2180
2181 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2182 {
2183 mr->flush_coalesced_mmio = true;
2184 }
2185
2186 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2187 {
2188 qemu_flush_coalesced_mmio_buffer();
2189 if (QTAILQ_EMPTY(&mr->coalesced)) {
2190 mr->flush_coalesced_mmio = false;
2191 }
2192 }
2193
2194 void memory_region_clear_global_locking(MemoryRegion *mr)
2195 {
2196 mr->global_locking = false;
2197 }
2198
2199 static bool userspace_eventfd_warning;
2200
2201 void memory_region_add_eventfd(MemoryRegion *mr,
2202 hwaddr addr,
2203 unsigned size,
2204 bool match_data,
2205 uint64_t data,
2206 EventNotifier *e)
2207 {
2208 MemoryRegionIoeventfd mrfd = {
2209 .addr.start = int128_make64(addr),
2210 .addr.size = int128_make64(size),
2211 .match_data = match_data,
2212 .data = data,
2213 .e = e,
2214 };
2215 unsigned i;
2216
2217 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2218 userspace_eventfd_warning))) {
2219 userspace_eventfd_warning = true;
2220 error_report("Using eventfd without MMIO binding in KVM. "
2221 "Suboptimal performance expected");
2222 }
2223
2224 if (size) {
2225 adjust_endianness(mr, &mrfd.data, size);
2226 }
2227 memory_region_transaction_begin();
2228 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2229 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2230 break;
2231 }
2232 }
2233 ++mr->ioeventfd_nb;
2234 mr->ioeventfds = g_realloc(mr->ioeventfds,
2235 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2236 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2237 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2238 mr->ioeventfds[i] = mrfd;
2239 ioeventfd_update_pending |= mr->enabled;
2240 memory_region_transaction_commit();
2241 }
2242
2243 void memory_region_del_eventfd(MemoryRegion *mr,
2244 hwaddr addr,
2245 unsigned size,
2246 bool match_data,
2247 uint64_t data,
2248 EventNotifier *e)
2249 {
2250 MemoryRegionIoeventfd mrfd = {
2251 .addr.start = int128_make64(addr),
2252 .addr.size = int128_make64(size),
2253 .match_data = match_data,
2254 .data = data,
2255 .e = e,
2256 };
2257 unsigned i;
2258
2259 if (size) {
2260 adjust_endianness(mr, &mrfd.data, size);
2261 }
2262 memory_region_transaction_begin();
2263 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2264 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2265 break;
2266 }
2267 }
2268 assert(i != mr->ioeventfd_nb);
2269 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2270 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2271 --mr->ioeventfd_nb;
2272 mr->ioeventfds = g_realloc(mr->ioeventfds,
2273 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2274 ioeventfd_update_pending |= mr->enabled;
2275 memory_region_transaction_commit();
2276 }
2277
2278 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2279 {
2280 MemoryRegion *mr = subregion->container;
2281 MemoryRegion *other;
2282
2283 memory_region_transaction_begin();
2284
2285 memory_region_ref(subregion);
2286 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2287 if (subregion->priority >= other->priority) {
2288 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2289 goto done;
2290 }
2291 }
2292 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2293 done:
2294 memory_region_update_pending |= mr->enabled && subregion->enabled;
2295 memory_region_transaction_commit();
2296 }
2297
2298 static void memory_region_add_subregion_common(MemoryRegion *mr,
2299 hwaddr offset,
2300 MemoryRegion *subregion)
2301 {
2302 assert(!subregion->container);
2303 subregion->container = mr;
2304 subregion->addr = offset;
2305 memory_region_update_container_subregions(subregion);
2306 }
2307
2308 void memory_region_add_subregion(MemoryRegion *mr,
2309 hwaddr offset,
2310 MemoryRegion *subregion)
2311 {
2312 subregion->priority = 0;
2313 memory_region_add_subregion_common(mr, offset, subregion);
2314 }
2315
2316 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2317 hwaddr offset,
2318 MemoryRegion *subregion,
2319 int priority)
2320 {
2321 subregion->priority = priority;
2322 memory_region_add_subregion_common(mr, offset, subregion);
2323 }
2324
2325 void memory_region_del_subregion(MemoryRegion *mr,
2326 MemoryRegion *subregion)
2327 {
2328 memory_region_transaction_begin();
2329 assert(subregion->container == mr);
2330 subregion->container = NULL;
2331 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2332 memory_region_unref(subregion);
2333 memory_region_update_pending |= mr->enabled && subregion->enabled;
2334 memory_region_transaction_commit();
2335 }
2336
2337 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2338 {
2339 if (enabled == mr->enabled) {
2340 return;
2341 }
2342 memory_region_transaction_begin();
2343 mr->enabled = enabled;
2344 memory_region_update_pending = true;
2345 memory_region_transaction_commit();
2346 }
2347
2348 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2349 {
2350 Int128 s = int128_make64(size);
2351
2352 if (size == UINT64_MAX) {
2353 s = int128_2_64();
2354 }
2355 if (int128_eq(s, mr->size)) {
2356 return;
2357 }
2358 memory_region_transaction_begin();
2359 mr->size = s;
2360 memory_region_update_pending = true;
2361 memory_region_transaction_commit();
2362 }
2363
2364 static void memory_region_readd_subregion(MemoryRegion *mr)
2365 {
2366 MemoryRegion *container = mr->container;
2367
2368 if (container) {
2369 memory_region_transaction_begin();
2370 memory_region_ref(mr);
2371 memory_region_del_subregion(container, mr);
2372 mr->container = container;
2373 memory_region_update_container_subregions(mr);
2374 memory_region_unref(mr);
2375 memory_region_transaction_commit();
2376 }
2377 }
2378
2379 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2380 {
2381 if (addr != mr->addr) {
2382 mr->addr = addr;
2383 memory_region_readd_subregion(mr);
2384 }
2385 }
2386
2387 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2388 {
2389 assert(mr->alias);
2390
2391 if (offset == mr->alias_offset) {
2392 return;
2393 }
2394
2395 memory_region_transaction_begin();
2396 mr->alias_offset = offset;
2397 memory_region_update_pending |= mr->enabled;
2398 memory_region_transaction_commit();
2399 }
2400
2401 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2402 {
2403 return mr->align;
2404 }
2405
2406 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2407 {
2408 const AddrRange *addr = addr_;
2409 const FlatRange *fr = fr_;
2410
2411 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2412 return -1;
2413 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2414 return 1;
2415 }
2416 return 0;
2417 }
2418
2419 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2420 {
2421 return bsearch(&addr, view->ranges, view->nr,
2422 sizeof(FlatRange), cmp_flatrange_addr);
2423 }
2424
2425 bool memory_region_is_mapped(MemoryRegion *mr)
2426 {
2427 return mr->container ? true : false;
2428 }
2429
2430 /* Same as memory_region_find, but it does not add a reference to the
2431 * returned region. It must be called from an RCU critical section.
2432 */
2433 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2434 hwaddr addr, uint64_t size)
2435 {
2436 MemoryRegionSection ret = { .mr = NULL };
2437 MemoryRegion *root;
2438 AddressSpace *as;
2439 AddrRange range;
2440 FlatView *view;
2441 FlatRange *fr;
2442
2443 addr += mr->addr;
2444 for (root = mr; root->container; ) {
2445 root = root->container;
2446 addr += root->addr;
2447 }
2448
2449 as = memory_region_to_address_space(root);
2450 if (!as) {
2451 return ret;
2452 }
2453 range = addrrange_make(int128_make64(addr), int128_make64(size));
2454
2455 view = address_space_to_flatview(as);
2456 fr = flatview_lookup(view, range);
2457 if (!fr) {
2458 return ret;
2459 }
2460
2461 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2462 --fr;
2463 }
2464
2465 ret.mr = fr->mr;
2466 ret.fv = view;
2467 range = addrrange_intersection(range, fr->addr);
2468 ret.offset_within_region = fr->offset_in_region;
2469 ret.offset_within_region += int128_get64(int128_sub(range.start,
2470 fr->addr.start));
2471 ret.size = range.size;
2472 ret.offset_within_address_space = int128_get64(range.start);
2473 ret.readonly = fr->readonly;
2474 return ret;
2475 }
2476
2477 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2478 hwaddr addr, uint64_t size)
2479 {
2480 MemoryRegionSection ret;
2481 rcu_read_lock();
2482 ret = memory_region_find_rcu(mr, addr, size);
2483 if (ret.mr) {
2484 memory_region_ref(ret.mr);
2485 }
2486 rcu_read_unlock();
2487 return ret;
2488 }
2489
2490 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2491 {
2492 MemoryRegion *mr;
2493
2494 rcu_read_lock();
2495 mr = memory_region_find_rcu(container, addr, 1).mr;
2496 rcu_read_unlock();
2497 return mr && mr != container;
2498 }
2499
2500 void memory_global_dirty_log_sync(void)
2501 {
2502 MemoryListener *listener;
2503 AddressSpace *as;
2504 FlatView *view;
2505 FlatRange *fr;
2506
2507 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2508 if (!listener->log_sync) {
2509 continue;
2510 }
2511 as = listener->address_space;
2512 view = address_space_get_flatview(as);
2513 FOR_EACH_FLAT_RANGE(fr, view) {
2514 if (fr->dirty_log_mask) {
2515 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2516
2517 listener->log_sync(listener, &mrs);
2518 }
2519 }
2520 flatview_unref(view);
2521 }
2522 }
2523
2524 static VMChangeStateEntry *vmstate_change;
2525
2526 void memory_global_dirty_log_start(void)
2527 {
2528 if (vmstate_change) {
2529 qemu_del_vm_change_state_handler(vmstate_change);
2530 vmstate_change = NULL;
2531 }
2532
2533 global_dirty_log = true;
2534
2535 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2536
2537 /* Refresh DIRTY_LOG_MIGRATION bit. */
2538 memory_region_transaction_begin();
2539 memory_region_update_pending = true;
2540 memory_region_transaction_commit();
2541 }
2542
2543 static void memory_global_dirty_log_do_stop(void)
2544 {
2545 global_dirty_log = false;
2546
2547 /* Refresh DIRTY_LOG_MIGRATION bit. */
2548 memory_region_transaction_begin();
2549 memory_region_update_pending = true;
2550 memory_region_transaction_commit();
2551
2552 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2553 }
2554
2555 static void memory_vm_change_state_handler(void *opaque, int running,
2556 RunState state)
2557 {
2558 if (running) {
2559 memory_global_dirty_log_do_stop();
2560
2561 if (vmstate_change) {
2562 qemu_del_vm_change_state_handler(vmstate_change);
2563 vmstate_change = NULL;
2564 }
2565 }
2566 }
2567
2568 void memory_global_dirty_log_stop(void)
2569 {
2570 if (!runstate_is_running()) {
2571 if (vmstate_change) {
2572 return;
2573 }
2574 vmstate_change = qemu_add_vm_change_state_handler(
2575 memory_vm_change_state_handler, NULL);
2576 return;
2577 }
2578
2579 memory_global_dirty_log_do_stop();
2580 }
2581
2582 static void listener_add_address_space(MemoryListener *listener,
2583 AddressSpace *as)
2584 {
2585 FlatView *view;
2586 FlatRange *fr;
2587
2588 if (listener->begin) {
2589 listener->begin(listener);
2590 }
2591 if (global_dirty_log) {
2592 if (listener->log_global_start) {
2593 listener->log_global_start(listener);
2594 }
2595 }
2596
2597 view = address_space_get_flatview(as);
2598 FOR_EACH_FLAT_RANGE(fr, view) {
2599 MemoryRegionSection section = section_from_flat_range(fr, view);
2600
2601 if (listener->region_add) {
2602 listener->region_add(listener, &section);
2603 }
2604 if (fr->dirty_log_mask && listener->log_start) {
2605 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2606 }
2607 }
2608 if (listener->commit) {
2609 listener->commit(listener);
2610 }
2611 flatview_unref(view);
2612 }
2613
2614 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2615 {
2616 MemoryListener *other = NULL;
2617
2618 listener->address_space = as;
2619 if (QTAILQ_EMPTY(&memory_listeners)
2620 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2621 memory_listeners)->priority) {
2622 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2623 } else {
2624 QTAILQ_FOREACH(other, &memory_listeners, link) {
2625 if (listener->priority < other->priority) {
2626 break;
2627 }
2628 }
2629 QTAILQ_INSERT_BEFORE(other, listener, link);
2630 }
2631
2632 if (QTAILQ_EMPTY(&as->listeners)
2633 || listener->priority >= QTAILQ_LAST(&as->listeners,
2634 memory_listeners)->priority) {
2635 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2636 } else {
2637 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2638 if (listener->priority < other->priority) {
2639 break;
2640 }
2641 }
2642 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2643 }
2644
2645 listener_add_address_space(listener, as);
2646 }
2647
2648 void memory_listener_unregister(MemoryListener *listener)
2649 {
2650 if (!listener->address_space) {
2651 return;
2652 }
2653
2654 QTAILQ_REMOVE(&memory_listeners, listener, link);
2655 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2656 listener->address_space = NULL;
2657 }
2658
2659 bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2660 {
2661 void *host;
2662 unsigned size = 0;
2663 unsigned offset = 0;
2664 Object *new_interface;
2665
2666 if (!mr || !mr->ops->request_ptr) {
2667 return false;
2668 }
2669
2670 /*
2671 * Avoid an update if the request_ptr call
2672 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2673 * a cache.
2674 */
2675 memory_region_transaction_begin();
2676
2677 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2678
2679 if (!host || !size) {
2680 memory_region_transaction_commit();
2681 return false;
2682 }
2683
2684 new_interface = object_new("mmio_interface");
2685 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2686 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2687 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2688 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2689 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2690 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2691
2692 memory_region_transaction_commit();
2693 return true;
2694 }
2695
2696 typedef struct MMIOPtrInvalidate {
2697 MemoryRegion *mr;
2698 hwaddr offset;
2699 unsigned size;
2700 int busy;
2701 int allocated;
2702 } MMIOPtrInvalidate;
2703
2704 #define MAX_MMIO_INVALIDATE 10
2705 static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2706
2707 static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2708 run_on_cpu_data data)
2709 {
2710 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2711 MemoryRegion *mr = invalidate_data->mr;
2712 hwaddr offset = invalidate_data->offset;
2713 unsigned size = invalidate_data->size;
2714 MemoryRegionSection section = memory_region_find(mr, offset, size);
2715
2716 qemu_mutex_lock_iothread();
2717
2718 /* Reset dirty so this doesn't happen later. */
2719 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2720
2721 if (section.mr != mr) {
2722 /* memory_region_find add a ref on section.mr */
2723 memory_region_unref(section.mr);
2724 if (MMIO_INTERFACE(section.mr->owner)) {
2725 /* We found the interface just drop it. */
2726 object_property_set_bool(section.mr->owner, false, "realized",
2727 NULL);
2728 object_unref(section.mr->owner);
2729 object_unparent(section.mr->owner);
2730 }
2731 }
2732
2733 qemu_mutex_unlock_iothread();
2734
2735 if (invalidate_data->allocated) {
2736 g_free(invalidate_data);
2737 } else {
2738 invalidate_data->busy = 0;
2739 }
2740 }
2741
2742 void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2743 unsigned size)
2744 {
2745 size_t i;
2746 MMIOPtrInvalidate *invalidate_data = NULL;
2747
2748 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2749 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2750 invalidate_data = &mmio_ptr_invalidate_list[i];
2751 break;
2752 }
2753 }
2754
2755 if (!invalidate_data) {
2756 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2757 invalidate_data->allocated = 1;
2758 }
2759
2760 invalidate_data->mr = mr;
2761 invalidate_data->offset = offset;
2762 invalidate_data->size = size;
2763
2764 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2765 RUN_ON_CPU_HOST_PTR(invalidate_data));
2766 }
2767
2768 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2769 {
2770 memory_region_ref(root);
2771 as->root = root;
2772 as->current_map = NULL;
2773 as->ioeventfd_nb = 0;
2774 as->ioeventfds = NULL;
2775 QTAILQ_INIT(&as->listeners);
2776 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2777 as->name = g_strdup(name ? name : "anonymous");
2778 address_space_update_topology(as);
2779 address_space_update_ioeventfds(as);
2780 }
2781
2782 static void do_address_space_destroy(AddressSpace *as)
2783 {
2784 assert(QTAILQ_EMPTY(&as->listeners));
2785
2786 flatview_unref(as->current_map);
2787 g_free(as->name);
2788 g_free(as->ioeventfds);
2789 memory_region_unref(as->root);
2790 }
2791
2792 void address_space_destroy(AddressSpace *as)
2793 {
2794 MemoryRegion *root = as->root;
2795
2796 /* Flush out anything from MemoryListeners listening in on this */
2797 memory_region_transaction_begin();
2798 as->root = NULL;
2799 memory_region_transaction_commit();
2800 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2801
2802 /* At this point, as->dispatch and as->current_map are dummy
2803 * entries that the guest should never use. Wait for the old
2804 * values to expire before freeing the data.
2805 */
2806 as->root = root;
2807 call_rcu(as, do_address_space_destroy, rcu);
2808 }
2809
2810 static const char *memory_region_type(MemoryRegion *mr)
2811 {
2812 if (memory_region_is_ram_device(mr)) {
2813 return "ramd";
2814 } else if (memory_region_is_romd(mr)) {
2815 return "romd";
2816 } else if (memory_region_is_rom(mr)) {
2817 return "rom";
2818 } else if (memory_region_is_ram(mr)) {
2819 return "ram";
2820 } else {
2821 return "i/o";
2822 }
2823 }
2824
2825 typedef struct MemoryRegionList MemoryRegionList;
2826
2827 struct MemoryRegionList {
2828 const MemoryRegion *mr;
2829 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2830 };
2831
2832 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2833
2834 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2835 int128_sub((size), int128_one())) : 0)
2836 #define MTREE_INDENT " "
2837
2838 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2839 const MemoryRegion *mr, unsigned int level,
2840 hwaddr base,
2841 MemoryRegionListHead *alias_print_queue)
2842 {
2843 MemoryRegionList *new_ml, *ml, *next_ml;
2844 MemoryRegionListHead submr_print_queue;
2845 const MemoryRegion *submr;
2846 unsigned int i;
2847 hwaddr cur_start, cur_end;
2848
2849 if (!mr) {
2850 return;
2851 }
2852
2853 for (i = 0; i < level; i++) {
2854 mon_printf(f, MTREE_INDENT);
2855 }
2856
2857 cur_start = base + mr->addr;
2858 cur_end = cur_start + MR_SIZE(mr->size);
2859
2860 /*
2861 * Try to detect overflow of memory region. This should never
2862 * happen normally. When it happens, we dump something to warn the
2863 * user who is observing this.
2864 */
2865 if (cur_start < base || cur_end < cur_start) {
2866 mon_printf(f, "[DETECTED OVERFLOW!] ");
2867 }
2868
2869 if (mr->alias) {
2870 MemoryRegionList *ml;
2871 bool found = false;
2872
2873 /* check if the alias is already in the queue */
2874 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2875 if (ml->mr == mr->alias) {
2876 found = true;
2877 }
2878 }
2879
2880 if (!found) {
2881 ml = g_new(MemoryRegionList, 1);
2882 ml->mr = mr->alias;
2883 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2884 }
2885 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2886 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2887 "-" TARGET_FMT_plx "%s\n",
2888 cur_start, cur_end,
2889 mr->priority,
2890 memory_region_type((MemoryRegion *)mr),
2891 memory_region_name(mr),
2892 memory_region_name(mr->alias),
2893 mr->alias_offset,
2894 mr->alias_offset + MR_SIZE(mr->size),
2895 mr->enabled ? "" : " [disabled]");
2896 } else {
2897 mon_printf(f,
2898 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
2899 cur_start, cur_end,
2900 mr->priority,
2901 memory_region_type((MemoryRegion *)mr),
2902 memory_region_name(mr),
2903 mr->enabled ? "" : " [disabled]");
2904 }
2905
2906 QTAILQ_INIT(&submr_print_queue);
2907
2908 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2909 new_ml = g_new(MemoryRegionList, 1);
2910 new_ml->mr = submr;
2911 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2912 if (new_ml->mr->addr < ml->mr->addr ||
2913 (new_ml->mr->addr == ml->mr->addr &&
2914 new_ml->mr->priority > ml->mr->priority)) {
2915 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2916 new_ml = NULL;
2917 break;
2918 }
2919 }
2920 if (new_ml) {
2921 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2922 }
2923 }
2924
2925 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2926 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2927 alias_print_queue);
2928 }
2929
2930 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2931 g_free(ml);
2932 }
2933 }
2934
2935 struct FlatViewInfo {
2936 fprintf_function mon_printf;
2937 void *f;
2938 int counter;
2939 bool dispatch_tree;
2940 };
2941
2942 static void mtree_print_flatview(gpointer key, gpointer value,
2943 gpointer user_data)
2944 {
2945 FlatView *view = key;
2946 GArray *fv_address_spaces = value;
2947 struct FlatViewInfo *fvi = user_data;
2948 fprintf_function p = fvi->mon_printf;
2949 void *f = fvi->f;
2950 FlatRange *range = &view->ranges[0];
2951 MemoryRegion *mr;
2952 int n = view->nr;
2953 int i;
2954 AddressSpace *as;
2955
2956 p(f, "FlatView #%d\n", fvi->counter);
2957 ++fvi->counter;
2958
2959 for (i = 0; i < fv_address_spaces->len; ++i) {
2960 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2961 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2962 if (as->root->alias) {
2963 p(f, ", alias %s", memory_region_name(as->root->alias));
2964 }
2965 p(f, "\n");
2966 }
2967
2968 p(f, " Root memory region: %s\n",
2969 view->root ? memory_region_name(view->root) : "(none)");
2970
2971 if (n <= 0) {
2972 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2973 return;
2974 }
2975
2976 while (n--) {
2977 mr = range->mr;
2978 if (range->offset_in_region) {
2979 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2980 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2981 int128_get64(range->addr.start),
2982 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2983 mr->priority,
2984 range->readonly ? "rom" : memory_region_type(mr),
2985 memory_region_name(mr),
2986 range->offset_in_region);
2987 } else {
2988 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2989 TARGET_FMT_plx " (prio %d, %s): %s\n",
2990 int128_get64(range->addr.start),
2991 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2992 mr->priority,
2993 range->readonly ? "rom" : memory_region_type(mr),
2994 memory_region_name(mr));
2995 }
2996 range++;
2997 }
2998
2999 #if !defined(CONFIG_USER_ONLY)
3000 if (fvi->dispatch_tree && view->root) {
3001 mtree_print_dispatch(p, f, view->dispatch, view->root);
3002 }
3003 #endif
3004
3005 p(f, "\n");
3006 }
3007
3008 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3009 gpointer user_data)
3010 {
3011 FlatView *view = key;
3012 GArray *fv_address_spaces = value;
3013
3014 g_array_unref(fv_address_spaces);
3015 flatview_unref(view);
3016
3017 return true;
3018 }
3019
3020 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3021 bool dispatch_tree)
3022 {
3023 MemoryRegionListHead ml_head;
3024 MemoryRegionList *ml, *ml2;
3025 AddressSpace *as;
3026
3027 if (flatview) {
3028 FlatView *view;
3029 struct FlatViewInfo fvi = {
3030 .mon_printf = mon_printf,
3031 .f = f,
3032 .counter = 0,
3033 .dispatch_tree = dispatch_tree
3034 };
3035 GArray *fv_address_spaces;
3036 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3037
3038 /* Gather all FVs in one table */
3039 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3040 view = address_space_get_flatview(as);
3041
3042 fv_address_spaces = g_hash_table_lookup(views, view);
3043 if (!fv_address_spaces) {
3044 fv_address_spaces = g_array_new(false, false, sizeof(as));
3045 g_hash_table_insert(views, view, fv_address_spaces);
3046 }
3047
3048 g_array_append_val(fv_address_spaces, as);
3049 }
3050
3051 /* Print */
3052 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3053
3054 /* Free */
3055 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3056 g_hash_table_unref(views);
3057
3058 return;
3059 }
3060
3061 QTAILQ_INIT(&ml_head);
3062
3063 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3064 mon_printf(f, "address-space: %s\n", as->name);
3065 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3066 mon_printf(f, "\n");
3067 }
3068
3069 /* print aliased regions */
3070 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3071 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3072 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3073 mon_printf(f, "\n");
3074 }
3075
3076 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3077 g_free(ml);
3078 }
3079 }
3080
3081 void memory_region_init_ram(MemoryRegion *mr,
3082 struct Object *owner,
3083 const char *name,
3084 uint64_t size,
3085 Error **errp)
3086 {
3087 DeviceState *owner_dev;
3088 Error *err = NULL;
3089
3090 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3091 if (err) {
3092 error_propagate(errp, err);
3093 return;
3094 }
3095 /* This will assert if owner is neither NULL nor a DeviceState.
3096 * We only want the owner here for the purposes of defining a
3097 * unique name for migration. TODO: Ideally we should implement
3098 * a naming scheme for Objects which are not DeviceStates, in
3099 * which case we can relax this restriction.
3100 */
3101 owner_dev = DEVICE(owner);
3102 vmstate_register_ram(mr, owner_dev);
3103 }
3104
3105 void memory_region_init_rom(MemoryRegion *mr,
3106 struct Object *owner,
3107 const char *name,
3108 uint64_t size,
3109 Error **errp)
3110 {
3111 DeviceState *owner_dev;
3112 Error *err = NULL;
3113
3114 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3115 if (err) {
3116 error_propagate(errp, err);
3117 return;
3118 }
3119 /* This will assert if owner is neither NULL nor a DeviceState.
3120 * We only want the owner here for the purposes of defining a
3121 * unique name for migration. TODO: Ideally we should implement
3122 * a naming scheme for Objects which are not DeviceStates, in
3123 * which case we can relax this restriction.
3124 */
3125 owner_dev = DEVICE(owner);
3126 vmstate_register_ram(mr, owner_dev);
3127 }
3128
3129 void memory_region_init_rom_device(MemoryRegion *mr,
3130 struct Object *owner,
3131 const MemoryRegionOps *ops,
3132 void *opaque,
3133 const char *name,
3134 uint64_t size,
3135 Error **errp)
3136 {
3137 DeviceState *owner_dev;
3138 Error *err = NULL;
3139
3140 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3141 name, size, &err);
3142 if (err) {
3143 error_propagate(errp, err);
3144 return;
3145 }
3146 /* This will assert if owner is neither NULL nor a DeviceState.
3147 * We only want the owner here for the purposes of defining a
3148 * unique name for migration. TODO: Ideally we should implement
3149 * a naming scheme for Objects which are not DeviceStates, in
3150 * which case we can relax this restriction.
3151 */
3152 owner_dev = DEVICE(owner);
3153 vmstate_register_ram(mr, owner_dev);
3154 }
3155
3156 static const TypeInfo memory_region_info = {
3157 .parent = TYPE_OBJECT,
3158 .name = TYPE_MEMORY_REGION,
3159 .instance_size = sizeof(MemoryRegion),
3160 .instance_init = memory_region_initfn,
3161 .instance_finalize = memory_region_finalize,
3162 };
3163
3164 static const TypeInfo iommu_memory_region_info = {
3165 .parent = TYPE_MEMORY_REGION,
3166 .name = TYPE_IOMMU_MEMORY_REGION,
3167 .class_size = sizeof(IOMMUMemoryRegionClass),
3168 .instance_size = sizeof(IOMMUMemoryRegion),
3169 .instance_init = iommu_memory_region_initfn,
3170 .abstract = true,
3171 };
3172
3173 static void memory_register_types(void)
3174 {
3175 type_register_static(&memory_region_info);
3176 type_register_static(&iommu_memory_region_info);
3177 }
3178
3179 type_init(memory_register_types)
AR7 emulation for QEMU