softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * Generate helpers used by TCG for qemu_ld/st ops and code load
   5  * functions.
   6  *
   7  * Included from target op helpers and exec.c.
   8  *
   9  *  Copyright (c) 2003 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License as published by the Free Software Foundation; either
  14  * version 2 of the License, or (at your option) any later version.
  15  *
  16  * This library is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * Lesser General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU Lesser General Public
  22  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24 #include "qemu/timer.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/memory.h"
  27
  28 #define DATA_SIZE (1 << SHIFT)
  29
  30 #if DATA_SIZE == 8
  31 #define SUFFIX q
  32 #define LSUFFIX q
  33 #define SDATA_TYPE  int64_t
  34 #define DATA_TYPE  uint64_t
  35 #elif DATA_SIZE == 4
  36 #define SUFFIX l
  37 #define LSUFFIX l
  38 #define SDATA_TYPE  int32_t
  39 #define DATA_TYPE  uint32_t
  40 #elif DATA_SIZE == 2
  41 #define SUFFIX w
  42 #define LSUFFIX uw
  43 #define SDATA_TYPE  int16_t
  44 #define DATA_TYPE  uint16_t
  45 #elif DATA_SIZE == 1
  46 #define SUFFIX b
  47 #define LSUFFIX ub
  48 #define SDATA_TYPE  int8_t
  49 #define DATA_TYPE  uint8_t
  50 #else
  51 #error unsupported data size
  52 #endif
  53
  54
  55 /* For the benefit of TCG generated code, we want to avoid the complication
  56    of ABI-specific return type promotion and always return a value extended
  57    to the register size of the host.  This is tcg_target_long, except in the
  58    case of a 32-bit host and 64-bit data, and for that we always have
  59    uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
  60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
  61 # define WORD_TYPE  DATA_TYPE
  62 # define USUFFIX    SUFFIX
  63 #else
  64 # define WORD_TYPE  tcg_target_ulong
  65 # define USUFFIX    glue(u, SUFFIX)
  66 # define SSUFFIX    glue(s, SUFFIX)
  67 #endif
  68
  69 #ifdef SOFTMMU_CODE_ACCESS
  70 #define READ_ACCESS_TYPE MMU_INST_FETCH
  71 #define ADDR_READ addr_code
  72 #else
  73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
  74 #define ADDR_READ addr_read
  75 #endif
  76
  77 #if DATA_SIZE == 8
  78 # define BSWAP(X)  bswap64(X)
  79 #elif DATA_SIZE == 4
  80 # define BSWAP(X)  bswap32(X)
  81 #elif DATA_SIZE == 2
  82 # define BSWAP(X)  bswap16(X)
  83 #else
  84 # define BSWAP(X)  (X)
  85 #endif
  86
  87 #ifdef TARGET_WORDS_BIGENDIAN
  88 # define TGT_BE(X)  (X)
  89 # define TGT_LE(X)  BSWAP(X)
  90 #else
  91 # define TGT_BE(X)  BSWAP(X)
  92 # define TGT_LE(X)  (X)
  93 #endif
  94
  95 #if DATA_SIZE == 1
  96 # define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
  97 # define helper_be_ld_name  helper_le_ld_name
  98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
  99 # define helper_be_lds_name helper_le_lds_name
 100 # define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
 101 # define helper_be_st_name  helper_le_st_name
 102 #else
 103 # define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
 104 # define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
 105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
 106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
 107 # define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
 108 # define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
 109 #endif
 110
 111 #ifdef TARGET_WORDS_BIGENDIAN
 112 # define helper_te_ld_name  helper_be_ld_name
 113 # define helper_te_st_name  helper_be_st_name
 114 #else
 115 # define helper_te_ld_name  helper_le_ld_name
 116 # define helper_te_st_name  helper_le_st_name
 117 #endif
 118
 119 /* macro to check the victim tlb */
 120 #define VICTIM_TLB_HIT(ty)                                                    \
 121 ({                                                                            \
 122     /* we are about to do a page table walk. our last hope is the             \
 123      * victim tlb. try to refill from the victim tlb before walking the       \
 124      * page table. */                                                         \
 125     int vidx;                                                                 \
 126     CPUIOTLBEntry tmpiotlb;                                                   \
 127     CPUTLBEntry tmptlb;                                                       \
 128     for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) {                         \
 129         if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
 130             /* found entry in victim tlb, swap tlb and iotlb */               \
 131             tmptlb = env->tlb_table[mmu_idx][index];                          \
 132             env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
 133             env->tlb_v_table[mmu_idx][vidx] = tmptlb;                         \
 134             tmpiotlb = env->iotlb[mmu_idx][index];                            \
 135             env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx];         \
 136             env->iotlb_v[mmu_idx][vidx] = tmpiotlb;                           \
 137             break;                                                            \
 138         }                                                                     \
 139     }                                                                         \
 140     /* return true when there is a vtlb hit, i.e. vidx >=0 */                 \
 141     vidx >= 0;                                                                \
 142 })
 143
 144 #ifndef SOFTMMU_CODE_ACCESS
 145 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
 146                                               CPUIOTLBEntry *iotlbentry,
 147                                               target_ulong addr,
 148                                               uintptr_t retaddr)
 149 {
 150     uint64_t val;
 151     CPUState *cpu = ENV_GET_CPU(env);
 152     hwaddr physaddr = iotlbentry->addr;
 153     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 154
 155     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 156     cpu->mem_io_pc = retaddr;
 157     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
 158         cpu_io_recompile(cpu, retaddr);
 159     }
 160
 161     cpu->mem_io_vaddr = addr;
 162     memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
 163                                 iotlbentry->attrs);
 164     return val;
 165 }
 166 #endif
 167
 168 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
 169                             TCGMemOpIdx oi, uintptr_t retaddr)
 170 {
 171     unsigned mmu_idx = get_mmuidx(oi);
 172     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 173     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 174     uintptr_t haddr;
 175     DATA_TYPE res;
 176
 177     /* Adjust the given return address.  */
 178     retaddr -= GETPC_ADJ;
 179
 180     /* If the TLB entry is for a different page, reload and try again.  */
 181     if ((addr & TARGET_PAGE_MASK)
 182          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 183         if ((addr & (DATA_SIZE - 1)) != 0
 184             && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 185             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 186                                  mmu_idx, retaddr);
 187         }
 188         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 189             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 190                      mmu_idx, retaddr);
 191         }
 192         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 193     }
 194
 195     /* Handle an IO access.  */
 196     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 197         CPUIOTLBEntry *iotlbentry;
 198         if ((addr & (DATA_SIZE - 1)) != 0) {
 199             goto do_unaligned_access;
 200         }
 201         iotlbentry = &env->iotlb[mmu_idx][index];
 202
 203         /* ??? Note that the io helpers always read data in the target
 204            byte ordering.  We should push the LE/BE request down into io.  */
 205         res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
 206         res = TGT_LE(res);
 207         return res;
 208     }
 209
 210     /* Handle slow unaligned access (it spans two pages or IO).  */
 211     if (DATA_SIZE > 1
 212         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 213                     >= TARGET_PAGE_SIZE)) {
 214         target_ulong addr1, addr2;
 215         DATA_TYPE res1, res2;
 216         unsigned shift;
 217     do_unaligned_access:
 218         if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 219             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 220                                  mmu_idx, retaddr);
 221         }
 222         addr1 = addr & ~(DATA_SIZE - 1);
 223         addr2 = addr1 + DATA_SIZE;
 224         /* Note the adjustment at the beginning of the function.
 225            Undo that for the recursion.  */
 226         res1 = helper_le_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
 227         res2 = helper_le_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
 228         shift = (addr & (DATA_SIZE - 1)) * 8;
 229
 230         /* Little-endian combine.  */
 231         res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 232         return res;
 233     }
 234
 235     /* Handle aligned access or unaligned access in the same page.  */
 236     if ((addr & (DATA_SIZE - 1)) != 0
 237         && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 238         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 239                              mmu_idx, retaddr);
 240     }
 241
 242     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 243 #if DATA_SIZE == 1
 244     res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
 245 #else
 246     res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
 247 #endif
 248     return res;
 249 }
 250
 251 #if DATA_SIZE > 1
 252 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
 253                             TCGMemOpIdx oi, uintptr_t retaddr)
 254 {
 255     unsigned mmu_idx = get_mmuidx(oi);
 256     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 257     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 258     uintptr_t haddr;
 259     DATA_TYPE res;
 260
 261     /* Adjust the given return address.  */
 262     retaddr -= GETPC_ADJ;
 263
 264     /* If the TLB entry is for a different page, reload and try again.  */
 265     if ((addr & TARGET_PAGE_MASK)
 266          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 267         if ((addr & (DATA_SIZE - 1)) != 0
 268             && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 269             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 270                                  mmu_idx, retaddr);
 271         }
 272         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 273             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 274                      mmu_idx, retaddr);
 275         }
 276         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 277     }
 278
 279     /* Handle an IO access.  */
 280     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 281         CPUIOTLBEntry *iotlbentry;
 282         if ((addr & (DATA_SIZE - 1)) != 0) {
 283             goto do_unaligned_access;
 284         }
 285         iotlbentry = &env->iotlb[mmu_idx][index];
 286
 287         /* ??? Note that the io helpers always read data in the target
 288            byte ordering.  We should push the LE/BE request down into io.  */
 289         res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
 290         res = TGT_BE(res);
 291         return res;
 292     }
 293
 294     /* Handle slow unaligned access (it spans two pages or IO).  */
 295     if (DATA_SIZE > 1
 296         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 297                     >= TARGET_PAGE_SIZE)) {
 298         target_ulong addr1, addr2;
 299         DATA_TYPE res1, res2;
 300         unsigned shift;
 301     do_unaligned_access:
 302         if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 303             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 304                                  mmu_idx, retaddr);
 305         }
 306         addr1 = addr & ~(DATA_SIZE - 1);
 307         addr2 = addr1 + DATA_SIZE;
 308         /* Note the adjustment at the beginning of the function.
 309            Undo that for the recursion.  */
 310         res1 = helper_be_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
 311         res2 = helper_be_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
 312         shift = (addr & (DATA_SIZE - 1)) * 8;
 313
 314         /* Big-endian combine.  */
 315         res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 316         return res;
 317     }
 318
 319     /* Handle aligned access or unaligned access in the same page.  */
 320     if ((addr & (DATA_SIZE - 1)) != 0
 321         && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 322         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 323                              mmu_idx, retaddr);
 324     }
 325
 326     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 327     res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
 328     return res;
 329 }
 330 #endif /* DATA_SIZE > 1 */
 331
 332 #ifndef SOFTMMU_CODE_ACCESS
 333
 334 /* Provide signed versions of the load routines as well.  We can of course
 335    avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
 336 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
 337 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
 338                              TCGMemOpIdx oi, uintptr_t retaddr)
 339 {
 340     return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
 341 }
 342
 343 # if DATA_SIZE > 1
 344 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
 345                              TCGMemOpIdx oi, uintptr_t retaddr)
 346 {
 347     return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
 348 }
 349 # endif
 350 #endif
 351
 352 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
 353                                           CPUIOTLBEntry *iotlbentry,
 354                                           DATA_TYPE val,
 355                                           target_ulong addr,
 356                                           uintptr_t retaddr)
 357 {
 358     CPUState *cpu = ENV_GET_CPU(env);
 359     hwaddr physaddr = iotlbentry->addr;
 360     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 361
 362     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 363     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
 364         cpu_io_recompile(cpu, retaddr);
 365     }
 366
 367     cpu->mem_io_vaddr = addr;
 368     cpu->mem_io_pc = retaddr;
 369     memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
 370                                  iotlbentry->attrs);
 371 }
 372
 373 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 374                        TCGMemOpIdx oi, uintptr_t retaddr)
 375 {
 376     unsigned mmu_idx = get_mmuidx(oi);
 377     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 378     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 379     uintptr_t haddr;
 380
 381     /* Adjust the given return address.  */
 382     retaddr -= GETPC_ADJ;
 383
 384     /* If the TLB entry is for a different page, reload and try again.  */
 385     if ((addr & TARGET_PAGE_MASK)
 386         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 387         if ((addr & (DATA_SIZE - 1)) != 0
 388             && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 389             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 390                                  mmu_idx, retaddr);
 391         }
 392         if (!VICTIM_TLB_HIT(addr_write)) {
 393             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 394         }
 395         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 396     }
 397
 398     /* Handle an IO access.  */
 399     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 400         CPUIOTLBEntry *iotlbentry;
 401         if ((addr & (DATA_SIZE - 1)) != 0) {
 402             goto do_unaligned_access;
 403         }
 404         iotlbentry = &env->iotlb[mmu_idx][index];
 405
 406         /* ??? Note that the io helpers always read data in the target
 407            byte ordering.  We should push the LE/BE request down into io.  */
 408         val = TGT_LE(val);
 409         glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
 410         return;
 411     }
 412
 413     /* Handle slow unaligned access (it spans two pages or IO).  */
 414     if (DATA_SIZE > 1
 415         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 416                      >= TARGET_PAGE_SIZE)) {
 417         int i;
 418     do_unaligned_access:
 419         if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 420             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 421                                  mmu_idx, retaddr);
 422         }
 423         /* XXX: not efficient, but simple */
 424         /* Note: relies on the fact that tlb_fill() does not remove the
 425          * previous page from the TLB cache.  */
 426         for (i = DATA_SIZE - 1; i >= 0; i--) {
 427             /* Little-endian extract.  */
 428             uint8_t val8 = val >> (i * 8);
 429             /* Note the adjustment at the beginning of the function.
 430                Undo that for the recursion.  */
 431             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 432                                             oi, retaddr + GETPC_ADJ);
 433         }
 434         return;
 435     }
 436
 437     /* Handle aligned access or unaligned access in the same page.  */
 438     if ((addr & (DATA_SIZE - 1)) != 0
 439         && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 440         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 441                              mmu_idx, retaddr);
 442     }
 443
 444     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 445 #if DATA_SIZE == 1
 446     glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
 447 #else
 448     glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
 449 #endif
 450 }
 451
 452 #if DATA_SIZE > 1
 453 void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 454                        TCGMemOpIdx oi, uintptr_t retaddr)
 455 {
 456     unsigned mmu_idx = get_mmuidx(oi);
 457     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 458     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 459     uintptr_t haddr;
 460
 461     /* Adjust the given return address.  */
 462     retaddr -= GETPC_ADJ;
 463
 464     /* If the TLB entry is for a different page, reload and try again.  */
 465     if ((addr & TARGET_PAGE_MASK)
 466         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 467         if ((addr & (DATA_SIZE - 1)) != 0
 468             && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 469             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 470                                  mmu_idx, retaddr);
 471         }
 472         if (!VICTIM_TLB_HIT(addr_write)) {
 473             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 474         }
 475         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 476     }
 477
 478     /* Handle an IO access.  */
 479     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 480         CPUIOTLBEntry *iotlbentry;
 481         if ((addr & (DATA_SIZE - 1)) != 0) {
 482             goto do_unaligned_access;
 483         }
 484         iotlbentry = &env->iotlb[mmu_idx][index];
 485
 486         /* ??? Note that the io helpers always read data in the target
 487            byte ordering.  We should push the LE/BE request down into io.  */
 488         val = TGT_BE(val);
 489         glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
 490         return;
 491     }
 492
 493     /* Handle slow unaligned access (it spans two pages or IO).  */
 494     if (DATA_SIZE > 1
 495         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 496                      >= TARGET_PAGE_SIZE)) {
 497         int i;
 498     do_unaligned_access:
 499         if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 500             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 501                                  mmu_idx, retaddr);
 502         }
 503         /* XXX: not efficient, but simple */
 504         /* Note: relies on the fact that tlb_fill() does not remove the
 505          * previous page from the TLB cache.  */
 506         for (i = DATA_SIZE - 1; i >= 0; i--) {
 507             /* Big-endian extract.  */
 508             uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
 509             /* Note the adjustment at the beginning of the function.
 510                Undo that for the recursion.  */
 511             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 512                                             oi, retaddr + GETPC_ADJ);
 513         }
 514         return;
 515     }
 516
 517     /* Handle aligned access or unaligned access in the same page.  */
 518     if ((addr & (DATA_SIZE - 1)) != 0
 519         && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
 520         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 521                              mmu_idx, retaddr);
 522     }
 523
 524     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 525     glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
 526 }
 527 #endif /* DATA_SIZE > 1 */
 528
 529 #if DATA_SIZE == 1
 530 /* Probe for whether the specified guest write access is permitted.
 531  * If it is not permitted then an exception will be taken in the same
 532  * way as if this were a real write access (and we will not return).
 533  * Otherwise the function will return, and there will be a valid
 534  * entry in the TLB for this access.
 535  */
 536 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 537                  uintptr_t retaddr)
 538 {
 539     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 540     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 541
 542     if ((addr & TARGET_PAGE_MASK)
 543         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 544         /* TLB entry is for a different page */
 545         if (!VICTIM_TLB_HIT(addr_write)) {
 546             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 547         }
 548     }
 549 }
 550 #endif
 551 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 552
 553 #undef READ_ACCESS_TYPE
 554 #undef SHIFT
 555 #undef DATA_TYPE
 556 #undef SUFFIX
 557 #undef LSUFFIX
 558 #undef DATA_SIZE
 559 #undef ADDR_READ
 560 #undef WORD_TYPE
 561 #undef SDATA_TYPE
 562 #undef USUFFIX
 563 #undef SSUFFIX
 564 #undef BSWAP
 565 #undef TGT_BE
 566 #undef TGT_LE
 567 #undef CPU_BE
 568 #undef CPU_LE
 569 #undef helper_le_ld_name
 570 #undef helper_be_ld_name
 571 #undef helper_le_lds_name
 572 #undef helper_be_lds_name
 573 #undef helper_le_st_name
 574 #undef helper_be_st_name
 575 #undef helper_te_ld_name
 576 #undef helper_te_st_name